drivers/mtd/nand/raw/jz4740_nand.c

   1 /*
   2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *  JZ4740 SoC NAND controller driver
   4  *
   5  *  This program is free software; you can redistribute it and/or modify it
   6  *  under  the terms of the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the GNU General Public License along
  11  *  with this program; if not, write to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/rawnand.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <linux/gpio/consumer.h>
  28
  29 #include <linux/platform_data/jz4740/jz4740_nand.h>
  30
  31 #define JZ_REG_NAND_CTRL        0x50
  32 #define JZ_REG_NAND_ECC_CTRL    0x100
  33 #define JZ_REG_NAND_DATA        0x104
  34 #define JZ_REG_NAND_PAR0        0x108
  35 #define JZ_REG_NAND_PAR1        0x10C
  36 #define JZ_REG_NAND_PAR2        0x110
  37 #define JZ_REG_NAND_IRQ_STAT    0x114
  38 #define JZ_REG_NAND_IRQ_CTRL    0x118
  39 #define JZ_REG_NAND_ERR(x)      (0x11C + ((x) << 2))
  40
  41 #define JZ_NAND_ECC_CTRL_PAR_READY      BIT(4)
  42 #define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
  43 #define JZ_NAND_ECC_CTRL_RS             BIT(2)
  44 #define JZ_NAND_ECC_CTRL_RESET          BIT(1)
  45 #define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
  46
  47 #define JZ_NAND_STATUS_ERR_COUNT        (BIT(31) | BIT(30) | BIT(29))
  48 #define JZ_NAND_STATUS_PAD_FINISH       BIT(4)
  49 #define JZ_NAND_STATUS_DEC_FINISH       BIT(3)
  50 #define JZ_NAND_STATUS_ENC_FINISH       BIT(2)
  51 #define JZ_NAND_STATUS_UNCOR_ERROR      BIT(1)
  52 #define JZ_NAND_STATUS_ERROR            BIT(0)
  53
  54 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
  55 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
  56 #define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
  57
  58 #define JZ_NAND_MEM_CMD_OFFSET 0x08000
  59 #define JZ_NAND_MEM_ADDR_OFFSET 0x10000
  60
  61 struct jz_nand {
  62         struct nand_chip chip;
  63         void __iomem *base;
  64         struct resource *mem;
  65
  66         unsigned char banks[JZ_NAND_NUM_BANKS];
  67         void __iomem *bank_base[JZ_NAND_NUM_BANKS];
  68         struct resource *bank_mem[JZ_NAND_NUM_BANKS];
  69
  70         int selected_bank;
  71
  72         struct gpio_desc *busy_gpio;
  73         bool is_reading;
  74 };
  75
  76 static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
  77 {
  78         return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
  79 }
  80
  81 static void jz_nand_select_chip(struct nand_chip *chip, int chipnr)
  82 {
  83         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
  84         uint32_t ctrl;
  85         int banknr;
  86
  87         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
  88         ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
  89
  90         if (chipnr == -1) {
  91                 banknr = -1;
  92         } else {
  93                 banknr = nand->banks[chipnr] - 1;
  94                 chip->legacy.IO_ADDR_R = nand->bank_base[banknr];
  95                 chip->legacy.IO_ADDR_W = nand->bank_base[banknr];
  96         }
  97         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
  98
  99         nand->selected_bank = banknr;
 100 }
 101
 102 static void jz_nand_cmd_ctrl(struct nand_chip *chip, int dat,
 103                              unsigned int ctrl)
 104 {
 105         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
 106         uint32_t reg;
 107         void __iomem *bank_base = nand->bank_base[nand->selected_bank];
 108
 109         BUG_ON(nand->selected_bank < 0);
 110
 111         if (ctrl & NAND_CTRL_CHANGE) {
 112                 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
 113                 if (ctrl & NAND_ALE)
 114                         bank_base += JZ_NAND_MEM_ADDR_OFFSET;
 115                 else if (ctrl & NAND_CLE)
 116                         bank_base += JZ_NAND_MEM_CMD_OFFSET;
 117                 chip->legacy.IO_ADDR_W = bank_base;
 118
 119                 reg = readl(nand->base + JZ_REG_NAND_CTRL);
 120                 if (ctrl & NAND_NCE)
 121                         reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 122                 else
 123                         reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
 124                 writel(reg, nand->base + JZ_REG_NAND_CTRL);
 125         }
 126         if (dat != NAND_CMD_NONE)
 127                 writeb(dat, chip->legacy.IO_ADDR_W);
 128 }
 129
 130 static int jz_nand_dev_ready(struct nand_chip *chip)
 131 {
 132         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
 133         return gpiod_get_value_cansleep(nand->busy_gpio);
 134 }
 135
 136 static void jz_nand_hwctl(struct nand_chip *chip, int mode)
 137 {
 138         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
 139         uint32_t reg;
 140
 141         writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
 142         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 143
 144         reg |= JZ_NAND_ECC_CTRL_RESET;
 145         reg |= JZ_NAND_ECC_CTRL_ENABLE;
 146         reg |= JZ_NAND_ECC_CTRL_RS;
 147
 148         switch (mode) {
 149         case NAND_ECC_READ:
 150                 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
 151                 nand->is_reading = true;
 152                 break;
 153         case NAND_ECC_WRITE:
 154                 reg |= JZ_NAND_ECC_CTRL_ENCODING;
 155                 nand->is_reading = false;
 156                 break;
 157         default:
 158                 break;
 159         }
 160
 161         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 162 }
 163
 164 static int jz_nand_calculate_ecc_rs(struct nand_chip *chip, const uint8_t *dat,
 165                                     uint8_t *ecc_code)
 166 {
 167         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
 168         uint32_t reg, status;
 169         int i;
 170         unsigned int timeout = 1000;
 171         static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
 172                                                 0x8b, 0xff, 0xb7, 0x6f};
 173
 174         if (nand->is_reading)
 175                 return 0;
 176
 177         do {
 178                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 179         } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
 180
 181         if (timeout == 0)
 182             return -1;
 183
 184         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 185         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 186         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 187
 188         for (i = 0; i < 9; ++i)
 189                 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
 190
 191         /* If the written data is completly 0xff, we also want to write 0xff as
 192          * ecc, otherwise we will get in trouble when doing subpage writes. */
 193         if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
 194                 memset(ecc_code, 0xff, 9);
 195
 196         return 0;
 197 }
 198
 199 static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
 200 {
 201         int offset = index & 0x7;
 202         uint16_t data;
 203
 204         index += (index >> 3);
 205
 206         data = dat[index];
 207         data |= dat[index+1] << 8;
 208
 209         mask ^= (data >> offset) & 0x1ff;
 210         data &= ~(0x1ff << offset);
 211         data |= (mask << offset);
 212
 213         dat[index] = data & 0xff;
 214         dat[index+1] = (data >> 8) & 0xff;
 215 }
 216
 217 static int jz_nand_correct_ecc_rs(struct nand_chip *chip, uint8_t *dat,
 218                                   uint8_t *read_ecc, uint8_t *calc_ecc)
 219 {
 220         struct jz_nand *nand = mtd_to_jz_nand(nand_to_mtd(chip));
 221         int i, error_count, index;
 222         uint32_t reg, status, error;
 223         unsigned int timeout = 1000;
 224
 225         for (i = 0; i < 9; ++i)
 226                 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
 227
 228         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 229         reg |= JZ_NAND_ECC_CTRL_PAR_READY;
 230         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 231
 232         do {
 233                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 234         } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
 235
 236         if (timeout == 0)
 237                 return -ETIMEDOUT;
 238
 239         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 240         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 241         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 242
 243         if (status & JZ_NAND_STATUS_ERROR) {
 244                 if (status & JZ_NAND_STATUS_UNCOR_ERROR)
 245                         return -EBADMSG;
 246
 247                 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
 248
 249                 for (i = 0; i < error_count; ++i) {
 250                         error = readl(nand->base + JZ_REG_NAND_ERR(i));
 251                         index = ((error >> 16) & 0x1ff) - 1;
 252                         if (index >= 0 && index < 512)
 253                                 jz_nand_correct_data(dat, index, error & 0x1ff);
 254                 }
 255
 256                 return error_count;
 257         }
 258
 259         return 0;
 260 }
 261
 262 static int jz_nand_ioremap_resource(struct platform_device *pdev,
 263         const char *name, struct resource **res, void __iomem **base)
 264 {
 265         int ret;
 266
 267         *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 268         if (!*res) {
 269                 dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
 270                 ret = -ENXIO;
 271                 goto err;
 272         }
 273
 274         *res = request_mem_region((*res)->start, resource_size(*res),
 275                                 pdev->name);
 276         if (!*res) {
 277                 dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
 278                 ret = -EBUSY;
 279                 goto err;
 280         }
 281
 282         *base = ioremap((*res)->start, resource_size(*res));
 283         if (!*base) {
 284                 dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
 285                 ret = -EBUSY;
 286                 goto err_release_mem;
 287         }
 288
 289         return 0;
 290
 291 err_release_mem:
 292         release_mem_region((*res)->start, resource_size(*res));
 293 err:
 294         *res = NULL;
 295         *base = NULL;
 296         return ret;
 297 }
 298
 299 static inline void jz_nand_iounmap_resource(struct resource *res,
 300                                             void __iomem *base)
 301 {
 302         iounmap(base);
 303         release_mem_region(res->start, resource_size(res));
 304 }
 305
 306 static int jz_nand_detect_bank(struct platform_device *pdev,
 307                                struct jz_nand *nand, unsigned char bank,
 308                                size_t chipnr, uint8_t *nand_maf_id,
 309                                uint8_t *nand_dev_id)
 310 {
 311         int ret;
 312         char res_name[6];
 313         uint32_t ctrl;
 314         struct nand_chip *chip = &nand->chip;
 315         struct mtd_info *mtd = nand_to_mtd(chip);
 316         u8 id[2];
 317
 318         /* Request I/O resource. */
 319         sprintf(res_name, "bank%d", bank);
 320         ret = jz_nand_ioremap_resource(pdev, res_name,
 321                                         &nand->bank_mem[bank - 1],
 322                                         &nand->bank_base[bank - 1]);
 323         if (ret)
 324                 return ret;
 325
 326         /* Enable chip in bank. */
 327         ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
 328         ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
 329         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 330
 331         if (chipnr == 0) {
 332                 /* Detect first chip. */
 333                 ret = nand_scan(chip, 1);
 334                 if (ret)
 335                         goto notfound_id;
 336
 337                 /* Retrieve the IDs from the first chip. */
 338                 nand_select_target(chip, 0);
 339                 nand_reset_op(chip);
 340                 nand_readid_op(chip, 0, id, sizeof(id));
 341                 *nand_maf_id = id[0];
 342                 *nand_dev_id = id[1];
 343         } else {
 344                 /* Detect additional chip. */
 345                 nand_select_target(chip, chipnr);
 346                 nand_reset_op(chip);
 347                 nand_readid_op(chip, 0, id, sizeof(id));
 348                 if (*nand_maf_id != id[0] || *nand_dev_id != id[1]) {
 349                         ret = -ENODEV;
 350                         goto notfound_id;
 351                 }
 352
 353                 /* Update size of the MTD. */
 354                 chip->numchips++;
 355                 mtd->size += chip->chipsize;
 356         }
 357
 358         dev_info(&pdev->dev, "Found chip %zu on bank %i\n", chipnr, bank);
 359         return 0;
 360
 361 notfound_id:
 362         dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
 363         ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
 364         writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
 365         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 366                                  nand->bank_base[bank - 1]);
 367         return ret;
 368 }
 369
 370 static int jz_nand_attach_chip(struct nand_chip *chip)
 371 {
 372         struct mtd_info *mtd = nand_to_mtd(chip);
 373         struct device *dev = mtd->dev.parent;
 374         struct jz_nand_platform_data *pdata = dev_get_platdata(dev);
 375         struct platform_device *pdev = to_platform_device(dev);
 376
 377         if (pdata && pdata->ident_callback)
 378                 pdata->ident_callback(pdev, mtd, &pdata->partitions,
 379                                       &pdata->num_partitions);
 380
 381         return 0;
 382 }
 383
 384 static const struct nand_controller_ops jz_nand_controller_ops = {
 385         .attach_chip = jz_nand_attach_chip,
 386 };
 387
 388 static int jz_nand_probe(struct platform_device *pdev)
 389 {
 390         int ret;
 391         struct jz_nand *nand;
 392         struct nand_chip *chip;
 393         struct mtd_info *mtd;
 394         struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 395         size_t chipnr, bank_idx;
 396         uint8_t nand_maf_id = 0, nand_dev_id = 0;
 397
 398         nand = kzalloc(sizeof(*nand), GFP_KERNEL);
 399         if (!nand)
 400                 return -ENOMEM;
 401
 402         ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
 403         if (ret)
 404                 goto err_free;
 405
 406         nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
 407         if (IS_ERR(nand->busy_gpio)) {
 408                 ret = PTR_ERR(nand->busy_gpio);
 409                 dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
 410                     ret);
 411                 goto err_iounmap_mmio;
 412         }
 413
 414         chip            = &nand->chip;
 415         mtd             = nand_to_mtd(chip);
 416         mtd->dev.parent = &pdev->dev;
 417         mtd->name       = "jz4740-nand";
 418
 419         chip->ecc.hwctl         = jz_nand_hwctl;
 420         chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
 421         chip->ecc.correct       = jz_nand_correct_ecc_rs;
 422         chip->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
 423         chip->ecc.size          = 512;
 424         chip->ecc.bytes         = 9;
 425         chip->ecc.strength      = 4;
 426         chip->ecc.options       = NAND_ECC_GENERIC_ERASED_CHECK;
 427
 428         chip->legacy.chip_delay = 50;
 429         chip->legacy.cmd_ctrl = jz_nand_cmd_ctrl;
 430         chip->legacy.select_chip = jz_nand_select_chip;
 431         chip->legacy.dummy_controller.ops = &jz_nand_controller_ops;
 432
 433         if (nand->busy_gpio)
 434                 chip->legacy.dev_ready = jz_nand_dev_ready;
 435
 436         platform_set_drvdata(pdev, nand);
 437
 438         /* We are going to autodetect NAND chips in the banks specified in the
 439          * platform data. Although nand_scan_ident() can detect multiple chips,
 440          * it requires those chips to be numbered consecuitively, which is not
 441          * always the case for external memory banks. And a fixed chip-to-bank
 442          * mapping is not practical either, since for example Dingoo units
 443          * produced at different times have NAND chips in different banks.
 444          */
 445         chipnr = 0;
 446         for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
 447                 unsigned char bank;
 448
 449                 /* If there is no platform data, look for NAND in bank 1,
 450                  * which is the most likely bank since it is the only one
 451                  * that can be booted from.
 452                  */
 453                 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
 454                 if (bank == 0)
 455                         break;
 456                 if (bank > JZ_NAND_NUM_BANKS) {
 457                         dev_warn(&pdev->dev,
 458                                 "Skipping non-existing bank: %d\n", bank);
 459                         continue;
 460                 }
 461                 /* The detection routine will directly or indirectly call
 462                  * jz_nand_select_chip(), so nand->banks has to contain the
 463                  * bank we're checking.
 464                  */
 465                 nand->banks[chipnr] = bank;
 466                 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
 467                                         &nand_maf_id, &nand_dev_id) == 0)
 468                         chipnr++;
 469                 else
 470                         nand->banks[chipnr] = 0;
 471         }
 472         if (chipnr == 0) {
 473                 dev_err(&pdev->dev, "No NAND chips found\n");
 474                 goto err_iounmap_mmio;
 475         }
 476
 477         ret = mtd_device_register(mtd, pdata ? pdata->partitions : NULL,
 478                                   pdata ? pdata->num_partitions : 0);
 479
 480         if (ret) {
 481                 dev_err(&pdev->dev, "Failed to add mtd device\n");
 482                 goto err_cleanup_nand;
 483         }
 484
 485         dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
 486
 487         return 0;
 488
 489 err_cleanup_nand:
 490         nand_cleanup(chip);
 491         while (chipnr--) {
 492                 unsigned char bank = nand->banks[chipnr];
 493                 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 494                                          nand->bank_base[bank - 1]);
 495         }
 496         writel(0, nand->base + JZ_REG_NAND_CTRL);
 497 err_iounmap_mmio:
 498         jz_nand_iounmap_resource(nand->mem, nand->base);
 499 err_free:
 500         kfree(nand);
 501         return ret;
 502 }
 503
 504 static int jz_nand_remove(struct platform_device *pdev)
 505 {
 506         struct jz_nand *nand = platform_get_drvdata(pdev);
 507         size_t i;
 508
 509         nand_release(&nand->chip);
 510
 511         /* Deassert and disable all chips */
 512         writel(0, nand->base + JZ_REG_NAND_CTRL);
 513
 514         for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
 515                 unsigned char bank = nand->banks[i];
 516                 if (bank != 0) {
 517                         jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
 518                                                  nand->bank_base[bank - 1]);
 519                 }
 520         }
 521
 522         jz_nand_iounmap_resource(nand->mem, nand->base);
 523
 524         kfree(nand);
 525
 526         return 0;
 527 }
 528
 529 static struct platform_driver jz_nand_driver = {
 530         .probe = jz_nand_probe,
 531         .remove = jz_nand_remove,
 532         .driver = {
 533                 .name = "jz4740-nand",
 534         },
 535 };
 536
 537 module_platform_driver(jz_nand_driver);
 538
 539 MODULE_LICENSE("GPL");
 540 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 541 MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
 542 MODULE_ALIAS("platform:jz4740-nand");