drivers/mtd/nand/raw/fsmc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ST Microelectronics
   4  * Flexible Static Memory Controller (FSMC)
   5  * Driver for NAND portions
   6  *
   7  * Copyright © 2010 ST Microelectronics
   8  * Vipin Kumar <vipin.kumar@st.com>
   9  * Ashish Priyadarshi
  10  *
  11  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
  12  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
  13  *  Copyright © 2009 Alessandro Rubini
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/completion.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/dma-direction.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/resource.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/nand-ecc-sw-hamming.h>
  29 #include <linux/mtd/rawnand.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/of.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35 #include <linux/amba/bus.h>
  36 #include <mtd/mtd-abi.h>
  37
  38 /* fsmc controller registers for NOR flash */
  39 #define CTRL                    0x0
  40         /* ctrl register definitions */
  41         #define BANK_ENABLE             BIT(0)
  42         #define MUXED                   BIT(1)
  43         #define NOR_DEV                 (2 << 2)
  44         #define WIDTH_16                BIT(4)
  45         #define RSTPWRDWN               BIT(6)
  46         #define WPROT                   BIT(7)
  47         #define WRT_ENABLE              BIT(12)
  48         #define WAIT_ENB                BIT(13)
  49
  50 #define CTRL_TIM                0x4
  51         /* ctrl_tim register definitions */
  52
  53 #define FSMC_NOR_BANK_SZ        0x8
  54 #define FSMC_NOR_REG_SIZE       0x40
  55
  56 #define FSMC_NOR_REG(base, bank, reg)   ((base) +                       \
  57                                          (FSMC_NOR_BANK_SZ * (bank)) +  \
  58                                          (reg))
  59
  60 /* fsmc controller registers for NAND flash */
  61 #define FSMC_PC                 0x00
  62         /* pc register definitions */
  63         #define FSMC_RESET              BIT(0)
  64         #define FSMC_WAITON             BIT(1)
  65         #define FSMC_ENABLE             BIT(2)
  66         #define FSMC_DEVTYPE_NAND       BIT(3)
  67         #define FSMC_DEVWID_16          BIT(4)
  68         #define FSMC_ECCEN              BIT(6)
  69         #define FSMC_ECCPLEN_256        BIT(7)
  70         #define FSMC_TCLR_SHIFT         (9)
  71         #define FSMC_TCLR_MASK          (0xF)
  72         #define FSMC_TAR_SHIFT          (13)
  73         #define FSMC_TAR_MASK           (0xF)
  74 #define STS                     0x04
  75         /* sts register definitions */
  76         #define FSMC_CODE_RDY           BIT(15)
  77 #define COMM                    0x08
  78         /* comm register definitions */
  79         #define FSMC_TSET_SHIFT         0
  80         #define FSMC_TSET_MASK          0xFF
  81         #define FSMC_TWAIT_SHIFT        8
  82         #define FSMC_TWAIT_MASK         0xFF
  83         #define FSMC_THOLD_SHIFT        16
  84         #define FSMC_THOLD_MASK         0xFF
  85         #define FSMC_THIZ_SHIFT         24
  86         #define FSMC_THIZ_MASK          0xFF
  87 #define ATTRIB                  0x0C
  88 #define IOATA                   0x10
  89 #define ECC1                    0x14
  90 #define ECC2                    0x18
  91 #define ECC3                    0x1C
  92 #define FSMC_NAND_BANK_SZ       0x20
  93
  94 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
  95
  96 struct fsmc_nand_timings {
  97         u8 tclr;
  98         u8 tar;
  99         u8 thiz;
 100         u8 thold;
 101         u8 twait;
 102         u8 tset;
 103 };
 104
 105 enum access_mode {
 106         USE_DMA_ACCESS = 1,
 107         USE_WORD_ACCESS,
 108 };
 109
 110 /**
 111  * struct fsmc_nand_data - structure for FSMC NAND device state
 112  *
 113  * @base:               Inherit from the nand_controller struct
 114  * @pid:                Part ID on the AMBA PrimeCell format
 115  * @nand:               Chip related info for a NAND flash.
 116  *
 117  * @bank:               Bank number for probed device.
 118  * @dev:                Parent device
 119  * @mode:               Access mode
 120  * @clk:                Clock structure for FSMC.
 121  *
 122  * @read_dma_chan:      DMA channel for read access
 123  * @write_dma_chan:     DMA channel for write access to NAND
 124  * @dma_access_complete: Completion structure
 125  *
 126  * @dev_timings:        NAND timings
 127  *
 128  * @data_pa:            NAND Physical port for Data.
 129  * @data_va:            NAND port for Data.
 130  * @cmd_va:             NAND port for Command.
 131  * @addr_va:            NAND port for Address.
 132  * @regs_va:            Registers base address for a given bank.
 133  */
 134 struct fsmc_nand_data {
 135         struct nand_controller  base;
 136         u32                     pid;
 137         struct nand_chip        nand;
 138
 139         unsigned int            bank;
 140         struct device           *dev;
 141         enum access_mode        mode;
 142         struct clk              *clk;
 143
 144         /* DMA related objects */
 145         struct dma_chan         *read_dma_chan;
 146         struct dma_chan         *write_dma_chan;
 147         struct completion       dma_access_complete;
 148
 149         struct fsmc_nand_timings *dev_timings;
 150
 151         dma_addr_t              data_pa;
 152         void __iomem            *data_va;
 153         void __iomem            *cmd_va;
 154         void __iomem            *addr_va;
 155         void __iomem            *regs_va;
 156 };
 157
 158 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 159                                    struct mtd_oob_region *oobregion)
 160 {
 161         struct nand_chip *chip = mtd_to_nand(mtd);
 162
 163         if (section >= chip->ecc.steps)
 164                 return -ERANGE;
 165
 166         oobregion->offset = (section * 16) + 2;
 167         oobregion->length = 3;
 168
 169         return 0;
 170 }
 171
 172 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 173                                     struct mtd_oob_region *oobregion)
 174 {
 175         struct nand_chip *chip = mtd_to_nand(mtd);
 176
 177         if (section >= chip->ecc.steps)
 178                 return -ERANGE;
 179
 180         oobregion->offset = (section * 16) + 8;
 181
 182         if (section < chip->ecc.steps - 1)
 183                 oobregion->length = 8;
 184         else
 185                 oobregion->length = mtd->oobsize - oobregion->offset;
 186
 187         return 0;
 188 }
 189
 190 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 191         .ecc = fsmc_ecc1_ooblayout_ecc,
 192         .free = fsmc_ecc1_ooblayout_free,
 193 };
 194
 195 /*
 196  * ECC placement definitions in oobfree type format.
 197  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 198  * consecutively and immediately after the 512 byte data block for hardware to
 199  * generate the error bit offsets in 512 byte data.
 200  */
 201 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 202                                    struct mtd_oob_region *oobregion)
 203 {
 204         struct nand_chip *chip = mtd_to_nand(mtd);
 205
 206         if (section >= chip->ecc.steps)
 207                 return -ERANGE;
 208
 209         oobregion->length = chip->ecc.bytes;
 210
 211         if (!section && mtd->writesize <= 512)
 212                 oobregion->offset = 0;
 213         else
 214                 oobregion->offset = (section * 16) + 2;
 215
 216         return 0;
 217 }
 218
 219 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 220                                     struct mtd_oob_region *oobregion)
 221 {
 222         struct nand_chip *chip = mtd_to_nand(mtd);
 223
 224         if (section >= chip->ecc.steps)
 225                 return -ERANGE;
 226
 227         oobregion->offset = (section * 16) + 15;
 228
 229         if (section < chip->ecc.steps - 1)
 230                 oobregion->length = 3;
 231         else
 232                 oobregion->length = mtd->oobsize - oobregion->offset;
 233
 234         return 0;
 235 }
 236
 237 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 238         .ecc = fsmc_ecc4_ooblayout_ecc,
 239         .free = fsmc_ecc4_ooblayout_free,
 240 };
 241
 242 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
 243 {
 244         return container_of(chip, struct fsmc_nand_data, nand);
 245 }
 246
 247 /*
 248  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 249  *
 250  * This routine initializes timing parameters related to NAND memory access in
 251  * FSMC registers
 252  */
 253 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 254                             struct fsmc_nand_timings *tims)
 255 {
 256         u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 257         u32 tclr, tar, thiz, thold, twait, tset;
 258
 259         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 260         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 261         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 262         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 263         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 264         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 265
 266         if (host->nand.options & NAND_BUSWIDTH_16)
 267                 value |= FSMC_DEVWID_16;
 268
 269         writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
 270         writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
 271         writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
 272 }
 273
 274 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 275                              const struct nand_sdr_timings *sdrt,
 276                              struct fsmc_nand_timings *tims)
 277 {
 278         unsigned long hclk = clk_get_rate(host->clk);
 279         unsigned long hclkn = NSEC_PER_SEC / hclk;
 280         u32 thiz, thold, twait, tset;
 281
 282         if (sdrt->tRC_min < 30000)
 283                 return -EOPNOTSUPP;
 284
 285         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 286         if (tims->tar > FSMC_TAR_MASK)
 287                 tims->tar = FSMC_TAR_MASK;
 288         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 289         if (tims->tclr > FSMC_TCLR_MASK)
 290                 tims->tclr = FSMC_TCLR_MASK;
 291
 292         thiz = sdrt->tCS_min - sdrt->tWP_min;
 293         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 294
 295         thold = sdrt->tDH_min;
 296         if (thold < sdrt->tCH_min)
 297                 thold = sdrt->tCH_min;
 298         if (thold < sdrt->tCLH_min)
 299                 thold = sdrt->tCLH_min;
 300         if (thold < sdrt->tWH_min)
 301                 thold = sdrt->tWH_min;
 302         if (thold < sdrt->tALH_min)
 303                 thold = sdrt->tALH_min;
 304         if (thold < sdrt->tREH_min)
 305                 thold = sdrt->tREH_min;
 306         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 307         if (tims->thold == 0)
 308                 tims->thold = 1;
 309         else if (tims->thold > FSMC_THOLD_MASK)
 310                 tims->thold = FSMC_THOLD_MASK;
 311
 312         twait = max(sdrt->tRP_min, sdrt->tWP_min);
 313         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 314         if (tims->twait == 0)
 315                 tims->twait = 1;
 316         else if (tims->twait > FSMC_TWAIT_MASK)
 317                 tims->twait = FSMC_TWAIT_MASK;
 318
 319         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 320                    sdrt->tCEA_max - sdrt->tREA_max);
 321         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 322         if (tims->tset == 0)
 323                 tims->tset = 1;
 324         else if (tims->tset > FSMC_TSET_MASK)
 325                 tims->tset = FSMC_TSET_MASK;
 326
 327         return 0;
 328 }
 329
 330 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
 331                                 const struct nand_interface_config *conf)
 332 {
 333         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 334         struct fsmc_nand_timings tims;
 335         const struct nand_sdr_timings *sdrt;
 336         int ret;
 337
 338         sdrt = nand_get_sdr_timings(conf);
 339         if (IS_ERR(sdrt))
 340                 return PTR_ERR(sdrt);
 341
 342         ret = fsmc_calc_timings(host, sdrt, &tims);
 343         if (ret)
 344                 return ret;
 345
 346         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
 347                 return 0;
 348
 349         fsmc_nand_setup(host, &tims);
 350
 351         return 0;
 352 }
 353
 354 /*
 355  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 356  */
 357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
 358 {
 359         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 360
 361         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
 362                        host->regs_va + FSMC_PC);
 363         writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
 364                        host->regs_va + FSMC_PC);
 365         writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
 366                        host->regs_va + FSMC_PC);
 367 }
 368
 369 /*
 370  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 371  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 372  * max of 8-bits)
 373  */
 374 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
 375                                 u8 *ecc)
 376 {
 377         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 378         u32 ecc_tmp;
 379         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 380
 381         do {
 382                 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
 383                         break;
 384
 385                 cond_resched();
 386         } while (!time_after_eq(jiffies, deadline));
 387
 388         if (time_after_eq(jiffies, deadline)) {
 389                 dev_err(host->dev, "calculate ecc timed out\n");
 390                 return -ETIMEDOUT;
 391         }
 392
 393         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 394         ecc[0] = ecc_tmp;
 395         ecc[1] = ecc_tmp >> 8;
 396         ecc[2] = ecc_tmp >> 16;
 397         ecc[3] = ecc_tmp >> 24;
 398
 399         ecc_tmp = readl_relaxed(host->regs_va + ECC2);
 400         ecc[4] = ecc_tmp;
 401         ecc[5] = ecc_tmp >> 8;
 402         ecc[6] = ecc_tmp >> 16;
 403         ecc[7] = ecc_tmp >> 24;
 404
 405         ecc_tmp = readl_relaxed(host->regs_va + ECC3);
 406         ecc[8] = ecc_tmp;
 407         ecc[9] = ecc_tmp >> 8;
 408         ecc[10] = ecc_tmp >> 16;
 409         ecc[11] = ecc_tmp >> 24;
 410
 411         ecc_tmp = readl_relaxed(host->regs_va + STS);
 412         ecc[12] = ecc_tmp >> 16;
 413
 414         return 0;
 415 }
 416
 417 /*
 418  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 419  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 420  * max of 1-bit)
 421  */
 422 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
 423                                 u8 *ecc)
 424 {
 425         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 426         u32 ecc_tmp;
 427
 428         ecc_tmp = readl_relaxed(host->regs_va + ECC1);
 429         ecc[0] = ecc_tmp;
 430         ecc[1] = ecc_tmp >> 8;
 431         ecc[2] = ecc_tmp >> 16;
 432
 433         return 0;
 434 }
 435
 436 static int fsmc_correct_ecc1(struct nand_chip *chip,
 437                              unsigned char *buf,
 438                              unsigned char *read_ecc,
 439                              unsigned char *calc_ecc)
 440 {
 441         return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
 442                                       chip->ecc.size, false);
 443 }
 444
 445 /* Count the number of 0's in buff upto a max of max_bits */
 446 static int count_written_bits(u8 *buff, int size, int max_bits)
 447 {
 448         int k, written_bits = 0;
 449
 450         for (k = 0; k < size; k++) {
 451                 written_bits += hweight8(~buff[k]);
 452                 if (written_bits > max_bits)
 453                         break;
 454         }
 455
 456         return written_bits;
 457 }
 458
 459 static void dma_complete(void *param)
 460 {
 461         struct fsmc_nand_data *host = param;
 462
 463         complete(&host->dma_access_complete);
 464 }
 465
 466 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 467                     enum dma_data_direction direction)
 468 {
 469         struct dma_chan *chan;
 470         struct dma_device *dma_dev;
 471         struct dma_async_tx_descriptor *tx;
 472         dma_addr_t dma_dst, dma_src, dma_addr;
 473         dma_cookie_t cookie;
 474         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 475         int ret;
 476         unsigned long time_left;
 477
 478         if (direction == DMA_TO_DEVICE)
 479                 chan = host->write_dma_chan;
 480         else if (direction == DMA_FROM_DEVICE)
 481                 chan = host->read_dma_chan;
 482         else
 483                 return -EINVAL;
 484
 485         dma_dev = chan->device;
 486         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 487
 488         if (direction == DMA_TO_DEVICE) {
 489                 dma_src = dma_addr;
 490                 dma_dst = host->data_pa;
 491         } else {
 492                 dma_src = host->data_pa;
 493                 dma_dst = dma_addr;
 494         }
 495
 496         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 497                         len, flags);
 498         if (!tx) {
 499                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 500                 ret = -EIO;
 501                 goto unmap_dma;
 502         }
 503
 504         tx->callback = dma_complete;
 505         tx->callback_param = host;
 506         cookie = tx->tx_submit(tx);
 507
 508         ret = dma_submit_error(cookie);
 509         if (ret) {
 510                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 511                 goto unmap_dma;
 512         }
 513
 514         dma_async_issue_pending(chan);
 515
 516         time_left =
 517         wait_for_completion_timeout(&host->dma_access_complete,
 518                                     msecs_to_jiffies(3000));
 519         if (time_left == 0) {
 520                 dmaengine_terminate_all(chan);
 521                 dev_err(host->dev, "wait_for_completion_timeout\n");
 522                 ret = -ETIMEDOUT;
 523                 goto unmap_dma;
 524         }
 525
 526         ret = 0;
 527
 528 unmap_dma:
 529         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 530
 531         return ret;
 532 }
 533
 534 /*
 535  * fsmc_write_buf - write buffer to chip
 536  * @host:       FSMC NAND controller
 537  * @buf:        data buffer
 538  * @len:        number of bytes to write
 539  */
 540 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
 541                            int len)
 542 {
 543         int i;
 544
 545         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 546             IS_ALIGNED(len, sizeof(u32))) {
 547                 u32 *p = (u32 *)buf;
 548
 549                 len = len >> 2;
 550                 for (i = 0; i < len; i++)
 551                         writel_relaxed(p[i], host->data_va);
 552         } else {
 553                 for (i = 0; i < len; i++)
 554                         writeb_relaxed(buf[i], host->data_va);
 555         }
 556 }
 557
 558 /*
 559  * fsmc_read_buf - read chip data into buffer
 560  * @host:       FSMC NAND controller
 561  * @buf:        buffer to store date
 562  * @len:        number of bytes to read
 563  */
 564 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
 565 {
 566         int i;
 567
 568         if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
 569             IS_ALIGNED(len, sizeof(u32))) {
 570                 u32 *p = (u32 *)buf;
 571
 572                 len = len >> 2;
 573                 for (i = 0; i < len; i++)
 574                         p[i] = readl_relaxed(host->data_va);
 575         } else {
 576                 for (i = 0; i < len; i++)
 577                         buf[i] = readb_relaxed(host->data_va);
 578         }
 579 }
 580
 581 /*
 582  * fsmc_read_buf_dma - read chip data into buffer
 583  * @host:       FSMC NAND controller
 584  * @buf:        buffer to store date
 585  * @len:        number of bytes to read
 586  */
 587 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
 588                               int len)
 589 {
 590         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 591 }
 592
 593 /*
 594  * fsmc_write_buf_dma - write buffer to chip
 595  * @host:       FSMC NAND controller
 596  * @buf:        data buffer
 597  * @len:        number of bytes to write
 598  */
 599 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
 600                                int len)
 601 {
 602         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 603 }
 604
 605 /*
 606  * fsmc_exec_op - hook called by the core to execute NAND operations
 607  *
 608  * This controller is simple enough and thus does not need to use the parser
 609  * provided by the core, instead, handle every situation here.
 610  */
 611 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
 612                         bool check_only)
 613 {
 614         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 615         const struct nand_op_instr *instr = NULL;
 616         int ret = 0;
 617         unsigned int op_id;
 618         int i;
 619
 620         if (check_only)
 621                 return 0;
 622
 623         pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
 624
 625         for (op_id = 0; op_id < op->ninstrs; op_id++) {
 626                 instr = &op->instrs[op_id];
 627
 628                 nand_op_trace("  ", instr);
 629
 630                 switch (instr->type) {
 631                 case NAND_OP_CMD_INSTR:
 632                         writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
 633                         break;
 634
 635                 case NAND_OP_ADDR_INSTR:
 636                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
 637                                 writeb_relaxed(instr->ctx.addr.addrs[i],
 638                                                host->addr_va);
 639                         break;
 640
 641                 case NAND_OP_DATA_IN_INSTR:
 642                         if (host->mode == USE_DMA_ACCESS)
 643                                 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
 644                                                   instr->ctx.data.len);
 645                         else
 646                                 fsmc_read_buf(host, instr->ctx.data.buf.in,
 647                                               instr->ctx.data.len);
 648                         break;
 649
 650                 case NAND_OP_DATA_OUT_INSTR:
 651                         if (host->mode == USE_DMA_ACCESS)
 652                                 fsmc_write_buf_dma(host,
 653                                                    instr->ctx.data.buf.out,
 654                                                    instr->ctx.data.len);
 655                         else
 656                                 fsmc_write_buf(host, instr->ctx.data.buf.out,
 657                                                instr->ctx.data.len);
 658                         break;
 659
 660                 case NAND_OP_WAITRDY_INSTR:
 661                         ret = nand_soft_waitrdy(chip,
 662                                                 instr->ctx.waitrdy.timeout_ms);
 663                         break;
 664                 }
 665         }
 666
 667         return ret;
 668 }
 669
 670 /*
 671  * fsmc_read_page_hwecc
 672  * @chip:       nand chip info structure
 673  * @buf:        buffer to store read data
 674  * @oob_required:       caller expects OOB data read to chip->oob_poi
 675  * @page:       page number to read
 676  *
 677  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 678  * performed in a strict sequence as follows:
 679  * data(512 byte) -> ecc(13 byte)
 680  * After this read, fsmc hardware generates and reports error data bits(up to a
 681  * max of 8 bits)
 682  */
 683 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
 684                                 int oob_required, int page)
 685 {
 686         struct mtd_info *mtd = nand_to_mtd(chip);
 687         int i, j, s, stat, eccsize = chip->ecc.size;
 688         int eccbytes = chip->ecc.bytes;
 689         int eccsteps = chip->ecc.steps;
 690         u8 *p = buf;
 691         u8 *ecc_calc = chip->ecc.calc_buf;
 692         u8 *ecc_code = chip->ecc.code_buf;
 693         int off, len, ret, group = 0;
 694         /*
 695          * ecc_oob is intentionally taken as u16. In 16bit devices, we
 696          * end up reading 14 bytes (7 words) from oob. The local array is
 697          * to maintain word alignment
 698          */
 699         u16 ecc_oob[7];
 700         u8 *oob = (u8 *)&ecc_oob[0];
 701         unsigned int max_bitflips = 0;
 702
 703         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 704                 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
 705                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 706                 ret = nand_read_data_op(chip, p, eccsize, false, false);
 707                 if (ret)
 708                         return ret;
 709
 710                 for (j = 0; j < eccbytes;) {
 711                         struct mtd_oob_region oobregion;
 712
 713                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 714                         if (ret)
 715                                 return ret;
 716
 717                         off = oobregion.offset;
 718                         len = oobregion.length;
 719
 720                         /*
 721                          * length is intentionally kept a higher multiple of 2
 722                          * to read at least 13 bytes even in case of 16 bit NAND
 723                          * devices
 724                          */
 725                         if (chip->options & NAND_BUSWIDTH_16)
 726                                 len = roundup(len, 2);
 727
 728                         nand_read_oob_op(chip, page, off, oob + j, len);
 729                         j += len;
 730                 }
 731
 732                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 733                 chip->ecc.calculate(chip, p, &ecc_calc[i]);
 734
 735                 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
 736                 if (stat < 0) {
 737                         mtd->ecc_stats.failed++;
 738                 } else {
 739                         mtd->ecc_stats.corrected += stat;
 740                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 741                 }
 742         }
 743
 744         return max_bitflips;
 745 }
 746
 747 /*
 748  * fsmc_bch8_correct_data
 749  * @mtd:        mtd info structure
 750  * @dat:        buffer of read data
 751  * @read_ecc:   ecc read from device spare area
 752  * @calc_ecc:   ecc calculated from read data
 753  *
 754  * calc_ecc is a 104 bit information containing maximum of 8 error
 755  * offset information of 13 bits each in 512 bytes of read data.
 756  */
 757 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
 758                                   u8 *read_ecc, u8 *calc_ecc)
 759 {
 760         struct fsmc_nand_data *host = nand_to_fsmc(chip);
 761         u32 err_idx[8];
 762         u32 num_err, i;
 763         u32 ecc1, ecc2, ecc3, ecc4;
 764
 765         num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
 766
 767         /* no bit flipping */
 768         if (likely(num_err == 0))
 769                 return 0;
 770
 771         /* too many errors */
 772         if (unlikely(num_err > 8)) {
 773                 /*
 774                  * This is a temporary erase check. A newly erased page read
 775                  * would result in an ecc error because the oob data is also
 776                  * erased to FF and the calculated ecc for an FF data is not
 777                  * FF..FF.
 778                  * This is a workaround to skip performing correction in case
 779                  * data is FF..FF
 780                  *
 781                  * Logic:
 782                  * For every page, each bit written as 0 is counted until these
 783                  * number of bits are greater than 8 (the maximum correction
 784                  * capability of FSMC for each 512 + 13 bytes)
 785                  */
 786
 787                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 788                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 789
 790                 if ((bits_ecc + bits_data) <= 8) {
 791                         if (bits_data)
 792                                 memset(dat, 0xff, chip->ecc.size);
 793                         return bits_data;
 794                 }
 795
 796                 return -EBADMSG;
 797         }
 798
 799         /*
 800          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 801          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 802          *
 803          * calc_ecc is a 104 bit information containing maximum of 8 error
 804          * offset information of 13 bits each. calc_ecc is copied into a
 805          * u64 array and error offset indexes are populated in err_idx
 806          * array
 807          */
 808         ecc1 = readl_relaxed(host->regs_va + ECC1);
 809         ecc2 = readl_relaxed(host->regs_va + ECC2);
 810         ecc3 = readl_relaxed(host->regs_va + ECC3);
 811         ecc4 = readl_relaxed(host->regs_va + STS);
 812
 813         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 814         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 815         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 816         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 817         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 818         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 819         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 820         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 821
 822         i = 0;
 823         while (num_err--) {
 824                 err_idx[i] ^= 3;
 825
 826                 if (err_idx[i] < chip->ecc.size * 8) {
 827                         int err = err_idx[i];
 828
 829                         dat[err >> 3] ^= BIT(err & 7);
 830                         i++;
 831                 }
 832         }
 833         return i;
 834 }
 835
 836 static bool filter(struct dma_chan *chan, void *slave)
 837 {
 838         chan->private = slave;
 839         return true;
 840 }
 841
 842 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 843                                      struct fsmc_nand_data *host,
 844                                      struct nand_chip *nand)
 845 {
 846         struct device_node *np = pdev->dev.of_node;
 847         u32 val;
 848         int ret;
 849
 850         nand->options = 0;
 851
 852         if (!of_property_read_u32(np, "bank-width", &val)) {
 853                 if (val == 2) {
 854                         nand->options |= NAND_BUSWIDTH_16;
 855                 } else if (val != 1) {
 856                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 857                         return -EINVAL;
 858                 }
 859         }
 860
 861         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 862                 nand->options |= NAND_SKIP_BBTSCAN;
 863
 864         host->dev_timings = devm_kzalloc(&pdev->dev,
 865                                          sizeof(*host->dev_timings),
 866                                          GFP_KERNEL);
 867         if (!host->dev_timings)
 868                 return -ENOMEM;
 869
 870         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 871                                         sizeof(*host->dev_timings));
 872         if (ret)
 873                 host->dev_timings = NULL;
 874
 875         /* Set default NAND bank to 0 */
 876         host->bank = 0;
 877         if (!of_property_read_u32(np, "bank", &val)) {
 878                 if (val > 3) {
 879                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 880                         return -EINVAL;
 881                 }
 882                 host->bank = val;
 883         }
 884         return 0;
 885 }
 886
 887 static int fsmc_nand_attach_chip(struct nand_chip *nand)
 888 {
 889         struct mtd_info *mtd = nand_to_mtd(nand);
 890         struct fsmc_nand_data *host = nand_to_fsmc(nand);
 891
 892         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
 893                 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
 894
 895         if (!nand->ecc.size)
 896                 nand->ecc.size = 512;
 897
 898         if (AMBA_REV_BITS(host->pid) >= 8) {
 899                 nand->ecc.read_page = fsmc_read_page_hwecc;
 900                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 901                 nand->ecc.correct = fsmc_bch8_correct_data;
 902                 nand->ecc.bytes = 13;
 903                 nand->ecc.strength = 8;
 904         }
 905
 906         if (AMBA_REV_BITS(host->pid) >= 8) {
 907                 switch (mtd->oobsize) {
 908                 case 16:
 909                 case 64:
 910                 case 128:
 911                 case 224:
 912                 case 256:
 913                         break;
 914                 default:
 915                         dev_warn(host->dev,
 916                                  "No oob scheme defined for oobsize %d\n",
 917                                  mtd->oobsize);
 918                         return -EINVAL;
 919                 }
 920
 921                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 922
 923                 return 0;
 924         }
 925
 926         switch (nand->ecc.engine_type) {
 927         case NAND_ECC_ENGINE_TYPE_ON_HOST:
 928                 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
 929                 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 930                 nand->ecc.correct = fsmc_correct_ecc1;
 931                 nand->ecc.hwctl = fsmc_enable_hwecc;
 932                 nand->ecc.bytes = 3;
 933                 nand->ecc.strength = 1;
 934                 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
 935                 break;
 936
 937         case NAND_ECC_ENGINE_TYPE_SOFT:
 938                 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
 939                         dev_info(host->dev,
 940                                  "Using 4-bit SW BCH ECC scheme\n");
 941                         break;
 942                 }
 943                 break;
 944
 945         case NAND_ECC_ENGINE_TYPE_ON_DIE:
 946                 break;
 947
 948         default:
 949                 dev_err(host->dev, "Unsupported ECC mode!\n");
 950                 return -ENOTSUPP;
 951         }
 952
 953         /*
 954          * Don't set layout for BCH4 SW ECC. This will be
 955          * generated later during BCH initialization.
 956          */
 957         if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
 958                 switch (mtd->oobsize) {
 959                 case 16:
 960                 case 64:
 961                 case 128:
 962                         mtd_set_ooblayout(mtd,
 963                                           &fsmc_ecc1_ooblayout_ops);
 964                         break;
 965                 default:
 966                         dev_warn(host->dev,
 967                                  "No oob scheme defined for oobsize %d\n",
 968                                  mtd->oobsize);
 969                         return -EINVAL;
 970                 }
 971         }
 972
 973         return 0;
 974 }
 975
 976 static const struct nand_controller_ops fsmc_nand_controller_ops = {
 977         .attach_chip = fsmc_nand_attach_chip,
 978         .exec_op = fsmc_exec_op,
 979         .setup_interface = fsmc_setup_interface,
 980 };
 981
 982 /**
 983  * fsmc_nand_disable() - Disables the NAND bank
 984  * @host: The instance to disable
 985  */
 986 static void fsmc_nand_disable(struct fsmc_nand_data *host)
 987 {
 988         u32 val;
 989
 990         val = readl(host->regs_va + FSMC_PC);
 991         val &= ~FSMC_ENABLE;
 992         writel(val, host->regs_va + FSMC_PC);
 993 }
 994
 995 /*
 996  * fsmc_nand_probe - Probe function
 997  * @pdev:       platform device structure
 998  */
 999 static int __init fsmc_nand_probe(struct platform_device *pdev)
1000 {
1001         struct fsmc_nand_data *host;
1002         struct mtd_info *mtd;
1003         struct nand_chip *nand;
1004         struct resource *res;
1005         void __iomem *base;
1006         dma_cap_mask_t mask;
1007         int ret = 0;
1008         u32 pid;
1009         int i;
1010
1011         /* Allocate memory for the device structure (and zero it) */
1012         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1013         if (!host)
1014                 return -ENOMEM;
1015
1016         nand = &host->nand;
1017
1018         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1019         if (ret)
1020                 return ret;
1021
1022         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1023         host->data_va = devm_ioremap_resource(&pdev->dev, res);
1024         if (IS_ERR(host->data_va))
1025                 return PTR_ERR(host->data_va);
1026
1027         host->data_pa = (dma_addr_t)res->start;
1028
1029         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1030         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1031         if (IS_ERR(host->addr_va))
1032                 return PTR_ERR(host->addr_va);
1033
1034         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1035         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1036         if (IS_ERR(host->cmd_va))
1037                 return PTR_ERR(host->cmd_va);
1038
1039         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1040         base = devm_ioremap_resource(&pdev->dev, res);
1041         if (IS_ERR(base))
1042                 return PTR_ERR(base);
1043
1044         host->regs_va = base + FSMC_NOR_REG_SIZE +
1045                 (host->bank * FSMC_NAND_BANK_SZ);
1046
1047         host->clk = devm_clk_get(&pdev->dev, NULL);
1048         if (IS_ERR(host->clk)) {
1049                 dev_err(&pdev->dev, "failed to fetch block clock\n");
1050                 return PTR_ERR(host->clk);
1051         }
1052
1053         ret = clk_prepare_enable(host->clk);
1054         if (ret)
1055                 return ret;
1056
1057         /*
1058          * This device ID is actually a common AMBA ID as used on the
1059          * AMBA PrimeCell bus. However it is not a PrimeCell.
1060          */
1061         for (pid = 0, i = 0; i < 4; i++)
1062                 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1063                         255) << (i * 8);
1064
1065         host->pid = pid;
1066
1067         dev_info(&pdev->dev,
1068                  "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1069                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1070                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1071
1072         host->dev = &pdev->dev;
1073
1074         if (host->mode == USE_DMA_ACCESS)
1075                 init_completion(&host->dma_access_complete);
1076
1077         /* Link all private pointers */
1078         mtd = nand_to_mtd(&host->nand);
1079         nand_set_flash_node(nand, pdev->dev.of_node);
1080
1081         mtd->dev.parent = &pdev->dev;
1082
1083         nand->badblockbits = 7;
1084
1085         if (host->mode == USE_DMA_ACCESS) {
1086                 dma_cap_zero(mask);
1087                 dma_cap_set(DMA_MEMCPY, mask);
1088                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1089                 if (!host->read_dma_chan) {
1090                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1091                         ret = -ENODEV;
1092                         goto disable_clk;
1093                 }
1094                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1095                 if (!host->write_dma_chan) {
1096                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1097                         ret = -ENODEV;
1098                         goto release_dma_read_chan;
1099                 }
1100         }
1101
1102         if (host->dev_timings) {
1103                 fsmc_nand_setup(host, host->dev_timings);
1104                 nand->options |= NAND_KEEP_TIMINGS;
1105         }
1106
1107         nand_controller_init(&host->base);
1108         host->base.ops = &fsmc_nand_controller_ops;
1109         nand->controller = &host->base;
1110
1111         /*
1112          * Scan to find existence of the device
1113          */
1114         ret = nand_scan(nand, 1);
1115         if (ret)
1116                 goto release_dma_write_chan;
1117
1118         mtd->name = "nand";
1119         ret = mtd_device_register(mtd, NULL, 0);
1120         if (ret)
1121                 goto cleanup_nand;
1122
1123         platform_set_drvdata(pdev, host);
1124         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1125
1126         return 0;
1127
1128 cleanup_nand:
1129         nand_cleanup(nand);
1130 release_dma_write_chan:
1131         if (host->mode == USE_DMA_ACCESS)
1132                 dma_release_channel(host->write_dma_chan);
1133 release_dma_read_chan:
1134         if (host->mode == USE_DMA_ACCESS)
1135                 dma_release_channel(host->read_dma_chan);
1136 disable_clk:
1137         fsmc_nand_disable(host);
1138         clk_disable_unprepare(host->clk);
1139
1140         return ret;
1141 }
1142
1143 /*
1144  * Clean up routine
1145  */
1146 static int fsmc_nand_remove(struct platform_device *pdev)
1147 {
1148         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1149
1150         if (host) {
1151                 struct nand_chip *chip = &host->nand;
1152                 int ret;
1153
1154                 ret = mtd_device_unregister(nand_to_mtd(chip));
1155                 WARN_ON(ret);
1156                 nand_cleanup(chip);
1157                 fsmc_nand_disable(host);
1158
1159                 if (host->mode == USE_DMA_ACCESS) {
1160                         dma_release_channel(host->write_dma_chan);
1161                         dma_release_channel(host->read_dma_chan);
1162                 }
1163                 clk_disable_unprepare(host->clk);
1164         }
1165
1166         return 0;
1167 }
1168
1169 #ifdef CONFIG_PM_SLEEP
1170 static int fsmc_nand_suspend(struct device *dev)
1171 {
1172         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1173
1174         if (host)
1175                 clk_disable_unprepare(host->clk);
1176
1177         return 0;
1178 }
1179
1180 static int fsmc_nand_resume(struct device *dev)
1181 {
1182         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1183
1184         if (host) {
1185                 clk_prepare_enable(host->clk);
1186                 if (host->dev_timings)
1187                         fsmc_nand_setup(host, host->dev_timings);
1188                 nand_reset(&host->nand, 0);
1189         }
1190
1191         return 0;
1192 }
1193 #endif
1194
1195 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1196
1197 static const struct of_device_id fsmc_nand_id_table[] = {
1198         { .compatible = "st,spear600-fsmc-nand" },
1199         { .compatible = "stericsson,fsmc-nand" },
1200         {}
1201 };
1202 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1203
1204 static struct platform_driver fsmc_nand_driver = {
1205         .remove = fsmc_nand_remove,
1206         .driver = {
1207                 .name = "fsmc-nand",
1208                 .of_match_table = fsmc_nand_id_table,
1209                 .pm = &fsmc_nand_pm_ops,
1210         },
1211 };
1212
1213 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1214
1215 MODULE_LICENSE("GPL v2");
1216 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1217 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");