drivers/mmc/host/sdhci-omap.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * SDHCI Controller driver for TI's OMAP SoCs
   4  *
   5  * Copyright (C) 2017 Texas Instruments
   6  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/mmc/mmc.h>
  11 #include <linux/mmc/slot-gpio.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/sys_soc.h>
  20 #include <linux/thermal.h>
  21
  22 #include "sdhci-pltfm.h"
  23
  24 #define SDHCI_OMAP_CON          0x12c
  25 #define CON_DW8                 BIT(5)
  26 #define CON_DMA_MASTER          BIT(20)
  27 #define CON_DDR                 BIT(19)
  28 #define CON_CLKEXTFREE          BIT(16)
  29 #define CON_PADEN               BIT(15)
  30 #define CON_CTPL                BIT(11)
  31 #define CON_INIT                BIT(1)
  32 #define CON_OD                  BIT(0)
  33
  34 #define SDHCI_OMAP_DLL          0x0134
  35 #define DLL_SWT                 BIT(20)
  36 #define DLL_FORCE_SR_C_SHIFT    13
  37 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  38 #define DLL_FORCE_VALUE         BIT(12)
  39 #define DLL_CALIB               BIT(1)
  40
  41 #define SDHCI_OMAP_CMD          0x20c
  42
  43 #define SDHCI_OMAP_PSTATE       0x0224
  44 #define PSTATE_DLEV_DAT0        BIT(20)
  45 #define PSTATE_DATI             BIT(1)
  46
  47 #define SDHCI_OMAP_HCTL         0x228
  48 #define HCTL_SDBP               BIT(8)
  49 #define HCTL_SDVS_SHIFT         9
  50 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  51 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  52 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  53 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  54
  55 #define SDHCI_OMAP_SYSCTL       0x22c
  56 #define SYSCTL_CEN              BIT(2)
  57 #define SYSCTL_CLKD_SHIFT       6
  58 #define SYSCTL_CLKD_MASK        0x3ff
  59
  60 #define SDHCI_OMAP_STAT         0x230
  61
  62 #define SDHCI_OMAP_IE           0x234
  63 #define INT_CC_EN               BIT(0)
  64
  65 #define SDHCI_OMAP_AC12         0x23c
  66 #define AC12_V1V8_SIGEN         BIT(19)
  67 #define AC12_SCLK_SEL           BIT(23)
  68
  69 #define SDHCI_OMAP_CAPA         0x240
  70 #define CAPA_VS33               BIT(24)
  71 #define CAPA_VS30               BIT(25)
  72 #define CAPA_VS18               BIT(26)
  73
  74 #define SDHCI_OMAP_CAPA2        0x0244
  75 #define CAPA2_TSDR50            BIT(13)
  76
  77 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  78
  79 #define SYSCTL_CLKD_MAX         0x3FF
  80
  81 #define IOV_1V8                 1800000         /* 180000 uV */
  82 #define IOV_3V0                 3000000         /* 300000 uV */
  83 #define IOV_3V3                 3300000         /* 330000 uV */
  84
  85 #define MAX_PHASE_DELAY         0x7C
  86
  87 /* sdhci-omap controller flags */
  88 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  89 #define SDHCI_OMAP_SPECIAL_RESET        BIT(1)
  90
  91 struct sdhci_omap_data {
  92         u32 offset;
  93         u8 flags;
  94 };
  95
  96 struct sdhci_omap_host {
  97         char                    *version;
  98         void __iomem            *base;
  99         struct device           *dev;
 100         struct  regulator       *pbias;
 101         bool                    pbias_enabled;
 102         struct sdhci_host       *host;
 103         u8                      bus_mode;
 104         u8                      power_mode;
 105         u8                      timing;
 106         u8                      flags;
 107
 108         struct pinctrl          *pinctrl;
 109         struct pinctrl_state    **pinctrl_state;
 110         bool                    is_tuning;
 111         /* Omap specific context save */
 112         u32                     con;
 113         u32                     hctl;
 114         u32                     sysctl;
 115         u32                     capa;
 116 };
 117
 118 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 119 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 120
 121 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 122                                    unsigned int offset)
 123 {
 124         return readl(host->base + offset);
 125 }
 126
 127 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 128                                      unsigned int offset, u32 data)
 129 {
 130         writel(data, host->base + offset);
 131 }
 132
 133 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 134                                 bool power_on, unsigned int iov)
 135 {
 136         int ret;
 137         struct device *dev = omap_host->dev;
 138
 139         if (IS_ERR(omap_host->pbias))
 140                 return 0;
 141
 142         if (power_on) {
 143                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 144                 if (ret) {
 145                         dev_err(dev, "pbias set voltage failed\n");
 146                         return ret;
 147                 }
 148
 149                 if (omap_host->pbias_enabled)
 150                         return 0;
 151
 152                 ret = regulator_enable(omap_host->pbias);
 153                 if (ret) {
 154                         dev_err(dev, "pbias reg enable fail\n");
 155                         return ret;
 156                 }
 157
 158                 omap_host->pbias_enabled = true;
 159         } else {
 160                 if (!omap_host->pbias_enabled)
 161                         return 0;
 162
 163                 ret = regulator_disable(omap_host->pbias);
 164                 if (ret) {
 165                         dev_err(dev, "pbias reg disable fail\n");
 166                         return ret;
 167                 }
 168                 omap_host->pbias_enabled = false;
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 175                                  unsigned int iov)
 176 {
 177         int ret;
 178         struct sdhci_host *host = omap_host->host;
 179         struct mmc_host *mmc = host->mmc;
 180
 181         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 182         if (ret)
 183                 return ret;
 184
 185         if (!IS_ERR(mmc->supply.vqmmc)) {
 186                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 187                 if (ret) {
 188                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 189                         return ret;
 190                 }
 191         }
 192
 193         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 194         if (ret)
 195                 return ret;
 196
 197         return 0;
 198 }
 199
 200 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 201                                       unsigned char signal_voltage)
 202 {
 203         u32 reg;
 204         ktime_t timeout;
 205
 206         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 207         reg &= ~HCTL_SDVS_MASK;
 208
 209         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 210                 reg |= HCTL_SDVS_33;
 211         else
 212                 reg |= HCTL_SDVS_18;
 213
 214         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 215
 216         reg |= HCTL_SDBP;
 217         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 218
 219         /* wait 1ms */
 220         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 221         while (1) {
 222                 bool timedout = ktime_after(ktime_get(), timeout);
 223
 224                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
 225                         break;
 226                 if (WARN_ON(timedout))
 227                         return;
 228                 usleep_range(5, 10);
 229         }
 230 }
 231
 232 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
 233 {
 234         struct sdhci_host *host = mmc_priv(mmc);
 235         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 236         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 237         u32 reg;
 238
 239         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 240         if (enable)
 241                 reg |= (CON_CTPL | CON_CLKEXTFREE);
 242         else
 243                 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
 244         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 245
 246         sdhci_enable_sdio_irq(mmc, enable);
 247 }
 248
 249 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 250                                       int count)
 251 {
 252         int i;
 253         u32 reg;
 254
 255         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 256         reg |= DLL_FORCE_VALUE;
 257         reg &= ~DLL_FORCE_SR_C_MASK;
 258         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 259         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 260
 261         reg |= DLL_CALIB;
 262         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 263         for (i = 0; i < 1000; i++) {
 264                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 265                 if (reg & DLL_CALIB)
 266                         break;
 267         }
 268         reg &= ~DLL_CALIB;
 269         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 270 }
 271
 272 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 273 {
 274         u32 reg;
 275
 276         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 277         reg &= ~AC12_SCLK_SEL;
 278         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 279
 280         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 281         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 282         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 283 }
 284
 285 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 286 {
 287         struct sdhci_host *host = mmc_priv(mmc);
 288         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 289         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 290         struct thermal_zone_device *thermal_dev;
 291         struct device *dev = omap_host->dev;
 292         struct mmc_ios *ios = &mmc->ios;
 293         u32 start_window = 0, max_window = 0;
 294         bool single_point_failure = false;
 295         bool dcrc_was_enabled = false;
 296         u8 cur_match, prev_match = 0;
 297         u32 length = 0, max_len = 0;
 298         u32 phase_delay = 0;
 299         int temperature;
 300         int ret = 0;
 301         u32 reg;
 302         int i;
 303
 304         /* clock tuning is not needed for upto 52MHz */
 305         if (ios->clock <= 52000000)
 306                 return 0;
 307
 308         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 309         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 310                 return 0;
 311
 312         thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
 313         if (IS_ERR(thermal_dev)) {
 314                 dev_err(dev, "Unable to get thermal zone for tuning\n");
 315                 return PTR_ERR(thermal_dev);
 316         }
 317
 318         ret = thermal_zone_get_temp(thermal_dev, &temperature);
 319         if (ret)
 320                 return ret;
 321
 322         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 323         reg |= DLL_SWT;
 324         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 325
 326         /*
 327          * OMAP5/DRA74X/DRA72x Errata i802:
 328          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 329          * during the tuning procedure. So disable it during the
 330          * tuning procedure.
 331          */
 332         if (host->ier & SDHCI_INT_DATA_CRC) {
 333                 host->ier &= ~SDHCI_INT_DATA_CRC;
 334                 dcrc_was_enabled = true;
 335         }
 336
 337         omap_host->is_tuning = true;
 338
 339         /*
 340          * Stage 1: Search for a maximum pass window ignoring any
 341          * any single point failures. If the tuning value ends up
 342          * near it, move away from it in stage 2 below
 343          */
 344         while (phase_delay <= MAX_PHASE_DELAY) {
 345                 sdhci_omap_set_dll(omap_host, phase_delay);
 346
 347                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 348                 if (cur_match) {
 349                         if (prev_match) {
 350                                 length++;
 351                         } else if (single_point_failure) {
 352                                 /* ignore single point failure */
 353                                 length++;
 354                         } else {
 355                                 start_window = phase_delay;
 356                                 length = 1;
 357                         }
 358                 } else {
 359                         single_point_failure = prev_match;
 360                 }
 361
 362                 if (length > max_len) {
 363                         max_window = start_window;
 364                         max_len = length;
 365                 }
 366
 367                 prev_match = cur_match;
 368                 phase_delay += 4;
 369         }
 370
 371         if (!max_len) {
 372                 dev_err(dev, "Unable to find match\n");
 373                 ret = -EIO;
 374                 goto tuning_error;
 375         }
 376
 377         /*
 378          * Assign tuning value as a ratio of maximum pass window based
 379          * on temperature
 380          */
 381         if (temperature < -20000)
 382                 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
 383                                   max_window +
 384                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 385         else if (temperature < 20000)
 386                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 387         else if (temperature < 40000)
 388                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 389         else if (temperature < 70000)
 390                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 391         else if (temperature < 90000)
 392                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 393         else if (temperature < 120000)
 394                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 395         else
 396                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 397
 398         /*
 399          * Stage 2: Search for a single point failure near the chosen tuning
 400          * value in two steps. First in the +3 to +10 range and then in the
 401          * +2 to -10 range. If found, move away from it in the appropriate
 402          * direction by the appropriate amount depending on the temperature.
 403          */
 404         for (i = 3; i <= 10; i++) {
 405                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 406
 407                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 408                         if (temperature < 10000)
 409                                 phase_delay += i + 6;
 410                         else if (temperature < 20000)
 411                                 phase_delay += i - 12;
 412                         else if (temperature < 70000)
 413                                 phase_delay += i - 8;
 414                         else
 415                                 phase_delay += i - 6;
 416
 417                         goto single_failure_found;
 418                 }
 419         }
 420
 421         for (i = 2; i >= -10; i--) {
 422                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 423
 424                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 425                         if (temperature < 10000)
 426                                 phase_delay += i + 12;
 427                         else if (temperature < 20000)
 428                                 phase_delay += i + 8;
 429                         else if (temperature < 70000)
 430                                 phase_delay += i + 8;
 431                         else if (temperature < 90000)
 432                                 phase_delay += i + 10;
 433                         else
 434                                 phase_delay += i + 12;
 435
 436                         goto single_failure_found;
 437                 }
 438         }
 439
 440 single_failure_found:
 441         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 442         if (!(reg & AC12_SCLK_SEL)) {
 443                 ret = -EIO;
 444                 goto tuning_error;
 445         }
 446
 447         sdhci_omap_set_dll(omap_host, phase_delay);
 448
 449         omap_host->is_tuning = false;
 450
 451         goto ret;
 452
 453 tuning_error:
 454         omap_host->is_tuning = false;
 455         dev_err(dev, "Tuning failed\n");
 456         sdhci_omap_disable_tuning(omap_host);
 457
 458 ret:
 459         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 460         /* Reenable forbidden interrupt */
 461         if (dcrc_was_enabled)
 462                 host->ier |= SDHCI_INT_DATA_CRC;
 463         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 464         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 465         return ret;
 466 }
 467
 468 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 469 {
 470         u32 reg, ac12;
 471         int ret = false;
 472         struct sdhci_host *host = mmc_priv(mmc);
 473         struct sdhci_pltfm_host *pltfm_host;
 474         struct sdhci_omap_host *omap_host;
 475         u32 ier = host->ier;
 476
 477         pltfm_host = sdhci_priv(host);
 478         omap_host = sdhci_pltfm_priv(pltfm_host);
 479
 480         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 481         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 482         reg &= ~CON_CLKEXTFREE;
 483         if (ac12 & AC12_V1V8_SIGEN)
 484                 reg |= CON_CLKEXTFREE;
 485         reg |= CON_PADEN;
 486         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 487
 488         disable_irq(host->irq);
 489         ier |= SDHCI_INT_CARD_INT;
 490         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 491         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 492
 493         /*
 494          * Delay is required for PSTATE to correctly reflect
 495          * DLEV/CLEV values after PADEN is set.
 496          */
 497         usleep_range(50, 100);
 498         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 499         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 500                 ret = true;
 501
 502         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 503         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 504         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 505
 506         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 507         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 508         enable_irq(host->irq);
 509
 510         return ret;
 511 }
 512
 513 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 514                                                   struct mmc_ios *ios)
 515 {
 516         u32 reg;
 517         int ret;
 518         unsigned int iov;
 519         struct sdhci_host *host = mmc_priv(mmc);
 520         struct sdhci_pltfm_host *pltfm_host;
 521         struct sdhci_omap_host *omap_host;
 522         struct device *dev;
 523
 524         pltfm_host = sdhci_priv(host);
 525         omap_host = sdhci_pltfm_priv(pltfm_host);
 526         dev = omap_host->dev;
 527
 528         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 529                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 530                 if (!(reg & CAPA_VS33))
 531                         return -EOPNOTSUPP;
 532
 533                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 534
 535                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 536                 reg &= ~AC12_V1V8_SIGEN;
 537                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 538
 539                 iov = IOV_3V3;
 540         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 541                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 542                 if (!(reg & CAPA_VS18))
 543                         return -EOPNOTSUPP;
 544
 545                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 546
 547                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 548                 reg |= AC12_V1V8_SIGEN;
 549                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 550
 551                 iov = IOV_1V8;
 552         } else {
 553                 return -EOPNOTSUPP;
 554         }
 555
 556         ret = sdhci_omap_enable_iov(omap_host, iov);
 557         if (ret) {
 558                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 559                 return ret;
 560         }
 561
 562         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 563         return 0;
 564 }
 565
 566 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 567 {
 568         int ret;
 569         struct pinctrl_state *pinctrl_state;
 570         struct device *dev = omap_host->dev;
 571
 572         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 573                 return;
 574
 575         if (omap_host->timing == timing)
 576                 return;
 577
 578         sdhci_omap_stop_clock(omap_host);
 579
 580         pinctrl_state = omap_host->pinctrl_state[timing];
 581         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 582         if (ret) {
 583                 dev_err(dev, "failed to select pinctrl state\n");
 584                 return;
 585         }
 586
 587         sdhci_omap_start_clock(omap_host);
 588         omap_host->timing = timing;
 589 }
 590
 591 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 592                                       u8 power_mode)
 593 {
 594         if (omap_host->bus_mode == MMC_POWER_OFF)
 595                 sdhci_omap_disable_tuning(omap_host);
 596         omap_host->power_mode = power_mode;
 597 }
 598
 599 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 600                                     unsigned int mode)
 601 {
 602         u32 reg;
 603
 604         if (omap_host->bus_mode == mode)
 605                 return;
 606
 607         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 608         if (mode == MMC_BUSMODE_OPENDRAIN)
 609                 reg |= CON_OD;
 610         else
 611                 reg &= ~CON_OD;
 612         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 613
 614         omap_host->bus_mode = mode;
 615 }
 616
 617 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 618 {
 619         struct sdhci_host *host = mmc_priv(mmc);
 620         struct sdhci_pltfm_host *pltfm_host;
 621         struct sdhci_omap_host *omap_host;
 622
 623         pltfm_host = sdhci_priv(host);
 624         omap_host = sdhci_pltfm_priv(pltfm_host);
 625
 626         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 627         sdhci_omap_set_timing(omap_host, ios->timing);
 628         sdhci_set_ios(mmc, ios);
 629         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 630 }
 631
 632 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 633                                    unsigned int clock)
 634 {
 635         u16 dsor;
 636
 637         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 638         if (dsor > SYSCTL_CLKD_MAX)
 639                 dsor = SYSCTL_CLKD_MAX;
 640
 641         return dsor;
 642 }
 643
 644 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 645 {
 646         u32 reg;
 647
 648         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 649         reg |= SYSCTL_CEN;
 650         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 651 }
 652
 653 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 654 {
 655         u32 reg;
 656
 657         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 658         reg &= ~SYSCTL_CEN;
 659         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 660 }
 661
 662 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 663 {
 664         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 665         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 666         unsigned long clkdiv;
 667
 668         sdhci_omap_stop_clock(omap_host);
 669
 670         if (!clock)
 671                 return;
 672
 673         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 674         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 675         sdhci_enable_clk(host, clkdiv);
 676
 677         sdhci_omap_start_clock(omap_host);
 678 }
 679
 680 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 681                           unsigned short vdd)
 682 {
 683         struct mmc_host *mmc = host->mmc;
 684
 685         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 686 }
 687
 688 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 689 {
 690         u32 reg;
 691         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 692         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 693
 694         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 695         reg &= ~CON_DMA_MASTER;
 696         /* Switch to DMA slave mode when using external DMA */
 697         if (!host->use_external_dma)
 698                 reg |= CON_DMA_MASTER;
 699
 700         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 701
 702         return 0;
 703 }
 704
 705 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 706 {
 707         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 708
 709         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 710 }
 711
 712 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 713 {
 714         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 715         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 716         u32 reg;
 717
 718         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 719         if (width == MMC_BUS_WIDTH_8)
 720                 reg |= CON_DW8;
 721         else
 722                 reg &= ~CON_DW8;
 723         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 724
 725         sdhci_set_bus_width(host, width);
 726 }
 727
 728 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 729 {
 730         u32 reg;
 731         ktime_t timeout;
 732         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 733         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 734
 735         if (omap_host->power_mode == power_mode)
 736                 return;
 737
 738         if (power_mode != MMC_POWER_ON)
 739                 return;
 740
 741         disable_irq(host->irq);
 742
 743         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 744         reg |= CON_INIT;
 745         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 746         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 747
 748         /* wait 1ms */
 749         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 750         while (1) {
 751                 bool timedout = ktime_after(ktime_get(), timeout);
 752
 753                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
 754                         break;
 755                 if (WARN_ON(timedout))
 756                         return;
 757                 usleep_range(5, 10);
 758         }
 759
 760         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 761         reg &= ~CON_INIT;
 762         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 763         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 764
 765         enable_irq(host->irq);
 766 }
 767
 768 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 769                                          unsigned int timing)
 770 {
 771         u32 reg;
 772         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 773         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 774
 775         sdhci_omap_stop_clock(omap_host);
 776
 777         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 778         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 779                 reg |= CON_DDR;
 780         else
 781                 reg &= ~CON_DDR;
 782         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 783
 784         sdhci_set_uhs_signaling(host, timing);
 785         sdhci_omap_start_clock(omap_host);
 786 }
 787
 788 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 789 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
 790 {
 791         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 792         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 793         unsigned long limit = MMC_TIMEOUT_US;
 794         unsigned long i = 0;
 795
 796         /* Don't reset data lines during tuning operation */
 797         if (omap_host->is_tuning)
 798                 mask &= ~SDHCI_RESET_DATA;
 799
 800         if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
 801                 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 802                 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
 803                        (i++ < limit))
 804                         udelay(1);
 805                 i = 0;
 806                 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
 807                        (i++ < limit))
 808                         udelay(1);
 809
 810                 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
 811                         dev_err(mmc_dev(host->mmc),
 812                                 "Timeout waiting on controller reset in %s\n",
 813                                 __func__);
 814                 return;
 815         }
 816
 817         sdhci_reset(host, mask);
 818 }
 819
 820 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
 821                       SDHCI_INT_TIMEOUT)
 822 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
 823
 824 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
 825 {
 826         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 827         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 828
 829         if (omap_host->is_tuning && host->cmd && !host->data_early &&
 830             (intmask & CMD_ERR_MASK)) {
 831
 832                 /*
 833                  * Since we are not resetting data lines during tuning
 834                  * operation, data error or data complete interrupts
 835                  * might still arrive. Mark this request as a failure
 836                  * but still wait for the data interrupt
 837                  */
 838                 if (intmask & SDHCI_INT_TIMEOUT)
 839                         host->cmd->error = -ETIMEDOUT;
 840                 else
 841                         host->cmd->error = -EILSEQ;
 842
 843                 host->cmd = NULL;
 844
 845                 /*
 846                  * Sometimes command error interrupts and command complete
 847                  * interrupt will arrive together. Clear all command related
 848                  * interrupts here.
 849                  */
 850                 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
 851                 intmask &= ~CMD_MASK;
 852         }
 853
 854         return intmask;
 855 }
 856
 857 static void sdhci_omap_set_timeout(struct sdhci_host *host,
 858                                    struct mmc_command *cmd)
 859 {
 860         if (cmd->opcode == MMC_ERASE)
 861                 sdhci_set_data_timeout_irq(host, false);
 862
 863         __sdhci_set_timeout(host, cmd);
 864 }
 865
 866 static struct sdhci_ops sdhci_omap_ops = {
 867         .set_clock = sdhci_omap_set_clock,
 868         .set_power = sdhci_omap_set_power,
 869         .enable_dma = sdhci_omap_enable_dma,
 870         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 871         .get_min_clock = sdhci_omap_get_min_clock,
 872         .set_bus_width = sdhci_omap_set_bus_width,
 873         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 874         .reset = sdhci_omap_reset,
 875         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 876         .irq = sdhci_omap_irq,
 877         .set_timeout = sdhci_omap_set_timeout,
 878 };
 879
 880 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 881 {
 882         u32 reg;
 883         int ret = 0;
 884         struct device *dev = omap_host->dev;
 885         struct regulator *vqmmc;
 886
 887         vqmmc = regulator_get(dev, "vqmmc");
 888         if (IS_ERR(vqmmc)) {
 889                 ret = PTR_ERR(vqmmc);
 890                 goto reg_put;
 891         }
 892
 893         /* voltage capabilities might be set by boot loader, clear it */
 894         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 895         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 896
 897         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 898                 reg |= CAPA_VS33;
 899         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 900                 reg |= CAPA_VS18;
 901
 902         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 903
 904 reg_put:
 905         regulator_put(vqmmc);
 906
 907         return ret;
 908 }
 909
 910 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 911         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 912                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 913                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 914                   SDHCI_QUIRK_NO_HISPD_BIT |
 915                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 916         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
 917                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 918                    SDHCI_QUIRK2_RSP_136_HAS_CRC |
 919                    SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
 920         .ops = &sdhci_omap_ops,
 921 };
 922
 923 static const struct sdhci_omap_data k2g_data = {
 924         .offset = 0x200,
 925 };
 926
 927 static const struct sdhci_omap_data am335_data = {
 928         .offset = 0x200,
 929         .flags = SDHCI_OMAP_SPECIAL_RESET,
 930 };
 931
 932 static const struct sdhci_omap_data am437_data = {
 933         .offset = 0x200,
 934         .flags = SDHCI_OMAP_SPECIAL_RESET,
 935 };
 936
 937 static const struct sdhci_omap_data dra7_data = {
 938         .offset = 0x200,
 939         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 940 };
 941
 942 static const struct of_device_id omap_sdhci_match[] = {
 943         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 944         { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
 945         { .compatible = "ti,am335-sdhci", .data = &am335_data },
 946         { .compatible = "ti,am437-sdhci", .data = &am437_data },
 947         {},
 948 };
 949 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 950
 951 static struct pinctrl_state
 952 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 953                                   u32 *caps, u32 capmask)
 954 {
 955         struct device *dev = omap_host->dev;
 956         char *version = omap_host->version;
 957         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 958         char str[20];
 959
 960         if (!(*caps & capmask))
 961                 goto ret;
 962
 963         if (version) {
 964                 snprintf(str, 20, "%s-%s", mode, version);
 965                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
 966         }
 967
 968         if (IS_ERR(pinctrl_state))
 969                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 970
 971         if (IS_ERR(pinctrl_state)) {
 972                 dev_err(dev, "no pinctrl state for %s mode", mode);
 973                 *caps &= ~capmask;
 974         }
 975
 976 ret:
 977         return pinctrl_state;
 978 }
 979
 980 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 981                                                    *omap_host)
 982 {
 983         struct device *dev = omap_host->dev;
 984         struct sdhci_host *host = omap_host->host;
 985         struct mmc_host *mmc = host->mmc;
 986         u32 *caps = &mmc->caps;
 987         u32 *caps2 = &mmc->caps2;
 988         struct pinctrl_state *state;
 989         struct pinctrl_state **pinctrl_state;
 990
 991         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 992                 return 0;
 993
 994         pinctrl_state = devm_kcalloc(dev,
 995                                      MMC_TIMING_MMC_HS200 + 1,
 996                                      sizeof(*pinctrl_state),
 997                                      GFP_KERNEL);
 998         if (!pinctrl_state)
 999                 return -ENOMEM;
1000
1001         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1002         if (IS_ERR(omap_host->pinctrl)) {
1003                 dev_err(dev, "Cannot get pinctrl\n");
1004                 return PTR_ERR(omap_host->pinctrl);
1005         }
1006
1007         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1008         if (IS_ERR(state)) {
1009                 dev_err(dev, "no pinctrl state for default mode\n");
1010                 return PTR_ERR(state);
1011         }
1012         pinctrl_state[MMC_TIMING_LEGACY] = state;
1013
1014         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1015                                                  MMC_CAP_UHS_SDR104);
1016         if (!IS_ERR(state))
1017                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1018
1019         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1020                                                  MMC_CAP_UHS_DDR50);
1021         if (!IS_ERR(state))
1022                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1023
1024         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1025                                                  MMC_CAP_UHS_SDR50);
1026         if (!IS_ERR(state))
1027                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1028
1029         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1030                                                  MMC_CAP_UHS_SDR25);
1031         if (!IS_ERR(state))
1032                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1033
1034         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1035                                                  MMC_CAP_UHS_SDR12);
1036         if (!IS_ERR(state))
1037                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1038
1039         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1040                                                  MMC_CAP_1_8V_DDR);
1041         if (!IS_ERR(state)) {
1042                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1043         } else {
1044                 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1045                                                          caps,
1046                                                          MMC_CAP_3_3V_DDR);
1047                 if (!IS_ERR(state))
1048                         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1049         }
1050
1051         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1052                                                  MMC_CAP_SD_HIGHSPEED);
1053         if (!IS_ERR(state))
1054                 pinctrl_state[MMC_TIMING_SD_HS] = state;
1055
1056         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1057                                                  MMC_CAP_MMC_HIGHSPEED);
1058         if (!IS_ERR(state))
1059                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1060
1061         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1062                                                  MMC_CAP2_HS200_1_8V_SDR);
1063         if (!IS_ERR(state))
1064                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1065
1066         omap_host->pinctrl_state = pinctrl_state;
1067
1068         return 0;
1069 }
1070
1071 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1072         {
1073                 .machine = "DRA7[45]*",
1074                 .revision = "ES1.[01]",
1075         },
1076         {
1077                 /* sentinel */
1078         }
1079 };
1080
1081 static int sdhci_omap_probe(struct platform_device *pdev)
1082 {
1083         int ret;
1084         u32 offset;
1085         struct device *dev = &pdev->dev;
1086         struct sdhci_host *host;
1087         struct sdhci_pltfm_host *pltfm_host;
1088         struct sdhci_omap_host *omap_host;
1089         struct mmc_host *mmc;
1090         const struct of_device_id *match;
1091         struct sdhci_omap_data *data;
1092         const struct soc_device_attribute *soc;
1093         struct resource *regs;
1094
1095         match = of_match_device(omap_sdhci_match, dev);
1096         if (!match)
1097                 return -EINVAL;
1098
1099         data = (struct sdhci_omap_data *)match->data;
1100         if (!data) {
1101                 dev_err(dev, "no sdhci omap data\n");
1102                 return -EINVAL;
1103         }
1104         offset = data->offset;
1105
1106         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1107         if (!regs)
1108                 return -ENXIO;
1109
1110         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1111                                 sizeof(*omap_host));
1112         if (IS_ERR(host)) {
1113                 dev_err(dev, "Failed sdhci_pltfm_init\n");
1114                 return PTR_ERR(host);
1115         }
1116
1117         pltfm_host = sdhci_priv(host);
1118         omap_host = sdhci_pltfm_priv(pltfm_host);
1119         omap_host->host = host;
1120         omap_host->base = host->ioaddr;
1121         omap_host->dev = dev;
1122         omap_host->power_mode = MMC_POWER_UNDEFINED;
1123         omap_host->timing = MMC_TIMING_LEGACY;
1124         omap_host->flags = data->flags;
1125         host->ioaddr += offset;
1126         host->mapbase = regs->start + offset;
1127
1128         mmc = host->mmc;
1129         sdhci_get_of_property(pdev);
1130         ret = mmc_of_parse(mmc);
1131         if (ret)
1132                 goto err_pltfm_free;
1133
1134         soc = soc_device_match(sdhci_omap_soc_devices);
1135         if (soc) {
1136                 omap_host->version = "rev11";
1137                 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1138                         mmc->f_max = 96000000;
1139                 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1140                         mmc->f_max = 48000000;
1141                 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1142                         mmc->f_max = 48000000;
1143         }
1144
1145         if (!mmc_can_gpio_ro(mmc))
1146                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1147
1148         pltfm_host->clk = devm_clk_get(dev, "fck");
1149         if (IS_ERR(pltfm_host->clk)) {
1150                 ret = PTR_ERR(pltfm_host->clk);
1151                 goto err_pltfm_free;
1152         }
1153
1154         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1155         if (ret) {
1156                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1157                 goto err_pltfm_free;
1158         }
1159
1160         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1161         if (IS_ERR(omap_host->pbias)) {
1162                 ret = PTR_ERR(omap_host->pbias);
1163                 if (ret != -ENODEV)
1164                         goto err_pltfm_free;
1165                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1166         }
1167         omap_host->pbias_enabled = false;
1168
1169         /*
1170          * omap_device_pm_domain has callbacks to enable the main
1171          * functional clock, interface clock and also configure the
1172          * SYSCONFIG register of omap devices. The callback will be invoked
1173          * as part of pm_runtime_get_sync.
1174          */
1175         pm_runtime_enable(dev);
1176         ret = pm_runtime_resume_and_get(dev);
1177         if (ret) {
1178                 dev_err(dev, "pm_runtime_get_sync failed\n");
1179                 goto err_rpm_disable;
1180         }
1181
1182         ret = sdhci_omap_set_capabilities(omap_host);
1183         if (ret) {
1184                 dev_err(dev, "failed to set system capabilities\n");
1185                 goto err_put_sync;
1186         }
1187
1188         host->mmc_host_ops.start_signal_voltage_switch =
1189                                         sdhci_omap_start_signal_voltage_switch;
1190         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1191         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1192         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1193         host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1194
1195         /* Switch to external DMA only if there is the "dmas" property */
1196         if (of_find_property(dev->of_node, "dmas", NULL))
1197                 sdhci_switch_external_dma(host, true);
1198
1199         /* R1B responses is required to properly manage HW busy detection. */
1200         mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1201
1202         ret = sdhci_setup_host(host);
1203         if (ret)
1204                 goto err_put_sync;
1205
1206         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1207         if (ret)
1208                 goto err_cleanup_host;
1209
1210         ret = __sdhci_add_host(host);
1211         if (ret)
1212                 goto err_cleanup_host;
1213
1214         return 0;
1215
1216 err_cleanup_host:
1217         sdhci_cleanup_host(host);
1218
1219 err_put_sync:
1220         pm_runtime_put_sync(dev);
1221
1222 err_rpm_disable:
1223         pm_runtime_disable(dev);
1224
1225 err_pltfm_free:
1226         sdhci_pltfm_free(pdev);
1227         return ret;
1228 }
1229
1230 static int sdhci_omap_remove(struct platform_device *pdev)
1231 {
1232         struct device *dev = &pdev->dev;
1233         struct sdhci_host *host = platform_get_drvdata(pdev);
1234
1235         sdhci_remove_host(host, true);
1236         pm_runtime_put_sync(dev);
1237         pm_runtime_disable(dev);
1238         sdhci_pltfm_free(pdev);
1239
1240         return 0;
1241 }
1242 #ifdef CONFIG_PM_SLEEP
1243 static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1244 {
1245         omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1246         omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1247         omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1248 }
1249
1250 static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1251 {
1252         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1253         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1254         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1255 }
1256
1257 static int __maybe_unused sdhci_omap_suspend(struct device *dev)
1258 {
1259         struct sdhci_host *host = dev_get_drvdata(dev);
1260         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1261         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1262
1263         sdhci_suspend_host(host);
1264
1265         sdhci_omap_context_save(omap_host);
1266
1267         pinctrl_pm_select_idle_state(dev);
1268
1269         pm_runtime_force_suspend(dev);
1270
1271         return 0;
1272 }
1273
1274 static int __maybe_unused sdhci_omap_resume(struct device *dev)
1275 {
1276         struct sdhci_host *host = dev_get_drvdata(dev);
1277         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1278         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1279
1280         pm_runtime_force_resume(dev);
1281
1282         pinctrl_pm_select_default_state(dev);
1283
1284         sdhci_omap_context_restore(omap_host);
1285
1286         sdhci_resume_host(host);
1287
1288         return 0;
1289 }
1290 #endif
1291 static SIMPLE_DEV_PM_OPS(sdhci_omap_dev_pm_ops, sdhci_omap_suspend,
1292                          sdhci_omap_resume);
1293
1294 static struct platform_driver sdhci_omap_driver = {
1295         .probe = sdhci_omap_probe,
1296         .remove = sdhci_omap_remove,
1297         .driver = {
1298                    .name = "sdhci-omap",
1299                    .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1300                    .pm = &sdhci_omap_dev_pm_ops,
1301                    .of_match_table = omap_sdhci_match,
1302                   },
1303 };
1304
1305 module_platform_driver(sdhci_omap_driver);
1306
1307 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1308 MODULE_AUTHOR("Texas Instruments Inc.");
1309 MODULE_LICENSE("GPL v2");
1310 MODULE_ALIAS("platform:sdhci_omap");