1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
5 #include <linux/delay.h>
6 #include <linux/highmem.h>
8 #include <linux/module.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/slab.h>
11 #include <linux/scatterlist.h>
12 #include <linux/platform_device.h>
13 #include <linux/ktime.h>
15 #include <linux/mmc/mmc.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/card.h>
25 struct mmc_request *mrq;
27 #define CQHCI_EXTERNAL_TIMEOUT BIT(0)
28 #define CQHCI_COMPLETED BIT(1)
29 #define CQHCI_HOST_CRC BIT(2)
30 #define CQHCI_HOST_TIMEOUT BIT(3)
31 #define CQHCI_HOST_OTHER BIT(4)
34 static inline u8 *get_desc(struct cqhci_host *cq_host, u8 tag)
36 return cq_host->desc_base + (tag * cq_host->slot_sz);
39 static inline u8 *get_link_desc(struct cqhci_host *cq_host, u8 tag)
41 u8 *desc = get_desc(cq_host, tag);
43 return desc + cq_host->task_desc_len;
46 static inline dma_addr_t get_trans_desc_dma(struct cqhci_host *cq_host, u8 tag)
48 return cq_host->trans_desc_dma_base +
49 (cq_host->mmc->max_segs * tag *
50 cq_host->trans_desc_len);
53 static inline u8 *get_trans_desc(struct cqhci_host *cq_host, u8 tag)
55 return cq_host->trans_desc_base +
56 (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag);
59 static void setup_trans_desc(struct cqhci_host *cq_host, u8 tag)
62 dma_addr_t trans_temp;
64 link_temp = get_link_desc(cq_host, tag);
65 trans_temp = get_trans_desc_dma(cq_host, tag);
67 memset(link_temp, 0, cq_host->link_desc_len);
68 if (cq_host->link_desc_len > 8)
71 if (tag == DCMD_SLOT && (cq_host->mmc->caps2 & MMC_CAP2_CQE_DCMD)) {
72 *link_temp = CQHCI_VALID(0) | CQHCI_ACT(0) | CQHCI_END(1);
76 *link_temp = CQHCI_VALID(1) | CQHCI_ACT(0x6) | CQHCI_END(0);
79 __le64 *data_addr = (__le64 __force *)(link_temp + 4);
81 data_addr[0] = cpu_to_le64(trans_temp);
83 __le32 *data_addr = (__le32 __force *)(link_temp + 4);
85 data_addr[0] = cpu_to_le32(trans_temp);
89 static void cqhci_set_irqs(struct cqhci_host *cq_host, u32 set)
91 cqhci_writel(cq_host, set, CQHCI_ISTE);
92 cqhci_writel(cq_host, set, CQHCI_ISGE);
95 #define DRV_NAME "cqhci"
97 #define CQHCI_DUMP(f, x...) \
98 pr_err("%s: " DRV_NAME ": " f, mmc_hostname(mmc), ## x)
100 static void cqhci_dumpregs(struct cqhci_host *cq_host)
102 struct mmc_host *mmc = cq_host->mmc;
104 CQHCI_DUMP("============ CQHCI REGISTER DUMP ===========\n");
106 CQHCI_DUMP("Caps: 0x%08x | Version: 0x%08x\n",
107 cqhci_readl(cq_host, CQHCI_CAP),
108 cqhci_readl(cq_host, CQHCI_VER));
109 CQHCI_DUMP("Config: 0x%08x | Control: 0x%08x\n",
110 cqhci_readl(cq_host, CQHCI_CFG),
111 cqhci_readl(cq_host, CQHCI_CTL));
112 CQHCI_DUMP("Int stat: 0x%08x | Int enab: 0x%08x\n",
113 cqhci_readl(cq_host, CQHCI_IS),
114 cqhci_readl(cq_host, CQHCI_ISTE));
115 CQHCI_DUMP("Int sig: 0x%08x | Int Coal: 0x%08x\n",
116 cqhci_readl(cq_host, CQHCI_ISGE),
117 cqhci_readl(cq_host, CQHCI_IC));
118 CQHCI_DUMP("TDL base: 0x%08x | TDL up32: 0x%08x\n",
119 cqhci_readl(cq_host, CQHCI_TDLBA),
120 cqhci_readl(cq_host, CQHCI_TDLBAU));
121 CQHCI_DUMP("Doorbell: 0x%08x | TCN: 0x%08x\n",
122 cqhci_readl(cq_host, CQHCI_TDBR),
123 cqhci_readl(cq_host, CQHCI_TCN));
124 CQHCI_DUMP("Dev queue: 0x%08x | Dev Pend: 0x%08x\n",
125 cqhci_readl(cq_host, CQHCI_DQS),
126 cqhci_readl(cq_host, CQHCI_DPT));
127 CQHCI_DUMP("Task clr: 0x%08x | SSC1: 0x%08x\n",
128 cqhci_readl(cq_host, CQHCI_TCLR),
129 cqhci_readl(cq_host, CQHCI_SSC1));
130 CQHCI_DUMP("SSC2: 0x%08x | DCMD rsp: 0x%08x\n",
131 cqhci_readl(cq_host, CQHCI_SSC2),
132 cqhci_readl(cq_host, CQHCI_CRDCT));
133 CQHCI_DUMP("RED mask: 0x%08x | TERRI: 0x%08x\n",
134 cqhci_readl(cq_host, CQHCI_RMEM),
135 cqhci_readl(cq_host, CQHCI_TERRI));
136 CQHCI_DUMP("Resp idx: 0x%08x | Resp arg: 0x%08x\n",
137 cqhci_readl(cq_host, CQHCI_CRI),
138 cqhci_readl(cq_host, CQHCI_CRA));
140 if (cq_host->ops->dumpregs)
141 cq_host->ops->dumpregs(mmc);
143 CQHCI_DUMP(": ===========================================\n");
147 * The allocated descriptor table for task, link & transfer descritors
150 * |task desc | |->|----------|
151 * |----------| | |trans desc|
152 * |link desc-|->| |----------|
155 * no. of slots max-segs
158 * The idea here is to create the [task+trans] table and mark & point the
159 * link desc to the transfer desc table on a per slot basis.
161 static int cqhci_host_alloc_tdl(struct cqhci_host *cq_host)
165 /* task descriptor can be 64/128 bit irrespective of arch */
166 if (cq_host->caps & CQHCI_TASK_DESC_SZ_128) {
167 cqhci_writel(cq_host, cqhci_readl(cq_host, CQHCI_CFG) |
168 CQHCI_TASK_DESC_SZ, CQHCI_CFG);
169 cq_host->task_desc_len = 16;
171 cq_host->task_desc_len = 8;
175 * 96 bits length of transfer desc instead of 128 bits which means
176 * ADMA would expect next valid descriptor at the 96th bit
179 if (cq_host->dma64) {
180 if (cq_host->quirks & CQHCI_QUIRK_SHORT_TXFR_DESC_SZ)
181 cq_host->trans_desc_len = 12;
183 cq_host->trans_desc_len = 16;
184 cq_host->link_desc_len = 16;
186 cq_host->trans_desc_len = 8;
187 cq_host->link_desc_len = 8;
190 /* total size of a slot: 1 task & 1 transfer (link) */
191 cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len;
193 cq_host->desc_size = cq_host->slot_sz * cq_host->num_slots;
195 cq_host->data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs *
196 cq_host->mmc->cqe_qdepth;
198 pr_debug("%s: cqhci: desc_size: %zu data_sz: %zu slot-sz: %d\n",
199 mmc_hostname(cq_host->mmc), cq_host->desc_size, cq_host->data_size,
203 * allocate a dma-mapped chunk of memory for the descriptors
204 * allocate a dma-mapped chunk of memory for link descriptors
205 * setup each link-desc memory offset per slot-number to
206 * the descriptor table.
208 cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc),
210 &cq_host->desc_dma_base,
212 if (!cq_host->desc_base)
215 cq_host->trans_desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc),
217 &cq_host->trans_desc_dma_base,
219 if (!cq_host->trans_desc_base) {
220 dmam_free_coherent(mmc_dev(cq_host->mmc), cq_host->desc_size,
222 cq_host->desc_dma_base);
223 cq_host->desc_base = NULL;
224 cq_host->desc_dma_base = 0;
228 pr_debug("%s: cqhci: desc-base: 0x%p trans-base: 0x%p\n desc_dma 0x%llx trans_dma: 0x%llx\n",
229 mmc_hostname(cq_host->mmc), cq_host->desc_base, cq_host->trans_desc_base,
230 (unsigned long long)cq_host->desc_dma_base,
231 (unsigned long long)cq_host->trans_desc_dma_base);
233 for (; i < (cq_host->num_slots); i++)
234 setup_trans_desc(cq_host, i);
239 static void __cqhci_enable(struct cqhci_host *cq_host)
241 struct mmc_host *mmc = cq_host->mmc;
244 cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
246 /* Configuration must not be changed while enabled */
247 if (cqcfg & CQHCI_ENABLE) {
248 cqcfg &= ~CQHCI_ENABLE;
249 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
252 cqcfg &= ~(CQHCI_DCMD | CQHCI_TASK_DESC_SZ);
254 if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
257 if (cq_host->caps & CQHCI_TASK_DESC_SZ_128)
258 cqcfg |= CQHCI_TASK_DESC_SZ;
260 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
262 cqhci_writel(cq_host, lower_32_bits(cq_host->desc_dma_base),
264 cqhci_writel(cq_host, upper_32_bits(cq_host->desc_dma_base),
267 cqhci_writel(cq_host, cq_host->rca, CQHCI_SSC2);
269 cqhci_set_irqs(cq_host, 0);
271 cqcfg |= CQHCI_ENABLE;
273 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
277 if (cq_host->ops->enable)
278 cq_host->ops->enable(mmc);
280 /* Ensure all writes are done before interrupts are enabled */
283 cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
285 cq_host->activated = true;
288 static void __cqhci_disable(struct cqhci_host *cq_host)
292 cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
293 cqcfg &= ~CQHCI_ENABLE;
294 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
296 cq_host->mmc->cqe_on = false;
298 cq_host->activated = false;
301 int cqhci_suspend(struct mmc_host *mmc)
303 struct cqhci_host *cq_host = mmc->cqe_private;
305 if (cq_host->enabled)
306 __cqhci_disable(cq_host);
310 EXPORT_SYMBOL(cqhci_suspend);
312 int cqhci_resume(struct mmc_host *mmc)
314 /* Re-enable is done upon first request */
317 EXPORT_SYMBOL(cqhci_resume);
319 static int cqhci_enable(struct mmc_host *mmc, struct mmc_card *card)
321 struct cqhci_host *cq_host = mmc->cqe_private;
324 if (!card->ext_csd.cmdq_en)
327 if (cq_host->enabled)
330 cq_host->rca = card->rca;
332 err = cqhci_host_alloc_tdl(cq_host);
334 pr_err("%s: Failed to enable CQE, error %d\n",
335 mmc_hostname(mmc), err);
339 __cqhci_enable(cq_host);
341 cq_host->enabled = true;
344 cqhci_dumpregs(cq_host);
349 /* CQHCI is idle and should halt immediately, so set a small timeout */
350 #define CQHCI_OFF_TIMEOUT 100
352 static void cqhci_off(struct mmc_host *mmc)
354 struct cqhci_host *cq_host = mmc->cqe_private;
359 if (!cq_host->enabled || !mmc->cqe_on || cq_host->recovery_halt)
362 if (cq_host->ops->disable)
363 cq_host->ops->disable(mmc, false);
365 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
367 timeout = ktime_add_us(ktime_get(), CQHCI_OFF_TIMEOUT);
369 timed_out = ktime_compare(ktime_get(), timeout) > 0;
370 reg = cqhci_readl(cq_host, CQHCI_CTL);
371 if ((reg & CQHCI_HALT) || timed_out)
376 pr_err("%s: cqhci: CQE stuck on\n", mmc_hostname(mmc));
378 pr_debug("%s: cqhci: CQE off\n", mmc_hostname(mmc));
383 static void cqhci_disable(struct mmc_host *mmc)
385 struct cqhci_host *cq_host = mmc->cqe_private;
387 if (!cq_host->enabled)
392 __cqhci_disable(cq_host);
394 dmam_free_coherent(mmc_dev(mmc), cq_host->data_size,
395 cq_host->trans_desc_base,
396 cq_host->trans_desc_dma_base);
398 dmam_free_coherent(mmc_dev(mmc), cq_host->desc_size,
400 cq_host->desc_dma_base);
402 cq_host->trans_desc_base = NULL;
403 cq_host->desc_base = NULL;
405 cq_host->enabled = false;
408 static void cqhci_prep_task_desc(struct mmc_request *mrq,
409 u64 *data, bool intr)
411 u32 req_flags = mrq->data->flags;
413 *data = CQHCI_VALID(1) |
417 CQHCI_FORCED_PROG(!!(req_flags & MMC_DATA_FORCED_PRG)) |
418 CQHCI_DATA_TAG(!!(req_flags & MMC_DATA_DAT_TAG)) |
419 CQHCI_DATA_DIR(!!(req_flags & MMC_DATA_READ)) |
420 CQHCI_PRIORITY(!!(req_flags & MMC_DATA_PRIO)) |
421 CQHCI_QBAR(!!(req_flags & MMC_DATA_QBR)) |
422 CQHCI_REL_WRITE(!!(req_flags & MMC_DATA_REL_WR)) |
423 CQHCI_BLK_COUNT(mrq->data->blocks) |
424 CQHCI_BLK_ADDR((u64)mrq->data->blk_addr);
426 pr_debug("%s: cqhci: tag %d task descriptor 0x016%llx\n",
427 mmc_hostname(mrq->host), mrq->tag, (unsigned long long)*data);
430 static int cqhci_dma_map(struct mmc_host *host, struct mmc_request *mrq)
433 struct mmc_data *data = mrq->data;
438 sg_count = dma_map_sg(mmc_dev(host), data->sg,
440 (data->flags & MMC_DATA_WRITE) ?
441 DMA_TO_DEVICE : DMA_FROM_DEVICE);
443 pr_err("%s: sg-len: %d\n", __func__, data->sg_len);
450 static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end,
453 __le32 *attr = (__le32 __force *)desc;
455 *attr = (CQHCI_VALID(1) |
456 CQHCI_END(end ? 1 : 0) |
459 CQHCI_DAT_LENGTH(len));
462 __le64 *dataddr = (__le64 __force *)(desc + 4);
464 dataddr[0] = cpu_to_le64(addr);
466 __le32 *dataddr = (__le32 __force *)(desc + 4);
468 dataddr[0] = cpu_to_le32(addr);
472 static int cqhci_prep_tran_desc(struct mmc_request *mrq,
473 struct cqhci_host *cq_host, int tag)
475 struct mmc_data *data = mrq->data;
476 int i, sg_count, len;
478 bool dma64 = cq_host->dma64;
481 struct scatterlist *sg;
483 sg_count = cqhci_dma_map(mrq->host, mrq);
485 pr_err("%s: %s: unable to map sg lists, %d\n",
486 mmc_hostname(mrq->host), __func__, sg_count);
490 desc = get_trans_desc(cq_host, tag);
492 for_each_sg(data->sg, sg, sg_count, i) {
493 addr = sg_dma_address(sg);
494 len = sg_dma_len(sg);
496 if ((i+1) == sg_count)
498 cqhci_set_tran_desc(desc, addr, len, end, dma64);
499 desc += cq_host->trans_desc_len;
505 static void cqhci_prep_dcmd_desc(struct mmc_host *mmc,
506 struct mmc_request *mrq)
508 u64 *task_desc = NULL;
513 struct cqhci_host *cq_host = mmc->cqe_private;
516 if (!(mrq->cmd->flags & MMC_RSP_PRESENT)) {
520 if (mrq->cmd->flags & MMC_RSP_R1B) {
529 task_desc = (__le64 __force *)get_desc(cq_host, cq_host->dcmd_slot);
530 memset(task_desc, 0, cq_host->task_desc_len);
531 data |= (CQHCI_VALID(1) |
536 CQHCI_CMD_INDEX(mrq->cmd->opcode) |
537 CQHCI_CMD_TIMING(timing) | CQHCI_RESP_TYPE(resp_type));
538 if (cq_host->ops->update_dcmd_desc)
539 cq_host->ops->update_dcmd_desc(mmc, mrq, &data);
541 desc = (u8 *)task_desc;
542 pr_debug("%s: cqhci: dcmd: cmd: %d timing: %d resp: %d\n",
543 mmc_hostname(mmc), mrq->cmd->opcode, timing, resp_type);
544 dataddr = (__le64 __force *)(desc + 4);
545 dataddr[0] = cpu_to_le64((u64)mrq->cmd->arg);
549 static void cqhci_post_req(struct mmc_host *host, struct mmc_request *mrq)
551 struct mmc_data *data = mrq->data;
554 dma_unmap_sg(mmc_dev(host), data->sg, data->sg_len,
555 (data->flags & MMC_DATA_READ) ?
556 DMA_FROM_DEVICE : DMA_TO_DEVICE);
560 static inline int cqhci_tag(struct mmc_request *mrq)
562 return mrq->cmd ? DCMD_SLOT : mrq->tag;
565 static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
569 u64 *task_desc = NULL;
570 int tag = cqhci_tag(mrq);
571 struct cqhci_host *cq_host = mmc->cqe_private;
574 if (!cq_host->enabled) {
575 pr_err("%s: cqhci: not enabled\n", mmc_hostname(mmc));
579 /* First request after resume has to re-enable */
580 if (!cq_host->activated)
581 __cqhci_enable(cq_host);
584 cqhci_writel(cq_host, 0, CQHCI_CTL);
586 pr_debug("%s: cqhci: CQE on\n", mmc_hostname(mmc));
587 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) {
588 pr_err("%s: cqhci: CQE failed to exit halt state\n",
591 if (cq_host->ops->enable)
592 cq_host->ops->enable(mmc);
596 task_desc = (__le64 __force *)get_desc(cq_host, tag);
597 cqhci_prep_task_desc(mrq, &data, 1);
598 *task_desc = cpu_to_le64(data);
599 err = cqhci_prep_tran_desc(mrq, cq_host, tag);
601 pr_err("%s: cqhci: failed to setup tx desc: %d\n",
602 mmc_hostname(mmc), err);
606 cqhci_prep_dcmd_desc(mmc, mrq);
609 spin_lock_irqsave(&cq_host->lock, flags);
611 if (cq_host->recovery_halt) {
616 cq_host->slot[tag].mrq = mrq;
617 cq_host->slot[tag].flags = 0;
620 /* Make sure descriptors are ready before ringing the doorbell */
622 cqhci_writel(cq_host, 1 << tag, CQHCI_TDBR);
623 if (!(cqhci_readl(cq_host, CQHCI_TDBR) & (1 << tag)))
624 pr_debug("%s: cqhci: doorbell not set for tag %d\n",
625 mmc_hostname(mmc), tag);
627 spin_unlock_irqrestore(&cq_host->lock, flags);
630 cqhci_post_req(mmc, mrq);
635 static void cqhci_recovery_needed(struct mmc_host *mmc, struct mmc_request *mrq,
638 struct cqhci_host *cq_host = mmc->cqe_private;
640 if (!cq_host->recovery_halt) {
641 cq_host->recovery_halt = true;
642 pr_debug("%s: cqhci: recovery needed\n", mmc_hostname(mmc));
643 wake_up(&cq_host->wait_queue);
644 if (notify && mrq->recovery_notifier)
645 mrq->recovery_notifier(mrq);
649 static unsigned int cqhci_error_flags(int error1, int error2)
651 int error = error1 ? error1 : error2;
655 return CQHCI_HOST_CRC;
657 return CQHCI_HOST_TIMEOUT;
659 return CQHCI_HOST_OTHER;
663 static void cqhci_error_irq(struct mmc_host *mmc, u32 status, int cmd_error,
666 struct cqhci_host *cq_host = mmc->cqe_private;
667 struct cqhci_slot *slot;
671 spin_lock(&cq_host->lock);
673 terri = cqhci_readl(cq_host, CQHCI_TERRI);
675 pr_debug("%s: cqhci: error IRQ status: 0x%08x cmd error %d data error %d TERRI: 0x%08x\n",
676 mmc_hostname(mmc), status, cmd_error, data_error, terri);
678 /* Forget about errors when recovery has already been triggered */
679 if (cq_host->recovery_halt)
682 if (!cq_host->qcnt) {
683 WARN_ONCE(1, "%s: cqhci: error when idle. IRQ status: 0x%08x cmd error %d data error %d TERRI: 0x%08x\n",
684 mmc_hostname(mmc), status, cmd_error, data_error,
689 if (CQHCI_TERRI_C_VALID(terri)) {
690 tag = CQHCI_TERRI_C_TASK(terri);
691 slot = &cq_host->slot[tag];
693 slot->flags = cqhci_error_flags(cmd_error, data_error);
694 cqhci_recovery_needed(mmc, slot->mrq, true);
698 if (CQHCI_TERRI_D_VALID(terri)) {
699 tag = CQHCI_TERRI_D_TASK(terri);
700 slot = &cq_host->slot[tag];
702 slot->flags = cqhci_error_flags(data_error, cmd_error);
703 cqhci_recovery_needed(mmc, slot->mrq, true);
707 if (!cq_host->recovery_halt) {
709 * The only way to guarantee forward progress is to mark at
710 * least one task in error, so if none is indicated, pick one.
712 for (tag = 0; tag < NUM_SLOTS; tag++) {
713 slot = &cq_host->slot[tag];
716 slot->flags = cqhci_error_flags(data_error, cmd_error);
717 cqhci_recovery_needed(mmc, slot->mrq, true);
723 spin_unlock(&cq_host->lock);
726 static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag)
728 struct cqhci_host *cq_host = mmc->cqe_private;
729 struct cqhci_slot *slot = &cq_host->slot[tag];
730 struct mmc_request *mrq = slot->mrq;
731 struct mmc_data *data;
734 WARN_ONCE(1, "%s: cqhci: spurious TCN for tag %d\n",
735 mmc_hostname(mmc), tag);
739 /* No completions allowed during recovery */
740 if (cq_host->recovery_halt) {
741 slot->flags |= CQHCI_COMPLETED;
752 data->bytes_xfered = 0;
754 data->bytes_xfered = data->blksz * data->blocks;
757 mmc_cqe_request_done(mmc, mrq);
760 irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
764 unsigned long tag = 0, comp_status;
765 struct cqhci_host *cq_host = mmc->cqe_private;
767 status = cqhci_readl(cq_host, CQHCI_IS);
768 cqhci_writel(cq_host, status, CQHCI_IS);
770 pr_debug("%s: cqhci: IRQ status: 0x%08x\n", mmc_hostname(mmc), status);
772 if ((status & CQHCI_IS_RED) || cmd_error || data_error)
773 cqhci_error_irq(mmc, status, cmd_error, data_error);
775 if (status & CQHCI_IS_TCC) {
776 /* read TCN and complete the request */
777 comp_status = cqhci_readl(cq_host, CQHCI_TCN);
778 cqhci_writel(cq_host, comp_status, CQHCI_TCN);
779 pr_debug("%s: cqhci: TCN: 0x%08lx\n",
780 mmc_hostname(mmc), comp_status);
782 spin_lock(&cq_host->lock);
784 for_each_set_bit(tag, &comp_status, cq_host->num_slots) {
785 /* complete the corresponding mrq */
786 pr_debug("%s: cqhci: completing tag %lu\n",
787 mmc_hostname(mmc), tag);
788 cqhci_finish_mrq(mmc, tag);
791 if (cq_host->waiting_for_idle && !cq_host->qcnt) {
792 cq_host->waiting_for_idle = false;
793 wake_up(&cq_host->wait_queue);
796 spin_unlock(&cq_host->lock);
799 if (status & CQHCI_IS_TCL)
800 wake_up(&cq_host->wait_queue);
802 if (status & CQHCI_IS_HAC)
803 wake_up(&cq_host->wait_queue);
807 EXPORT_SYMBOL(cqhci_irq);
809 static bool cqhci_is_idle(struct cqhci_host *cq_host, int *ret)
814 spin_lock_irqsave(&cq_host->lock, flags);
815 is_idle = !cq_host->qcnt || cq_host->recovery_halt;
816 *ret = cq_host->recovery_halt ? -EBUSY : 0;
817 cq_host->waiting_for_idle = !is_idle;
818 spin_unlock_irqrestore(&cq_host->lock, flags);
823 static int cqhci_wait_for_idle(struct mmc_host *mmc)
825 struct cqhci_host *cq_host = mmc->cqe_private;
828 wait_event(cq_host->wait_queue, cqhci_is_idle(cq_host, &ret));
833 static bool cqhci_timeout(struct mmc_host *mmc, struct mmc_request *mrq,
834 bool *recovery_needed)
836 struct cqhci_host *cq_host = mmc->cqe_private;
837 int tag = cqhci_tag(mrq);
838 struct cqhci_slot *slot = &cq_host->slot[tag];
842 spin_lock_irqsave(&cq_host->lock, flags);
843 timed_out = slot->mrq == mrq;
845 slot->flags |= CQHCI_EXTERNAL_TIMEOUT;
846 cqhci_recovery_needed(mmc, mrq, false);
847 *recovery_needed = cq_host->recovery_halt;
849 spin_unlock_irqrestore(&cq_host->lock, flags);
852 pr_err("%s: cqhci: timeout for tag %d\n",
853 mmc_hostname(mmc), tag);
854 cqhci_dumpregs(cq_host);
860 static bool cqhci_tasks_cleared(struct cqhci_host *cq_host)
862 return !(cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_CLEAR_ALL_TASKS);
865 static bool cqhci_clear_all_tasks(struct mmc_host *mmc, unsigned int timeout)
867 struct cqhci_host *cq_host = mmc->cqe_private;
871 cqhci_set_irqs(cq_host, CQHCI_IS_TCL);
873 ctl = cqhci_readl(cq_host, CQHCI_CTL);
874 ctl |= CQHCI_CLEAR_ALL_TASKS;
875 cqhci_writel(cq_host, ctl, CQHCI_CTL);
877 wait_event_timeout(cq_host->wait_queue, cqhci_tasks_cleared(cq_host),
878 msecs_to_jiffies(timeout) + 1);
880 cqhci_set_irqs(cq_host, 0);
882 ret = cqhci_tasks_cleared(cq_host);
885 pr_debug("%s: cqhci: Failed to clear tasks\n",
891 static bool cqhci_halted(struct cqhci_host *cq_host)
893 return cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT;
896 static bool cqhci_halt(struct mmc_host *mmc, unsigned int timeout)
898 struct cqhci_host *cq_host = mmc->cqe_private;
902 if (cqhci_halted(cq_host))
905 cqhci_set_irqs(cq_host, CQHCI_IS_HAC);
907 ctl = cqhci_readl(cq_host, CQHCI_CTL);
909 cqhci_writel(cq_host, ctl, CQHCI_CTL);
911 wait_event_timeout(cq_host->wait_queue, cqhci_halted(cq_host),
912 msecs_to_jiffies(timeout) + 1);
914 cqhci_set_irqs(cq_host, 0);
916 ret = cqhci_halted(cq_host);
919 pr_debug("%s: cqhci: Failed to halt\n", mmc_hostname(mmc));
925 * After halting we expect to be able to use the command line. We interpret the
926 * failure to halt to mean the data lines might still be in use (and the upper
927 * layers will need to send a STOP command), so we set the timeout based on a
928 * generous command timeout.
930 #define CQHCI_START_HALT_TIMEOUT 5
932 static void cqhci_recovery_start(struct mmc_host *mmc)
934 struct cqhci_host *cq_host = mmc->cqe_private;
936 pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);
938 WARN_ON(!cq_host->recovery_halt);
940 cqhci_halt(mmc, CQHCI_START_HALT_TIMEOUT);
942 if (cq_host->ops->disable)
943 cq_host->ops->disable(mmc, true);
948 static int cqhci_error_from_flags(unsigned int flags)
953 /* CRC errors might indicate re-tuning so prefer to report that */
954 if (flags & CQHCI_HOST_CRC)
957 if (flags & (CQHCI_EXTERNAL_TIMEOUT | CQHCI_HOST_TIMEOUT))
963 static void cqhci_recover_mrq(struct cqhci_host *cq_host, unsigned int tag)
965 struct cqhci_slot *slot = &cq_host->slot[tag];
966 struct mmc_request *mrq = slot->mrq;
967 struct mmc_data *data;
978 data->bytes_xfered = 0;
979 data->error = cqhci_error_from_flags(slot->flags);
981 mrq->cmd->error = cqhci_error_from_flags(slot->flags);
984 mmc_cqe_request_done(cq_host->mmc, mrq);
987 static void cqhci_recover_mrqs(struct cqhci_host *cq_host)
991 for (i = 0; i < cq_host->num_slots; i++)
992 cqhci_recover_mrq(cq_host, i);
996 * By now the command and data lines should be unused so there is no reason for
997 * CQHCI to take a long time to halt, but if it doesn't halt there could be
998 * problems clearing tasks, so be generous.
1000 #define CQHCI_FINISH_HALT_TIMEOUT 20
1002 /* CQHCI could be expected to clear it's internal state pretty quickly */
1003 #define CQHCI_CLEAR_TIMEOUT 20
1005 static void cqhci_recovery_finish(struct mmc_host *mmc)
1007 struct cqhci_host *cq_host = mmc->cqe_private;
1008 unsigned long flags;
1012 pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);
1014 WARN_ON(!cq_host->recovery_halt);
1016 ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);
1018 if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))
1022 * The specification contradicts itself, by saying that tasks cannot be
1023 * cleared if CQHCI does not halt, but if CQHCI does not halt, it should
1024 * be disabled/re-enabled, but not to disable before clearing tasks.
1028 pr_debug("%s: cqhci: disable / re-enable\n", mmc_hostname(mmc));
1029 cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
1030 cqcfg &= ~CQHCI_ENABLE;
1031 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
1032 cqcfg |= CQHCI_ENABLE;
1033 cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
1034 /* Be sure that there are no tasks */
1035 ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);
1036 if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))
1041 cqhci_recover_mrqs(cq_host);
1043 WARN_ON(cq_host->qcnt);
1045 spin_lock_irqsave(&cq_host->lock, flags);
1047 cq_host->recovery_halt = false;
1048 mmc->cqe_on = false;
1049 spin_unlock_irqrestore(&cq_host->lock, flags);
1051 /* Ensure all writes are done before interrupts are re-enabled */
1054 cqhci_writel(cq_host, CQHCI_IS_HAC | CQHCI_IS_TCL, CQHCI_IS);
1056 cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
1058 pr_debug("%s: cqhci: recovery done\n", mmc_hostname(mmc));
1061 static const struct mmc_cqe_ops cqhci_cqe_ops = {
1062 .cqe_enable = cqhci_enable,
1063 .cqe_disable = cqhci_disable,
1064 .cqe_request = cqhci_request,
1065 .cqe_post_req = cqhci_post_req,
1066 .cqe_off = cqhci_off,
1067 .cqe_wait_for_idle = cqhci_wait_for_idle,
1068 .cqe_timeout = cqhci_timeout,
1069 .cqe_recovery_start = cqhci_recovery_start,
1070 .cqe_recovery_finish = cqhci_recovery_finish,
1073 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev)
1075 struct cqhci_host *cq_host;
1076 struct resource *cqhci_memres = NULL;
1078 /* check and setup CMDQ interface */
1079 cqhci_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1081 if (!cqhci_memres) {
1082 dev_dbg(&pdev->dev, "CMDQ not supported\n");
1083 return ERR_PTR(-EINVAL);
1086 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1088 return ERR_PTR(-ENOMEM);
1089 cq_host->mmio = devm_ioremap(&pdev->dev,
1090 cqhci_memres->start,
1091 resource_size(cqhci_memres));
1092 if (!cq_host->mmio) {
1093 dev_err(&pdev->dev, "failed to remap cqhci regs\n");
1094 return ERR_PTR(-EBUSY);
1096 dev_dbg(&pdev->dev, "CMDQ ioremap: done\n");
1100 EXPORT_SYMBOL(cqhci_pltfm_init);
1102 static unsigned int cqhci_ver_major(struct cqhci_host *cq_host)
1104 return CQHCI_VER_MAJOR(cqhci_readl(cq_host, CQHCI_VER));
1107 static unsigned int cqhci_ver_minor(struct cqhci_host *cq_host)
1109 u32 ver = cqhci_readl(cq_host, CQHCI_VER);
1111 return CQHCI_VER_MINOR1(ver) * 10 + CQHCI_VER_MINOR2(ver);
1114 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc,
1119 cq_host->dma64 = dma64;
1121 cq_host->mmc->cqe_private = cq_host;
1123 cq_host->num_slots = NUM_SLOTS;
1124 cq_host->dcmd_slot = DCMD_SLOT;
1126 mmc->cqe_ops = &cqhci_cqe_ops;
1128 mmc->cqe_qdepth = NUM_SLOTS;
1129 if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
1130 mmc->cqe_qdepth -= 1;
1132 cq_host->slot = devm_kcalloc(mmc_dev(mmc), cq_host->num_slots,
1133 sizeof(*cq_host->slot), GFP_KERNEL);
1134 if (!cq_host->slot) {
1139 spin_lock_init(&cq_host->lock);
1141 init_completion(&cq_host->halt_comp);
1142 init_waitqueue_head(&cq_host->wait_queue);
1144 pr_info("%s: CQHCI version %u.%02u\n",
1145 mmc_hostname(mmc), cqhci_ver_major(cq_host),
1146 cqhci_ver_minor(cq_host));
1151 pr_err("%s: CQHCI version %u.%02u failed to initialize, error %d\n",
1152 mmc_hostname(mmc), cqhci_ver_major(cq_host),
1153 cqhci_ver_minor(cq_host), err);
1156 EXPORT_SYMBOL(cqhci_init);
1158 MODULE_AUTHOR("Venkat Gopalakrishnan <venkatg@codeaurora.org>");
1159 MODULE_DESCRIPTION("Command Queue Host Controller Interface driver");
1160 MODULE_LICENSE("GPL v2");