drivers/misc/habanalabs/include/common/hl_boot_if.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2018-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HL_BOOT_IF_H
   9 #define HL_BOOT_IF_H
  10
  11 #define LKD_HARD_RESET_MAGIC            0xED7BD694 /* deprecated - do not use */
  12 #define HL_POWER9_HOST_MAGIC            0x1DA30009
  13
  14 #define BOOT_FIT_SRAM_OFFSET            0x200000
  15
  16 #define VERSION_MAX_LEN                 128
  17
  18 /*
  19  * CPU error bits in BOOT_ERROR registers
  20  *
  21  * CPU_BOOT_ERR0_DRAM_INIT_FAIL         DRAM initialization failed.
  22  *                                      DRAM is not reliable to use.
  23  *
  24  * CPU_BOOT_ERR0_FIT_CORRUPTED          FIT data integrity verification of the
  25  *                                      image provided by the host has failed.
  26  *
  27  * CPU_BOOT_ERR0_TS_INIT_FAIL           Thermal Sensor initialization failed.
  28  *                                      Boot continues as usual, but keep in
  29  *                                      mind this is a warning.
  30  *
  31  * CPU_BOOT_ERR0_DRAM_SKIPPED           DRAM initialization has been skipped.
  32  *                                      Skipping DRAM initialization has been
  33  *                                      requested (e.g. strap, command, etc.)
  34  *                                      and FW skipped the DRAM initialization.
  35  *                                      Host can initialize the DRAM.
  36  *
  37  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED       Waiting for BMC data will be skipped.
  38  *                                      Meaning the BMC data might not be
  39  *                                      available until reset.
  40  *
  41  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY       NIC data from BMC is not ready.
  42  *                                      BMC has not provided the NIC data yet.
  43  *                                      Once provided this bit will be cleared.
  44  *
  45  * CPU_BOOT_ERR0_NIC_FW_FAIL            NIC FW loading failed.
  46  *                                      The NIC FW loading and initialization
  47  *                                      failed. This means NICs are not usable.
  48  *
  49  * CPU_BOOT_ERR0_SECURITY_NOT_RDY       Chip security initialization has been
  50  *                                      started, but is not ready yet - chip
  51  *                                      cannot be accessed.
  52  *
  53  * CPU_BOOT_ERR0_SECURITY_FAIL          Security related tasks have failed.
  54  *                                      The tasks are security init (root of
  55  *                                      trust), boot authentication (chain of
  56  *                                      trust), data packets authentication.
  57  *
  58  * CPU_BOOT_ERR0_EFUSE_FAIL             Reading from eFuse failed.
  59  *                                      The PCI device ID might be wrong.
  60  *
  61  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL       Verification of primary image failed.
  62  *                                      It mean that ppboot checksum
  63  *                                      verification for the preboot primary
  64  *                                      image has failed to match expected
  65  *                                      checksum. Trying to program image again
  66  *                                      might solve this.
  67  *
  68  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL       Verification of secondary image failed.
  69  *                                      It mean that ppboot checksum
  70  *                                      verification for the preboot secondary
  71  *                                      image has failed to match expected
  72  *                                      checksum. Trying to program image again
  73  *                                      might solve this.
  74  *
  75  * CPU_BOOT_ERR0_PLL_FAIL               PLL settings failed, meaning that one
  76  *                                      of the PLLs remains in REF_CLK
  77  *
  78  * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL   Device is unusable and customer support
  79  *                                      should be contacted.
  80  *
  81  * CPU_BOOT_ERR0_ENABLED                Error registers enabled.
  82  *                                      This is a main indication that the
  83  *                                      running FW populates the error
  84  *                                      registers. Meaning the error bits are
  85  *                                      not garbage, but actual error statuses.
  86  */
  87 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL            (1 << 0)
  88 #define CPU_BOOT_ERR0_FIT_CORRUPTED             (1 << 1)
  89 #define CPU_BOOT_ERR0_TS_INIT_FAIL              (1 << 2)
  90 #define CPU_BOOT_ERR0_DRAM_SKIPPED              (1 << 3)
  91 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED          (1 << 4)
  92 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY          (1 << 5)
  93 #define CPU_BOOT_ERR0_NIC_FW_FAIL               (1 << 6)
  94 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY          (1 << 7)
  95 #define CPU_BOOT_ERR0_SECURITY_FAIL             (1 << 8)
  96 #define CPU_BOOT_ERR0_EFUSE_FAIL                (1 << 9)
  97 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL          (1 << 10)
  98 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL          (1 << 11)
  99 #define CPU_BOOT_ERR0_PLL_FAIL                  (1 << 12)
 100 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL      (1 << 13)
 101 #define CPU_BOOT_ERR0_ENABLED                   (1 << 31)
 102 #define CPU_BOOT_ERR1_ENABLED                   (1 << 31)
 103
 104 /*
 105  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
 106  *
 107  * CPU_BOOT_DEV_STS0_SECURITY_EN        Security is Enabled.
 108  *                                      This is an indication for security
 109  *                                      enabled in FW, which means that
 110  *                                      all conditions for security are met:
 111  *                                      device is indicated as security enabled,
 112  *                                      registers are protected, and device
 113  *                                      uses keys for image verification.
 114  *                                      Initialized in: preboot
 115  *
 116  * CPU_BOOT_DEV_STS0_DEBUG_EN           Debug is enabled.
 117  *                                      Enabled when JTAG or DEBUG is enabled
 118  *                                      in FW.
 119  *                                      Initialized in: preboot
 120  *
 121  * CPU_BOOT_DEV_STS0_WATCHDOG_EN        Watchdog is enabled.
 122  *                                      Watchdog is enabled in FW.
 123  *                                      Initialized in: preboot
 124  *
 125  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN       DRAM initialization is enabled.
 126  *                                      DRAM initialization has been done in FW.
 127  *                                      Initialized in: u-boot
 128  *
 129  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN        Waiting for BMC data enabled.
 130  *                                      If set, it means that during boot,
 131  *                                      FW waited for BMC data.
 132  *                                      Initialized in: u-boot
 133  *
 134  * CPU_BOOT_DEV_STS0_E2E_CRED_EN        E2E credits initialized.
 135  *                                      FW initialized E2E credits.
 136  *                                      Initialized in: u-boot
 137  *
 138  * CPU_BOOT_DEV_STS0_HBM_CRED_EN        HBM credits initialized.
 139  *                                      FW initialized HBM credits.
 140  *                                      Initialized in: u-boot
 141  *
 142  * CPU_BOOT_DEV_STS0_RL_EN              Rate limiter initialized.
 143  *                                      FW initialized rate limiter.
 144  *                                      Initialized in: u-boot
 145  *
 146  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN        SRAM scrambler enabled.
 147  *                                      FW initialized SRAM scrambler.
 148  *                                      Initialized in: linux
 149  *
 150  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN        DRAM scrambler enabled.
 151  *                                      FW initialized DRAM scrambler.
 152  *                                      Initialized in: u-boot
 153  *
 154  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN     FW hard reset procedure is enabled.
 155  *                                      FW has the hard reset procedure
 156  *                                      implemented. This means that FW will
 157  *                                      perform hard reset procedure on
 158  *                                      receiving the halt-machine event.
 159  *                                      Initialized in: preboot, u-boot, linux
 160  *
 161  * CPU_BOOT_DEV_STS0_PLL_INFO_EN        FW retrieval of PLL info is enabled.
 162  *                                      Initialized in: linux
 163  *
 164  * CPU_BOOT_DEV_STS0_SP_SRAM_EN         SP SRAM is initialized and available
 165  *                                      for use.
 166  *                                      Initialized in: preboot
 167  *
 168  * CPU_BOOT_DEV_STS0_CLK_GATE_EN        Clock Gating enabled.
 169  *                                      FW initialized Clock Gating.
 170  *                                      Initialized in: preboot
 171  *
 172  * CPU_BOOT_DEV_STS0_HBM_ECC_EN         HBM ECC handling Enabled.
 173  *                                      FW handles HBM ECC indications.
 174  *                                      Initialized in: linux
 175  *
 176  * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN      Packets ack value used in the armcpd
 177  *                                      is set to the PI counter.
 178  *                                      Initialized in: linux
 179  *
 180  * CPU_BOOT_DEV_STS0_FW_LD_COM_EN       Flexible FW loading communication
 181  *                                      protocol is enabled.
 182  *                                      Initialized in: preboot
 183  *
 184  * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN    FW iATU configuration is enabled.
 185  *                                      This bit if set, means the iATU has been
 186  *                                      configured and is ready for use.
 187  *                                      Initialized in: ppboot
 188  *
 189  * CPU_BOOT_DEV_STS0_DYN_PLL_EN         Dynamic PLL configuration is enabled.
 190  *                                      FW sends to host a bitmap of supported
 191  *                                      PLLs.
 192  *                                      Initialized in: linux
 193  *
 194  * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN  GIC access permission only from
 195  *                                      previleged entity. FW sets this status
 196  *                                      bit for host. If this bit is set then
 197  *                                      GIC can not be accessed from host.
 198  *                                      Initialized in: linux
 199  *
 200  * CPU_BOOT_DEV_STS0_EQ_INDEX_EN        Event Queue (EQ) index is a running
 201  *                                      index for each new event sent to host.
 202  *                                      This is used as a method in host to
 203  *                                      identify that the waiting event in
 204  *                                      queue is actually a new event which
 205  *                                      was not served before.
 206  *                                      Initialized in: linux
 207  *
 208  * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN  Use multiple scratchpad interfaces to
 209  *                                      prevent IRQs overriding each other.
 210  *                                      Initialized in: linux
 211  *
 212  * CPU_BOOT_DEV_STS0_ENABLED            Device status register enabled.
 213  *                                      This is a main indication that the
 214  *                                      running FW populates the device status
 215  *                                      register. Meaning the device status
 216  *                                      bits are not garbage, but actual
 217  *                                      statuses.
 218  *                                      Initialized in: preboot
 219  *
 220  */
 221 #define CPU_BOOT_DEV_STS0_SECURITY_EN                   (1 << 0)
 222 #define CPU_BOOT_DEV_STS0_DEBUG_EN                      (1 << 1)
 223 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN                   (1 << 2)
 224 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN                  (1 << 3)
 225 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN                   (1 << 4)
 226 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN                   (1 << 5)
 227 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN                   (1 << 6)
 228 #define CPU_BOOT_DEV_STS0_RL_EN                         (1 << 7)
 229 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN                   (1 << 8)
 230 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN                   (1 << 9)
 231 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN                (1 << 10)
 232 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN                   (1 << 11)
 233 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN                    (1 << 12)
 234 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN                   (1 << 13)
 235 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN                    (1 << 14)
 236 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN                 (1 << 15)
 237 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN                  (1 << 16)
 238 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN               (1 << 17)
 239 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN                    (1 << 19)
 240 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN             (1 << 20)
 241 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN                   (1 << 21)
 242 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN             (1 << 22)
 243 #define CPU_BOOT_DEV_STS0_ENABLED                       (1 << 31)
 244 #define CPU_BOOT_DEV_STS1_ENABLED                       (1 << 31)
 245
 246 enum cpu_boot_status {
 247         CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
 248         CPU_BOOT_STATUS_IN_WFE = 1,
 249         CPU_BOOT_STATUS_DRAM_RDY = 2,
 250         CPU_BOOT_STATUS_SRAM_AVAIL = 3,
 251         CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
 252         CPU_BOOT_STATUS_IN_PREBOOT = 5,
 253         CPU_BOOT_STATUS_IN_SPL,         /* deprecated - not reported */
 254         CPU_BOOT_STATUS_IN_UBOOT = 7,
 255         CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
 256         CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
 257         /* U-Boot console prompt activated, commands are not processed */
 258         CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
 259         /* Finished NICs init, reported after DRAM and NICs */
 260         CPU_BOOT_STATUS_NIC_FW_RDY = 11,
 261         CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
 262         CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
 263         CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
 264         /* Last boot loader progress status, ready to receive commands */
 265         CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 266         /* Internal Boot finished, ready for boot-fit */
 267         CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
 268         /* Internal Security has been initialized, device can be accessed */
 269         CPU_BOOT_STATUS_SECURITY_READY = 17,
 270 };
 271
 272 enum kmd_msg {
 273         KMD_MSG_NA = 0,
 274         KMD_MSG_GOTO_WFE,
 275         KMD_MSG_FIT_RDY,
 276         KMD_MSG_SKIP_BMC,
 277         RESERVED,
 278         KMD_MSG_RST_DEV,
 279         KMD_MSG_LAST
 280 };
 281
 282 enum cpu_msg_status {
 283         CPU_MSG_CLR = 0,
 284         CPU_MSG_OK,
 285         CPU_MSG_ERR,
 286 };
 287
 288 /* communication registers mapping - consider ABI when changing */
 289 struct cpu_dyn_regs {
 290         __le32 cpu_pq_base_addr_low;
 291         __le32 cpu_pq_base_addr_high;
 292         __le32 cpu_pq_length;
 293         __le32 cpu_pq_init_status;
 294         __le32 cpu_eq_base_addr_low;
 295         __le32 cpu_eq_base_addr_high;
 296         __le32 cpu_eq_length;
 297         __le32 cpu_eq_ci;
 298         __le32 cpu_cq_base_addr_low;
 299         __le32 cpu_cq_base_addr_high;
 300         __le32 cpu_cq_length;
 301         __le32 cpu_pf_pq_pi;
 302         __le32 cpu_boot_dev_sts0;
 303         __le32 cpu_boot_dev_sts1;
 304         __le32 cpu_boot_err0;
 305         __le32 cpu_boot_err1;
 306         __le32 cpu_boot_status;
 307         __le32 fw_upd_sts;
 308         __le32 fw_upd_cmd;
 309         __le32 fw_upd_pending_sts;
 310         __le32 fuse_ver_offset;
 311         __le32 preboot_ver_offset;
 312         __le32 uboot_ver_offset;
 313         __le32 hw_state;
 314         __le32 kmd_msg_to_cpu;
 315         __le32 cpu_cmd_status_to_host;
 316         union {
 317                 __le32 gic_host_irq_ctrl;
 318                 __le32 gic_host_pi_upd_irq;
 319         };
 320         __le32 gic_tpc_qm_irq_ctrl;
 321         __le32 gic_mme_qm_irq_ctrl;
 322         __le32 gic_dma_qm_irq_ctrl;
 323         __le32 gic_nic_qm_irq_ctrl;
 324         __le32 gic_dma_core_irq_ctrl;
 325         __le32 gic_host_halt_irq;
 326         __le32 gic_host_ints_irq;
 327         __le32 reserved1[24];           /* reserve for future use */
 328 };
 329
 330 /* TODO: remove the desc magic after the code is updated to use message */
 331 /* HCDM - Habana Communications Descriptor Magic */
 332 #define HL_COMMS_DESC_MAGIC     0x4843444D
 333 #define HL_COMMS_DESC_VER       1
 334
 335 /* HCMv - Habana Communications Message + header version */
 336 #define HL_COMMS_MSG_MAGIC_VALUE        0x48434D00
 337 #define HL_COMMS_MSG_MAGIC_MASK         0xFFFFFF00
 338 #define HL_COMMS_MSG_MAGIC_VER_MASK     0xFF
 339
 340 #define HL_COMMS_MSG_MAGIC_VER(ver)     (HL_COMMS_MSG_MAGIC_VALUE |     \
 341                                         ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 342 #define HL_COMMS_MSG_MAGIC_V0           HL_COMMS_DESC_MAGIC
 343 #define HL_COMMS_MSG_MAGIC_V1           HL_COMMS_MSG_MAGIC_VER(1)
 344
 345 #define HL_COMMS_MSG_MAGIC              HL_COMMS_MSG_MAGIC_V1
 346
 347 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic)                        \
 348                 (((magic) & HL_COMMS_MSG_MAGIC_MASK) ==                 \
 349                 HL_COMMS_MSG_MAGIC_VALUE)
 350
 351 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver)                 \
 352                 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >=             \
 353                 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 354
 355 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver)                         \
 356                 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) &&          \
 357                 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver)))
 358
 359 enum comms_msg_type {
 360         HL_COMMS_DESC_TYPE = 0,
 361         HL_COMMS_RESET_CAUSE_TYPE = 1,
 362 };
 363
 364 /* TODO: remove this struct after the code is updated to use message */
 365 /* this is the comms descriptor header - meta data */
 366 struct comms_desc_header {
 367         __le32 magic;           /* magic for validation */
 368         __le32 crc32;           /* CRC32 of the descriptor w/o header */
 369         __le16 size;            /* size of the descriptor w/o header */
 370         __u8 version;   /* descriptor version */
 371         __u8 reserved[5];       /* pad to 64 bit */
 372 };
 373
 374 /* this is the comms message header - meta data */
 375 struct comms_msg_header {
 376         __le32 magic;           /* magic for validation */
 377         __le32 crc32;           /* CRC32 of the message w/o header */
 378         __le16 size;            /* size of the message w/o header */
 379         __u8 version;   /* message payload version */
 380         __u8 type;              /* message type */
 381         __u8 reserved[4];       /* pad to 64 bit */
 382 };
 383
 384 /* this is the main FW descriptor - consider ABI when changing */
 385 struct lkd_fw_comms_desc {
 386         struct comms_desc_header header;
 387         struct cpu_dyn_regs cpu_dyn_regs;
 388         char fuse_ver[VERSION_MAX_LEN];
 389         char cur_fw_ver[VERSION_MAX_LEN];
 390         /* can be used for 1 more version w/o ABI change */
 391         char reserved0[VERSION_MAX_LEN];
 392         __le64 img_addr;        /* address for next FW component load */
 393 };
 394
 395 enum comms_reset_cause {
 396         HL_RESET_CAUSE_UNKNOWN = 0,
 397         HL_RESET_CAUSE_HEARTBEAT = 1,
 398         HL_RESET_CAUSE_TDR = 2,
 399 };
 400
 401 /* TODO: remove define after struct name is aligned on all projects */
 402 #define lkd_msg_comms lkd_fw_comms_msg
 403
 404 /* this is the comms message descriptor */
 405 struct lkd_fw_comms_msg {
 406         struct comms_msg_header header;
 407         /* union for future expantions of new messages */
 408         union {
 409                 struct {
 410                         struct cpu_dyn_regs cpu_dyn_regs;
 411                         char fuse_ver[VERSION_MAX_LEN];
 412                         char cur_fw_ver[VERSION_MAX_LEN];
 413                         /* can be used for 1 more version w/o ABI change */
 414                         char reserved0[VERSION_MAX_LEN];
 415                         /* address for next FW component load */
 416                         __le64 img_addr;
 417                 };
 418                 struct {
 419                         __u8 reset_cause;
 420                 };
 421         };
 422 };
 423
 424 /*
 425  * LKD commands:
 426  *
 427  * COMMS_NOOP                   Used to clear the command register and no actual
 428  *                              command is send.
 429  *
 430  * COMMS_CLR_STS                Clear status command - FW should clear the
 431  *                              status register. Used for synchronization
 432  *                              between the commands as part of the race free
 433  *                              protocol.
 434  *
 435  * COMMS_RST_STATE              Reset the current communication state which is
 436  *                              kept by FW for proper responses.
 437  *                              Should be used in the beginning of the
 438  *                              communication cycle to clean any leftovers from
 439  *                              previous communication attempts.
 440  *
 441  * COMMS_PREP_DESC              Prepare descriptor for setting up the
 442  *                              communication and other dynamic data:
 443  *                              struct lkd_fw_comms_desc.
 444  *                              This command has a parameter stating the next FW
 445  *                              component size, so the FW can actually prepare a
 446  *                              space for it and in the status response provide
 447  *                              the descriptor offset. The Offset of the next FW
 448  *                              data component is a part of the descriptor
 449  *                              structure.
 450  *
 451  * COMMS_DATA_RDY               The FW data has been uploaded and is ready for
 452  *                              validation.
 453  *
 454  * COMMS_EXEC                   Execute the next FW component.
 455  *
 456  * COMMS_RST_DEV                Reset the device.
 457  *
 458  * COMMS_GOTO_WFE               Execute WFE command. Allowed only on non-secure
 459  *                              devices.
 460  *
 461  * COMMS_SKIP_BMC               Perform actions required for BMC-less servers.
 462  *                              Do not wait for BMC response.
 463  *
 464  * COMMS_LOW_PLL_OPP            Initialize PLLs for low OPP.
 465  */
 466 enum comms_cmd {
 467         COMMS_NOOP = 0,
 468         COMMS_CLR_STS = 1,
 469         COMMS_RST_STATE = 2,
 470         COMMS_PREP_DESC = 3,
 471         COMMS_DATA_RDY = 4,
 472         COMMS_EXEC = 5,
 473         COMMS_RST_DEV = 6,
 474         COMMS_GOTO_WFE = 7,
 475         COMMS_SKIP_BMC = 8,
 476         COMMS_LOW_PLL_OPP = 9,
 477         COMMS_INVLD_LAST
 478 };
 479
 480 #define COMMS_COMMAND_SIZE_SHIFT        0
 481 #define COMMS_COMMAND_SIZE_MASK         0x1FFFFFF
 482 #define COMMS_COMMAND_CMD_SHIFT         27
 483 #define COMMS_COMMAND_CMD_MASK          0xF8000000
 484
 485 /*
 486  * LKD command to FW register structure
 487  * @size        - FW component size
 488  * @cmd         - command from enum comms_cmd
 489  */
 490 struct comms_command {
 491         union {         /* bit fields are only for FW use */
 492                 struct {
 493                         u32 size :25;           /* 32MB max. */
 494                         u32 reserved :2;
 495                         enum comms_cmd cmd :5;          /* 32 commands */
 496                 };
 497                 __le32 val;
 498         };
 499 };
 500
 501 /*
 502  * FW status
 503  *
 504  * COMMS_STS_NOOP               Used to clear the status register and no actual
 505  *                              status is provided.
 506  *
 507  * COMMS_STS_ACK                Command has been received and recognized.
 508  *
 509  * COMMS_STS_OK                 Command execution has finished successfully.
 510  *
 511  * COMMS_STS_ERR                Command execution was unsuccessful and resulted
 512  *                              in error.
 513  *
 514  * COMMS_STS_VALID_ERR          FW validation has failed.
 515  *
 516  * COMMS_STS_TIMEOUT_ERR        Command execution has timed out.
 517  */
 518 enum comms_sts {
 519         COMMS_STS_NOOP = 0,
 520         COMMS_STS_ACK = 1,
 521         COMMS_STS_OK = 2,
 522         COMMS_STS_ERR = 3,
 523         COMMS_STS_VALID_ERR = 4,
 524         COMMS_STS_TIMEOUT_ERR = 5,
 525         COMMS_STS_INVLD_LAST
 526 };
 527
 528 /* RAM types for FW components loading - defines the base address */
 529 enum comms_ram_types {
 530         COMMS_SRAM = 0,
 531         COMMS_DRAM = 1,
 532 };
 533
 534 #define COMMS_STATUS_OFFSET_SHIFT       0
 535 #define COMMS_STATUS_OFFSET_MASK        0x03FFFFFF
 536 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2
 537 #define COMMS_STATUS_RAM_TYPE_SHIFT     26
 538 #define COMMS_STATUS_RAM_TYPE_MASK      0x0C000000
 539 #define COMMS_STATUS_STATUS_SHIFT       28
 540 #define COMMS_STATUS_STATUS_MASK        0xF0000000
 541
 542 /*
 543  * FW status to LKD register structure
 544  * @offset      - an offset from the base of the ram_type shifted right by
 545  *                2 bits (always aligned to 32 bits).
 546  *                Allows a maximum addressable offset of 256MB from RAM base.
 547  *                Example: for real offset in RAM of 0x800000 (8MB), the value
 548  *                in offset field is (0x800000 >> 2) = 0x200000.
 549  * @ram_type    - the RAM type that should be used for offset from
 550  *                enum comms_ram_types
 551  * @status      - status from enum comms_sts
 552  */
 553 struct comms_status {
 554         union {         /* bit fields are only for FW use */
 555                 struct {
 556                         u32 offset :26;
 557                         enum comms_ram_types ram_type :2;
 558                         enum comms_sts status :4;       /* 16 statuses */
 559                 };
 560                 __le32 val;
 561         };
 562 };
 563
 564 #endif /* HL_BOOT_IF_H */