drivers/misc/habanalabs/include/common/hl_boot_if.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2018-2020 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HL_BOOT_IF_H
   9 #define HL_BOOT_IF_H
  10
  11 #define LKD_HARD_RESET_MAGIC            0xED7BD694 /* deprecated - do not use */
  12 #define HL_POWER9_HOST_MAGIC            0x1DA30009
  13
  14 #define BOOT_FIT_SRAM_OFFSET            0x200000
  15
  16 #define VERSION_MAX_LEN                 128
  17
  18 enum cpu_boot_err {
  19         CPU_BOOT_ERR_DRAM_INIT_FAIL = 0,
  20         CPU_BOOT_ERR_FIT_CORRUPTED = 1,
  21         CPU_BOOT_ERR_TS_INIT_FAIL = 2,
  22         CPU_BOOT_ERR_DRAM_SKIPPED = 3,
  23         CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4,
  24         CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5,
  25         CPU_BOOT_ERR_NIC_FW_FAIL = 6,
  26         CPU_BOOT_ERR_SECURITY_NOT_RDY = 7,
  27         CPU_BOOT_ERR_SECURITY_FAIL = 8,
  28         CPU_BOOT_ERR_EFUSE_FAIL = 9,
  29         CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10,
  30         CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11,
  31         CPU_BOOT_ERR_PLL_FAIL = 12,
  32         CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13,
  33         CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18,
  34         CPU_BOOT_ERR_BINNING_FAIL = 19,
  35         CPU_BOOT_ERR_TPM_FAIL = 20,
  36         CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21,
  37         CPU_BOOT_ERR_ENABLED = 31,
  38         CPU_BOOT_ERR_SCND_EN = 63,
  39         CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */
  40 };
  41
  42 /*
  43  * CPU error bits in BOOT_ERROR registers
  44  *
  45  * CPU_BOOT_ERR0_DRAM_INIT_FAIL         DRAM initialization failed.
  46  *                                      DRAM is not reliable to use.
  47  *
  48  * CPU_BOOT_ERR0_FIT_CORRUPTED          FIT data integrity verification of the
  49  *                                      image provided by the host has failed.
  50  *
  51  * CPU_BOOT_ERR0_TS_INIT_FAIL           Thermal Sensor initialization failed.
  52  *                                      Boot continues as usual, but keep in
  53  *                                      mind this is a warning.
  54  *
  55  * CPU_BOOT_ERR0_DRAM_SKIPPED           DRAM initialization has been skipped.
  56  *                                      Skipping DRAM initialization has been
  57  *                                      requested (e.g. strap, command, etc.)
  58  *                                      and FW skipped the DRAM initialization.
  59  *                                      Host can initialize the DRAM.
  60  *
  61  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED       Waiting for BMC data will be skipped.
  62  *                                      Meaning the BMC data might not be
  63  *                                      available until reset.
  64  *
  65  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY       NIC data from BMC is not ready.
  66  *                                      BMC has not provided the NIC data yet.
  67  *                                      Once provided this bit will be cleared.
  68  *
  69  * CPU_BOOT_ERR0_NIC_FW_FAIL            NIC FW loading failed.
  70  *                                      The NIC FW loading and initialization
  71  *                                      failed. This means NICs are not usable.
  72  *
  73  * CPU_BOOT_ERR0_SECURITY_NOT_RDY       Chip security initialization has been
  74  *                                      started, but is not ready yet - chip
  75  *                                      cannot be accessed.
  76  *
  77  * CPU_BOOT_ERR0_SECURITY_FAIL          Security related tasks have failed.
  78  *                                      The tasks are security init (root of
  79  *                                      trust), boot authentication (chain of
  80  *                                      trust), data packets authentication.
  81  *
  82  * CPU_BOOT_ERR0_EFUSE_FAIL             Reading from eFuse failed.
  83  *                                      The PCI device ID might be wrong.
  84  *
  85  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL       Verification of primary image failed.
  86  *                                      It mean that ppboot checksum
  87  *                                      verification for the preboot primary
  88  *                                      image has failed to match expected
  89  *                                      checksum. Trying to program image again
  90  *                                      might solve this.
  91  *
  92  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL       Verification of secondary image failed.
  93  *                                      It mean that ppboot checksum
  94  *                                      verification for the preboot secondary
  95  *                                      image has failed to match expected
  96  *                                      checksum. Trying to program image again
  97  *                                      might solve this.
  98  *
  99  * CPU_BOOT_ERR0_PLL_FAIL               PLL settings failed, meaning that one
 100  *                                      of the PLLs remains in REF_CLK
 101  *
 102  * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL   Device is unusable and customer support
 103  *                                      should be contacted.
 104  *
 105  * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR       Critical error was detected during
 106  *                                      the execution of ppboot or preboot.
 107  *                                      for example: stack overflow.
 108  *
 109  * CPU_BOOT_ERR0_BINNING_FAIL           Binning settings failed, meaning
 110  *                                      malfunctioning components might still be
 111  *                                      in use.
 112  *
 113  * CPU_BOOT_ERR0_TPM_FAIL               TPM verification flow failed.
 114  *
 115  * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL   Failed to set threshold for tmperature
 116  *                                      sensor.
 117  *
 118  * CPU_BOOT_ERR0_ENABLED                Error registers enabled.
 119  *                                      This is a main indication that the
 120  *                                      running FW populates the error
 121  *                                      registers. Meaning the error bits are
 122  *                                      not garbage, but actual error statuses.
 123  */
 124 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL            (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL)
 125 #define CPU_BOOT_ERR0_FIT_CORRUPTED             (1 << CPU_BOOT_ERR_FIT_CORRUPTED)
 126 #define CPU_BOOT_ERR0_TS_INIT_FAIL              (1 << CPU_BOOT_ERR_TS_INIT_FAIL)
 127 #define CPU_BOOT_ERR0_DRAM_SKIPPED              (1 << CPU_BOOT_ERR_DRAM_SKIPPED)
 128 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED          (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED)
 129 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY          (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY)
 130 #define CPU_BOOT_ERR0_NIC_FW_FAIL               (1 << CPU_BOOT_ERR_NIC_FW_FAIL)
 131 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY          (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY)
 132 #define CPU_BOOT_ERR0_SECURITY_FAIL             (1 << CPU_BOOT_ERR_SECURITY_FAIL)
 133 #define CPU_BOOT_ERR0_EFUSE_FAIL                (1 << CPU_BOOT_ERR_EFUSE_FAIL)
 134 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL)
 135 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL)
 136 #define CPU_BOOT_ERR0_PLL_FAIL                  (1 << CPU_BOOT_ERR_PLL_FAIL)
 137 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL      (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL)
 138 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR          (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR)
 139 #define CPU_BOOT_ERR0_BINNING_FAIL              (1 << CPU_BOOT_ERR_BINNING_FAIL)
 140 #define CPU_BOOT_ERR0_TPM_FAIL                  (1 << CPU_BOOT_ERR_TPM_FAIL)
 141 #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL      (1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL)
 142 #define CPU_BOOT_ERR0_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 143 #define CPU_BOOT_ERR1_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 144
 145 enum cpu_boot_dev_sts {
 146         CPU_BOOT_DEV_STS_SECURITY_EN = 0,
 147         CPU_BOOT_DEV_STS_DEBUG_EN = 1,
 148         CPU_BOOT_DEV_STS_WATCHDOG_EN = 2,
 149         CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3,
 150         CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4,
 151         CPU_BOOT_DEV_STS_E2E_CRED_EN = 5,
 152         CPU_BOOT_DEV_STS_HBM_CRED_EN = 6,
 153         CPU_BOOT_DEV_STS_RL_EN = 7,
 154         CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8,
 155         CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9,
 156         CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10,
 157         CPU_BOOT_DEV_STS_PLL_INFO_EN = 11,
 158         CPU_BOOT_DEV_STS_SP_SRAM_EN = 12,
 159         CPU_BOOT_DEV_STS_CLK_GATE_EN = 13,
 160         CPU_BOOT_DEV_STS_HBM_ECC_EN = 14,
 161         CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15,
 162         CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16,
 163         CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17,
 164         CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18,
 165         CPU_BOOT_DEV_STS_DYN_PLL_EN = 19,
 166         CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20,
 167         CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21,
 168         CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22,
 169         CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23,
 170         CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24,
 171         CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25,
 172         CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26,
 173         CPU_BOOT_DEV_STS_ENABLED = 31,
 174         CPU_BOOT_DEV_STS_SCND_EN = 63,
 175         CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */
 176 };
 177
 178 /*
 179  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
 180  *
 181  * CPU_BOOT_DEV_STS0_SECURITY_EN        Security is Enabled.
 182  *                                      This is an indication for security
 183  *                                      enabled in FW, which means that
 184  *                                      all conditions for security are met:
 185  *                                      device is indicated as security enabled,
 186  *                                      registers are protected, and device
 187  *                                      uses keys for image verification.
 188  *                                      Initialized in: preboot
 189  *
 190  * CPU_BOOT_DEV_STS0_DEBUG_EN           Debug is enabled.
 191  *                                      Enabled when JTAG or DEBUG is enabled
 192  *                                      in FW.
 193  *                                      Initialized in: preboot
 194  *
 195  * CPU_BOOT_DEV_STS0_WATCHDOG_EN        Watchdog is enabled.
 196  *                                      Watchdog is enabled in FW.
 197  *                                      Initialized in: preboot
 198  *
 199  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN       DRAM initialization is enabled.
 200  *                                      DRAM initialization has been done in FW.
 201  *                                      Initialized in: u-boot
 202  *
 203  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN        Waiting for BMC data enabled.
 204  *                                      If set, it means that during boot,
 205  *                                      FW waited for BMC data.
 206  *                                      Initialized in: u-boot
 207  *
 208  * CPU_BOOT_DEV_STS0_E2E_CRED_EN        E2E credits initialized.
 209  *                                      FW initialized E2E credits.
 210  *                                      Initialized in: u-boot
 211  *
 212  * CPU_BOOT_DEV_STS0_HBM_CRED_EN        HBM credits initialized.
 213  *                                      FW initialized HBM credits.
 214  *                                      Initialized in: u-boot
 215  *
 216  * CPU_BOOT_DEV_STS0_RL_EN              Rate limiter initialized.
 217  *                                      FW initialized rate limiter.
 218  *                                      Initialized in: u-boot
 219  *
 220  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN        SRAM scrambler enabled.
 221  *                                      FW initialized SRAM scrambler.
 222  *                                      Initialized in: linux
 223  *
 224  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN        DRAM scrambler enabled.
 225  *                                      FW initialized DRAM scrambler.
 226  *                                      Initialized in: u-boot
 227  *
 228  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN     FW hard reset procedure is enabled.
 229  *                                      FW has the hard reset procedure
 230  *                                      implemented. This means that FW will
 231  *                                      perform hard reset procedure on
 232  *                                      receiving the halt-machine event.
 233  *                                      Initialized in: preboot, u-boot, linux
 234  *
 235  * CPU_BOOT_DEV_STS0_PLL_INFO_EN        FW retrieval of PLL info is enabled.
 236  *                                      Initialized in: linux
 237  *
 238  * CPU_BOOT_DEV_STS0_SP_SRAM_EN         SP SRAM is initialized and available
 239  *                                      for use.
 240  *                                      Initialized in: preboot
 241  *
 242  * CPU_BOOT_DEV_STS0_CLK_GATE_EN        Clock Gating enabled.
 243  *                                      FW initialized Clock Gating.
 244  *                                      Initialized in: preboot
 245  *
 246  * CPU_BOOT_DEV_STS0_HBM_ECC_EN         HBM ECC handling Enabled.
 247  *                                      FW handles HBM ECC indications.
 248  *                                      Initialized in: linux
 249  *
 250  * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN      Packets ack value used in the armcpd
 251  *                                      is set to the PI counter.
 252  *                                      Initialized in: linux
 253  *
 254  * CPU_BOOT_DEV_STS0_FW_LD_COM_EN       Flexible FW loading communication
 255  *                                      protocol is enabled.
 256  *                                      Initialized in: preboot
 257  *
 258  * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN    FW iATU configuration is enabled.
 259  *                                      This bit if set, means the iATU has been
 260  *                                      configured and is ready for use.
 261  *                                      Initialized in: ppboot
 262  *
 263  * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN      NIC MAC channels init is done by FW and
 264  *                                      any access to them is done via the FW.
 265  *                                      Initialized in: linux
 266  *
 267  * CPU_BOOT_DEV_STS0_DYN_PLL_EN         Dynamic PLL configuration is enabled.
 268  *                                      FW sends to host a bitmap of supported
 269  *                                      PLLs.
 270  *                                      Initialized in: linux
 271  *
 272  * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN  GIC access permission only from
 273  *                                      previleged entity. FW sets this status
 274  *                                      bit for host. If this bit is set then
 275  *                                      GIC can not be accessed from host.
 276  *                                      Initialized in: linux
 277  *
 278  * CPU_BOOT_DEV_STS0_EQ_INDEX_EN        Event Queue (EQ) index is a running
 279  *                                      index for each new event sent to host.
 280  *                                      This is used as a method in host to
 281  *                                      identify that the waiting event in
 282  *                                      queue is actually a new event which
 283  *                                      was not served before.
 284  *                                      Initialized in: linux
 285  *
 286  * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN  Use multiple scratchpad interfaces to
 287  *                                      prevent IRQs overriding each other.
 288  *                                      Initialized in: linux
 289  *
 290  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN
 291  *                                      NIC STAT and XPCS91 access is restricted
 292  *                                      and is done via FW only.
 293  *                                      Initialized in: linux
 294  *
 295  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN
 296  *                                      NIC STAT get all is supported.
 297  *                                      Initialized in: linux
 298  *
 299  * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN
 300  *                                      F/W checks if the device is idle by reading defined set
 301  *                                      of registers. It returns a bitmask of all the engines,
 302  *                                      where a bit is set if the engine is not idle.
 303  *                                      Initialized in: linux
 304  *
 305  * CPU_BOOT_DEV_STS0_MAP_HWMON_EN
 306  *                                      If set, means f/w supports proprietary
 307  *                                      HWMON enum mapping to cpucp enums.
 308  *                                      Initialized in: linux
 309  *
 310  * CPU_BOOT_DEV_STS0_ENABLED            Device status register enabled.
 311  *                                      This is a main indication that the
 312  *                                      running FW populates the device status
 313  *                                      register. Meaning the device status
 314  *                                      bits are not garbage, but actual
 315  *                                      statuses.
 316  *                                      Initialized in: preboot
 317  *
 318  */
 319 #define CPU_BOOT_DEV_STS0_SECURITY_EN           (1 << CPU_BOOT_DEV_STS_SECURITY_EN)
 320 #define CPU_BOOT_DEV_STS0_DEBUG_EN              (1 << CPU_BOOT_DEV_STS_DEBUG_EN)
 321 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN           (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN)
 322 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN          (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN)
 323 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN           (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN)
 324 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN           (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN)
 325 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN           (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN)
 326 #define CPU_BOOT_DEV_STS0_RL_EN                 (1 << CPU_BOOT_DEV_STS_RL_EN)
 327 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN)
 328 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN)
 329 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN        (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN)
 330 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN           (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN)
 331 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN            (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN)
 332 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN           (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN)
 333 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN            (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN)
 334 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN         (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN)
 335 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN          (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN)
 336 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN       (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN)
 337 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN         (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN)
 338 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN            (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN)
 339 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN     (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN)
 340 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN           (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN)
 341 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN     (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN)
 342 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN)
 343 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN    (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN)
 344 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN      (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN)
 345 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN          (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN)
 346 #define CPU_BOOT_DEV_STS0_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 347 #define CPU_BOOT_DEV_STS1_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 348
 349 enum cpu_boot_status {
 350         CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
 351         CPU_BOOT_STATUS_IN_WFE = 1,
 352         CPU_BOOT_STATUS_DRAM_RDY = 2,
 353         CPU_BOOT_STATUS_SRAM_AVAIL = 3,
 354         CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
 355         CPU_BOOT_STATUS_IN_PREBOOT = 5,
 356         CPU_BOOT_STATUS_IN_SPL,         /* deprecated - not reported */
 357         CPU_BOOT_STATUS_IN_UBOOT = 7,
 358         CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
 359         CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
 360         /* U-Boot console prompt activated, commands are not processed */
 361         CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
 362         /* Finished NICs init, reported after DRAM and NICs */
 363         CPU_BOOT_STATUS_NIC_FW_RDY = 11,
 364         CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
 365         CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
 366         CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
 367         /* Last boot loader progress status, ready to receive commands */
 368         CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 369         /* Internal Boot finished, ready for boot-fit */
 370         CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
 371         /* Internal Security has been initialized, device can be accessed */
 372         CPU_BOOT_STATUS_SECURITY_READY = 17,
 373 };
 374
 375 enum kmd_msg {
 376         KMD_MSG_NA = 0,
 377         KMD_MSG_GOTO_WFE,
 378         KMD_MSG_FIT_RDY,
 379         KMD_MSG_SKIP_BMC,
 380         RESERVED,
 381         KMD_MSG_RST_DEV,
 382         KMD_MSG_LAST
 383 };
 384
 385 enum cpu_msg_status {
 386         CPU_MSG_CLR = 0,
 387         CPU_MSG_OK,
 388         CPU_MSG_ERR,
 389 };
 390
 391 /* communication registers mapping - consider ABI when changing */
 392 struct cpu_dyn_regs {
 393         __le32 cpu_pq_base_addr_low;
 394         __le32 cpu_pq_base_addr_high;
 395         __le32 cpu_pq_length;
 396         __le32 cpu_pq_init_status;
 397         __le32 cpu_eq_base_addr_low;
 398         __le32 cpu_eq_base_addr_high;
 399         __le32 cpu_eq_length;
 400         __le32 cpu_eq_ci;
 401         __le32 cpu_cq_base_addr_low;
 402         __le32 cpu_cq_base_addr_high;
 403         __le32 cpu_cq_length;
 404         __le32 cpu_pf_pq_pi;
 405         __le32 cpu_boot_dev_sts0;
 406         __le32 cpu_boot_dev_sts1;
 407         __le32 cpu_boot_err0;
 408         __le32 cpu_boot_err1;
 409         __le32 cpu_boot_status;
 410         __le32 fw_upd_sts;
 411         __le32 fw_upd_cmd;
 412         __le32 fw_upd_pending_sts;
 413         __le32 fuse_ver_offset;
 414         __le32 preboot_ver_offset;
 415         __le32 uboot_ver_offset;
 416         __le32 hw_state;
 417         __le32 kmd_msg_to_cpu;
 418         __le32 cpu_cmd_status_to_host;
 419         __le32 gic_host_pi_upd_irq;
 420         __le32 gic_tpc_qm_irq_ctrl;
 421         __le32 gic_mme_qm_irq_ctrl;
 422         __le32 gic_dma_qm_irq_ctrl;
 423         __le32 gic_nic_qm_irq_ctrl;
 424         __le32 gic_dma_core_irq_ctrl;
 425         __le32 gic_host_halt_irq;
 426         __le32 gic_host_ints_irq;
 427         __le32 gic_host_soft_rst_irq;
 428         __le32 gic_rot_qm_irq_ctrl;
 429         __le32 reserved1[22];           /* reserve for future use */
 430 };
 431
 432 /* TODO: remove the desc magic after the code is updated to use message */
 433 /* HCDM - Habana Communications Descriptor Magic */
 434 #define HL_COMMS_DESC_MAGIC     0x4843444D
 435 #define HL_COMMS_DESC_VER       1
 436
 437 /* HCMv - Habana Communications Message + header version */
 438 #define HL_COMMS_MSG_MAGIC_VALUE        0x48434D00
 439 #define HL_COMMS_MSG_MAGIC_MASK         0xFFFFFF00
 440 #define HL_COMMS_MSG_MAGIC_VER_MASK     0xFF
 441
 442 #define HL_COMMS_MSG_MAGIC_VER(ver)     (HL_COMMS_MSG_MAGIC_VALUE |     \
 443                                         ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 444 #define HL_COMMS_MSG_MAGIC_V0           HL_COMMS_DESC_MAGIC
 445 #define HL_COMMS_MSG_MAGIC_V1           HL_COMMS_MSG_MAGIC_VER(1)
 446
 447 #define HL_COMMS_MSG_MAGIC              HL_COMMS_MSG_MAGIC_V1
 448
 449 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic)                        \
 450                 (((magic) & HL_COMMS_MSG_MAGIC_MASK) ==                 \
 451                 HL_COMMS_MSG_MAGIC_VALUE)
 452
 453 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver)                 \
 454                 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >=             \
 455                 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 456
 457 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver)                         \
 458                 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) &&          \
 459                 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver)))
 460
 461 enum comms_msg_type {
 462         HL_COMMS_DESC_TYPE = 0,
 463         HL_COMMS_RESET_CAUSE_TYPE = 1,
 464         HL_COMMS_FW_CFG_SKIP_TYPE = 2,
 465         HL_COMMS_BINNING_CONF_TYPE = 3,
 466 };
 467
 468 /* TODO: remove this struct after the code is updated to use message */
 469 /* this is the comms descriptor header - meta data */
 470 struct comms_desc_header {
 471         __le32 magic;           /* magic for validation */
 472         __le32 crc32;           /* CRC32 of the descriptor w/o header */
 473         __le16 size;            /* size of the descriptor w/o header */
 474         __u8 version;   /* descriptor version */
 475         __u8 reserved[5];       /* pad to 64 bit */
 476 };
 477
 478 /* this is the comms message header - meta data */
 479 struct comms_msg_header {
 480         __le32 magic;           /* magic for validation */
 481         __le32 crc32;           /* CRC32 of the message w/o header */
 482         __le16 size;            /* size of the message w/o header */
 483         __u8 version;   /* message payload version */
 484         __u8 type;              /* message type */
 485         __u8 reserved[4];       /* pad to 64 bit */
 486 };
 487
 488 /* this is the main FW descriptor - consider ABI when changing */
 489 struct lkd_fw_comms_desc {
 490         struct comms_desc_header header;
 491         struct cpu_dyn_regs cpu_dyn_regs;
 492         char fuse_ver[VERSION_MAX_LEN];
 493         char cur_fw_ver[VERSION_MAX_LEN];
 494         /* can be used for 1 more version w/o ABI change */
 495         char reserved0[VERSION_MAX_LEN];
 496         __le64 img_addr;        /* address for next FW component load */
 497 };
 498
 499 enum comms_reset_cause {
 500         HL_RESET_CAUSE_UNKNOWN = 0,
 501         HL_RESET_CAUSE_HEARTBEAT = 1,
 502         HL_RESET_CAUSE_TDR = 2,
 503 };
 504
 505 /* TODO: remove define after struct name is aligned on all projects */
 506 #define lkd_msg_comms lkd_fw_comms_msg
 507
 508 /* this is the comms message descriptor */
 509 struct lkd_fw_comms_msg {
 510         struct comms_msg_header header;
 511         /* union for future expantions of new messages */
 512         union {
 513                 struct {
 514                         struct cpu_dyn_regs cpu_dyn_regs;
 515                         char fuse_ver[VERSION_MAX_LEN];
 516                         char cur_fw_ver[VERSION_MAX_LEN];
 517                         /* can be used for 1 more version w/o ABI change */
 518                         char reserved0[VERSION_MAX_LEN];
 519                         /* address for next FW component load */
 520                         __le64 img_addr;
 521                 };
 522                 struct {
 523                         __u8 reset_cause;
 524                 };
 525                 struct {
 526                         __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */
 527                 };
 528         };
 529 };
 530
 531 /*
 532  * LKD commands:
 533  *
 534  * COMMS_NOOP                   Used to clear the command register and no actual
 535  *                              command is send.
 536  *
 537  * COMMS_CLR_STS                Clear status command - FW should clear the
 538  *                              status register. Used for synchronization
 539  *                              between the commands as part of the race free
 540  *                              protocol.
 541  *
 542  * COMMS_RST_STATE              Reset the current communication state which is
 543  *                              kept by FW for proper responses.
 544  *                              Should be used in the beginning of the
 545  *                              communication cycle to clean any leftovers from
 546  *                              previous communication attempts.
 547  *
 548  * COMMS_PREP_DESC              Prepare descriptor for setting up the
 549  *                              communication and other dynamic data:
 550  *                              struct lkd_fw_comms_desc.
 551  *                              This command has a parameter stating the next FW
 552  *                              component size, so the FW can actually prepare a
 553  *                              space for it and in the status response provide
 554  *                              the descriptor offset. The Offset of the next FW
 555  *                              data component is a part of the descriptor
 556  *                              structure.
 557  *
 558  * COMMS_DATA_RDY               The FW data has been uploaded and is ready for
 559  *                              validation.
 560  *
 561  * COMMS_EXEC                   Execute the next FW component.
 562  *
 563  * COMMS_RST_DEV                Reset the device.
 564  *
 565  * COMMS_GOTO_WFE               Execute WFE command. Allowed only on non-secure
 566  *                              devices.
 567  *
 568  * COMMS_SKIP_BMC               Perform actions required for BMC-less servers.
 569  *                              Do not wait for BMC response.
 570  *
 571  * COMMS_PREP_DESC_ELBI         Same as COMMS_PREP_DESC only that the memory
 572  *                              space is allocated in a ELBI access only
 573  *                              address range.
 574  *
 575  */
 576 enum comms_cmd {
 577         COMMS_NOOP = 0,
 578         COMMS_CLR_STS = 1,
 579         COMMS_RST_STATE = 2,
 580         COMMS_PREP_DESC = 3,
 581         COMMS_DATA_RDY = 4,
 582         COMMS_EXEC = 5,
 583         COMMS_RST_DEV = 6,
 584         COMMS_GOTO_WFE = 7,
 585         COMMS_SKIP_BMC = 8,
 586         COMMS_PREP_DESC_ELBI = 10,
 587         COMMS_INVLD_LAST
 588 };
 589
 590 #define COMMS_COMMAND_SIZE_SHIFT        0
 591 #define COMMS_COMMAND_SIZE_MASK         0x1FFFFFF
 592 #define COMMS_COMMAND_CMD_SHIFT         27
 593 #define COMMS_COMMAND_CMD_MASK          0xF8000000
 594
 595 /*
 596  * LKD command to FW register structure
 597  * @size        - FW component size
 598  * @cmd         - command from enum comms_cmd
 599  */
 600 struct comms_command {
 601         union {         /* bit fields are only for FW use */
 602                 struct {
 603                         u32 size :25;           /* 32MB max. */
 604                         u32 reserved :2;
 605                         enum comms_cmd cmd :5;          /* 32 commands */
 606                 };
 607                 __le32 val;
 608         };
 609 };
 610
 611 /*
 612  * FW status
 613  *
 614  * COMMS_STS_NOOP               Used to clear the status register and no actual
 615  *                              status is provided.
 616  *
 617  * COMMS_STS_ACK                Command has been received and recognized.
 618  *
 619  * COMMS_STS_OK                 Command execution has finished successfully.
 620  *
 621  * COMMS_STS_ERR                Command execution was unsuccessful and resulted
 622  *                              in error.
 623  *
 624  * COMMS_STS_VALID_ERR          FW validation has failed.
 625  *
 626  * COMMS_STS_TIMEOUT_ERR        Command execution has timed out.
 627  */
 628 enum comms_sts {
 629         COMMS_STS_NOOP = 0,
 630         COMMS_STS_ACK = 1,
 631         COMMS_STS_OK = 2,
 632         COMMS_STS_ERR = 3,
 633         COMMS_STS_VALID_ERR = 4,
 634         COMMS_STS_TIMEOUT_ERR = 5,
 635         COMMS_STS_INVLD_LAST
 636 };
 637
 638 /* RAM types for FW components loading - defines the base address */
 639 enum comms_ram_types {
 640         COMMS_SRAM = 0,
 641         COMMS_DRAM = 1,
 642 };
 643
 644 #define COMMS_STATUS_OFFSET_SHIFT       0
 645 #define COMMS_STATUS_OFFSET_MASK        0x03FFFFFF
 646 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2
 647 #define COMMS_STATUS_RAM_TYPE_SHIFT     26
 648 #define COMMS_STATUS_RAM_TYPE_MASK      0x0C000000
 649 #define COMMS_STATUS_STATUS_SHIFT       28
 650 #define COMMS_STATUS_STATUS_MASK        0xF0000000
 651
 652 /*
 653  * FW status to LKD register structure
 654  * @offset      - an offset from the base of the ram_type shifted right by
 655  *                2 bits (always aligned to 32 bits).
 656  *                Allows a maximum addressable offset of 256MB from RAM base.
 657  *                Example: for real offset in RAM of 0x800000 (8MB), the value
 658  *                in offset field is (0x800000 >> 2) = 0x200000.
 659  * @ram_type    - the RAM type that should be used for offset from
 660  *                enum comms_ram_types
 661  * @status      - status from enum comms_sts
 662  */
 663 struct comms_status {
 664         union {         /* bit fields are only for FW use */
 665                 struct {
 666                         u32 offset :26;
 667                         enum comms_ram_types ram_type :2;
 668                         enum comms_sts status :4;       /* 16 statuses */
 669                 };
 670                 __le32 val;
 671         };
 672 };
 673
 674 #endif /* HL_BOOT_IF_H */