1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/if_ether.h>
14 #include "hl_boot_if.h"
16 #define NUM_HBM_PSEUDO_CH 2
17 #define NUM_HBM_CH_PER_DEV 8
18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0
19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001
20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1
21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002
22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2
23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004
24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3
25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008
26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4
27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010
28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5
29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020
30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6
31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0
33 #define PLL_MAP_MAX_BITS 128
34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8)
37 * info of the pkt queue pointers in the first async occurrence
39 struct cpucp_pkt_sync_err {
44 struct hl_eq_hbm_ecc_data {
49 /* Supplemental Information according to the mask bits */
51 /* Address in hbm where the ecc happened */
53 /* SERR continuous address counter */
67 struct hl_eq_ecc_data {
70 __u8 memory_wrapper_idx;
74 enum hl_sm_sei_cause {
76 SM_SEI_LBW_4B_UNALIGNED,
77 SM_SEI_AXI_RESPONSE_ERR
80 struct hl_eq_sm_sei_data {
82 /* enum hl_sm_sei_cause */
87 enum hl_fw_alive_severity {
88 FW_ALIVE_SEVERITY_MINOR,
89 FW_ALIVE_SEVERITY_CRITICAL
92 struct hl_eq_fw_alive {
93 __le64 uptime_seconds;
96 /* enum hl_fw_alive_severity */
102 struct hl_eq_header hdr;
104 struct hl_eq_ecc_data ecc_data;
105 struct hl_eq_hbm_ecc_data hbm_ecc_data;
106 struct hl_eq_sm_sei_data sm_sei_data;
107 struct cpucp_pkt_sync_err pkt_sync_err;
108 struct hl_eq_fw_alive fw_alive;
113 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry)
115 #define EQ_CTL_READY_SHIFT 31
116 #define EQ_CTL_READY_MASK 0x80000000
118 #define EQ_CTL_EVENT_TYPE_SHIFT 16
119 #define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000
121 #define EQ_CTL_INDEX_SHIFT 0
122 #define EQ_CTL_INDEX_MASK 0x0000FFFF
124 enum pq_init_status {
125 PQ_INIT_STATUS_NA = 0,
126 PQ_INIT_STATUS_READY_FOR_CP,
127 PQ_INIT_STATUS_READY_FOR_HOST,
128 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI,
129 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR,
130 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR
134 * CpuCP Primary Queue Packets
136 * During normal operation, the host's kernel driver needs to send various
137 * messages to CpuCP, usually either to SET some value into a H/W periphery or
138 * to GET the current value of some H/W periphery. For example, SET the
139 * frequency of MME/TPC and GET the value of the thermal sensor.
141 * These messages can be initiated either by the User application or by the
142 * host's driver itself, e.g. power management code. In either case, the
143 * communication from the host's driver to CpuCP will *always* be in
144 * synchronous mode, meaning that the host will send a single message and poll
145 * until the message was acknowledged and the results are ready (if results are
148 * This means that only a single message can be sent at a time and the host's
149 * driver must wait for its result before sending the next message. Having said
150 * that, because these are control messages which are sent in a relatively low
151 * frequency, this limitation seems acceptable. It's important to note that
152 * in case of multiple devices, messages to different devices *can* be sent
155 * The message, inputs/outputs (if relevant) and fence object will be located
156 * on the device DDR at an address that will be determined by the host's driver.
157 * During device initialization phase, the host will pass to CpuCP that address.
158 * Most of the message types will contain inputs/outputs inside the message
159 * itself. The common part of each message will contain the opcode of the
160 * message (its type) and a field representing a fence object.
162 * When the host's driver wishes to send a message to CPU CP, it will write the
163 * message contents to the device DDR, clear the fence object and then write to
164 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU.
166 * Upon receiving the interrupt (#121), CpuCP will read the message from the
167 * DDR. In case the message is a SET operation, CpuCP will first perform the
168 * operation and then write to the fence object on the device DDR. In case the
169 * message is a GET operation, CpuCP will first fill the results section on the
170 * device DDR and then write to the fence object. If an error occurred, CpuCP
171 * will fill the rc field with the right error code.
173 * In the meantime, the host's driver will poll on the fence object. Once the
174 * host sees that the fence object is signaled, it will read the results from
175 * the device DDR (if relevant) and resume the code execution in the host's
178 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8
179 * so the value being put by the host's driver matches the value read by CpuCP
181 * Non-QMAN packets should be limited to values 1 through (2^8 - 1)
183 * Detailed description:
185 * CPUCP_PACKET_DISABLE_PCI_ACCESS -
186 * After receiving this packet the embedded CPU must NOT issue PCI
187 * transactions (read/write) towards the Host CPU. This also include
188 * sending MSI-X interrupts.
189 * This packet is usually sent before the device is moved to D3Hot state.
191 * CPUCP_PACKET_ENABLE_PCI_ACCESS -
192 * After receiving this packet the embedded CPU is allowed to issue PCI
193 * transactions towards the Host CPU, including sending MSI-X interrupts.
194 * This packet is usually send after the device is moved to D0 state.
196 * CPUCP_PACKET_TEMPERATURE_GET -
197 * Fetch the current temperature / Max / Max Hyst / Critical /
198 * Critical Hyst of a specified thermal sensor. The packet's
199 * arguments specify the desired sensor and the field to get.
201 * CPUCP_PACKET_VOLTAGE_GET -
202 * Fetch the voltage / Max / Min of a specified sensor. The packet's
203 * arguments specify the sensor and type.
205 * CPUCP_PACKET_CURRENT_GET -
206 * Fetch the current / Max / Min of a specified sensor. The packet's
207 * arguments specify the sensor and type.
209 * CPUCP_PACKET_FAN_SPEED_GET -
210 * Fetch the speed / Max / Min of a specified fan. The packet's
211 * arguments specify the sensor and type.
213 * CPUCP_PACKET_PWM_GET -
214 * Fetch the pwm value / mode of a specified pwm. The packet's
215 * arguments specify the sensor and type.
217 * CPUCP_PACKET_PWM_SET -
218 * Set the pwm value / mode of a specified pwm. The packet's
219 * arguments specify the sensor, type and value.
221 * CPUCP_PACKET_FREQUENCY_SET -
222 * Set the frequency of a specified PLL. The packet's arguments specify
223 * the PLL and the desired frequency. The actual frequency in the device
224 * might differ from the requested frequency.
226 * CPUCP_PACKET_FREQUENCY_GET -
227 * Fetch the frequency of a specified PLL. The packet's arguments specify
230 * CPUCP_PACKET_LED_SET -
231 * Set the state of a specified led. The packet's arguments
232 * specify the led and the desired state.
234 * CPUCP_PACKET_I2C_WR -
235 * Write 32-bit value to I2C device. The packet's arguments specify the
236 * I2C bus, address and value.
238 * CPUCP_PACKET_I2C_RD -
239 * Read 32-bit value from I2C device. The packet's arguments specify the
240 * I2C bus and address.
242 * CPUCP_PACKET_INFO_GET -
243 * Fetch information from the device as specified in the packet's
244 * structure. The host's driver passes the max size it allows the CpuCP to
245 * write to the structure, to prevent data corruption in case of
246 * mismatched driver/FW versions.
248 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed
250 * CPUCP_PACKET_UNMASK_RAZWI_IRQ -
251 * Unmask the given IRQ. The IRQ number is specified in the value field.
252 * The packet is sent after receiving an interrupt and printing its
253 * relevant information.
255 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY -
256 * Unmask the given IRQs. The IRQs numbers are specified in an array right
257 * after the cpucp_packet structure, where its first element is the array
258 * length. The packet is sent after a soft reset was done in order to
259 * handle any interrupts that were sent during the reset process.
261 * CPUCP_PACKET_TEST -
262 * Test packet for CpuCP connectivity. The CPU will put the fence value
263 * in the result field.
265 * CPUCP_PACKET_FREQUENCY_CURR_GET -
266 * Fetch the current frequency of a specified PLL. The packet's arguments
269 * CPUCP_PACKET_MAX_POWER_GET -
270 * Fetch the maximal power of the device.
272 * CPUCP_PACKET_MAX_POWER_SET -
273 * Set the maximal power of the device. The packet's arguments specify
276 * CPUCP_PACKET_EEPROM_DATA_GET -
277 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the
278 * addr field. The CPU will put the returned data size in the result
279 * field. In addition, the host's driver passes the max size it allows the
280 * CpuCP to write to the structure, to prevent data corruption in case of
281 * mismatched driver/FW versions.
283 * CPUCP_PACKET_NIC_INFO_GET -
284 * Fetch information from the device regarding the NIC. the host's driver
285 * passes the max size it allows the CpuCP to write to the structure, to
286 * prevent data corruption in case of mismatched driver/FW versions.
288 * CPUCP_PACKET_TEMPERATURE_SET -
289 * Set the value of the offset property of a specified thermal sensor.
290 * The packet's arguments specify the desired sensor and the field to
293 * CPUCP_PACKET_VOLTAGE_SET -
294 * Trigger the reset_history property of a specified voltage sensor.
295 * The packet's arguments specify the desired sensor and the field to
298 * CPUCP_PACKET_CURRENT_SET -
299 * Trigger the reset_history property of a specified current sensor.
300 * The packet's arguments specify the desired sensor and the field to
303 * CPUCP_PACKET_PCIE_THROUGHPUT_GET
304 * Get throughput of PCIe.
305 * The packet's arguments specify the transaction direction (TX/RX).
306 * The window measurement is 10[msec], and the return value is in KB/sec.
308 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET
309 * Replay count measures number of "replay" events, which is basicly
310 * number of retries done by PCIe.
312 * CPUCP_PACKET_TOTAL_ENERGY_GET
313 * Total Energy is measurement of energy from the time FW Linux
314 * is loaded. It is calculated by multiplying the average power
315 * by time (passed from armcp start). The units are in MilliJouls.
317 * CPUCP_PACKET_PLL_INFO_GET
318 * Fetch frequencies of PLL from the required PLL IP.
319 * The packet's arguments specify the device PLL type
320 * Pll type is the PLL from device pll_index enum.
321 * The result is composed of 4 outputs, each is 16-bit
324 * CPUCP_PACKET_POWER_GET
325 * Fetch the present power consumption of the device (Current * Voltage).
327 * CPUCP_PACKET_NIC_PFC_SET -
328 * Enable/Disable the NIC PFC feature. The packet's arguments specify the
329 * NIC port, relevant lanes to configure and one bit indication for
332 * CPUCP_PACKET_NIC_FAULT_GET -
333 * Fetch the current indication for local/remote faults from the NIC MAC.
334 * The result is 32-bit value of the relevant register.
336 * CPUCP_PACKET_NIC_LPBK_SET -
337 * Enable/Disable the MAC loopback feature. The packet's arguments specify
338 * the NIC port, relevant lanes to configure and one bit indication for
341 * CPUCP_PACKET_NIC_MAC_INIT -
342 * Configure the NIC MAC channels. The packet's arguments specify the
343 * NIC port and the speed.
345 * CPUCP_PACKET_MSI_INFO_SET -
346 * set the index number for each supported msi type going from
350 enum cpucp_packet_id {
351 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */
352 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */
353 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */
354 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */
355 CPUCP_PACKET_CURRENT_GET, /* sysfs */
356 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */
357 CPUCP_PACKET_PWM_GET, /* sysfs */
358 CPUCP_PACKET_PWM_SET, /* sysfs */
359 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */
360 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */
361 CPUCP_PACKET_LED_SET, /* debugfs */
362 CPUCP_PACKET_I2C_WR, /* debugfs */
363 CPUCP_PACKET_I2C_RD, /* debugfs */
364 CPUCP_PACKET_INFO_GET, /* IOCTL */
365 CPUCP_PACKET_FLASH_PROGRAM_REMOVED,
366 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */
367 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */
368 CPUCP_PACKET_TEST, /* internal */
369 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */
370 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */
371 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */
372 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */
373 CPUCP_PACKET_NIC_INFO_GET, /* internal */
374 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */
375 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */
376 CPUCP_PACKET_CURRENT_SET, /* sysfs */
377 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */
378 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */
379 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */
380 CPUCP_PACKET_PLL_INFO_GET, /* internal */
381 CPUCP_PACKET_NIC_STATUS, /* internal */
382 CPUCP_PACKET_POWER_GET, /* internal */
383 CPUCP_PACKET_NIC_PFC_SET, /* internal */
384 CPUCP_PACKET_NIC_FAULT_GET, /* internal */
385 CPUCP_PACKET_NIC_LPBK_SET, /* internal */
386 CPUCP_PACKET_NIC_MAC_CFG, /* internal */
387 CPUCP_PACKET_MSI_INFO_SET, /* internal */
390 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5
392 #define CPUCP_PKT_CTL_RC_SHIFT 12
393 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000
395 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16
396 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000
398 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0
399 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull
400 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16
401 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull
402 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32
403 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull
404 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48
405 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull
407 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0
408 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull
409 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1
410 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull
412 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0
413 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull
414 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1
415 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull
417 /* heartbeat status bits */
418 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0
419 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001
421 struct cpucp_packet {
423 __le64 value; /* For SET packets */
424 __le64 result; /* For GET packets */
425 __le64 addr; /* For PQ */
430 __le32 fence; /* Signal to host that message is completed */
433 struct {/* For temperature/current/voltage/fan/pwm get/set */
438 struct { /* For I2C read/write */
442 __u8 pad; /* unused */
445 struct {/* For PLL info fetch */
447 /* TODO pll_reg is kept temporary before removal */
451 /* For any general request */
454 /* For frequency get/set */
460 /* For get CpuCP info/EEPROM data/NIC info */
461 __le32 data_max_size;
464 * For any general status bitmask. Shall be used whenever the
465 * result cannot be used to hold general purpose data.
473 struct cpucp_unmask_irq_arr_packet {
474 struct cpucp_packet cpucp_pkt;
479 struct cpucp_array_data_packet {
480 struct cpucp_packet cpucp_pkt;
485 enum cpucp_packet_rc {
486 cpucp_packet_success,
487 cpucp_packet_invalid,
492 * cpucp_temp_type should adhere to hwmon_temp_attributes
493 * defined in Linux kernel hwmon.h file
495 enum cpucp_temp_type {
500 cpucp_temp_crit_hyst,
501 cpucp_temp_offset = 19,
502 cpucp_temp_highest = 22,
503 cpucp_temp_reset_history = 23
506 enum cpucp_in_attributes {
510 cpucp_in_highest = 7,
511 cpucp_in_reset_history
514 enum cpucp_curr_attributes {
518 cpucp_curr_highest = 7,
519 cpucp_curr_reset_history
522 enum cpucp_fan_attributes {
528 enum cpucp_pwm_attributes {
533 enum cpucp_pcie_throughput_attributes {
534 cpucp_pcie_throughput_tx,
535 cpucp_pcie_throughput_rx
538 /* TODO temporary kept before removal */
539 enum cpucp_pll_reg_attributes {
543 cpucp_pll_div_factor_reg,
544 cpucp_pll_div_sel_reg
547 /* TODO temporary kept before removal */
548 enum cpucp_pll_type_attributes {
554 * MSI type enumeration table for all ASICs and future SW versions.
555 * For future ASIC-LKD compatibility, we can only add new enumerations.
556 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES).
557 * Changing the order of entries or removing entries is not allowed.
559 enum cpucp_msi_type {
560 CPUCP_EVENT_QUEUE_MSI_TYPE,
561 CPUCP_NIC_PORT1_MSI_TYPE,
562 CPUCP_NIC_PORT3_MSI_TYPE,
563 CPUCP_NIC_PORT5_MSI_TYPE,
564 CPUCP_NIC_PORT7_MSI_TYPE,
565 CPUCP_NIC_PORT9_MSI_TYPE,
566 CPUCP_NUM_OF_MSI_TYPES
570 * PLL enumeration table used for all ASICs and future SW versions.
571 * For future ASIC-LKD compatibility, we can only add new enumerations.
572 * at the end of the table.
573 * Changing the order of entries or removing entries is not allowed.
598 /* Event Queue Packets */
600 struct eq_generic_event {
608 #define CARD_NAME_MAX_LEN 16
609 #define CPUCP_MAX_SENSORS 128
610 #define CPUCP_MAX_NICS 128
611 #define CPUCP_LANES_PER_NIC 4
612 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024
613 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC)
614 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64)
615 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64)
617 struct cpucp_sensor {
623 * struct cpucp_card_types - ASIC card type.
624 * @cpucp_card_type_pci: PCI card.
625 * @cpucp_card_type_pmc: PCI Mezzanine Card.
627 enum cpucp_card_types {
632 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0
633 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001
635 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1
636 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002
638 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2
639 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004
642 * struct cpucp_security_info - Security information.
643 * @config: configuration bit field
644 * @keys_num: number of stored keys
645 * @revoked_keys: revoked keys bit field
646 * @min_svn: minimal security version
648 struct cpucp_security_info {
656 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver
657 * @sensors: available sensors description.
658 * @kernel_version: CpuCP linux kernel version.
659 * @reserved: reserved field.
660 * @card_type: card configuration type.
661 * @card_location: in a server, each card has different connections topology
662 * depending on its location (relevant for PMC card type)
663 * @cpld_version: CPLD programmed F/W version.
664 * @infineon_version: Infineon main DC-DC version.
665 * @fuse_version: silicon production FUSE information.
666 * @thermal_version: thermald S/W version.
667 * @cpucp_version: CpuCP S/W version.
668 * @dram_size: available DRAM size.
669 * @card_name: card name that will be displayed in HWMON subsystem on the host
670 * @sec_info: security information
671 * @pll_map: Bit map of supported PLLs for current ASIC version.
672 * @mme_binning_mask: MME binning mask,
673 * (0 = functional, 1 = binned)
676 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
677 __u8 kernel_version[VERSION_MAX_LEN];
680 __le32 card_location;
682 __le32 infineon_version;
683 __u8 fuse_version[VERSION_MAX_LEN];
684 __u8 thermal_version[VERSION_MAX_LEN];
685 __u8 cpucp_version[VERSION_MAX_LEN];
688 char card_name[CARD_NAME_MAX_LEN];
693 struct cpucp_security_info sec_info;
695 __u8 pll_map[PLL_MAP_LEN];
696 __le64 mme_binning_mask;
699 struct cpucp_mac_addr {
700 __u8 mac_addr[ETH_ALEN];
703 struct cpucp_nic_info {
704 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
705 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
706 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
707 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
708 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
709 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
710 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
713 #endif /* CPUCP_IF_H */