1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
11 #include "../include/goya/asic_reg/goya_masks.h"
12 #include "../include/goya/goya_reg_map.h"
14 #include <linux/pci.h>
15 #include <linux/hwmon.h>
16 #include <linux/iommu.h>
17 #include <linux/seq_file.h>
20 * GOYA security scheme:
22 * 1. Host is protected by:
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
26 * 2. DRAM is protected by:
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
30 * 3. Configuration is protected by:
34 * When MMU is disabled:
36 * QMAN DMA: PQ, CQ, CP, DMA are secured.
37 * PQ, CB and the data are on the host.
40 * PQ, CQ and CP are not secured.
41 * PQ, CB and the data are on the SRAM/DRAM.
43 * Since QMAN DMA is secured, the driver is parsing the DMA CB:
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
46 * - MSG_LONG/SHORT are allowed.
48 * A read/write transaction by the QMAN to a protected area will succeed if
49 * and only if the QMAN's CP is secured and MSG_PROT is used
52 * When MMU is enabled:
54 * QMAN DMA: PQ, CQ and CP are secured.
55 * MMU is set to bypass on the Secure props register of the QMAN.
56 * The reasons we don't enable MMU for PQ, CQ and CP are:
57 * - PQ entry is in kernel address space and the driver doesn't map it.
58 * - CP writes to MSIX register and to kernel address space (completion
61 * DMA is not secured but because CP is secured, the driver still needs to parse
62 * the CB, but doesn't need to check the DMA addresses.
64 * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
65 * the driver doesn't map memory in MMU.
67 * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
69 * DMA RR does NOT protect host because DMA is not secured
73 #define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb"
74 #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb"
76 #define GOYA_MMU_REGS_NUM 63
78 #define GOYA_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */
80 #define GOYA_RESET_TIMEOUT_MSEC 500 /* 500ms */
81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC 20000 /* 20s */
82 #define GOYA_RESET_WAIT_MSEC 1 /* 1ms */
83 #define GOYA_CPU_RESET_WAIT_MSEC 100 /* 100ms */
84 #define GOYA_PLDM_RESET_WAIT_MSEC 1000 /* 1s */
85 #define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */
86 #define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100)
87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30)
88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */
89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */
90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC 15000000 /* 15s */
92 #define GOYA_QMAN0_FENCE_VAL 0xD169B243
94 #define GOYA_MAX_STRING_LEN 20
96 #define GOYA_CB_POOL_CB_CNT 512
97 #define GOYA_CB_POOL_CB_SIZE 0x20000 /* 128KB */
99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
100 (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
101 #define IS_DMA_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(DMA, qm_glbl_sts0)
102 #define IS_TPC_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(TPC, qm_glbl_sts0)
103 #define IS_MME_QM_IDLE(qm_glbl_sts0) IS_QM_IDLE(MME, qm_glbl_sts0)
105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
106 (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
107 engine##_CMDQ_IDLE_MASK)
108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
109 IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
111 IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
113 #define IS_DMA_IDLE(dma_core_sts0) \
114 !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
116 #define IS_TPC_IDLE(tpc_cfg_sts) \
117 (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
119 #define IS_MME_IDLE(mme_arch_sts) \
120 (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
123 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
124 "goya cq 4", "goya cpu eq"
127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
128 [PACKET_WREG_32] = sizeof(struct packet_wreg32),
129 [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk),
130 [PACKET_MSG_LONG] = sizeof(struct packet_msg_long),
131 [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short),
132 [PACKET_CP_DMA] = sizeof(struct packet_cp_dma),
133 [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot),
134 [PACKET_FENCE] = sizeof(struct packet_fence),
135 [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma),
136 [PACKET_NOP] = sizeof(struct packet_nop),
137 [PACKET_STOP] = sizeof(struct packet_stop)
140 static inline bool validate_packet_id(enum packet_id id)
144 case PACKET_WREG_BULK:
145 case PACKET_MSG_LONG:
146 case PACKET_MSG_SHORT:
148 case PACKET_MSG_PROT:
159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
160 mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
161 mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
162 mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
163 mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
164 mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
165 mmTPC0_QM_GLBL_SECURE_PROPS,
166 mmTPC0_QM_GLBL_NON_SECURE_PROPS,
167 mmTPC0_CMDQ_GLBL_SECURE_PROPS,
168 mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
171 mmTPC1_QM_GLBL_SECURE_PROPS,
172 mmTPC1_QM_GLBL_NON_SECURE_PROPS,
173 mmTPC1_CMDQ_GLBL_SECURE_PROPS,
174 mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
177 mmTPC2_QM_GLBL_SECURE_PROPS,
178 mmTPC2_QM_GLBL_NON_SECURE_PROPS,
179 mmTPC2_CMDQ_GLBL_SECURE_PROPS,
180 mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
183 mmTPC3_QM_GLBL_SECURE_PROPS,
184 mmTPC3_QM_GLBL_NON_SECURE_PROPS,
185 mmTPC3_CMDQ_GLBL_SECURE_PROPS,
186 mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
189 mmTPC4_QM_GLBL_SECURE_PROPS,
190 mmTPC4_QM_GLBL_NON_SECURE_PROPS,
191 mmTPC4_CMDQ_GLBL_SECURE_PROPS,
192 mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
195 mmTPC5_QM_GLBL_SECURE_PROPS,
196 mmTPC5_QM_GLBL_NON_SECURE_PROPS,
197 mmTPC5_CMDQ_GLBL_SECURE_PROPS,
198 mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
201 mmTPC6_QM_GLBL_SECURE_PROPS,
202 mmTPC6_QM_GLBL_NON_SECURE_PROPS,
203 mmTPC6_CMDQ_GLBL_SECURE_PROPS,
204 mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
207 mmTPC7_QM_GLBL_SECURE_PROPS,
208 mmTPC7_QM_GLBL_NON_SECURE_PROPS,
209 mmTPC7_CMDQ_GLBL_SECURE_PROPS,
210 mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
213 mmMME_QM_GLBL_SECURE_PROPS,
214 mmMME_QM_GLBL_NON_SECURE_PROPS,
215 mmMME_CMDQ_GLBL_SECURE_PROPS,
216 mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
217 mmMME_SBA_CONTROL_DATA,
218 mmMME_SBB_CONTROL_DATA,
219 mmMME_SBC_CONTROL_DATA,
220 mmMME_WBC_CONTROL_DATA,
221 mmPCIE_WRAP_PSOC_ARUSER,
222 mmPCIE_WRAP_PSOC_AWUSER
225 static u32 goya_all_events[] = {
226 GOYA_ASYNC_EVENT_ID_PCIE_IF,
227 GOYA_ASYNC_EVENT_ID_TPC0_ECC,
228 GOYA_ASYNC_EVENT_ID_TPC1_ECC,
229 GOYA_ASYNC_EVENT_ID_TPC2_ECC,
230 GOYA_ASYNC_EVENT_ID_TPC3_ECC,
231 GOYA_ASYNC_EVENT_ID_TPC4_ECC,
232 GOYA_ASYNC_EVENT_ID_TPC5_ECC,
233 GOYA_ASYNC_EVENT_ID_TPC6_ECC,
234 GOYA_ASYNC_EVENT_ID_TPC7_ECC,
235 GOYA_ASYNC_EVENT_ID_MME_ECC,
236 GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
237 GOYA_ASYNC_EVENT_ID_MMU_ECC,
238 GOYA_ASYNC_EVENT_ID_DMA_MACRO,
239 GOYA_ASYNC_EVENT_ID_DMA_ECC,
240 GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
241 GOYA_ASYNC_EVENT_ID_PSOC_MEM,
242 GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
243 GOYA_ASYNC_EVENT_ID_SRAM0,
244 GOYA_ASYNC_EVENT_ID_SRAM1,
245 GOYA_ASYNC_EVENT_ID_SRAM2,
246 GOYA_ASYNC_EVENT_ID_SRAM3,
247 GOYA_ASYNC_EVENT_ID_SRAM4,
248 GOYA_ASYNC_EVENT_ID_SRAM5,
249 GOYA_ASYNC_EVENT_ID_SRAM6,
250 GOYA_ASYNC_EVENT_ID_SRAM7,
251 GOYA_ASYNC_EVENT_ID_SRAM8,
252 GOYA_ASYNC_EVENT_ID_SRAM9,
253 GOYA_ASYNC_EVENT_ID_SRAM10,
254 GOYA_ASYNC_EVENT_ID_SRAM11,
255 GOYA_ASYNC_EVENT_ID_SRAM12,
256 GOYA_ASYNC_EVENT_ID_SRAM13,
257 GOYA_ASYNC_EVENT_ID_SRAM14,
258 GOYA_ASYNC_EVENT_ID_SRAM15,
259 GOYA_ASYNC_EVENT_ID_SRAM16,
260 GOYA_ASYNC_EVENT_ID_SRAM17,
261 GOYA_ASYNC_EVENT_ID_SRAM18,
262 GOYA_ASYNC_EVENT_ID_SRAM19,
263 GOYA_ASYNC_EVENT_ID_SRAM20,
264 GOYA_ASYNC_EVENT_ID_SRAM21,
265 GOYA_ASYNC_EVENT_ID_SRAM22,
266 GOYA_ASYNC_EVENT_ID_SRAM23,
267 GOYA_ASYNC_EVENT_ID_SRAM24,
268 GOYA_ASYNC_EVENT_ID_SRAM25,
269 GOYA_ASYNC_EVENT_ID_SRAM26,
270 GOYA_ASYNC_EVENT_ID_SRAM27,
271 GOYA_ASYNC_EVENT_ID_SRAM28,
272 GOYA_ASYNC_EVENT_ID_SRAM29,
273 GOYA_ASYNC_EVENT_ID_GIC500,
274 GOYA_ASYNC_EVENT_ID_PLL0,
275 GOYA_ASYNC_EVENT_ID_PLL1,
276 GOYA_ASYNC_EVENT_ID_PLL3,
277 GOYA_ASYNC_EVENT_ID_PLL4,
278 GOYA_ASYNC_EVENT_ID_PLL5,
279 GOYA_ASYNC_EVENT_ID_PLL6,
280 GOYA_ASYNC_EVENT_ID_AXI_ECC,
281 GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
282 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
283 GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
284 GOYA_ASYNC_EVENT_ID_PCIE_DEC,
285 GOYA_ASYNC_EVENT_ID_TPC0_DEC,
286 GOYA_ASYNC_EVENT_ID_TPC1_DEC,
287 GOYA_ASYNC_EVENT_ID_TPC2_DEC,
288 GOYA_ASYNC_EVENT_ID_TPC3_DEC,
289 GOYA_ASYNC_EVENT_ID_TPC4_DEC,
290 GOYA_ASYNC_EVENT_ID_TPC5_DEC,
291 GOYA_ASYNC_EVENT_ID_TPC6_DEC,
292 GOYA_ASYNC_EVENT_ID_TPC7_DEC,
293 GOYA_ASYNC_EVENT_ID_MME_WACS,
294 GOYA_ASYNC_EVENT_ID_MME_WACSD,
295 GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
296 GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
297 GOYA_ASYNC_EVENT_ID_PSOC,
298 GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
299 GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
300 GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
301 GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
302 GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
303 GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
304 GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
305 GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
306 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
307 GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
308 GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
309 GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
310 GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
311 GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
312 GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
313 GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
314 GOYA_ASYNC_EVENT_ID_TPC0_QM,
315 GOYA_ASYNC_EVENT_ID_TPC1_QM,
316 GOYA_ASYNC_EVENT_ID_TPC2_QM,
317 GOYA_ASYNC_EVENT_ID_TPC3_QM,
318 GOYA_ASYNC_EVENT_ID_TPC4_QM,
319 GOYA_ASYNC_EVENT_ID_TPC5_QM,
320 GOYA_ASYNC_EVENT_ID_TPC6_QM,
321 GOYA_ASYNC_EVENT_ID_TPC7_QM,
322 GOYA_ASYNC_EVENT_ID_MME_QM,
323 GOYA_ASYNC_EVENT_ID_MME_CMDQ,
324 GOYA_ASYNC_EVENT_ID_DMA0_QM,
325 GOYA_ASYNC_EVENT_ID_DMA1_QM,
326 GOYA_ASYNC_EVENT_ID_DMA2_QM,
327 GOYA_ASYNC_EVENT_ID_DMA3_QM,
328 GOYA_ASYNC_EVENT_ID_DMA4_QM,
329 GOYA_ASYNC_EVENT_ID_DMA0_CH,
330 GOYA_ASYNC_EVENT_ID_DMA1_CH,
331 GOYA_ASYNC_EVENT_ID_DMA2_CH,
332 GOYA_ASYNC_EVENT_ID_DMA3_CH,
333 GOYA_ASYNC_EVENT_ID_DMA4_CH,
334 GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
335 GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
336 GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
337 GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
338 GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
339 GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
340 GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
341 GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
342 GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
343 GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
344 GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
345 GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
346 GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
347 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
348 GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
349 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
350 GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
360 int goya_set_fixed_properties(struct hl_device *hdev)
362 struct asic_fixed_properties *prop = &hdev->asic_prop;
365 prop->max_queues = GOYA_QUEUE_ID_SIZE;
366 prop->hw_queues_props = kcalloc(prop->max_queues,
367 sizeof(struct hw_queue_properties),
370 if (!prop->hw_queues_props)
373 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
374 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
375 prop->hw_queues_props[i].driver_only = 0;
376 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
379 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
380 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
381 prop->hw_queues_props[i].driver_only = 1;
382 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
385 for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
386 NUMBER_OF_INT_HW_QUEUES; i++) {
387 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
388 prop->hw_queues_props[i].driver_only = 0;
389 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
392 prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
393 prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
395 prop->dram_base_address = DRAM_PHYS_BASE;
396 prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
397 prop->dram_end_address = prop->dram_base_address + prop->dram_size;
398 prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
400 prop->sram_base_address = SRAM_BASE_ADDR;
401 prop->sram_size = SRAM_SIZE;
402 prop->sram_end_address = prop->sram_base_address + prop->sram_size;
403 prop->sram_user_base_address = prop->sram_base_address +
404 SRAM_USER_BASE_OFFSET;
406 prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
407 prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
409 prop->mmu_pgt_size = 0x800000; /* 8MB */
411 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
412 prop->mmu_pte_size = HL_PTE_SIZE;
413 prop->mmu_hop_table_size = HOP_TABLE_SIZE;
414 prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
415 prop->dram_page_size = PAGE_SIZE_2MB;
416 prop->dram_supports_virtual_memory = true;
418 prop->dmmu.hop0_shift = HOP0_SHIFT;
419 prop->dmmu.hop1_shift = HOP1_SHIFT;
420 prop->dmmu.hop2_shift = HOP2_SHIFT;
421 prop->dmmu.hop3_shift = HOP3_SHIFT;
422 prop->dmmu.hop4_shift = HOP4_SHIFT;
423 prop->dmmu.hop0_mask = HOP0_MASK;
424 prop->dmmu.hop1_mask = HOP1_MASK;
425 prop->dmmu.hop2_mask = HOP2_MASK;
426 prop->dmmu.hop3_mask = HOP3_MASK;
427 prop->dmmu.hop4_mask = HOP4_MASK;
428 prop->dmmu.start_addr = VA_DDR_SPACE_START;
429 prop->dmmu.end_addr = VA_DDR_SPACE_END;
430 prop->dmmu.page_size = PAGE_SIZE_2MB;
431 prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
433 /* shifts and masks are the same in PMMU and DMMU */
434 memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
435 prop->pmmu.start_addr = VA_HOST_SPACE_START;
436 prop->pmmu.end_addr = VA_HOST_SPACE_END;
437 prop->pmmu.page_size = PAGE_SIZE_4KB;
438 prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
440 /* PMMU and HPMMU are the same except of page size */
441 memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
442 prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
444 prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
445 prop->cfg_size = CFG_SIZE;
446 prop->max_asid = MAX_ASID;
447 prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
448 prop->high_pll = PLL_HIGH_DEFAULT;
449 prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
450 prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
451 prop->max_power_default = MAX_POWER_DEFAULT;
452 prop->dc_power_default = DC_POWER_DEFAULT;
453 prop->tpc_enabled_mask = TPC_ENABLED_MASK;
454 prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
455 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
457 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
460 prop->max_pending_cs = GOYA_MAX_PENDING_CS;
462 prop->first_available_user_msix_interrupt = USHRT_MAX;
464 for (i = 0 ; i < HL_MAX_DCORES ; i++)
465 prop->first_available_cq[i] = USHRT_MAX;
467 prop->fw_cpu_boot_dev_sts0_valid = false;
468 prop->fw_cpu_boot_dev_sts1_valid = false;
469 prop->hard_reset_done_by_fw = false;
470 prop->gic_interrupts_enable = true;
472 prop->server_type = HL_SERVER_TYPE_UNKNOWN;
478 * goya_pci_bars_map - Map PCI BARS of Goya device
480 * @hdev: pointer to hl_device structure
482 * Request PCI regions and map them to kernel virtual addresses.
483 * Returns 0 on success
486 static int goya_pci_bars_map(struct hl_device *hdev)
488 static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
489 bool is_wc[3] = {false, false, true};
492 rc = hl_pci_bars_map(hdev, name, is_wc);
496 hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
497 (CFG_BASE - SRAM_BASE_ADDR);
502 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
504 struct goya_device *goya = hdev->asic_specific;
505 struct hl_inbound_pci_region pci_region;
509 if ((goya) && (goya->ddr_bar_cur_addr == addr))
512 /* Inbound Region 1 - Bar 4 - Point to DDR */
513 pci_region.mode = PCI_BAR_MATCH_MODE;
514 pci_region.bar = DDR_BAR_ID;
515 pci_region.addr = addr;
516 rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
521 old_addr = goya->ddr_bar_cur_addr;
522 goya->ddr_bar_cur_addr = addr;
529 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
531 * @hdev: pointer to hl_device structure
533 * This is needed in case the firmware doesn't initialize the iATU
536 static int goya_init_iatu(struct hl_device *hdev)
538 struct hl_inbound_pci_region inbound_region;
539 struct hl_outbound_pci_region outbound_region;
542 if (hdev->asic_prop.iatu_done_by_fw)
545 /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
546 inbound_region.mode = PCI_BAR_MATCH_MODE;
547 inbound_region.bar = SRAM_CFG_BAR_ID;
548 inbound_region.addr = SRAM_BASE_ADDR;
549 rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
553 /* Inbound Region 1 - Bar 4 - Point to DDR */
554 inbound_region.mode = PCI_BAR_MATCH_MODE;
555 inbound_region.bar = DDR_BAR_ID;
556 inbound_region.addr = DRAM_PHYS_BASE;
557 rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
561 hdev->asic_funcs->set_dma_mask_from_fw(hdev);
563 /* Outbound Region 0 - Point to Host */
564 outbound_region.addr = HOST_PHYS_BASE;
565 outbound_region.size = HOST_PHYS_SIZE;
566 rc = hl_pci_set_outbound_region(hdev, &outbound_region);
572 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
574 return RREG32(mmHW_STATE);
578 * goya_early_init - GOYA early initialization code
580 * @hdev: pointer to hl_device structure
584 * PCI controller initialization
588 static int goya_early_init(struct hl_device *hdev)
590 struct asic_fixed_properties *prop = &hdev->asic_prop;
591 struct pci_dev *pdev = hdev->pdev;
592 u32 fw_boot_status, val;
595 rc = goya_set_fixed_properties(hdev);
597 dev_err(hdev->dev, "Failed to get fixed properties\n");
601 /* Check BAR sizes */
602 if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
604 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
606 (unsigned long long) pci_resource_len(pdev,
610 goto free_queue_props;
613 if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
615 "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
617 (unsigned long long) pci_resource_len(pdev,
621 goto free_queue_props;
624 prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
626 /* If FW security is enabled at this point it means no access to ELBI */
627 if (hdev->asic_prop.fw_security_enabled) {
628 hdev->asic_prop.iatu_done_by_fw = true;
632 rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
635 goto free_queue_props;
637 /* Check whether FW is configuring iATU */
638 if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
639 (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
640 hdev->asic_prop.iatu_done_by_fw = true;
643 rc = hl_pci_init(hdev);
645 goto free_queue_props;
647 /* Before continuing in the initialization, we need to read the preboot
648 * version to determine whether we run with a security-enabled firmware
650 rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
652 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
654 GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
656 if (hdev->reset_on_preboot_fail)
657 hdev->asic_funcs->hw_fini(hdev, true);
661 if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
663 "H/W state is dirty, must reset before initializing\n");
664 hdev->asic_funcs->hw_fini(hdev, true);
668 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
669 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
671 "PCI strap is not configured correctly, PCI bus errors may occur\n");
679 kfree(hdev->asic_prop.hw_queues_props);
684 * goya_early_fini - GOYA early finalization code
686 * @hdev: pointer to hl_device structure
691 static int goya_early_fini(struct hl_device *hdev)
693 kfree(hdev->asic_prop.hw_queues_props);
699 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
701 /* mask to zero the MMBP and ASID bits */
702 WREG32_AND(reg, ~0x7FF);
703 WREG32_OR(reg, asid);
706 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
708 struct goya_device *goya = hdev->asic_specific;
710 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
714 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
716 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
718 RREG32(mmDMA_QM_0_GLBL_PROT);
722 * goya_fetch_psoc_frequency - Fetch PSOC frequency values
724 * @hdev: pointer to hl_device structure
727 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
729 struct asic_fixed_properties *prop = &hdev->asic_prop;
730 u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
731 u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
734 if (hdev->asic_prop.fw_security_enabled) {
735 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
741 freq = pll_freq_arr[1];
743 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
744 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
745 nr = RREG32(mmPSOC_PCI_PLL_NR);
746 nf = RREG32(mmPSOC_PCI_PLL_NF);
747 od = RREG32(mmPSOC_PCI_PLL_OD);
749 if (div_sel == DIV_SEL_REF_CLK ||
750 div_sel == DIV_SEL_DIVIDED_REF) {
751 if (div_sel == DIV_SEL_REF_CLK)
754 freq = PLL_REF_CLK / (div_fctr + 1);
755 } else if (div_sel == DIV_SEL_PLL_CLK ||
756 div_sel == DIV_SEL_DIVIDED_PLL) {
757 pll_clk = PLL_REF_CLK * (nf + 1) /
758 ((nr + 1) * (od + 1));
759 if (div_sel == DIV_SEL_PLL_CLK)
762 freq = pll_clk / (div_fctr + 1);
765 "Received invalid div select value: %d",
771 prop->psoc_timestamp_frequency = freq;
772 prop->psoc_pci_pll_nr = nr;
773 prop->psoc_pci_pll_nf = nf;
774 prop->psoc_pci_pll_od = od;
775 prop->psoc_pci_pll_div_factor = div_fctr;
778 int goya_late_init(struct hl_device *hdev)
780 struct asic_fixed_properties *prop = &hdev->asic_prop;
783 goya_fetch_psoc_frequency(hdev);
785 rc = goya_mmu_clear_pgt_range(hdev);
788 "Failed to clear MMU page tables range %d\n", rc);
792 rc = goya_mmu_set_dram_default_page(hdev);
794 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
798 rc = goya_mmu_add_mappings_for_device_cpu(hdev);
802 rc = goya_init_cpu_queues(hdev);
806 rc = goya_test_cpu_queue(hdev);
810 rc = goya_cpucp_info_get(hdev);
812 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
816 /* Now that we have the DRAM size in ASIC prop, we need to check
817 * its size and configure the DMA_IF DDR wrap protection (which is in
818 * the MMU block) accordingly. The value is the log2 of the DRAM size
820 WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
822 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
825 "Failed to enable PCI access from CPU %d\n", rc);
833 * goya_late_fini - GOYA late tear-down code
835 * @hdev: pointer to hl_device structure
837 * Free sensors allocated structures
839 void goya_late_fini(struct hl_device *hdev)
841 const struct hwmon_channel_info **channel_info_arr;
844 if (!hdev->hl_chip_info->info)
847 channel_info_arr = hdev->hl_chip_info->info;
849 while (channel_info_arr[i]) {
850 kfree(channel_info_arr[i]->config);
851 kfree(channel_info_arr[i]);
855 kfree(channel_info_arr);
857 hdev->hl_chip_info->info = NULL;
860 static void goya_set_pci_memory_regions(struct hl_device *hdev)
862 struct asic_fixed_properties *prop = &hdev->asic_prop;
863 struct pci_mem_region *region;
866 region = &hdev->pci_mem_region[PCI_REGION_CFG];
867 region->region_base = CFG_BASE;
868 region->region_size = CFG_SIZE;
869 region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
870 region->bar_size = CFG_BAR_SIZE;
871 region->bar_id = SRAM_CFG_BAR_ID;
875 region = &hdev->pci_mem_region[PCI_REGION_SRAM];
876 region->region_base = SRAM_BASE_ADDR;
877 region->region_size = SRAM_SIZE;
878 region->offset_in_bar = 0;
879 region->bar_size = CFG_BAR_SIZE;
880 region->bar_id = SRAM_CFG_BAR_ID;
884 region = &hdev->pci_mem_region[PCI_REGION_DRAM];
885 region->region_base = DRAM_PHYS_BASE;
886 region->region_size = hdev->asic_prop.dram_size;
887 region->offset_in_bar = 0;
888 region->bar_size = prop->dram_pci_bar_size;
889 region->bar_id = DDR_BAR_ID;
894 * goya_sw_init - Goya software initialization code
896 * @hdev: pointer to hl_device structure
899 static int goya_sw_init(struct hl_device *hdev)
901 struct goya_device *goya;
904 /* Allocate device structure */
905 goya = kzalloc(sizeof(*goya), GFP_KERNEL);
909 /* according to goya_init_iatu */
910 goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
912 goya->mme_clk = GOYA_PLL_FREQ_LOW;
913 goya->tpc_clk = GOYA_PLL_FREQ_LOW;
914 goya->ic_clk = GOYA_PLL_FREQ_LOW;
916 hdev->asic_specific = goya;
918 /* Create DMA pool for small allocations */
919 hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
920 &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
921 if (!hdev->dma_pool) {
922 dev_err(hdev->dev, "failed to create DMA pool\n");
924 goto free_goya_device;
927 hdev->cpu_accessible_dma_mem =
928 hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
929 HL_CPU_ACCESSIBLE_MEM_SIZE,
930 &hdev->cpu_accessible_dma_address,
931 GFP_KERNEL | __GFP_ZERO);
933 if (!hdev->cpu_accessible_dma_mem) {
938 dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
939 &hdev->cpu_accessible_dma_address);
941 hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
942 if (!hdev->cpu_accessible_dma_pool) {
944 "Failed to create CPU accessible DMA pool\n");
946 goto free_cpu_dma_mem;
949 rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
950 (uintptr_t) hdev->cpu_accessible_dma_mem,
951 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
954 "Failed to add memory to CPU accessible DMA pool\n");
956 goto free_cpu_accessible_dma_pool;
959 spin_lock_init(&goya->hw_queues_lock);
960 hdev->supports_coresight = true;
961 hdev->supports_soft_reset = true;
962 hdev->allow_external_soft_reset = true;
963 hdev->supports_wait_for_multi_cs = false;
965 hdev->asic_funcs->set_pci_memory_regions(hdev);
969 free_cpu_accessible_dma_pool:
970 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
972 hdev->asic_funcs->asic_dma_free_coherent(hdev,
973 HL_CPU_ACCESSIBLE_MEM_SIZE,
974 hdev->cpu_accessible_dma_mem,
975 hdev->cpu_accessible_dma_address);
977 dma_pool_destroy(hdev->dma_pool);
985 * goya_sw_fini - Goya software tear-down code
987 * @hdev: pointer to hl_device structure
990 static int goya_sw_fini(struct hl_device *hdev)
992 struct goya_device *goya = hdev->asic_specific;
994 gen_pool_destroy(hdev->cpu_accessible_dma_pool);
996 hdev->asic_funcs->asic_dma_free_coherent(hdev,
997 HL_CPU_ACCESSIBLE_MEM_SIZE,
998 hdev->cpu_accessible_dma_mem,
999 hdev->cpu_accessible_dma_address);
1001 dma_pool_destroy(hdev->dma_pool);
1008 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1009 dma_addr_t bus_address)
1011 struct goya_device *goya = hdev->asic_specific;
1012 u32 mtr_base_lo, mtr_base_hi;
1013 u32 so_base_lo, so_base_hi;
1014 u32 gic_base_lo, gic_base_hi;
1015 u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1016 u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1018 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1019 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1020 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1021 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1024 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1026 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1028 WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1029 WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1031 WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1032 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1033 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1035 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1036 WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1037 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1038 WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1039 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1040 WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1041 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1042 GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1044 /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1045 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1046 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1048 if (goya->hw_cap_initialized & HW_CAP_MMU)
1049 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1051 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1053 if (hdev->stop_on_err)
1054 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1056 WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1057 WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1060 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1062 u32 gic_base_lo, gic_base_hi;
1064 u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1067 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1069 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1071 WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1072 WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1073 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1074 GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1077 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1080 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1082 WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1083 WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1087 * goya_init_dma_qmans - Initialize QMAN DMA registers
1089 * @hdev: pointer to hl_device structure
1091 * Initialize the H/W registers of the QMAN DMA channels
1094 void goya_init_dma_qmans(struct hl_device *hdev)
1096 struct goya_device *goya = hdev->asic_specific;
1097 struct hl_hw_queue *q;
1100 if (goya->hw_cap_initialized & HW_CAP_DMA)
1103 q = &hdev->kernel_queues[0];
1105 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1106 q->cq_id = q->msi_vec = i;
1107 goya_init_dma_qman(hdev, i, q->bus_address);
1108 goya_init_dma_ch(hdev, i);
1111 goya->hw_cap_initialized |= HW_CAP_DMA;
1115 * goya_disable_external_queues - Disable external queues
1117 * @hdev: pointer to hl_device structure
1120 static void goya_disable_external_queues(struct hl_device *hdev)
1122 struct goya_device *goya = hdev->asic_specific;
1124 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1127 WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1128 WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1129 WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1130 WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1131 WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1134 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1135 u32 cp_sts_reg, u32 glbl_sts0_reg)
1140 /* use the values of TPC0 as they are all the same*/
1142 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1144 status = RREG32(cp_sts_reg);
1145 if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1146 rc = hl_poll_timeout(
1150 !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1152 QMAN_FENCE_TIMEOUT_USEC);
1154 /* if QMAN is stuck in fence no need to check for stop */
1159 rc = hl_poll_timeout(
1163 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1165 QMAN_STOP_TIMEOUT_USEC);
1169 "Timeout while waiting for QMAN to stop\n");
1177 * goya_stop_external_queues - Stop external queues
1179 * @hdev: pointer to hl_device structure
1181 * Returns 0 on success
1184 static int goya_stop_external_queues(struct hl_device *hdev)
1188 struct goya_device *goya = hdev->asic_specific;
1190 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1193 rc = goya_stop_queue(hdev,
1194 mmDMA_QM_0_GLBL_CFG1,
1196 mmDMA_QM_0_GLBL_STS0);
1199 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1203 rc = goya_stop_queue(hdev,
1204 mmDMA_QM_1_GLBL_CFG1,
1206 mmDMA_QM_1_GLBL_STS0);
1209 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1213 rc = goya_stop_queue(hdev,
1214 mmDMA_QM_2_GLBL_CFG1,
1216 mmDMA_QM_2_GLBL_STS0);
1219 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1223 rc = goya_stop_queue(hdev,
1224 mmDMA_QM_3_GLBL_CFG1,
1226 mmDMA_QM_3_GLBL_STS0);
1229 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1233 rc = goya_stop_queue(hdev,
1234 mmDMA_QM_4_GLBL_CFG1,
1236 mmDMA_QM_4_GLBL_STS0);
1239 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1247 * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1249 * @hdev: pointer to hl_device structure
1251 * Returns 0 on success
1254 int goya_init_cpu_queues(struct hl_device *hdev)
1256 struct goya_device *goya = hdev->asic_specific;
1257 struct asic_fixed_properties *prop = &hdev->asic_prop;
1260 struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1263 if (!hdev->cpu_queues_enable)
1266 if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1269 eq = &hdev->event_queue;
1271 WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1272 WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1274 WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1275 WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1277 WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1278 lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1279 WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1280 upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1282 WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1283 WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1284 WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1286 /* Used for EQ CI */
1287 WREG32(mmCPU_EQ_CI, 0);
1289 WREG32(mmCPU_IF_PF_PQ_PI, 0);
1291 WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1293 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1294 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1296 err = hl_poll_timeout(
1298 mmCPU_PQ_INIT_STATUS,
1300 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1302 GOYA_CPU_TIMEOUT_USEC);
1306 "Failed to setup communication with device CPU\n");
1310 /* update FW application security bits */
1311 if (prop->fw_cpu_boot_dev_sts0_valid)
1312 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1314 if (prop->fw_cpu_boot_dev_sts1_valid)
1315 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1317 goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1321 static void goya_set_pll_refclk(struct hl_device *hdev)
1323 WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1324 WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1325 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1326 WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1328 WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1329 WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1330 WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1331 WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1333 WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1334 WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1335 WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1336 WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1338 WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1339 WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1340 WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1341 WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1343 WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1344 WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1345 WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1346 WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1348 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1349 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1350 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1351 WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1353 WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1354 WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1355 WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1356 WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1359 static void goya_disable_clk_rlx(struct hl_device *hdev)
1361 WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1362 WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1365 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1367 u64 tpc_eml_address;
1368 u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1371 tpc_offset = tpc_id * 0x40000;
1372 tpc_eml_offset = tpc_id * 0x200000;
1373 tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1374 tpc_slm_offset = tpc_eml_address + 0x100000;
1377 * Workaround for Bug H2 #2443 :
1378 * "TPC SB is not initialized on chip reset"
1381 val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1382 if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1383 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1386 WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1388 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1389 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1390 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1391 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1392 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1393 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1394 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1395 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1396 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1397 WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1399 WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1400 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1402 err = hl_poll_timeout(
1404 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1406 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1408 HL_DEVICE_TIMEOUT_USEC);
1412 "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1414 WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1415 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1417 msleep(GOYA_RESET_WAIT_MSEC);
1419 WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1420 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1422 msleep(GOYA_RESET_WAIT_MSEC);
1424 for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1425 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1427 val = RREG32(tpc_slm_offset);
1430 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1432 struct goya_device *goya = hdev->asic_specific;
1438 if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1441 /* Workaround for H2 #2443 */
1443 for (i = 0 ; i < TPC_MAX_NUM ; i++)
1444 _goya_tpc_mbist_workaround(hdev, i);
1446 goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1450 * goya_init_golden_registers - Initialize golden registers
1452 * @hdev: pointer to hl_device structure
1454 * Initialize the H/W registers of the device
1457 static void goya_init_golden_registers(struct hl_device *hdev)
1459 struct goya_device *goya = hdev->asic_specific;
1460 u32 polynom[10], tpc_intr_mask, offset;
1463 if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1466 polynom[0] = 0x00020080;
1467 polynom[1] = 0x00401000;
1468 polynom[2] = 0x00200800;
1469 polynom[3] = 0x00002000;
1470 polynom[4] = 0x00080200;
1471 polynom[5] = 0x00040100;
1472 polynom[6] = 0x00100400;
1473 polynom[7] = 0x00004000;
1474 polynom[8] = 0x00010000;
1475 polynom[9] = 0x00008000;
1477 /* Mask all arithmetic interrupts from TPC */
1478 tpc_intr_mask = 0x7FFF;
1480 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1481 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1482 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1483 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1484 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1485 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1487 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1488 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1489 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1490 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1491 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1494 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1495 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1496 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1497 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1498 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1500 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1501 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1502 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1503 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1504 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1506 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1507 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1508 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1509 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1510 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1512 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1513 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1514 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1515 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1516 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1519 WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1520 WREG32(mmMME_AGU, 0x0f0f0f10);
1521 WREG32(mmMME_SEI_MASK, ~0x0);
1523 WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1524 WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1525 WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1526 WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1527 WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1528 WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1529 WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1530 WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1531 WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1532 WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1533 WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1534 WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1535 WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1536 WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1537 WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1538 WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1539 WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1540 WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1541 WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1542 WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1543 WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1544 WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1545 WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1546 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1547 WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1548 WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1549 WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1550 WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1551 WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1552 WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1553 WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1554 WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1555 WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1556 WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1557 WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1558 WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1559 WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1560 WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1561 WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1562 WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1563 WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1564 WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1565 WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1566 WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1567 WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1568 WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1569 WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1570 WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1571 WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1572 WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1573 WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1574 WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1575 WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1576 WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1577 WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1578 WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1579 WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1580 WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1581 WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1582 WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1583 WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1584 WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1585 WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1586 WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1587 WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1588 WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1589 WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1590 WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1591 WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1592 WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1593 WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1594 WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1595 WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1596 WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1597 WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1598 WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1599 WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1600 WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1601 WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1602 WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1603 WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1604 WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1605 WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1606 WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1608 WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1609 WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1610 WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1611 WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1612 WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1613 WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1614 WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1615 WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1616 WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1617 WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1618 WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1619 WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1621 WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1622 WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1623 WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1624 WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1625 WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1626 WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1627 WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1628 WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1629 WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1630 WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1631 WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1632 WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1634 WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1635 WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1636 WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1637 WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1638 WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1639 WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1640 WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1641 WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1642 WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1643 WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1644 WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1645 WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1647 WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1648 WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1649 WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1650 WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1651 WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1652 WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1653 WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1654 WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1655 WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1656 WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1657 WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1658 WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1660 WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1661 WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1662 WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1663 WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1664 WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1665 WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1666 WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1667 WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1668 WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1669 WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1670 WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1671 WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1673 WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1674 WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1675 WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1676 WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1677 WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1678 WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1679 WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1680 WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1681 WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1682 WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1683 WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1684 WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1686 for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1687 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1688 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1689 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1690 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1691 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1692 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1694 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1695 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1696 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1697 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1698 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1699 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1700 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1701 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1703 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1704 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1707 for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1708 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1709 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1710 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1711 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1714 for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1716 * Workaround for Bug H2 #2441 :
1717 * "ST.NOP set trace event illegal opcode"
1719 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1721 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1722 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1723 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1724 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1726 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1727 ICACHE_FETCH_LINE_NUM, 2);
1730 WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1731 WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1732 1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1734 WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1735 WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1736 1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1739 * Workaround for H2 #HW-23 bug
1740 * Set DMA max outstanding read requests to 240 on DMA CH 1.
1741 * This limitation is still large enough to not affect Gen4 bandwidth.
1742 * We need to only limit that DMA channel because the user can only read
1743 * from Host using DMA CH 1
1745 WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1747 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1749 goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1752 static void goya_init_mme_qman(struct hl_device *hdev)
1754 u32 mtr_base_lo, mtr_base_hi;
1755 u32 so_base_lo, so_base_hi;
1756 u32 gic_base_lo, gic_base_hi;
1759 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1760 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1761 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1762 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1765 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1767 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1769 qman_base_addr = hdev->asic_prop.sram_base_address +
1770 MME_QMAN_BASE_OFFSET;
1772 WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1773 WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1774 WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1775 WREG32(mmMME_QM_PQ_PI, 0);
1776 WREG32(mmMME_QM_PQ_CI, 0);
1777 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1778 WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1779 WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1780 WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1782 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1783 WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1784 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1785 WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1787 /* QMAN CQ has 8 cache lines */
1788 WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1790 WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1791 WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1793 WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1795 WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1797 WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1799 WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1802 static void goya_init_mme_cmdq(struct hl_device *hdev)
1804 u32 mtr_base_lo, mtr_base_hi;
1805 u32 so_base_lo, so_base_hi;
1806 u32 gic_base_lo, gic_base_hi;
1808 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1809 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1810 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1811 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1814 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1816 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1818 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1819 WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1820 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1821 WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1823 /* CMDQ CQ has 20 cache lines */
1824 WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1826 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1827 WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1829 WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1831 WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1833 WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1835 WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1838 void goya_init_mme_qmans(struct hl_device *hdev)
1840 struct goya_device *goya = hdev->asic_specific;
1841 u32 so_base_lo, so_base_hi;
1843 if (goya->hw_cap_initialized & HW_CAP_MME)
1846 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1847 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1849 WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1850 WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1852 goya_init_mme_qman(hdev);
1853 goya_init_mme_cmdq(hdev);
1855 goya->hw_cap_initialized |= HW_CAP_MME;
1858 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1860 u32 mtr_base_lo, mtr_base_hi;
1861 u32 so_base_lo, so_base_hi;
1862 u32 gic_base_lo, gic_base_hi;
1864 u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1866 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1867 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1868 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1869 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1872 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1874 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1876 qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1878 WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1879 WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1880 WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1881 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1882 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1883 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1884 WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1885 WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1886 WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1888 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1889 WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1890 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1891 WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1893 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1895 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1896 WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1898 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1899 GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1901 WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1903 WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1905 WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1908 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1910 u32 mtr_base_lo, mtr_base_hi;
1911 u32 so_base_lo, so_base_hi;
1912 u32 gic_base_lo, gic_base_hi;
1913 u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1915 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1916 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1917 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1918 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1921 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1923 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1925 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1926 WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1927 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1928 WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1930 WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1932 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1933 WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1935 WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1936 GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1938 WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1940 WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1942 WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1945 void goya_init_tpc_qmans(struct hl_device *hdev)
1947 struct goya_device *goya = hdev->asic_specific;
1948 u32 so_base_lo, so_base_hi;
1949 u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1950 mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1953 if (goya->hw_cap_initialized & HW_CAP_TPC)
1956 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1957 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1959 for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1960 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1962 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1966 goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1967 goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1968 goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1969 goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1970 goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1971 goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1972 goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1973 goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1975 for (i = 0 ; i < TPC_MAX_NUM ; i++)
1976 goya_init_tpc_cmdq(hdev, i);
1978 goya->hw_cap_initialized |= HW_CAP_TPC;
1982 * goya_disable_internal_queues - Disable internal queues
1984 * @hdev: pointer to hl_device structure
1987 static void goya_disable_internal_queues(struct hl_device *hdev)
1989 struct goya_device *goya = hdev->asic_specific;
1991 if (!(goya->hw_cap_initialized & HW_CAP_MME))
1994 WREG32(mmMME_QM_GLBL_CFG0, 0);
1995 WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1998 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2001 WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2002 WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2004 WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2005 WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2007 WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2008 WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2010 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2011 WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2013 WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2014 WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2016 WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2017 WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2019 WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2020 WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2022 WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2023 WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2027 * goya_stop_internal_queues - Stop internal queues
2029 * @hdev: pointer to hl_device structure
2031 * Returns 0 on success
2034 static int goya_stop_internal_queues(struct hl_device *hdev)
2036 struct goya_device *goya = hdev->asic_specific;
2039 if (!(goya->hw_cap_initialized & HW_CAP_MME))
2043 * Each queue (QMAN) is a separate H/W logic. That means that each
2044 * QMAN can be stopped independently and failure to stop one does NOT
2045 * mandate we should not try to stop other QMANs
2048 rc = goya_stop_queue(hdev,
2051 mmMME_QM_GLBL_STS0);
2054 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2058 rc = goya_stop_queue(hdev,
2059 mmMME_CMDQ_GLBL_CFG1,
2061 mmMME_CMDQ_GLBL_STS0);
2064 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2069 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2072 rc = goya_stop_queue(hdev,
2073 mmTPC0_QM_GLBL_CFG1,
2075 mmTPC0_QM_GLBL_STS0);
2078 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2082 rc = goya_stop_queue(hdev,
2083 mmTPC0_CMDQ_GLBL_CFG1,
2085 mmTPC0_CMDQ_GLBL_STS0);
2088 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2092 rc = goya_stop_queue(hdev,
2093 mmTPC1_QM_GLBL_CFG1,
2095 mmTPC1_QM_GLBL_STS0);
2098 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2102 rc = goya_stop_queue(hdev,
2103 mmTPC1_CMDQ_GLBL_CFG1,
2105 mmTPC1_CMDQ_GLBL_STS0);
2108 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2112 rc = goya_stop_queue(hdev,
2113 mmTPC2_QM_GLBL_CFG1,
2115 mmTPC2_QM_GLBL_STS0);
2118 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2122 rc = goya_stop_queue(hdev,
2123 mmTPC2_CMDQ_GLBL_CFG1,
2125 mmTPC2_CMDQ_GLBL_STS0);
2128 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2132 rc = goya_stop_queue(hdev,
2133 mmTPC3_QM_GLBL_CFG1,
2135 mmTPC3_QM_GLBL_STS0);
2138 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2142 rc = goya_stop_queue(hdev,
2143 mmTPC3_CMDQ_GLBL_CFG1,
2145 mmTPC3_CMDQ_GLBL_STS0);
2148 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2152 rc = goya_stop_queue(hdev,
2153 mmTPC4_QM_GLBL_CFG1,
2155 mmTPC4_QM_GLBL_STS0);
2158 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2162 rc = goya_stop_queue(hdev,
2163 mmTPC4_CMDQ_GLBL_CFG1,
2165 mmTPC4_CMDQ_GLBL_STS0);
2168 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2172 rc = goya_stop_queue(hdev,
2173 mmTPC5_QM_GLBL_CFG1,
2175 mmTPC5_QM_GLBL_STS0);
2178 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2182 rc = goya_stop_queue(hdev,
2183 mmTPC5_CMDQ_GLBL_CFG1,
2185 mmTPC5_CMDQ_GLBL_STS0);
2188 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2192 rc = goya_stop_queue(hdev,
2193 mmTPC6_QM_GLBL_CFG1,
2195 mmTPC6_QM_GLBL_STS0);
2198 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2202 rc = goya_stop_queue(hdev,
2203 mmTPC6_CMDQ_GLBL_CFG1,
2205 mmTPC6_CMDQ_GLBL_STS0);
2208 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2212 rc = goya_stop_queue(hdev,
2213 mmTPC7_QM_GLBL_CFG1,
2215 mmTPC7_QM_GLBL_STS0);
2218 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2222 rc = goya_stop_queue(hdev,
2223 mmTPC7_CMDQ_GLBL_CFG1,
2225 mmTPC7_CMDQ_GLBL_STS0);
2228 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2235 static void goya_dma_stall(struct hl_device *hdev)
2237 struct goya_device *goya = hdev->asic_specific;
2239 if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2242 WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2243 WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2244 WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2245 WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2246 WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2249 static void goya_tpc_stall(struct hl_device *hdev)
2251 struct goya_device *goya = hdev->asic_specific;
2253 if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2256 WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2257 WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2258 WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2259 WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2260 WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2261 WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2262 WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2263 WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2266 static void goya_mme_stall(struct hl_device *hdev)
2268 struct goya_device *goya = hdev->asic_specific;
2270 if (!(goya->hw_cap_initialized & HW_CAP_MME))
2273 WREG32(mmMME_STALL, 0xFFFFFFFF);
2276 static int goya_enable_msix(struct hl_device *hdev)
2278 struct goya_device *goya = hdev->asic_specific;
2279 int cq_cnt = hdev->asic_prop.completion_queues_count;
2280 int rc, i, irq_cnt_init, irq;
2282 if (goya->hw_cap_initialized & HW_CAP_MSIX)
2285 rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2286 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2289 "MSI-X: Failed to enable support -- %d/%d\n",
2290 GOYA_MSIX_ENTRIES, rc);
2294 for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2295 irq = pci_irq_vector(hdev->pdev, i);
2296 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2297 &hdev->completion_queue[i]);
2299 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2304 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2306 rc = request_irq(irq, hl_irq_handler_eq, 0,
2307 goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2308 &hdev->event_queue);
2310 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2314 goya->hw_cap_initialized |= HW_CAP_MSIX;
2318 for (i = 0 ; i < irq_cnt_init ; i++)
2319 free_irq(pci_irq_vector(hdev->pdev, i),
2320 &hdev->completion_queue[i]);
2322 pci_free_irq_vectors(hdev->pdev);
2326 static void goya_sync_irqs(struct hl_device *hdev)
2328 struct goya_device *goya = hdev->asic_specific;
2331 if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2334 /* Wait for all pending IRQs to be finished */
2335 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2336 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2338 synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2341 static void goya_disable_msix(struct hl_device *hdev)
2343 struct goya_device *goya = hdev->asic_specific;
2346 if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2349 goya_sync_irqs(hdev);
2351 irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2352 free_irq(irq, &hdev->event_queue);
2354 for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2355 irq = pci_irq_vector(hdev->pdev, i);
2356 free_irq(irq, &hdev->completion_queue[i]);
2359 pci_free_irq_vectors(hdev->pdev);
2361 goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2364 static void goya_enable_timestamp(struct hl_device *hdev)
2366 /* Disable the timestamp counter */
2367 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2369 /* Zero the lower/upper parts of the 64-bit counter */
2370 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2371 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2373 /* Enable the counter */
2374 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2377 static void goya_disable_timestamp(struct hl_device *hdev)
2379 /* Disable the timestamp counter */
2380 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2383 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2385 u32 wait_timeout_ms;
2388 "Halting compute engines and disabling interrupts\n");
2391 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2393 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2395 goya_stop_external_queues(hdev);
2396 goya_stop_internal_queues(hdev);
2398 msleep(wait_timeout_ms);
2400 goya_dma_stall(hdev);
2401 goya_tpc_stall(hdev);
2402 goya_mme_stall(hdev);
2404 msleep(wait_timeout_ms);
2406 goya_disable_external_queues(hdev);
2407 goya_disable_internal_queues(hdev);
2409 goya_disable_timestamp(hdev);
2412 goya_disable_msix(hdev);
2413 goya_mmu_remove_device_cpu_mappings(hdev);
2415 goya_sync_irqs(hdev);
2420 * goya_load_firmware_to_device() - Load LINUX FW code to device.
2421 * @hdev: Pointer to hl_device structure.
2423 * Copy LINUX fw code from firmware file to HBM BAR.
2425 * Return: 0 on success, non-zero for failure.
2427 static int goya_load_firmware_to_device(struct hl_device *hdev)
2431 dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2433 return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2437 * goya_load_boot_fit_to_device() - Load boot fit to device.
2438 * @hdev: Pointer to hl_device structure.
2440 * Copy boot fit file to SRAM BAR.
2442 * Return: 0 on success, non-zero for failure.
2444 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2448 dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2450 return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2453 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2455 struct dynamic_fw_load_mgr *dynamic_loader;
2456 struct cpu_dyn_regs *dyn_regs;
2458 dynamic_loader = &hdev->fw_loader.dynamic_loader;
2461 * here we update initial values for few specific dynamic regs (as
2462 * before reading the first descriptor from FW those value has to be
2463 * hard-coded) in later stages of the protocol those values will be
2464 * updated automatically by reading the FW descriptor so data there
2465 * will always be up-to-date
2467 dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2468 dyn_regs->kmd_msg_to_cpu =
2469 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2470 dyn_regs->cpu_cmd_status_to_host =
2471 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2473 dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2476 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2478 struct static_fw_load_mgr *static_loader;
2480 static_loader = &hdev->fw_loader.static_loader;
2482 static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2483 static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2484 static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2485 static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2486 static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2487 static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2488 static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2489 static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2490 static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2491 static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2492 static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2493 static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2496 static void goya_init_firmware_loader(struct hl_device *hdev)
2498 struct asic_fixed_properties *prop = &hdev->asic_prop;
2499 struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2501 /* fill common fields */
2502 fw_loader->linux_loaded = false;
2503 fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2504 fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2505 fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2506 fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2507 fw_loader->skip_bmc = false;
2508 fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2509 fw_loader->dram_bar_id = DDR_BAR_ID;
2511 if (prop->dynamic_fw_load)
2512 goya_init_dynamic_firmware_loader(hdev);
2514 goya_init_static_firmware_loader(hdev);
2517 static int goya_init_cpu(struct hl_device *hdev)
2519 struct goya_device *goya = hdev->asic_specific;
2522 if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2525 if (goya->hw_cap_initialized & HW_CAP_CPU)
2529 * Before pushing u-boot/linux to device, need to set the ddr bar to
2530 * base address of dram
2532 if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2534 "failed to map DDR bar to DRAM base address\n");
2538 rc = hl_fw_init_cpu(hdev);
2543 goya->hw_cap_initialized |= HW_CAP_CPU;
2548 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2551 u32 status, timeout_usec;
2555 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2557 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2559 WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2560 WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2561 WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2563 rc = hl_poll_timeout(
2567 !(status & 0x80000000),
2573 "Timeout during MMU hop0 config of asid %d\n", asid);
2580 int goya_mmu_init(struct hl_device *hdev)
2582 struct asic_fixed_properties *prop = &hdev->asic_prop;
2583 struct goya_device *goya = hdev->asic_specific;
2587 if (!hdev->mmu_enable)
2590 if (goya->hw_cap_initialized & HW_CAP_MMU)
2593 hdev->dram_default_page_mapping = true;
2595 for (i = 0 ; i < prop->max_asid ; i++) {
2596 hop0_addr = prop->mmu_pgt_addr +
2597 (i * prop->mmu_hop_table_size);
2599 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2602 "failed to set hop0 addr for asid %d\n", i);
2607 goya->hw_cap_initialized |= HW_CAP_MMU;
2609 /* init MMU cache manage page */
2610 WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2611 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2612 WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2614 /* Remove follower feature due to performance bug */
2615 WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2616 (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2618 hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
2619 VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);
2621 WREG32(mmMMU_MMU_ENABLE, 1);
2622 WREG32(mmMMU_SPI_MASK, 0xF);
2631 * goya_hw_init - Goya hardware initialization code
2633 * @hdev: pointer to hl_device structure
2635 * Returns 0 on success
2638 static int goya_hw_init(struct hl_device *hdev)
2640 struct asic_fixed_properties *prop = &hdev->asic_prop;
2643 /* Perform read from the device to make sure device is up */
2644 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2647 * Let's mark in the H/W that we have reached this point. We check
2648 * this value in the reset_before_init function to understand whether
2649 * we need to reset the chip before doing H/W init. This register is
2650 * cleared by the H/W upon H/W reset
2652 WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2654 rc = goya_init_cpu(hdev);
2656 dev_err(hdev->dev, "failed to initialize CPU\n");
2660 goya_tpc_mbist_workaround(hdev);
2662 goya_init_golden_registers(hdev);
2665 * After CPU initialization is finished, change DDR bar mapping inside
2666 * iATU to point to the start address of the MMU page tables
2668 if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2669 ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2671 "failed to map DDR bar to MMU page tables\n");
2675 rc = goya_mmu_init(hdev);
2679 goya_init_security(hdev);
2681 goya_init_dma_qmans(hdev);
2683 goya_init_mme_qmans(hdev);
2685 goya_init_tpc_qmans(hdev);
2687 goya_enable_timestamp(hdev);
2689 /* MSI-X must be enabled before CPU queues are initialized */
2690 rc = goya_enable_msix(hdev);
2692 goto disable_queues;
2694 /* Perform read from the device to flush all MSI-X configuration */
2695 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2700 goya_disable_internal_queues(hdev);
2701 goya_disable_external_queues(hdev);
2707 * goya_hw_fini - Goya hardware tear-down code
2709 * @hdev: pointer to hl_device structure
2710 * @hard_reset: should we do hard reset to all engines or just reset the
2711 * compute/dma engines
2713 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2715 struct goya_device *goya = hdev->asic_specific;
2716 u32 reset_timeout_ms, cpu_timeout_ms, status;
2719 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2720 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2722 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2723 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2727 /* I don't know what is the state of the CPU so make sure it is
2728 * stopped in any means necessary
2730 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2731 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2732 GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2734 msleep(cpu_timeout_ms);
2736 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2737 goya_disable_clk_rlx(hdev);
2738 goya_set_pll_refclk(hdev);
2740 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2742 "Issued HARD reset command, going to wait %dms\n",
2745 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2747 "Issued SOFT reset command, going to wait %dms\n",
2752 * After hard reset, we can't poll the BTM_FSM register because the PSOC
2753 * itself is in reset. In either reset we need to wait until the reset
2756 msleep(reset_timeout_ms);
2758 status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2759 if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2761 "Timeout while waiting for device to reset 0x%x\n",
2764 if (!hard_reset && goya) {
2765 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2766 HW_CAP_GOLDEN | HW_CAP_TPC);
2767 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2768 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2772 /* Chicken bit to re-initiate boot sequencer flow */
2773 WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2774 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2775 /* Move boot manager FSM to pre boot sequencer init state */
2776 WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2777 0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2780 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2781 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2782 HW_CAP_DMA | HW_CAP_MME |
2783 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2784 HW_CAP_GOLDEN | HW_CAP_TPC);
2786 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2790 int goya_suspend(struct hl_device *hdev)
2794 rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
2796 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2801 int goya_resume(struct hl_device *hdev)
2803 return goya_init_iatu(hdev);
2806 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2807 void *cpu_addr, dma_addr_t dma_addr, size_t size)
2811 vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2812 VM_DONTCOPY | VM_NORESERVE;
2814 rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2815 (dma_addr - HOST_PHYS_BASE), size);
2817 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2822 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2824 u32 db_reg_offset, db_value;
2826 switch (hw_queue_id) {
2827 case GOYA_QUEUE_ID_DMA_0:
2828 db_reg_offset = mmDMA_QM_0_PQ_PI;
2831 case GOYA_QUEUE_ID_DMA_1:
2832 db_reg_offset = mmDMA_QM_1_PQ_PI;
2835 case GOYA_QUEUE_ID_DMA_2:
2836 db_reg_offset = mmDMA_QM_2_PQ_PI;
2839 case GOYA_QUEUE_ID_DMA_3:
2840 db_reg_offset = mmDMA_QM_3_PQ_PI;
2843 case GOYA_QUEUE_ID_DMA_4:
2844 db_reg_offset = mmDMA_QM_4_PQ_PI;
2847 case GOYA_QUEUE_ID_CPU_PQ:
2848 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2851 case GOYA_QUEUE_ID_MME:
2852 db_reg_offset = mmMME_QM_PQ_PI;
2855 case GOYA_QUEUE_ID_TPC0:
2856 db_reg_offset = mmTPC0_QM_PQ_PI;
2859 case GOYA_QUEUE_ID_TPC1:
2860 db_reg_offset = mmTPC1_QM_PQ_PI;
2863 case GOYA_QUEUE_ID_TPC2:
2864 db_reg_offset = mmTPC2_QM_PQ_PI;
2867 case GOYA_QUEUE_ID_TPC3:
2868 db_reg_offset = mmTPC3_QM_PQ_PI;
2871 case GOYA_QUEUE_ID_TPC4:
2872 db_reg_offset = mmTPC4_QM_PQ_PI;
2875 case GOYA_QUEUE_ID_TPC5:
2876 db_reg_offset = mmTPC5_QM_PQ_PI;
2879 case GOYA_QUEUE_ID_TPC6:
2880 db_reg_offset = mmTPC6_QM_PQ_PI;
2883 case GOYA_QUEUE_ID_TPC7:
2884 db_reg_offset = mmTPC7_QM_PQ_PI;
2888 /* Should never get here */
2889 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2896 /* ring the doorbell */
2897 WREG32(db_reg_offset, db_value);
2899 if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2900 /* make sure device CPU will read latest data from host */
2902 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2903 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2907 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2909 /* The QMANs are on the SRAM so need to copy to IO space */
2910 memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2913 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2914 dma_addr_t *dma_handle, gfp_t flags)
2916 void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2919 /* Shift to the device's base physical address of host memory */
2921 *dma_handle += HOST_PHYS_BASE;
2926 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2927 void *cpu_addr, dma_addr_t dma_handle)
2929 /* Cancel the device's base physical address of host memory */
2930 dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
2932 dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
2935 int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
2940 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2941 dma_addr_t *dma_handle, u16 *queue_len)
2946 *dma_handle = hdev->asic_prop.sram_base_address;
2948 base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2951 case GOYA_QUEUE_ID_MME:
2952 offset = MME_QMAN_BASE_OFFSET;
2953 *queue_len = MME_QMAN_LENGTH;
2955 case GOYA_QUEUE_ID_TPC0:
2956 offset = TPC0_QMAN_BASE_OFFSET;
2957 *queue_len = TPC_QMAN_LENGTH;
2959 case GOYA_QUEUE_ID_TPC1:
2960 offset = TPC1_QMAN_BASE_OFFSET;
2961 *queue_len = TPC_QMAN_LENGTH;
2963 case GOYA_QUEUE_ID_TPC2:
2964 offset = TPC2_QMAN_BASE_OFFSET;
2965 *queue_len = TPC_QMAN_LENGTH;
2967 case GOYA_QUEUE_ID_TPC3:
2968 offset = TPC3_QMAN_BASE_OFFSET;
2969 *queue_len = TPC_QMAN_LENGTH;
2971 case GOYA_QUEUE_ID_TPC4:
2972 offset = TPC4_QMAN_BASE_OFFSET;
2973 *queue_len = TPC_QMAN_LENGTH;
2975 case GOYA_QUEUE_ID_TPC5:
2976 offset = TPC5_QMAN_BASE_OFFSET;
2977 *queue_len = TPC_QMAN_LENGTH;
2979 case GOYA_QUEUE_ID_TPC6:
2980 offset = TPC6_QMAN_BASE_OFFSET;
2981 *queue_len = TPC_QMAN_LENGTH;
2983 case GOYA_QUEUE_ID_TPC7:
2984 offset = TPC7_QMAN_BASE_OFFSET;
2985 *queue_len = TPC_QMAN_LENGTH;
2988 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2993 *dma_handle += offset;
2998 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3000 struct packet_msg_prot *fence_pkt;
3002 dma_addr_t fence_dma_addr;
3008 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3010 timeout = HL_DEVICE_TIMEOUT_USEC;
3012 if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3013 dev_err_ratelimited(hdev->dev,
3014 "Can't send driver job on QMAN0 because the device is not idle\n");
3018 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3022 "Failed to allocate fence memory for QMAN0\n");
3026 goya_qman0_set_security(hdev, true);
3028 cb = job->patched_cb;
3030 fence_pkt = cb->kernel_address +
3031 job->job_cb_size - sizeof(struct packet_msg_prot);
3033 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3034 (1 << GOYA_PKT_CTL_EB_SHIFT) |
3035 (1 << GOYA_PKT_CTL_MB_SHIFT);
3036 fence_pkt->ctl = cpu_to_le32(tmp);
3037 fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3038 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3040 rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3041 job->job_cb_size, cb->bus_address);
3043 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3044 goto free_fence_ptr;
3047 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3048 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3051 hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3053 if (rc == -ETIMEDOUT) {
3054 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3055 goto free_fence_ptr;
3059 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3062 goya_qman0_set_security(hdev, false);
3067 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3068 u32 timeout, u64 *result)
3070 struct goya_device *goya = hdev->asic_specific;
3072 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3079 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3081 return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3085 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3087 struct packet_msg_prot *fence_pkt;
3088 dma_addr_t pkt_dma_addr;
3090 dma_addr_t fence_dma_addr;
3094 fence_val = GOYA_QMAN0_FENCE_VAL;
3096 fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3100 "Failed to allocate memory for H/W queue %d testing\n",
3107 fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
3108 sizeof(struct packet_msg_prot),
3109 GFP_KERNEL, &pkt_dma_addr);
3112 "Failed to allocate packet for H/W queue %d testing\n",
3115 goto free_fence_ptr;
3118 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3119 (1 << GOYA_PKT_CTL_EB_SHIFT) |
3120 (1 << GOYA_PKT_CTL_MB_SHIFT);
3121 fence_pkt->ctl = cpu_to_le32(tmp);
3122 fence_pkt->value = cpu_to_le32(fence_val);
3123 fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3125 rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3126 sizeof(struct packet_msg_prot),
3130 "Failed to send fence packet to H/W queue %d\n",
3135 rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3136 1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3138 hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3140 if (rc == -ETIMEDOUT) {
3142 "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3143 hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3148 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
3151 hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3156 int goya_test_cpu_queue(struct hl_device *hdev)
3158 struct goya_device *goya = hdev->asic_specific;
3161 * check capability here as send_cpu_message() won't update the result
3162 * value if no capability
3164 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3167 return hl_fw_test_cpu_queue(hdev);
3170 int goya_test_queues(struct hl_device *hdev)
3172 int i, rc, ret_val = 0;
3174 for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3175 rc = goya_test_queue(hdev, i);
3183 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3184 gfp_t mem_flags, dma_addr_t *dma_handle)
3188 if (size > GOYA_DMA_POOL_BLK_SIZE)
3191 kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3193 /* Shift to the device's base physical address of host memory */
3195 *dma_handle += HOST_PHYS_BASE;
3200 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3201 dma_addr_t dma_addr)
3203 /* Cancel the device's base physical address of host memory */
3204 dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3206 dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3209 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3210 dma_addr_t *dma_handle)
3214 vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3215 *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3216 VA_CPU_ACCESSIBLE_MEM_ADDR;
3221 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3224 hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3227 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3228 int nents, enum dma_data_direction dir)
3230 struct scatterlist *sg;
3233 if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3236 /* Shift to the device's base physical address of host memory */
3237 for_each_sg(sgl, sg, nents, i)
3238 sg->dma_address += HOST_PHYS_BASE;
3243 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3244 int nents, enum dma_data_direction dir)
3246 struct scatterlist *sg;
3249 /* Cancel the device's base physical address of host memory */
3250 for_each_sg(sgl, sg, nents, i)
3251 sg->dma_address -= HOST_PHYS_BASE;
3253 dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3256 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3258 struct scatterlist *sg, *sg_next_iter;
3259 u32 count, dma_desc_cnt;
3261 dma_addr_t addr, addr_next;
3265 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3267 len = sg_dma_len(sg);
3268 addr = sg_dma_address(sg);
3273 while ((count + 1) < sgt->nents) {
3274 sg_next_iter = sg_next(sg);
3275 len_next = sg_dma_len(sg_next_iter);
3276 addr_next = sg_dma_address(sg_next_iter);
3281 if ((addr + len == addr_next) &&
3282 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3294 return dma_desc_cnt * sizeof(struct packet_lin_dma);
3297 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3298 struct hl_cs_parser *parser,
3299 struct packet_lin_dma *user_dma_pkt,
3300 u64 addr, enum dma_data_direction dir)
3302 struct hl_userptr *userptr;
3305 if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3306 parser->job_userptr_list, &userptr))
3307 goto already_pinned;
3309 userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3313 rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3318 list_add_tail(&userptr->job_node, parser->job_userptr_list);
3320 rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3321 userptr->sgt->nents, dir);
3323 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3327 userptr->dma_mapped = true;
3331 parser->patched_cb_size +=
3332 goya_get_dma_desc_list_size(hdev, userptr->sgt);
3337 list_del(&userptr->job_node);
3338 hl_unpin_host_memory(hdev, userptr);
3344 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3345 struct hl_cs_parser *parser,
3346 struct packet_lin_dma *user_dma_pkt)
3348 u64 device_memory_addr, addr;
3349 enum dma_data_direction dir;
3350 enum goya_dma_direction user_dir;
3351 bool sram_addr = true;
3352 bool skip_host_mem_pin = false;
3357 ctl = le32_to_cpu(user_dma_pkt->ctl);
3359 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3360 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3362 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3363 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3366 case DMA_HOST_TO_DRAM:
3367 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3368 dir = DMA_TO_DEVICE;
3370 addr = le64_to_cpu(user_dma_pkt->src_addr);
3371 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3373 skip_host_mem_pin = true;
3376 case DMA_DRAM_TO_HOST:
3377 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3378 dir = DMA_FROM_DEVICE;
3380 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3381 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3384 case DMA_HOST_TO_SRAM:
3385 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3386 dir = DMA_TO_DEVICE;
3387 addr = le64_to_cpu(user_dma_pkt->src_addr);
3388 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3390 skip_host_mem_pin = true;
3393 case DMA_SRAM_TO_HOST:
3394 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3395 dir = DMA_FROM_DEVICE;
3396 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3397 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3400 dev_err(hdev->dev, "DMA direction is undefined\n");
3405 if (!hl_mem_area_inside_range(device_memory_addr,
3406 le32_to_cpu(user_dma_pkt->tsize),
3407 hdev->asic_prop.sram_user_base_address,
3408 hdev->asic_prop.sram_end_address)) {
3411 "SRAM address 0x%llx + 0x%x is invalid\n",
3413 user_dma_pkt->tsize);
3417 if (!hl_mem_area_inside_range(device_memory_addr,
3418 le32_to_cpu(user_dma_pkt->tsize),
3419 hdev->asic_prop.dram_user_base_address,
3420 hdev->asic_prop.dram_end_address)) {
3423 "DRAM address 0x%llx + 0x%x is invalid\n",
3425 user_dma_pkt->tsize);
3430 if (skip_host_mem_pin)
3431 parser->patched_cb_size += sizeof(*user_dma_pkt);
3433 if ((dir == DMA_TO_DEVICE) &&
3434 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3436 "Can't DMA from host on queue other then 1\n");
3440 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3447 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3448 struct hl_cs_parser *parser,
3449 struct packet_lin_dma *user_dma_pkt)
3451 u64 sram_memory_addr, dram_memory_addr;
3452 enum goya_dma_direction user_dir;
3455 ctl = le32_to_cpu(user_dma_pkt->ctl);
3456 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3457 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3459 if (user_dir == DMA_DRAM_TO_SRAM) {
3460 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3461 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3462 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3464 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3465 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3466 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3469 if (!hl_mem_area_inside_range(sram_memory_addr,
3470 le32_to_cpu(user_dma_pkt->tsize),
3471 hdev->asic_prop.sram_user_base_address,
3472 hdev->asic_prop.sram_end_address)) {
3473 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3474 sram_memory_addr, user_dma_pkt->tsize);
3478 if (!hl_mem_area_inside_range(dram_memory_addr,
3479 le32_to_cpu(user_dma_pkt->tsize),
3480 hdev->asic_prop.dram_user_base_address,
3481 hdev->asic_prop.dram_end_address)) {
3482 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3483 dram_memory_addr, user_dma_pkt->tsize);
3487 parser->patched_cb_size += sizeof(*user_dma_pkt);
3492 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3493 struct hl_cs_parser *parser,
3494 struct packet_lin_dma *user_dma_pkt)
3496 enum goya_dma_direction user_dir;
3500 dev_dbg(hdev->dev, "DMA packet details:\n");
3501 dev_dbg(hdev->dev, "source == 0x%llx\n",
3502 le64_to_cpu(user_dma_pkt->src_addr));
3503 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3504 le64_to_cpu(user_dma_pkt->dst_addr));
3505 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3507 ctl = le32_to_cpu(user_dma_pkt->ctl);
3508 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3509 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3512 * Special handling for DMA with size 0. The H/W has a bug where
3513 * this can cause the QMAN DMA to get stuck, so block it here.
3515 if (user_dma_pkt->tsize == 0) {
3517 "Got DMA with size 0, might reset the device\n");
3521 if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3522 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3524 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3529 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3530 struct hl_cs_parser *parser,
3531 struct packet_lin_dma *user_dma_pkt)
3533 dev_dbg(hdev->dev, "DMA packet details:\n");
3534 dev_dbg(hdev->dev, "source == 0x%llx\n",
3535 le64_to_cpu(user_dma_pkt->src_addr));
3536 dev_dbg(hdev->dev, "destination == 0x%llx\n",
3537 le64_to_cpu(user_dma_pkt->dst_addr));
3538 dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3542 * We can't allow user to read from Host using QMANs other than 1.
3543 * PMMU and HPMMU addresses are equal, check only one of them.
3545 if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3546 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3547 le32_to_cpu(user_dma_pkt->tsize),
3548 hdev->asic_prop.pmmu.start_addr,
3549 hdev->asic_prop.pmmu.end_addr)) {
3551 "Can't DMA from host on queue other then 1\n");
3555 if (user_dma_pkt->tsize == 0) {
3557 "Got DMA with size 0, might reset the device\n");
3561 parser->patched_cb_size += sizeof(*user_dma_pkt);
3566 static int goya_validate_wreg32(struct hl_device *hdev,
3567 struct hl_cs_parser *parser,
3568 struct packet_wreg32 *wreg_pkt)
3570 struct goya_device *goya = hdev->asic_specific;
3571 u32 sob_start_addr, sob_end_addr;
3574 reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3575 GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3577 dev_dbg(hdev->dev, "WREG32 packet details:\n");
3578 dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3579 dev_dbg(hdev->dev, "value == 0x%x\n",
3580 le32_to_cpu(wreg_pkt->value));
3582 if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3583 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3589 * With MMU, DMA channels are not secured, so it doesn't matter where
3590 * the WR COMP will be written to because it will go out with
3591 * non-secured property
3593 if (goya->hw_cap_initialized & HW_CAP_MMU)
3596 sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3597 sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3599 if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3600 (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3602 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3610 static int goya_validate_cb(struct hl_device *hdev,
3611 struct hl_cs_parser *parser, bool is_mmu)
3613 u32 cb_parsed_length = 0;
3616 parser->patched_cb_size = 0;
3618 /* cb_user_size is more than 0 so loop will always be executed */
3619 while (cb_parsed_length < parser->user_cb_size) {
3620 enum packet_id pkt_id;
3622 struct goya_packet *user_pkt;
3624 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3626 pkt_id = (enum packet_id) (
3627 (le64_to_cpu(user_pkt->header) &
3628 PACKET_HEADER_PACKET_ID_MASK) >>
3629 PACKET_HEADER_PACKET_ID_SHIFT);
3631 if (!validate_packet_id(pkt_id)) {
3632 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3637 pkt_size = goya_packet_sizes[pkt_id];
3638 cb_parsed_length += pkt_size;
3639 if (cb_parsed_length > parser->user_cb_size) {
3641 "packet 0x%x is out of CB boundary\n", pkt_id);
3647 case PACKET_WREG_32:
3649 * Although it is validated after copy in patch_cb(),
3650 * need to validate here as well because patch_cb() is
3651 * not called in MMU path while this function is called
3653 rc = goya_validate_wreg32(hdev,
3654 parser, (struct packet_wreg32 *) user_pkt);
3655 parser->patched_cb_size += pkt_size;
3658 case PACKET_WREG_BULK:
3660 "User not allowed to use WREG_BULK\n");
3664 case PACKET_MSG_PROT:
3666 "User not allowed to use MSG_PROT\n");
3671 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3676 dev_err(hdev->dev, "User not allowed to use STOP\n");
3680 case PACKET_LIN_DMA:
3682 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3683 (struct packet_lin_dma *) user_pkt);
3685 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3686 (struct packet_lin_dma *) user_pkt);
3689 case PACKET_MSG_LONG:
3690 case PACKET_MSG_SHORT:
3693 parser->patched_cb_size += pkt_size;
3697 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3708 * The new CB should have space at the end for two MSG_PROT packets:
3709 * 1. A packet that will act as a completion packet
3710 * 2. A packet that will generate MSI-X interrupt
3712 parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3717 static int goya_patch_dma_packet(struct hl_device *hdev,
3718 struct hl_cs_parser *parser,
3719 struct packet_lin_dma *user_dma_pkt,
3720 struct packet_lin_dma *new_dma_pkt,
3721 u32 *new_dma_pkt_size)
3723 struct hl_userptr *userptr;
3724 struct scatterlist *sg, *sg_next_iter;
3725 u32 count, dma_desc_cnt;
3727 dma_addr_t dma_addr, dma_addr_next;
3728 enum goya_dma_direction user_dir;
3729 u64 device_memory_addr, addr;
3730 enum dma_data_direction dir;
3731 struct sg_table *sgt;
3732 bool skip_host_mem_pin = false;
3734 u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3736 ctl = le32_to_cpu(user_dma_pkt->ctl);
3738 user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3739 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3741 user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3742 GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3744 if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3745 (user_dma_pkt->tsize == 0)) {
3746 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3747 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3751 if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3752 addr = le64_to_cpu(user_dma_pkt->src_addr);
3753 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3754 dir = DMA_TO_DEVICE;
3756 skip_host_mem_pin = true;
3758 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3759 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3760 dir = DMA_FROM_DEVICE;
3763 if ((!skip_host_mem_pin) &&
3764 (hl_userptr_is_pinned(hdev, addr,
3765 le32_to_cpu(user_dma_pkt->tsize),
3766 parser->job_userptr_list, &userptr) == false)) {
3767 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3768 addr, user_dma_pkt->tsize);
3772 if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3773 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3774 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3778 user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3780 user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3785 for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3786 len = sg_dma_len(sg);
3787 dma_addr = sg_dma_address(sg);
3792 while ((count + 1) < sgt->nents) {
3793 sg_next_iter = sg_next(sg);
3794 len_next = sg_dma_len(sg_next_iter);
3795 dma_addr_next = sg_dma_address(sg_next_iter);
3800 if ((dma_addr + len == dma_addr_next) &&
3801 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3810 ctl = le32_to_cpu(user_dma_pkt->ctl);
3811 if (likely(dma_desc_cnt))
3812 ctl &= ~GOYA_PKT_CTL_EB_MASK;
3813 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3814 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3815 new_dma_pkt->ctl = cpu_to_le32(ctl);
3816 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3818 if (dir == DMA_TO_DEVICE) {
3819 new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3820 new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3822 new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3823 new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3827 device_memory_addr += len;
3832 if (!dma_desc_cnt) {
3834 "Error of 0 SG entries when patching DMA packet\n");
3838 /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3840 new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3842 *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3847 static int goya_patch_cb(struct hl_device *hdev,
3848 struct hl_cs_parser *parser)
3850 u32 cb_parsed_length = 0;
3851 u32 cb_patched_cur_length = 0;
3854 /* cb_user_size is more than 0 so loop will always be executed */
3855 while (cb_parsed_length < parser->user_cb_size) {
3856 enum packet_id pkt_id;
3858 u32 new_pkt_size = 0;
3859 struct goya_packet *user_pkt, *kernel_pkt;
3861 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3862 kernel_pkt = parser->patched_cb->kernel_address +
3863 cb_patched_cur_length;
3865 pkt_id = (enum packet_id) (
3866 (le64_to_cpu(user_pkt->header) &
3867 PACKET_HEADER_PACKET_ID_MASK) >>
3868 PACKET_HEADER_PACKET_ID_SHIFT);
3870 if (!validate_packet_id(pkt_id)) {
3871 dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3876 pkt_size = goya_packet_sizes[pkt_id];
3877 cb_parsed_length += pkt_size;
3878 if (cb_parsed_length > parser->user_cb_size) {
3880 "packet 0x%x is out of CB boundary\n", pkt_id);
3886 case PACKET_LIN_DMA:
3887 rc = goya_patch_dma_packet(hdev, parser,
3888 (struct packet_lin_dma *) user_pkt,
3889 (struct packet_lin_dma *) kernel_pkt,
3891 cb_patched_cur_length += new_pkt_size;
3894 case PACKET_WREG_32:
3895 memcpy(kernel_pkt, user_pkt, pkt_size);
3896 cb_patched_cur_length += pkt_size;
3897 rc = goya_validate_wreg32(hdev, parser,
3898 (struct packet_wreg32 *) kernel_pkt);
3901 case PACKET_WREG_BULK:
3903 "User not allowed to use WREG_BULK\n");
3907 case PACKET_MSG_PROT:
3909 "User not allowed to use MSG_PROT\n");
3914 dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3919 dev_err(hdev->dev, "User not allowed to use STOP\n");
3923 case PACKET_MSG_LONG:
3924 case PACKET_MSG_SHORT:
3927 memcpy(kernel_pkt, user_pkt, pkt_size);
3928 cb_patched_cur_length += pkt_size;
3932 dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3945 static int goya_parse_cb_mmu(struct hl_device *hdev,
3946 struct hl_cs_parser *parser)
3948 u64 patched_cb_handle;
3949 u32 patched_cb_size;
3950 struct hl_cb *user_cb;
3954 * The new CB should have space at the end for two MSG_PROT pkt:
3955 * 1. A packet that will act as a completion packet
3956 * 2. A packet that will generate MSI-X interrupt
3958 parser->patched_cb_size = parser->user_cb_size +
3959 sizeof(struct packet_msg_prot) * 2;
3961 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
3962 parser->patched_cb_size, false, false,
3963 &patched_cb_handle);
3967 "Failed to allocate patched CB for DMA CS %d\n",
3972 patched_cb_handle >>= PAGE_SHIFT;
3973 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3974 (u32) patched_cb_handle);
3975 /* hl_cb_get should never fail here */
3976 if (!parser->patched_cb) {
3977 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
3978 (u32) patched_cb_handle);
3984 * The check that parser->user_cb_size <= parser->user_cb->size was done
3985 * in validate_queue_index().
3987 memcpy(parser->patched_cb->kernel_address,
3988 parser->user_cb->kernel_address,
3989 parser->user_cb_size);
3991 patched_cb_size = parser->patched_cb_size;
3993 /* validate patched CB instead of user CB */
3994 user_cb = parser->user_cb;
3995 parser->user_cb = parser->patched_cb;
3996 rc = goya_validate_cb(hdev, parser, true);
3997 parser->user_cb = user_cb;
4000 hl_cb_put(parser->patched_cb);
4004 if (patched_cb_size != parser->patched_cb_size) {
4005 dev_err(hdev->dev, "user CB size mismatch\n");
4006 hl_cb_put(parser->patched_cb);
4013 * Always call cb destroy here because we still have 1 reference
4014 * to it by calling cb_get earlier. After the job will be completed,
4015 * cb_put will release it, but here we want to remove it from the
4018 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4019 patched_cb_handle << PAGE_SHIFT);
4024 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4025 struct hl_cs_parser *parser)
4027 u64 patched_cb_handle;
4030 rc = goya_validate_cb(hdev, parser, false);
4035 rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
4036 parser->patched_cb_size, false, false,
4037 &patched_cb_handle);
4040 "Failed to allocate patched CB for DMA CS %d\n", rc);
4044 patched_cb_handle >>= PAGE_SHIFT;
4045 parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4046 (u32) patched_cb_handle);
4047 /* hl_cb_get should never fail here */
4048 if (!parser->patched_cb) {
4049 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
4050 (u32) patched_cb_handle);
4055 rc = goya_patch_cb(hdev, parser);
4058 hl_cb_put(parser->patched_cb);
4062 * Always call cb destroy here because we still have 1 reference
4063 * to it by calling cb_get earlier. After the job will be completed,
4064 * cb_put will release it, but here we want to remove it from the
4067 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4068 patched_cb_handle << PAGE_SHIFT);
4072 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4076 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4077 struct hl_cs_parser *parser)
4079 struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4080 struct goya_device *goya = hdev->asic_specific;
4082 if (goya->hw_cap_initialized & HW_CAP_MMU)
4085 /* For internal queue jobs, just check if CB address is valid */
4086 if (hl_mem_area_inside_range(
4087 (u64) (uintptr_t) parser->user_cb,
4088 parser->user_cb_size,
4089 asic_prop->sram_user_base_address,
4090 asic_prop->sram_end_address))
4093 if (hl_mem_area_inside_range(
4094 (u64) (uintptr_t) parser->user_cb,
4095 parser->user_cb_size,
4096 asic_prop->dram_user_base_address,
4097 asic_prop->dram_end_address))
4101 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4102 parser->user_cb, parser->user_cb_size);
4107 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4109 struct goya_device *goya = hdev->asic_specific;
4111 if (parser->queue_type == QUEUE_TYPE_INT)
4112 return goya_parse_cb_no_ext_queue(hdev, parser);
4114 if (goya->hw_cap_initialized & HW_CAP_MMU)
4115 return goya_parse_cb_mmu(hdev, parser);
4117 return goya_parse_cb_no_mmu(hdev, parser);
4120 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4121 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
4124 struct packet_msg_prot *cq_pkt;
4127 cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4129 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4130 (1 << GOYA_PKT_CTL_EB_SHIFT) |
4131 (1 << GOYA_PKT_CTL_MB_SHIFT);
4132 cq_pkt->ctl = cpu_to_le32(tmp);
4133 cq_pkt->value = cpu_to_le32(cq_val);
4134 cq_pkt->addr = cpu_to_le64(cq_addr);
4138 tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4139 (1 << GOYA_PKT_CTL_MB_SHIFT);
4140 cq_pkt->ctl = cpu_to_le32(tmp);
4141 cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4142 cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4145 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4147 WREG32(mmCPU_EQ_CI, val);
4150 void goya_restore_phase_topology(struct hl_device *hdev)
4155 static void goya_clear_sm_regs(struct hl_device *hdev)
4157 int i, num_of_sob_in_longs, num_of_mon_in_longs;
4159 num_of_sob_in_longs =
4160 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4162 num_of_mon_in_longs =
4163 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4165 for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4166 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4168 for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4169 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4171 /* Flush all WREG to prevent race */
4172 i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4176 * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
4179 * @hdev: pointer to hl_device structure
4180 * @addr: device or host mapped address
4181 * @val: returned value
4183 * In case of DDR address that is not mapped into the default aperture that
4184 * the DDR bar exposes, the function will configure the iATU so that the DDR
4185 * bar will be positioned at a base address that allows reading from the
4186 * required address. Configuring the iATU during normal operation can
4187 * lead to undefined behavior and therefore, should be done with extreme care
4190 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,
4191 bool user_address, u32 *val)
4193 struct asic_fixed_properties *prop = &hdev->asic_prop;
4194 u64 ddr_bar_addr, host_phys_end;
4197 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4199 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4200 *val = RREG32(addr - CFG_BASE);
4202 } else if ((addr >= SRAM_BASE_ADDR) &&
4203 (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4205 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4206 (addr - SRAM_BASE_ADDR));
4208 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4210 u64 bar_base_addr = DRAM_PHYS_BASE +
4211 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4213 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4214 if (ddr_bar_addr != U64_MAX) {
4215 *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4216 (addr - bar_base_addr));
4218 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4221 if (ddr_bar_addr == U64_MAX)
4224 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4225 user_address && !iommu_present(&pci_bus_type)) {
4226 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4236 * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4239 * @hdev: pointer to hl_device structure
4240 * @addr: device or host mapped address
4241 * @val: returned value
4243 * In case of DDR address that is not mapped into the default aperture that
4244 * the DDR bar exposes, the function will configure the iATU so that the DDR
4245 * bar will be positioned at a base address that allows writing to the
4246 * required address. Configuring the iATU during normal operation can
4247 * lead to undefined behavior and therefore, should be done with extreme care
4250 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,
4251 bool user_address, u32 val)
4253 struct asic_fixed_properties *prop = &hdev->asic_prop;
4254 u64 ddr_bar_addr, host_phys_end;
4257 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4259 if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4260 WREG32(addr - CFG_BASE, val);
4262 } else if ((addr >= SRAM_BASE_ADDR) &&
4263 (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4265 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4266 (addr - SRAM_BASE_ADDR));
4268 } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4270 u64 bar_base_addr = DRAM_PHYS_BASE +
4271 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4273 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4274 if (ddr_bar_addr != U64_MAX) {
4275 writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4276 (addr - bar_base_addr));
4278 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4281 if (ddr_bar_addr == U64_MAX)
4284 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4285 user_address && !iommu_present(&pci_bus_type)) {
4286 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4295 static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,
4296 bool user_address, u64 *val)
4298 struct asic_fixed_properties *prop = &hdev->asic_prop;
4299 u64 ddr_bar_addr, host_phys_end;
4302 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4304 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4305 u32 val_l = RREG32(addr - CFG_BASE);
4306 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
4308 *val = (((u64) val_h) << 32) | val_l;
4310 } else if ((addr >= SRAM_BASE_ADDR) &&
4311 (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4313 *val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4314 (addr - SRAM_BASE_ADDR));
4317 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4319 u64 bar_base_addr = DRAM_PHYS_BASE +
4320 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4322 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4323 if (ddr_bar_addr != U64_MAX) {
4324 *val = readq(hdev->pcie_bar[DDR_BAR_ID] +
4325 (addr - bar_base_addr));
4327 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4330 if (ddr_bar_addr == U64_MAX)
4333 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4334 user_address && !iommu_present(&pci_bus_type)) {
4335 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
4344 static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,
4345 bool user_address, u64 val)
4347 struct asic_fixed_properties *prop = &hdev->asic_prop;
4348 u64 ddr_bar_addr, host_phys_end;
4351 host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4353 if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4354 WREG32(addr - CFG_BASE, lower_32_bits(val));
4355 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4357 } else if ((addr >= SRAM_BASE_ADDR) &&
4358 (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4360 writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4361 (addr - SRAM_BASE_ADDR));
4364 DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4366 u64 bar_base_addr = DRAM_PHYS_BASE +
4367 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4369 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4370 if (ddr_bar_addr != U64_MAX) {
4371 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4372 (addr - bar_base_addr));
4374 ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4377 if (ddr_bar_addr == U64_MAX)
4380 } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4381 user_address && !iommu_present(&pci_bus_type)) {
4382 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4391 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
4394 dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4398 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4400 struct goya_device *goya = hdev->asic_specific;
4402 if (hdev->hard_reset_pending)
4405 return readq(hdev->pcie_bar[DDR_BAR_ID] +
4406 (addr - goya->ddr_bar_cur_addr));
4409 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4411 struct goya_device *goya = hdev->asic_specific;
4413 if (hdev->hard_reset_pending)
4416 writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4417 (addr - goya->ddr_bar_cur_addr));
4420 static const char *_goya_get_event_desc(u16 event_type)
4422 switch (event_type) {
4423 case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4425 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4426 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4427 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4428 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4429 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4430 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4431 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4432 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4434 case GOYA_ASYNC_EVENT_ID_MME_ECC:
4436 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4437 return "MME_ecc_ext";
4438 case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4440 case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4442 case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4444 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4445 return "CPU_if_ecc";
4446 case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4448 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4449 return "PSOC_coresight";
4450 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4452 case GOYA_ASYNC_EVENT_ID_GIC500:
4454 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4456 case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4458 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4459 return "L2_ram_ecc";
4460 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4461 return "PSOC_gpio_05_sw_reset";
4462 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4463 return "PSOC_gpio_10_vrhot_icrit";
4464 case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4466 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4467 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4468 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4469 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4470 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4471 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4472 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4473 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4475 case GOYA_ASYNC_EVENT_ID_MME_WACS:
4477 case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4479 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4480 return "CPU_axi_splitter";
4481 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4482 return "PSOC_axi_dec";
4483 case GOYA_ASYNC_EVENT_ID_PSOC:
4485 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4486 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4487 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4488 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4489 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4490 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4491 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4492 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4493 return "TPC%d_krn_err";
4494 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4496 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4498 case GOYA_ASYNC_EVENT_ID_MME_QM:
4500 case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4502 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4504 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4506 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4507 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4508 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4509 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4510 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4511 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4512 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4513 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4514 return "TPC%d_bmon_spmu";
4515 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4516 return "DMA_bm_ch%d";
4517 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4518 return "POWER_ENV_S";
4519 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4520 return "POWER_ENV_E";
4521 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4522 return "THERMAL_ENV_S";
4523 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4524 return "THERMAL_ENV_E";
4525 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4526 return "QUEUE_OUT_OF_SYNC";
4532 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4536 switch (event_type) {
4537 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4538 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4539 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4540 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4541 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4542 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4543 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4544 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4545 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4546 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4548 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4549 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4550 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4552 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4553 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4554 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4556 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4557 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4558 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4559 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4560 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4561 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4562 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4563 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4564 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4565 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4567 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4568 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4569 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4570 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4571 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4572 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4573 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4574 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4575 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4576 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4578 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4579 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4580 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4582 case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4583 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4584 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4586 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4587 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4588 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4590 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4591 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4592 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4594 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4595 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4596 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4597 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4598 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4599 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4600 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4601 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4602 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4603 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4605 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4606 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4607 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4609 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4610 snprintf(desc, size, _goya_get_event_desc(event_type));
4613 snprintf(desc, size, _goya_get_event_desc(event_type));
4618 static void goya_print_razwi_info(struct hl_device *hdev)
4620 if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4621 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4622 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4625 if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4626 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4627 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4630 if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4631 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4632 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4635 if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4636 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4637 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4641 static void goya_print_mmu_error_info(struct hl_device *hdev)
4643 struct goya_device *goya = hdev->asic_specific;
4647 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4650 val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4651 if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4652 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4654 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4656 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4659 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4663 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4664 struct cpucp_pkt_sync_err *sync_err)
4666 struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4668 dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n",
4669 sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci));
4672 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4677 goya_get_event_desc(event_type, desc, sizeof(desc));
4678 dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4682 goya_print_razwi_info(hdev);
4683 goya_print_mmu_error_info(hdev);
4687 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4688 size_t irq_arr_size)
4690 struct cpucp_unmask_irq_arr_packet *pkt;
4691 size_t total_pkt_size;
4694 int irq_num_entries, irq_arr_index;
4695 __le32 *goya_irq_arr;
4697 total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4700 /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4701 total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4703 /* total_pkt_size is casted to u16 later on */
4704 if (total_pkt_size > USHRT_MAX) {
4705 dev_err(hdev->dev, "too many elements in IRQ array\n");
4709 pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4713 irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4714 pkt->length = cpu_to_le32(irq_num_entries);
4716 /* We must perform any necessary endianness conversation on the irq
4717 * array being passed to the goya hardware
4719 for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4720 irq_arr_index < irq_num_entries ; irq_arr_index++)
4721 goya_irq_arr[irq_arr_index] =
4722 cpu_to_le32(irq_arr[irq_arr_index]);
4724 pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4725 CPUCP_PKT_CTL_OPCODE_SHIFT);
4727 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4728 total_pkt_size, 0, &result);
4731 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4738 static int goya_soft_reset_late_init(struct hl_device *hdev)
4741 * Unmask all IRQs since some could have been received
4742 * during the soft reset
4744 return goya_unmask_irq_arr(hdev, goya_all_events,
4745 sizeof(goya_all_events));
4748 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4750 struct cpucp_packet pkt;
4754 memset(&pkt, 0, sizeof(pkt));
4756 pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4757 CPUCP_PKT_CTL_OPCODE_SHIFT);
4758 pkt.value = cpu_to_le64(event_type);
4760 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4764 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4769 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4771 switch (event_type) {
4772 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4773 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER;
4774 dev_info_ratelimited(hdev->dev,
4775 "Clock throttling due to power consumption\n");
4777 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4778 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER;
4779 dev_info_ratelimited(hdev->dev,
4780 "Power envelop is safe, back to optimal clock\n");
4782 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4783 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL;
4784 dev_info_ratelimited(hdev->dev,
4785 "Clock throttling due to overheating\n");
4787 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4788 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL;
4789 dev_info_ratelimited(hdev->dev,
4790 "Thermal envelop is safe, back to optimal clock\n");
4794 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4800 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4802 u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4803 u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4804 >> EQ_CTL_EVENT_TYPE_SHIFT);
4805 struct goya_device *goya = hdev->asic_specific;
4807 if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4808 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4809 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4813 goya->events_stat[event_type]++;
4814 goya->events_stat_aggregate[event_type]++;
4816 switch (event_type) {
4817 case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4818 case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4819 case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4820 case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4821 case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4822 case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4823 case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4824 case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4825 case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4826 case GOYA_ASYNC_EVENT_ID_MME_ECC:
4827 case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4828 case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4829 case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4830 case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4831 case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4832 case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4833 case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4834 case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4835 case GOYA_ASYNC_EVENT_ID_GIC500:
4836 case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4837 case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4838 case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4839 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4840 goya_print_irq_info(hdev, event_type, false);
4841 if (hdev->hard_reset_on_fw_events)
4842 hl_device_reset(hdev, HL_RESET_HARD);
4845 case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4846 case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4847 case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4848 case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4849 case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4850 case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4851 case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4852 case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4853 case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4854 case GOYA_ASYNC_EVENT_ID_MME_WACS:
4855 case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4856 case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4857 case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4858 case GOYA_ASYNC_EVENT_ID_PSOC:
4859 case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4860 case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4861 case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4862 case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4863 case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4864 case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4865 case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4866 case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4867 case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4868 case GOYA_ASYNC_EVENT_ID_MME_QM:
4869 case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4870 case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4871 case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4872 goya_print_irq_info(hdev, event_type, true);
4873 goya_unmask_irq(hdev, event_type);
4876 case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4877 case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4878 case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4879 case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4880 case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4881 case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4882 case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4883 case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4884 case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4885 case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4886 goya_print_irq_info(hdev, event_type, false);
4887 goya_unmask_irq(hdev, event_type);
4890 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4891 case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4892 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4893 case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4894 goya_print_clk_change_info(hdev, event_type);
4895 goya_unmask_irq(hdev, event_type);
4898 case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4899 goya_print_irq_info(hdev, event_type, false);
4900 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4901 if (hdev->hard_reset_on_fw_events)
4902 hl_device_reset(hdev, HL_RESET_HARD);
4904 hl_fw_unmask_irq(hdev, event_type);
4908 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4914 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4916 struct goya_device *goya = hdev->asic_specific;
4919 *size = (u32) sizeof(goya->events_stat_aggregate);
4920 return goya->events_stat_aggregate;
4923 *size = (u32) sizeof(goya->events_stat);
4924 return goya->events_stat;
4927 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4928 u64 val, bool is_dram)
4930 struct packet_lin_dma *lin_dma_pkt;
4931 struct hl_cs_job *job;
4934 int rc, lin_dma_pkts_cnt;
4936 lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4937 cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4938 sizeof(struct packet_msg_prot);
4939 cb = hl_cb_kernel_create(hdev, cb_size, false);
4943 lin_dma_pkt = cb->kernel_address;
4946 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4948 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4949 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4950 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4951 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4952 (1 << GOYA_PKT_CTL_MB_SHIFT));
4953 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4954 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4955 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4957 lin_dma_pkt->src_addr = cpu_to_le64(val);
4958 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4959 if (lin_dma_pkts_cnt > 1)
4960 lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4962 lin_dma_pkt->tsize = cpu_to_le32(size);
4967 } while (--lin_dma_pkts_cnt);
4969 job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4971 dev_err(hdev->dev, "Failed to allocate a new job\n");
4978 atomic_inc(&job->user_cb->cs_cnt);
4979 job->user_cb_size = cb_size;
4980 job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4981 job->patched_cb = job->user_cb;
4982 job->job_cb_size = job->user_cb_size;
4984 hl_debugfs_add_job(hdev, job);
4986 rc = goya_send_job_on_qman0(hdev, job);
4988 hl_debugfs_remove_job(hdev, job);
4990 atomic_dec(&cb->cs_cnt);
4994 hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4999 int goya_context_switch(struct hl_device *hdev, u32 asid)
5001 struct asic_fixed_properties *prop = &hdev->asic_prop;
5002 u64 addr = prop->sram_base_address, sob_addr;
5003 u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
5004 u64 val = 0x7777777777777777ull;
5006 u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
5007 mmDMA_CH_0_WR_COMP_ADDR_LO;
5009 rc = goya_memset_device_memory(hdev, addr, size, val, false);
5011 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
5015 /* we need to reset registers that the user is allowed to change */
5016 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
5017 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
5019 for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
5020 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
5022 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
5023 lower_32_bits(sob_addr));
5026 WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
5028 goya_clear_sm_regs(hdev);
5033 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
5035 struct asic_fixed_properties *prop = &hdev->asic_prop;
5036 struct goya_device *goya = hdev->asic_specific;
5037 u64 addr = prop->mmu_pgt_addr;
5038 u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
5041 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5044 return goya_memset_device_memory(hdev, addr, size, 0, true);
5047 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
5049 struct goya_device *goya = hdev->asic_specific;
5050 u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
5051 u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
5052 u64 val = 0x9999999999999999ull;
5054 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5057 return goya_memset_device_memory(hdev, addr, size, val, true);
5060 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
5062 struct asic_fixed_properties *prop = &hdev->asic_prop;
5063 struct goya_device *goya = hdev->asic_specific;
5067 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5070 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
5071 rc = hl_mmu_map_page(hdev->kernel_ctx,
5072 prop->dram_base_address + off,
5073 prop->dram_base_address + off, PAGE_SIZE_2MB,
5074 (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
5076 dev_err(hdev->dev, "Map failed for address 0x%llx\n",
5077 prop->dram_base_address + off);
5082 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5083 rc = hl_mmu_map_page(hdev->kernel_ctx,
5084 VA_CPU_ACCESSIBLE_MEM_ADDR,
5085 hdev->cpu_accessible_dma_address,
5086 PAGE_SIZE_2MB, true);
5090 "Map failed for CPU accessible memory\n");
5091 off -= PAGE_SIZE_2MB;
5095 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
5096 rc = hl_mmu_map_page(hdev->kernel_ctx,
5097 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5098 hdev->cpu_accessible_dma_address + cpu_off,
5099 PAGE_SIZE_4KB, true);
5102 "Map failed for CPU accessible memory\n");
5103 cpu_off -= PAGE_SIZE_4KB;
5109 goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
5110 goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
5111 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
5112 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
5114 /* Make sure configuration is flushed to device */
5115 RREG32(mmCPU_IF_AWUSER_OVR_EN);
5117 goya->device_cpu_mmu_mappings_done = true;
5122 for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
5123 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5124 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5125 PAGE_SIZE_4KB, true))
5126 dev_warn_ratelimited(hdev->dev,
5127 "failed to unmap address 0x%llx\n",
5128 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5130 for (; off >= 0 ; off -= PAGE_SIZE_2MB)
5131 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5132 prop->dram_base_address + off, PAGE_SIZE_2MB,
5134 dev_warn_ratelimited(hdev->dev,
5135 "failed to unmap address 0x%llx\n",
5136 prop->dram_base_address + off);
5141 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
5143 struct asic_fixed_properties *prop = &hdev->asic_prop;
5144 struct goya_device *goya = hdev->asic_specific;
5147 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5150 if (!goya->device_cpu_mmu_mappings_done)
5153 WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
5154 WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5156 if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5157 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5158 VA_CPU_ACCESSIBLE_MEM_ADDR,
5159 PAGE_SIZE_2MB, true))
5161 "Failed to unmap CPU accessible memory\n");
5163 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5164 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5165 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5167 (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5168 dev_warn_ratelimited(hdev->dev,
5169 "failed to unmap address 0x%llx\n",
5170 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5173 for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5174 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5175 prop->dram_base_address + off, PAGE_SIZE_2MB,
5176 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5177 dev_warn_ratelimited(hdev->dev,
5178 "Failed to unmap address 0x%llx\n",
5179 prop->dram_base_address + off);
5181 goya->device_cpu_mmu_mappings_done = false;
5184 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5186 struct goya_device *goya = hdev->asic_specific;
5189 if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5192 if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5193 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5197 /* zero the MMBP and ASID bits and then set the ASID */
5198 for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5199 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5202 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5205 struct goya_device *goya = hdev->asic_specific;
5206 u32 status, timeout_usec;
5209 if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5210 hdev->hard_reset_pending)
5213 /* no need in L1 only invalidation in Goya */
5218 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5220 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5222 /* L0 & L1 invalidation */
5223 WREG32(mmSTLB_INV_ALL_START, 1);
5225 rc = hl_poll_timeout(
5227 mmSTLB_INV_ALL_START,
5234 dev_err_ratelimited(hdev->dev,
5235 "MMU cache invalidation timeout\n");
5236 hl_device_reset(hdev, HL_RESET_HARD);
5242 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5243 bool is_hard, u32 flags,
5244 u32 asid, u64 va, u64 size)
5246 /* Treat as invalidate all because there is no range invalidation
5249 return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
5252 int goya_send_heartbeat(struct hl_device *hdev)
5254 struct goya_device *goya = hdev->asic_specific;
5256 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5259 return hl_fw_send_heartbeat(hdev);
5262 int goya_cpucp_info_get(struct hl_device *hdev)
5264 struct goya_device *goya = hdev->asic_specific;
5265 struct asic_fixed_properties *prop = &hdev->asic_prop;
5269 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5272 rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5273 mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5278 dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5280 if ((!is_power_of_2(dram_size)) ||
5281 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5283 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5285 dram_size = DRAM_PHYS_DEFAULT_SIZE;
5288 prop->dram_size = dram_size;
5289 prop->dram_end_address = prop->dram_base_address + dram_size;
5292 if (!strlen(prop->cpucp_info.card_name))
5293 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5299 static void goya_set_clock_gating(struct hl_device *hdev)
5301 /* clock gating not supported in Goya */
5304 static void goya_disable_clock_gating(struct hl_device *hdev)
5306 /* clock gating not supported in Goya */
5309 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
5310 u8 mask_len, struct seq_file *s)
5312 const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5313 const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5314 unsigned long *mask = (unsigned long *)mask_arr;
5315 u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5317 bool is_idle = true, is_eng_idle;
5322 seq_puts(s, "\nDMA is_idle QM_GLBL_STS0 DMA_CORE_STS0\n"
5323 "--- ------- ------------ -------------\n");
5325 offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5327 for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5328 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5329 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5330 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5331 IS_DMA_IDLE(dma_core_sts0);
5332 is_idle &= is_eng_idle;
5334 if (mask && !is_eng_idle)
5335 set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5337 seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
5338 qm_glbl_sts0, dma_core_sts0);
5343 "\nTPC is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 CFG_STATUS\n"
5344 "--- ------- ------------ -------------- ----------\n");
5346 offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5348 for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5349 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5350 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5351 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5352 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5353 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5354 IS_TPC_IDLE(tpc_cfg_sts);
5355 is_idle &= is_eng_idle;
5357 if (mask && !is_eng_idle)
5358 set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5360 seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
5361 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5366 "\nMME is_idle QM_GLBL_STS0 CMDQ_GLBL_STS0 ARCH_STATUS\n"
5367 "--- ------- ------------ -------------- -----------\n");
5369 qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5370 cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5371 mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5372 is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5373 IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5374 IS_MME_IDLE(mme_arch_sts);
5375 is_idle &= is_eng_idle;
5377 if (mask && !is_eng_idle)
5378 set_bit(GOYA_ENGINE_ID_MME_0, mask);
5380 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5381 cmdq_glbl_sts0, mme_arch_sts);
5388 static void goya_hw_queues_lock(struct hl_device *hdev)
5389 __acquires(&goya->hw_queues_lock)
5391 struct goya_device *goya = hdev->asic_specific;
5393 spin_lock(&goya->hw_queues_lock);
5396 static void goya_hw_queues_unlock(struct hl_device *hdev)
5397 __releases(&goya->hw_queues_lock)
5399 struct goya_device *goya = hdev->asic_specific;
5401 spin_unlock(&goya->hw_queues_lock);
5404 static u32 goya_get_pci_id(struct hl_device *hdev)
5406 return hdev->pdev->device;
5409 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5412 struct goya_device *goya = hdev->asic_specific;
5414 if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5417 return hl_fw_get_eeprom_data(hdev, data, max_size);
5420 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5425 static int goya_ctx_init(struct hl_ctx *ctx)
5427 if (ctx->asid != HL_KERNEL_ASID_ID)
5428 goya_mmu_prepare(ctx->hdev, ctx->asid);
5433 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5438 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5443 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5448 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5454 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5455 struct hl_gen_wait_properties *prop)
5460 static void goya_reset_sob(struct hl_device *hdev, void *data)
5465 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5470 static void goya_set_dma_mask_from_fw(struct hl_device *hdev)
5472 if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
5473 HL_POWER9_HOST_MAGIC) {
5474 dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n");
5475 hdev->power9_64bit_dma_enable = 1;
5476 hdev->dma_mask = 64;
5478 dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n");
5479 hdev->power9_64bit_dma_enable = 0;
5480 hdev->dma_mask = 48;
5484 u64 goya_get_device_time(struct hl_device *hdev)
5486 u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5488 return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5491 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5496 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5497 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5498 u32 collective_engine_id, u32 encaps_signal_offset)
5503 static void goya_ctx_fini(struct hl_ctx *ctx)
5508 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5509 u32 *block_size, u32 *block_id)
5514 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5515 u32 block_id, u32 block_size)
5520 static void goya_enable_events_from_fw(struct hl_device *hdev)
5522 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5523 GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5526 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5529 case HL_GOYA_CPU_PLL: return CPU_PLL;
5530 case HL_GOYA_PCI_PLL: return PCI_PLL;
5531 case HL_GOYA_MME_PLL: return MME_PLL;
5532 case HL_GOYA_TPC_PLL: return TPC_PLL;
5533 case HL_GOYA_IC_PLL: return IC_PLL;
5534 case HL_GOYA_MC_PLL: return MC_PLL;
5535 case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5536 default: return -EINVAL;
5540 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5541 struct hl_sync_to_engine_map *map)
5543 /* Not implemented */
5547 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5549 /* Not implemented */
5553 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5554 struct hl_device *hdev,
5555 struct hl_mon_state_dump *mon)
5557 /* Not implemented */
5562 static int goya_print_fences_single_engine(
5563 struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5564 enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5565 size_t *size, size_t *offset)
5567 /* Not implemented */
5572 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5573 .monitor_valid = goya_monitor_valid,
5574 .print_single_monitor = goya_print_single_monitor,
5575 .gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5576 .print_fences_single_engine = goya_print_fences_single_engine,
5579 static void goya_state_dump_init(struct hl_device *hdev)
5581 /* Not implemented */
5582 hdev->state_dump_specs.props = goya_state_dump_specs_props;
5583 hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5586 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5591 static u32 *goya_get_stream_master_qid_arr(void)
5596 static const struct hl_asic_funcs goya_funcs = {
5597 .early_init = goya_early_init,
5598 .early_fini = goya_early_fini,
5599 .late_init = goya_late_init,
5600 .late_fini = goya_late_fini,
5601 .sw_init = goya_sw_init,
5602 .sw_fini = goya_sw_fini,
5603 .hw_init = goya_hw_init,
5604 .hw_fini = goya_hw_fini,
5605 .halt_engines = goya_halt_engines,
5606 .suspend = goya_suspend,
5607 .resume = goya_resume,
5609 .ring_doorbell = goya_ring_doorbell,
5610 .pqe_write = goya_pqe_write,
5611 .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5612 .asic_dma_free_coherent = goya_dma_free_coherent,
5613 .scrub_device_mem = goya_scrub_device_mem,
5614 .get_int_queue_base = goya_get_int_queue_base,
5615 .test_queues = goya_test_queues,
5616 .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5617 .asic_dma_pool_free = goya_dma_pool_free,
5618 .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5619 .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5620 .hl_dma_unmap_sg = goya_dma_unmap_sg,
5621 .cs_parser = goya_cs_parser,
5622 .asic_dma_map_sg = goya_dma_map_sg,
5623 .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5624 .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5625 .update_eq_ci = goya_update_eq_ci,
5626 .context_switch = goya_context_switch,
5627 .restore_phase_topology = goya_restore_phase_topology,
5628 .debugfs_read32 = goya_debugfs_read32,
5629 .debugfs_write32 = goya_debugfs_write32,
5630 .debugfs_read64 = goya_debugfs_read64,
5631 .debugfs_write64 = goya_debugfs_write64,
5632 .debugfs_read_dma = goya_debugfs_read_dma,
5633 .add_device_attr = goya_add_device_attr,
5634 .handle_eqe = goya_handle_eqe,
5635 .set_pll_profile = goya_set_pll_profile,
5636 .get_events_stat = goya_get_events_stat,
5637 .read_pte = goya_read_pte,
5638 .write_pte = goya_write_pte,
5639 .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5640 .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5641 .send_heartbeat = goya_send_heartbeat,
5642 .set_clock_gating = goya_set_clock_gating,
5643 .disable_clock_gating = goya_disable_clock_gating,
5644 .debug_coresight = goya_debug_coresight,
5645 .is_device_idle = goya_is_device_idle,
5646 .soft_reset_late_init = goya_soft_reset_late_init,
5647 .hw_queues_lock = goya_hw_queues_lock,
5648 .hw_queues_unlock = goya_hw_queues_unlock,
5649 .get_pci_id = goya_get_pci_id,
5650 .get_eeprom_data = goya_get_eeprom_data,
5651 .send_cpu_message = goya_send_cpu_message,
5652 .pci_bars_map = goya_pci_bars_map,
5653 .init_iatu = goya_init_iatu,
5656 .halt_coresight = goya_halt_coresight,
5657 .ctx_init = goya_ctx_init,
5658 .ctx_fini = goya_ctx_fini,
5659 .get_clk_rate = goya_get_clk_rate,
5660 .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5661 .load_firmware_to_device = goya_load_firmware_to_device,
5662 .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5663 .get_signal_cb_size = goya_get_signal_cb_size,
5664 .get_wait_cb_size = goya_get_wait_cb_size,
5665 .gen_signal_cb = goya_gen_signal_cb,
5666 .gen_wait_cb = goya_gen_wait_cb,
5667 .reset_sob = goya_reset_sob,
5668 .reset_sob_group = goya_reset_sob_group,
5669 .set_dma_mask_from_fw = goya_set_dma_mask_from_fw,
5670 .get_device_time = goya_get_device_time,
5671 .collective_wait_init_cs = goya_collective_wait_init_cs,
5672 .collective_wait_create_jobs = goya_collective_wait_create_jobs,
5673 .scramble_addr = hl_mmu_scramble_addr,
5674 .descramble_addr = hl_mmu_descramble_addr,
5675 .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5676 .get_hw_block_id = goya_get_hw_block_id,
5677 .hw_block_mmap = goya_block_mmap,
5678 .enable_events_from_fw = goya_enable_events_from_fw,
5679 .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5680 .init_firmware_loader = goya_init_firmware_loader,
5681 .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5682 .state_dump_init = goya_state_dump_init,
5683 .get_sob_addr = &goya_get_sob_addr,
5684 .set_pci_memory_regions = goya_set_pci_memory_regions,
5685 .get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5689 * goya_set_asic_funcs - set Goya function pointers
5691 * @*hdev: pointer to hl_device structure
5694 void goya_set_asic_funcs(struct hl_device *hdev)
5696 hdev->asic_funcs = &goya_funcs;