drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "../include/hw_ip/mmu/mmu_general.h"
  10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "../include/goya/asic_reg/goya_masks.h"
  12 #include "../include/goya/goya_reg_map.h"
  13
  14 #include <linux/pci.h>
  15 #include <linux/hwmon.h>
  16 #include <linux/iommu.h>
  17 #include <linux/seq_file.h>
  18
  19 /*
  20  * GOYA security scheme:
  21  *
  22  * 1. Host is protected by:
  23  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  24  *        - MMU
  25  *
  26  * 2. DRAM is protected by:
  27  *        - Range registers (protect the first 512MB)
  28  *        - MMU (isolation between users)
  29  *
  30  * 3. Configuration is protected by:
  31  *        - Range registers
  32  *        - Protection bits
  33  *
  34  * When MMU is disabled:
  35  *
  36  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  37  * PQ, CB and the data are on the host.
  38  *
  39  * QMAN TPC/MME:
  40  * PQ, CQ and CP are not secured.
  41  * PQ, CB and the data are on the SRAM/DRAM.
  42  *
  43  * Since QMAN DMA is secured, the driver is parsing the DMA CB:
  44  *     - checks DMA pointer
  45  *     - WREG, MSG_PROT are not allowed.
  46  *     - MSG_LONG/SHORT are allowed.
  47  *
  48  * A read/write transaction by the QMAN to a protected area will succeed if
  49  * and only if the QMAN's CP is secured and MSG_PROT is used
  50  *
  51  *
  52  * When MMU is enabled:
  53  *
  54  * QMAN DMA: PQ, CQ and CP are secured.
  55  * MMU is set to bypass on the Secure props register of the QMAN.
  56  * The reasons we don't enable MMU for PQ, CQ and CP are:
  57  *     - PQ entry is in kernel address space and the driver doesn't map it.
  58  *     - CP writes to MSIX register and to kernel address space (completion
  59  *       queue).
  60  *
  61  * DMA is not secured but because CP is secured, the driver still needs to parse
  62  * the CB, but doesn't need to check the DMA addresses.
  63  *
  64  * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
  65  * the driver doesn't map memory in MMU.
  66  *
  67  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  68  *
  69  * DMA RR does NOT protect host because DMA is not secured
  70  *
  71  */
  72
  73 #define GOYA_BOOT_FIT_FILE      "habanalabs/goya/goya-boot-fit.itb"
  74 #define GOYA_LINUX_FW_FILE      "habanalabs/goya/goya-fit.itb"
  75
  76 #define GOYA_MMU_REGS_NUM               63
  77
  78 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  79
  80 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  82 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  83 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  84 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  85 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  86 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC  1000000         /* 1s */
  89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC    4000000         /* 4s */
  90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC   15000000        /* 15s */
  91
  92 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  93
  94 #define GOYA_MAX_STRING_LEN             20
  95
  96 #define GOYA_CB_POOL_CB_CNT             512
  97 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  98
  99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
 100         (((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
 101 #define IS_DMA_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(DMA, qm_glbl_sts0)
 102 #define IS_TPC_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(TPC, qm_glbl_sts0)
 103 #define IS_MME_QM_IDLE(qm_glbl_sts0)    IS_QM_IDLE(MME, qm_glbl_sts0)
 104
 105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
 106         (((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
 107                         engine##_CMDQ_IDLE_MASK)
 108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
 109         IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
 110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
 111         IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
 112
 113 #define IS_DMA_IDLE(dma_core_sts0) \
 114         !((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
 115
 116 #define IS_TPC_IDLE(tpc_cfg_sts) \
 117         (((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
 118
 119 #define IS_MME_IDLE(mme_arch_sts) \
 120         (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
 121
 122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
 123                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
 124                 "goya cq 4", "goya cpu eq"
 125 };
 126
 127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
 128         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
 129         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 130         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 131         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 132         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 133         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 134         [PACKET_FENCE]          = sizeof(struct packet_fence),
 135         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 136         [PACKET_NOP]            = sizeof(struct packet_nop),
 137         [PACKET_STOP]           = sizeof(struct packet_stop)
 138 };
 139
 140 static inline bool validate_packet_id(enum packet_id id)
 141 {
 142         switch (id) {
 143         case PACKET_WREG_32:
 144         case PACKET_WREG_BULK:
 145         case PACKET_MSG_LONG:
 146         case PACKET_MSG_SHORT:
 147         case PACKET_CP_DMA:
 148         case PACKET_MSG_PROT:
 149         case PACKET_FENCE:
 150         case PACKET_LIN_DMA:
 151         case PACKET_NOP:
 152         case PACKET_STOP:
 153                 return true;
 154         default:
 155                 return false;
 156         }
 157 }
 158
 159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 160         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 161         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 162         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 163         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 164         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 165         mmTPC0_QM_GLBL_SECURE_PROPS,
 166         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 167         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 168         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 169         mmTPC0_CFG_ARUSER,
 170         mmTPC0_CFG_AWUSER,
 171         mmTPC1_QM_GLBL_SECURE_PROPS,
 172         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 173         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 174         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 175         mmTPC1_CFG_ARUSER,
 176         mmTPC1_CFG_AWUSER,
 177         mmTPC2_QM_GLBL_SECURE_PROPS,
 178         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 179         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 180         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 181         mmTPC2_CFG_ARUSER,
 182         mmTPC2_CFG_AWUSER,
 183         mmTPC3_QM_GLBL_SECURE_PROPS,
 184         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 185         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 186         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 187         mmTPC3_CFG_ARUSER,
 188         mmTPC3_CFG_AWUSER,
 189         mmTPC4_QM_GLBL_SECURE_PROPS,
 190         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 191         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 192         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 193         mmTPC4_CFG_ARUSER,
 194         mmTPC4_CFG_AWUSER,
 195         mmTPC5_QM_GLBL_SECURE_PROPS,
 196         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 197         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 198         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 199         mmTPC5_CFG_ARUSER,
 200         mmTPC5_CFG_AWUSER,
 201         mmTPC6_QM_GLBL_SECURE_PROPS,
 202         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 203         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 204         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 205         mmTPC6_CFG_ARUSER,
 206         mmTPC6_CFG_AWUSER,
 207         mmTPC7_QM_GLBL_SECURE_PROPS,
 208         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 209         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 210         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 211         mmTPC7_CFG_ARUSER,
 212         mmTPC7_CFG_AWUSER,
 213         mmMME_QM_GLBL_SECURE_PROPS,
 214         mmMME_QM_GLBL_NON_SECURE_PROPS,
 215         mmMME_CMDQ_GLBL_SECURE_PROPS,
 216         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 217         mmMME_SBA_CONTROL_DATA,
 218         mmMME_SBB_CONTROL_DATA,
 219         mmMME_SBC_CONTROL_DATA,
 220         mmMME_WBC_CONTROL_DATA,
 221         mmPCIE_WRAP_PSOC_ARUSER,
 222         mmPCIE_WRAP_PSOC_AWUSER
 223 };
 224
 225 static u32 goya_all_events[] = {
 226         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 227         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 228         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 229         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 230         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 231         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 232         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 233         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 234         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 235         GOYA_ASYNC_EVENT_ID_MME_ECC,
 236         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 237         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 238         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 239         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 240         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 241         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 242         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 243         GOYA_ASYNC_EVENT_ID_SRAM0,
 244         GOYA_ASYNC_EVENT_ID_SRAM1,
 245         GOYA_ASYNC_EVENT_ID_SRAM2,
 246         GOYA_ASYNC_EVENT_ID_SRAM3,
 247         GOYA_ASYNC_EVENT_ID_SRAM4,
 248         GOYA_ASYNC_EVENT_ID_SRAM5,
 249         GOYA_ASYNC_EVENT_ID_SRAM6,
 250         GOYA_ASYNC_EVENT_ID_SRAM7,
 251         GOYA_ASYNC_EVENT_ID_SRAM8,
 252         GOYA_ASYNC_EVENT_ID_SRAM9,
 253         GOYA_ASYNC_EVENT_ID_SRAM10,
 254         GOYA_ASYNC_EVENT_ID_SRAM11,
 255         GOYA_ASYNC_EVENT_ID_SRAM12,
 256         GOYA_ASYNC_EVENT_ID_SRAM13,
 257         GOYA_ASYNC_EVENT_ID_SRAM14,
 258         GOYA_ASYNC_EVENT_ID_SRAM15,
 259         GOYA_ASYNC_EVENT_ID_SRAM16,
 260         GOYA_ASYNC_EVENT_ID_SRAM17,
 261         GOYA_ASYNC_EVENT_ID_SRAM18,
 262         GOYA_ASYNC_EVENT_ID_SRAM19,
 263         GOYA_ASYNC_EVENT_ID_SRAM20,
 264         GOYA_ASYNC_EVENT_ID_SRAM21,
 265         GOYA_ASYNC_EVENT_ID_SRAM22,
 266         GOYA_ASYNC_EVENT_ID_SRAM23,
 267         GOYA_ASYNC_EVENT_ID_SRAM24,
 268         GOYA_ASYNC_EVENT_ID_SRAM25,
 269         GOYA_ASYNC_EVENT_ID_SRAM26,
 270         GOYA_ASYNC_EVENT_ID_SRAM27,
 271         GOYA_ASYNC_EVENT_ID_SRAM28,
 272         GOYA_ASYNC_EVENT_ID_SRAM29,
 273         GOYA_ASYNC_EVENT_ID_GIC500,
 274         GOYA_ASYNC_EVENT_ID_PLL0,
 275         GOYA_ASYNC_EVENT_ID_PLL1,
 276         GOYA_ASYNC_EVENT_ID_PLL3,
 277         GOYA_ASYNC_EVENT_ID_PLL4,
 278         GOYA_ASYNC_EVENT_ID_PLL5,
 279         GOYA_ASYNC_EVENT_ID_PLL6,
 280         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 281         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 282         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 283         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 284         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 285         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 286         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 287         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 288         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 289         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 290         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 291         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 292         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 293         GOYA_ASYNC_EVENT_ID_MME_WACS,
 294         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 295         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 296         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 297         GOYA_ASYNC_EVENT_ID_PSOC,
 298         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 299         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 300         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 301         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 302         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 303         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 304         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 305         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 306         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 307         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 308         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 309         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 310         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 311         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 312         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 313         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 314         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 315         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 316         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 317         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 318         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 319         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 320         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 321         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 322         GOYA_ASYNC_EVENT_ID_MME_QM,
 323         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 324         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 325         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 326         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 327         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 328         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 329         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 330         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 331         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 332         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 333         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 334         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 335         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 336         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 337         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 338         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 339         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 340         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 341         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 342         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 343         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 344         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 345         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 346         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
 347         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
 348         GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
 349         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
 350         GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
 351 };
 352
 353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
 354
 355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
 356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
 357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
 358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
 359
 360 int goya_set_fixed_properties(struct hl_device *hdev)
 361 {
 362         struct asic_fixed_properties *prop = &hdev->asic_prop;
 363         int i;
 364
 365         prop->max_queues = GOYA_QUEUE_ID_SIZE;
 366         prop->hw_queues_props = kcalloc(prop->max_queues,
 367                         sizeof(struct hw_queue_properties),
 368                         GFP_KERNEL);
 369
 370         if (!prop->hw_queues_props)
 371                 return -ENOMEM;
 372
 373         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 374                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 375                 prop->hw_queues_props[i].driver_only = 0;
 376                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 377         }
 378
 379         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 380                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 381                 prop->hw_queues_props[i].driver_only = 1;
 382                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
 383         }
 384
 385         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 386                         NUMBER_OF_INT_HW_QUEUES; i++) {
 387                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 388                 prop->hw_queues_props[i].driver_only = 0;
 389                 prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
 390         }
 391
 392         prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
 393         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 394
 395         prop->dram_base_address = DRAM_PHYS_BASE;
 396         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 397         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 398         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 399
 400         prop->sram_base_address = SRAM_BASE_ADDR;
 401         prop->sram_size = SRAM_SIZE;
 402         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 403         prop->sram_user_base_address = prop->sram_base_address +
 404                                                 SRAM_USER_BASE_OFFSET;
 405
 406         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 407         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 408         if (hdev->pldm)
 409                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 410         else
 411                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 412         prop->mmu_pte_size = HL_PTE_SIZE;
 413         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 414         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 415         prop->dram_page_size = PAGE_SIZE_2MB;
 416         prop->dram_supports_virtual_memory = true;
 417
 418         prop->dmmu.hop0_shift = HOP0_SHIFT;
 419         prop->dmmu.hop1_shift = HOP1_SHIFT;
 420         prop->dmmu.hop2_shift = HOP2_SHIFT;
 421         prop->dmmu.hop3_shift = HOP3_SHIFT;
 422         prop->dmmu.hop4_shift = HOP4_SHIFT;
 423         prop->dmmu.hop0_mask = HOP0_MASK;
 424         prop->dmmu.hop1_mask = HOP1_MASK;
 425         prop->dmmu.hop2_mask = HOP2_MASK;
 426         prop->dmmu.hop3_mask = HOP3_MASK;
 427         prop->dmmu.hop4_mask = HOP4_MASK;
 428         prop->dmmu.start_addr = VA_DDR_SPACE_START;
 429         prop->dmmu.end_addr = VA_DDR_SPACE_END;
 430         prop->dmmu.page_size = PAGE_SIZE_2MB;
 431         prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
 432
 433         /* shifts and masks are the same in PMMU and DMMU */
 434         memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
 435         prop->pmmu.start_addr = VA_HOST_SPACE_START;
 436         prop->pmmu.end_addr = VA_HOST_SPACE_END;
 437         prop->pmmu.page_size = PAGE_SIZE_4KB;
 438         prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
 439
 440         /* PMMU and HPMMU are the same except of page size */
 441         memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
 442         prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
 443
 444         prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
 445         prop->cfg_size = CFG_SIZE;
 446         prop->max_asid = MAX_ASID;
 447         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 448         prop->high_pll = PLL_HIGH_DEFAULT;
 449         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 450         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 451         prop->max_power_default = MAX_POWER_DEFAULT;
 452         prop->dc_power_default = DC_POWER_DEFAULT;
 453         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 454         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 455         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 456
 457         strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
 458                 CARD_NAME_MAX_LEN);
 459
 460         prop->max_pending_cs = GOYA_MAX_PENDING_CS;
 461
 462         prop->first_available_user_msix_interrupt = USHRT_MAX;
 463
 464         for (i = 0 ; i < HL_MAX_DCORES ; i++)
 465                 prop->first_available_cq[i] = USHRT_MAX;
 466
 467         prop->fw_cpu_boot_dev_sts0_valid = false;
 468         prop->fw_cpu_boot_dev_sts1_valid = false;
 469         prop->hard_reset_done_by_fw = false;
 470         prop->gic_interrupts_enable = true;
 471
 472         prop->server_type = HL_SERVER_TYPE_UNKNOWN;
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * goya_pci_bars_map - Map PCI BARS of Goya device
 479  *
 480  * @hdev: pointer to hl_device structure
 481  *
 482  * Request PCI regions and map them to kernel virtual addresses.
 483  * Returns 0 on success
 484  *
 485  */
 486 static int goya_pci_bars_map(struct hl_device *hdev)
 487 {
 488         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 489         bool is_wc[3] = {false, false, true};
 490         int rc;
 491
 492         rc = hl_pci_bars_map(hdev, name, is_wc);
 493         if (rc)
 494                 return rc;
 495
 496         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 497                         (CFG_BASE - SRAM_BASE_ADDR);
 498
 499         return 0;
 500 }
 501
 502 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 503 {
 504         struct goya_device *goya = hdev->asic_specific;
 505         struct hl_inbound_pci_region pci_region;
 506         u64 old_addr = addr;
 507         int rc;
 508
 509         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 510                 return old_addr;
 511
 512         /* Inbound Region 1 - Bar 4 - Point to DDR */
 513         pci_region.mode = PCI_BAR_MATCH_MODE;
 514         pci_region.bar = DDR_BAR_ID;
 515         pci_region.addr = addr;
 516         rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
 517         if (rc)
 518                 return U64_MAX;
 519
 520         if (goya) {
 521                 old_addr = goya->ddr_bar_cur_addr;
 522                 goya->ddr_bar_cur_addr = addr;
 523         }
 524
 525         return old_addr;
 526 }
 527
 528 /*
 529  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 530  *
 531  * @hdev: pointer to hl_device structure
 532  *
 533  * This is needed in case the firmware doesn't initialize the iATU
 534  *
 535  */
 536 static int goya_init_iatu(struct hl_device *hdev)
 537 {
 538         struct hl_inbound_pci_region inbound_region;
 539         struct hl_outbound_pci_region outbound_region;
 540         int rc;
 541
 542         if (hdev->asic_prop.iatu_done_by_fw)
 543                 return 0;
 544
 545         /* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
 546         inbound_region.mode = PCI_BAR_MATCH_MODE;
 547         inbound_region.bar = SRAM_CFG_BAR_ID;
 548         inbound_region.addr = SRAM_BASE_ADDR;
 549         rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
 550         if (rc)
 551                 goto done;
 552
 553         /* Inbound Region 1 - Bar 4 - Point to DDR */
 554         inbound_region.mode = PCI_BAR_MATCH_MODE;
 555         inbound_region.bar = DDR_BAR_ID;
 556         inbound_region.addr = DRAM_PHYS_BASE;
 557         rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
 558         if (rc)
 559                 goto done;
 560
 561         hdev->asic_funcs->set_dma_mask_from_fw(hdev);
 562
 563         /* Outbound Region 0 - Point to Host  */
 564         outbound_region.addr = HOST_PHYS_BASE;
 565         outbound_region.size = HOST_PHYS_SIZE;
 566         rc = hl_pci_set_outbound_region(hdev, &outbound_region);
 567
 568 done:
 569         return rc;
 570 }
 571
 572 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
 573 {
 574         return RREG32(mmHW_STATE);
 575 }
 576
 577 /*
 578  * goya_early_init - GOYA early initialization code
 579  *
 580  * @hdev: pointer to hl_device structure
 581  *
 582  * Verify PCI bars
 583  * Set DMA masks
 584  * PCI controller initialization
 585  * Map PCI bars
 586  *
 587  */
 588 static int goya_early_init(struct hl_device *hdev)
 589 {
 590         struct asic_fixed_properties *prop = &hdev->asic_prop;
 591         struct pci_dev *pdev = hdev->pdev;
 592         u32 fw_boot_status, val;
 593         int rc;
 594
 595         rc = goya_set_fixed_properties(hdev);
 596         if (rc) {
 597                 dev_err(hdev->dev, "Failed to get fixed properties\n");
 598                 return rc;
 599         }
 600
 601         /* Check BAR sizes */
 602         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 603                 dev_err(hdev->dev,
 604                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 605                         SRAM_CFG_BAR_ID,
 606                         (unsigned long long) pci_resource_len(pdev,
 607                                                         SRAM_CFG_BAR_ID),
 608                         CFG_BAR_SIZE);
 609                 rc = -ENODEV;
 610                 goto free_queue_props;
 611         }
 612
 613         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 614                 dev_err(hdev->dev,
 615                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 616                         MSIX_BAR_ID,
 617                         (unsigned long long) pci_resource_len(pdev,
 618                                                                 MSIX_BAR_ID),
 619                         MSIX_BAR_SIZE);
 620                 rc = -ENODEV;
 621                 goto free_queue_props;
 622         }
 623
 624         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 625
 626         /* If FW security is enabled at this point it means no access to ELBI */
 627         if (hdev->asic_prop.fw_security_enabled) {
 628                 hdev->asic_prop.iatu_done_by_fw = true;
 629                 goto pci_init;
 630         }
 631
 632         rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
 633                                 &fw_boot_status);
 634         if (rc)
 635                 goto free_queue_props;
 636
 637         /* Check whether FW is configuring iATU */
 638         if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
 639                         (fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
 640                 hdev->asic_prop.iatu_done_by_fw = true;
 641
 642 pci_init:
 643         rc = hl_pci_init(hdev);
 644         if (rc)
 645                 goto free_queue_props;
 646
 647         /* Before continuing in the initialization, we need to read the preboot
 648          * version to determine whether we run with a security-enabled firmware
 649          */
 650         rc = hl_fw_read_preboot_status(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS,
 651                                         mmCPU_BOOT_DEV_STS0,
 652                                         mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
 653                                         mmCPU_BOOT_ERR1,
 654                                         GOYA_BOOT_FIT_REQ_TIMEOUT_USEC);
 655         if (rc) {
 656                 if (hdev->reset_on_preboot_fail)
 657                         hdev->asic_funcs->hw_fini(hdev, true, false);
 658                 goto pci_fini;
 659         }
 660
 661         if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
 662                 dev_info(hdev->dev,
 663                         "H/W state is dirty, must reset before initializing\n");
 664                 hdev->asic_funcs->hw_fini(hdev, true, false);
 665         }
 666
 667         if (!hdev->pldm) {
 668                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 669                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 670                         dev_warn(hdev->dev,
 671                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 672         }
 673
 674         return 0;
 675
 676 pci_fini:
 677         hl_pci_fini(hdev);
 678 free_queue_props:
 679         kfree(hdev->asic_prop.hw_queues_props);
 680         return rc;
 681 }
 682
 683 /*
 684  * goya_early_fini - GOYA early finalization code
 685  *
 686  * @hdev: pointer to hl_device structure
 687  *
 688  * Unmap PCI bars
 689  *
 690  */
 691 static int goya_early_fini(struct hl_device *hdev)
 692 {
 693         kfree(hdev->asic_prop.hw_queues_props);
 694         hl_pci_fini(hdev);
 695
 696         return 0;
 697 }
 698
 699 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 700 {
 701         /* mask to zero the MMBP and ASID bits */
 702         WREG32_AND(reg, ~0x7FF);
 703         WREG32_OR(reg, asid);
 704 }
 705
 706 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 707 {
 708         struct goya_device *goya = hdev->asic_specific;
 709
 710         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 711                 return;
 712
 713         if (secure)
 714                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 715         else
 716                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 717
 718         RREG32(mmDMA_QM_0_GLBL_PROT);
 719 }
 720
 721 /*
 722  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 723  *
 724  * @hdev: pointer to hl_device structure
 725  *
 726  */
 727 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 728 {
 729         struct asic_fixed_properties *prop = &hdev->asic_prop;
 730         u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
 731         u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
 732         int rc;
 733
 734         if (hdev->asic_prop.fw_security_enabled) {
 735                 rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
 736                                 pll_freq_arr);
 737
 738                 if (rc)
 739                         return;
 740
 741                 freq = pll_freq_arr[1];
 742         } else {
 743                 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 744                 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
 745                 nr = RREG32(mmPSOC_PCI_PLL_NR);
 746                 nf = RREG32(mmPSOC_PCI_PLL_NF);
 747                 od = RREG32(mmPSOC_PCI_PLL_OD);
 748
 749                 if (div_sel == DIV_SEL_REF_CLK ||
 750                                 div_sel == DIV_SEL_DIVIDED_REF) {
 751                         if (div_sel == DIV_SEL_REF_CLK)
 752                                 freq = PLL_REF_CLK;
 753                         else
 754                                 freq = PLL_REF_CLK / (div_fctr + 1);
 755                 } else if (div_sel == DIV_SEL_PLL_CLK ||
 756                                 div_sel == DIV_SEL_DIVIDED_PLL) {
 757                         pll_clk = PLL_REF_CLK * (nf + 1) /
 758                                         ((nr + 1) * (od + 1));
 759                         if (div_sel == DIV_SEL_PLL_CLK)
 760                                 freq = pll_clk;
 761                         else
 762                                 freq = pll_clk / (div_fctr + 1);
 763                 } else {
 764                         dev_warn(hdev->dev,
 765                                 "Received invalid div select value: %d",
 766                                 div_sel);
 767                         freq = 0;
 768                 }
 769         }
 770
 771         prop->psoc_timestamp_frequency = freq;
 772         prop->psoc_pci_pll_nr = nr;
 773         prop->psoc_pci_pll_nf = nf;
 774         prop->psoc_pci_pll_od = od;
 775         prop->psoc_pci_pll_div_factor = div_fctr;
 776 }
 777
 778 int goya_late_init(struct hl_device *hdev)
 779 {
 780         struct asic_fixed_properties *prop = &hdev->asic_prop;
 781         int rc;
 782
 783         goya_fetch_psoc_frequency(hdev);
 784
 785         rc = goya_mmu_clear_pgt_range(hdev);
 786         if (rc) {
 787                 dev_err(hdev->dev,
 788                         "Failed to clear MMU page tables range %d\n", rc);
 789                 return rc;
 790         }
 791
 792         rc = goya_mmu_set_dram_default_page(hdev);
 793         if (rc) {
 794                 dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
 795                 return rc;
 796         }
 797
 798         rc = goya_mmu_add_mappings_for_device_cpu(hdev);
 799         if (rc)
 800                 return rc;
 801
 802         rc = goya_init_cpu_queues(hdev);
 803         if (rc)
 804                 return rc;
 805
 806         rc = goya_test_cpu_queue(hdev);
 807         if (rc)
 808                 return rc;
 809
 810         rc = goya_cpucp_info_get(hdev);
 811         if (rc) {
 812                 dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
 813                 return rc;
 814         }
 815
 816         /* Now that we have the DRAM size in ASIC prop, we need to check
 817          * its size and configure the DMA_IF DDR wrap protection (which is in
 818          * the MMU block) accordingly. The value is the log2 of the DRAM size
 819          */
 820         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 821
 822         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS);
 823         if (rc) {
 824                 dev_err(hdev->dev,
 825                         "Failed to enable PCI access from CPU %d\n", rc);
 826                 return rc;
 827         }
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * goya_late_fini - GOYA late tear-down code
 834  *
 835  * @hdev: pointer to hl_device structure
 836  *
 837  * Free sensors allocated structures
 838  */
 839 void goya_late_fini(struct hl_device *hdev)
 840 {
 841         const struct hwmon_channel_info **channel_info_arr;
 842         int i = 0;
 843
 844         if (!hdev->hl_chip_info->info)
 845                 return;
 846
 847         channel_info_arr = hdev->hl_chip_info->info;
 848
 849         while (channel_info_arr[i]) {
 850                 kfree(channel_info_arr[i]->config);
 851                 kfree(channel_info_arr[i]);
 852                 i++;
 853         }
 854
 855         kfree(channel_info_arr);
 856
 857         hdev->hl_chip_info->info = NULL;
 858 }
 859
 860 static void goya_set_pci_memory_regions(struct hl_device *hdev)
 861 {
 862         struct asic_fixed_properties *prop = &hdev->asic_prop;
 863         struct pci_mem_region *region;
 864
 865         /* CFG */
 866         region = &hdev->pci_mem_region[PCI_REGION_CFG];
 867         region->region_base = CFG_BASE;
 868         region->region_size = CFG_SIZE;
 869         region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
 870         region->bar_size = CFG_BAR_SIZE;
 871         region->bar_id = SRAM_CFG_BAR_ID;
 872         region->used = 1;
 873
 874         /* SRAM */
 875         region = &hdev->pci_mem_region[PCI_REGION_SRAM];
 876         region->region_base = SRAM_BASE_ADDR;
 877         region->region_size = SRAM_SIZE;
 878         region->offset_in_bar = 0;
 879         region->bar_size = CFG_BAR_SIZE;
 880         region->bar_id = SRAM_CFG_BAR_ID;
 881         region->used = 1;
 882
 883         /* DRAM */
 884         region = &hdev->pci_mem_region[PCI_REGION_DRAM];
 885         region->region_base = DRAM_PHYS_BASE;
 886         region->region_size = hdev->asic_prop.dram_size;
 887         region->offset_in_bar = 0;
 888         region->bar_size = prop->dram_pci_bar_size;
 889         region->bar_id = DDR_BAR_ID;
 890         region->used = 1;
 891 }
 892
 893 /*
 894  * goya_sw_init - Goya software initialization code
 895  *
 896  * @hdev: pointer to hl_device structure
 897  *
 898  */
 899 static int goya_sw_init(struct hl_device *hdev)
 900 {
 901         struct goya_device *goya;
 902         int rc;
 903
 904         /* Allocate device structure */
 905         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 906         if (!goya)
 907                 return -ENOMEM;
 908
 909         /* according to goya_init_iatu */
 910         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 911
 912         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 913         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 914         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 915
 916         hdev->asic_specific = goya;
 917
 918         /* Create DMA pool for small allocations */
 919         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 920                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 921         if (!hdev->dma_pool) {
 922                 dev_err(hdev->dev, "failed to create DMA pool\n");
 923                 rc = -ENOMEM;
 924                 goto free_goya_device;
 925         }
 926
 927         hdev->cpu_accessible_dma_mem =
 928                         hdev->asic_funcs->asic_dma_alloc_coherent(hdev,
 929                                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 930                                         &hdev->cpu_accessible_dma_address,
 931                                         GFP_KERNEL | __GFP_ZERO);
 932
 933         if (!hdev->cpu_accessible_dma_mem) {
 934                 rc = -ENOMEM;
 935                 goto free_dma_pool;
 936         }
 937
 938         dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
 939                 &hdev->cpu_accessible_dma_address);
 940
 941         hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
 942         if (!hdev->cpu_accessible_dma_pool) {
 943                 dev_err(hdev->dev,
 944                         "Failed to create CPU accessible DMA pool\n");
 945                 rc = -ENOMEM;
 946                 goto free_cpu_dma_mem;
 947         }
 948
 949         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 950                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 951                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
 952         if (rc) {
 953                 dev_err(hdev->dev,
 954                         "Failed to add memory to CPU accessible DMA pool\n");
 955                 rc = -EFAULT;
 956                 goto free_cpu_accessible_dma_pool;
 957         }
 958
 959         spin_lock_init(&goya->hw_queues_lock);
 960         hdev->supports_coresight = true;
 961         hdev->supports_soft_reset = true;
 962         hdev->allow_external_soft_reset = true;
 963         hdev->supports_wait_for_multi_cs = false;
 964
 965         hdev->asic_funcs->set_pci_memory_regions(hdev);
 966
 967         return 0;
 968
 969 free_cpu_accessible_dma_pool:
 970         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 971 free_cpu_dma_mem:
 972         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 973                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 974                         hdev->cpu_accessible_dma_mem,
 975                         hdev->cpu_accessible_dma_address);
 976 free_dma_pool:
 977         dma_pool_destroy(hdev->dma_pool);
 978 free_goya_device:
 979         kfree(goya);
 980
 981         return rc;
 982 }
 983
 984 /*
 985  * goya_sw_fini - Goya software tear-down code
 986  *
 987  * @hdev: pointer to hl_device structure
 988  *
 989  */
 990 static int goya_sw_fini(struct hl_device *hdev)
 991 {
 992         struct goya_device *goya = hdev->asic_specific;
 993
 994         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 995
 996         hdev->asic_funcs->asic_dma_free_coherent(hdev,
 997                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 998                         hdev->cpu_accessible_dma_mem,
 999                         hdev->cpu_accessible_dma_address);
1000
1001         dma_pool_destroy(hdev->dma_pool);
1002
1003         kfree(goya);
1004
1005         return 0;
1006 }
1007
1008 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1009                 dma_addr_t bus_address)
1010 {
1011         struct goya_device *goya = hdev->asic_specific;
1012         u32 mtr_base_lo, mtr_base_hi;
1013         u32 so_base_lo, so_base_hi;
1014         u32 gic_base_lo, gic_base_hi;
1015         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1016         u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1017
1018         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1019         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1020         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1021         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1022
1023         gic_base_lo =
1024                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1025         gic_base_hi =
1026                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1027
1028         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1029         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1030
1031         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1032         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1033         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1034
1035         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1036         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1037         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1038         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1039         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1040         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1041         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1042                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1043
1044         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1045         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1046         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1047
1048         if (goya->hw_cap_initialized & HW_CAP_MMU)
1049                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1050         else
1051                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1052
1053         if (hdev->stop_on_err)
1054                 dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1055
1056         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1057         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1058 }
1059
1060 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1061 {
1062         u32 gic_base_lo, gic_base_hi;
1063         u64 sob_addr;
1064         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1065
1066         gic_base_lo =
1067                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1068         gic_base_hi =
1069                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1070
1071         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1072         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1073         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1074                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1075
1076         if (dma_id)
1077                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1078                                 (dma_id - 1) * 4;
1079         else
1080                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1081
1082         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1083         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1084 }
1085
1086 /*
1087  * goya_init_dma_qmans - Initialize QMAN DMA registers
1088  *
1089  * @hdev: pointer to hl_device structure
1090  *
1091  * Initialize the H/W registers of the QMAN DMA channels
1092  *
1093  */
1094 void goya_init_dma_qmans(struct hl_device *hdev)
1095 {
1096         struct goya_device *goya = hdev->asic_specific;
1097         struct hl_hw_queue *q;
1098         int i;
1099
1100         if (goya->hw_cap_initialized & HW_CAP_DMA)
1101                 return;
1102
1103         q = &hdev->kernel_queues[0];
1104
1105         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1106                 q->cq_id = q->msi_vec = i;
1107                 goya_init_dma_qman(hdev, i, q->bus_address);
1108                 goya_init_dma_ch(hdev, i);
1109         }
1110
1111         goya->hw_cap_initialized |= HW_CAP_DMA;
1112 }
1113
1114 /*
1115  * goya_disable_external_queues - Disable external queues
1116  *
1117  * @hdev: pointer to hl_device structure
1118  *
1119  */
1120 static void goya_disable_external_queues(struct hl_device *hdev)
1121 {
1122         struct goya_device *goya = hdev->asic_specific;
1123
1124         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1125                 return;
1126
1127         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1128         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1129         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1130         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1131         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1132 }
1133
1134 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1135                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
1136 {
1137         int rc;
1138         u32 status;
1139
1140         /* use the values of TPC0 as they are all the same*/
1141
1142         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1143
1144         status = RREG32(cp_sts_reg);
1145         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1146                 rc = hl_poll_timeout(
1147                         hdev,
1148                         cp_sts_reg,
1149                         status,
1150                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1151                         1000,
1152                         QMAN_FENCE_TIMEOUT_USEC);
1153
1154                 /* if QMAN is stuck in fence no need to check for stop */
1155                 if (rc)
1156                         return 0;
1157         }
1158
1159         rc = hl_poll_timeout(
1160                 hdev,
1161                 glbl_sts0_reg,
1162                 status,
1163                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1164                 1000,
1165                 QMAN_STOP_TIMEOUT_USEC);
1166
1167         if (rc) {
1168                 dev_err(hdev->dev,
1169                         "Timeout while waiting for QMAN to stop\n");
1170                 return -EINVAL;
1171         }
1172
1173         return 0;
1174 }
1175
1176 /*
1177  * goya_stop_external_queues - Stop external queues
1178  *
1179  * @hdev: pointer to hl_device structure
1180  *
1181  * Returns 0 on success
1182  *
1183  */
1184 static int goya_stop_external_queues(struct hl_device *hdev)
1185 {
1186         int rc, retval = 0;
1187
1188         struct goya_device *goya = hdev->asic_specific;
1189
1190         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1191                 return retval;
1192
1193         rc = goya_stop_queue(hdev,
1194                         mmDMA_QM_0_GLBL_CFG1,
1195                         mmDMA_QM_0_CP_STS,
1196                         mmDMA_QM_0_GLBL_STS0);
1197
1198         if (rc) {
1199                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1200                 retval = -EIO;
1201         }
1202
1203         rc = goya_stop_queue(hdev,
1204                         mmDMA_QM_1_GLBL_CFG1,
1205                         mmDMA_QM_1_CP_STS,
1206                         mmDMA_QM_1_GLBL_STS0);
1207
1208         if (rc) {
1209                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1210                 retval = -EIO;
1211         }
1212
1213         rc = goya_stop_queue(hdev,
1214                         mmDMA_QM_2_GLBL_CFG1,
1215                         mmDMA_QM_2_CP_STS,
1216                         mmDMA_QM_2_GLBL_STS0);
1217
1218         if (rc) {
1219                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1220                 retval = -EIO;
1221         }
1222
1223         rc = goya_stop_queue(hdev,
1224                         mmDMA_QM_3_GLBL_CFG1,
1225                         mmDMA_QM_3_CP_STS,
1226                         mmDMA_QM_3_GLBL_STS0);
1227
1228         if (rc) {
1229                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1230                 retval = -EIO;
1231         }
1232
1233         rc = goya_stop_queue(hdev,
1234                         mmDMA_QM_4_GLBL_CFG1,
1235                         mmDMA_QM_4_CP_STS,
1236                         mmDMA_QM_4_GLBL_STS0);
1237
1238         if (rc) {
1239                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1240                 retval = -EIO;
1241         }
1242
1243         return retval;
1244 }
1245
1246 /*
1247  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1248  *
1249  * @hdev: pointer to hl_device structure
1250  *
1251  * Returns 0 on success
1252  *
1253  */
1254 int goya_init_cpu_queues(struct hl_device *hdev)
1255 {
1256         struct goya_device *goya = hdev->asic_specific;
1257         struct asic_fixed_properties *prop = &hdev->asic_prop;
1258         struct hl_eq *eq;
1259         u32 status;
1260         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1261         int err;
1262
1263         if (!hdev->cpu_queues_enable)
1264                 return 0;
1265
1266         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1267                 return 0;
1268
1269         eq = &hdev->event_queue;
1270
1271         WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1272         WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1273
1274         WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1275         WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1276
1277         WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1278                         lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1279         WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1280                         upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1281
1282         WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1283         WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1284         WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1285
1286         /* Used for EQ CI */
1287         WREG32(mmCPU_EQ_CI, 0);
1288
1289         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1290
1291         WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1292
1293         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1294                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1295
1296         err = hl_poll_timeout(
1297                 hdev,
1298                 mmCPU_PQ_INIT_STATUS,
1299                 status,
1300                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1301                 1000,
1302                 GOYA_CPU_TIMEOUT_USEC);
1303
1304         if (err) {
1305                 dev_err(hdev->dev,
1306                         "Failed to setup communication with device CPU\n");
1307                 return -EIO;
1308         }
1309
1310         /* update FW application security bits */
1311         if (prop->fw_cpu_boot_dev_sts0_valid)
1312                 prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1313
1314         if (prop->fw_cpu_boot_dev_sts1_valid)
1315                 prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1316
1317         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1318         return 0;
1319 }
1320
1321 static void goya_set_pll_refclk(struct hl_device *hdev)
1322 {
1323         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1324         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1325         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1326         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1327
1328         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1329         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1330         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1331         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1332
1333         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1334         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1335         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1336         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1337
1338         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1339         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1340         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1341         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1342
1343         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1344         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1345         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1346         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1347
1348         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1349         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1350         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1351         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1352
1353         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1354         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1355         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1356         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1357 }
1358
1359 static void goya_disable_clk_rlx(struct hl_device *hdev)
1360 {
1361         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1362         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1363 }
1364
1365 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1366 {
1367         u64 tpc_eml_address;
1368         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1369         int err, slm_index;
1370
1371         tpc_offset = tpc_id * 0x40000;
1372         tpc_eml_offset = tpc_id * 0x200000;
1373         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1374         tpc_slm_offset = tpc_eml_address + 0x100000;
1375
1376         /*
1377          * Workaround for Bug H2 #2443 :
1378          * "TPC SB is not initialized on chip reset"
1379          */
1380
1381         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1382         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1383                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1384                         tpc_id);
1385
1386         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1387
1388         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1389         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1390         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1391         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1392         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1393         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1394         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1395         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1396         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1397         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1398
1399         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1400                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1401
1402         err = hl_poll_timeout(
1403                 hdev,
1404                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1405                 val,
1406                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1407                 1000,
1408                 HL_DEVICE_TIMEOUT_USEC);
1409
1410         if (err)
1411                 dev_err(hdev->dev,
1412                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1413
1414         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1415                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1416
1417         msleep(GOYA_RESET_WAIT_MSEC);
1418
1419         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1420                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1421
1422         msleep(GOYA_RESET_WAIT_MSEC);
1423
1424         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1425                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1426
1427         val = RREG32(tpc_slm_offset);
1428 }
1429
1430 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1431 {
1432         struct goya_device *goya = hdev->asic_specific;
1433         int i;
1434
1435         if (hdev->pldm)
1436                 return;
1437
1438         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1439                 return;
1440
1441         /* Workaround for H2 #2443 */
1442
1443         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1444                 _goya_tpc_mbist_workaround(hdev, i);
1445
1446         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1447 }
1448
1449 /*
1450  * goya_init_golden_registers - Initialize golden registers
1451  *
1452  * @hdev: pointer to hl_device structure
1453  *
1454  * Initialize the H/W registers of the device
1455  *
1456  */
1457 static void goya_init_golden_registers(struct hl_device *hdev)
1458 {
1459         struct goya_device *goya = hdev->asic_specific;
1460         u32 polynom[10], tpc_intr_mask, offset;
1461         int i;
1462
1463         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1464                 return;
1465
1466         polynom[0] = 0x00020080;
1467         polynom[1] = 0x00401000;
1468         polynom[2] = 0x00200800;
1469         polynom[3] = 0x00002000;
1470         polynom[4] = 0x00080200;
1471         polynom[5] = 0x00040100;
1472         polynom[6] = 0x00100400;
1473         polynom[7] = 0x00004000;
1474         polynom[8] = 0x00010000;
1475         polynom[9] = 0x00008000;
1476
1477         /* Mask all arithmetic interrupts from TPC */
1478         tpc_intr_mask = 0x7FFF;
1479
1480         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1481                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1482                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1483                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1484                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1485                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1486
1487                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1488                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1489                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1490                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1491                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1492
1493
1494                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1495                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1496                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1497                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1498                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1499
1500                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1501                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1502                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1503                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1504                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1505
1506                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1507                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1508                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1509                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1510                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1511
1512                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1513                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1514                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1515                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1516                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1517         }
1518
1519         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1520         WREG32(mmMME_AGU, 0x0f0f0f10);
1521         WREG32(mmMME_SEI_MASK, ~0x0);
1522
1523         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1524         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1525         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1526         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1527         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1528         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1529         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1530         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1531         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1532         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1533         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1534         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1535         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1536         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1537         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1538         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1539         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1540         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1541         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1542         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1543         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1544         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1545         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1546         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1547         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1548         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1549         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1550         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1551         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1552         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1553         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1554         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1555         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1556         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1557         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1558         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1559         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1560         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1561         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1562         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1563         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1564         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1565         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1566         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1567         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1568         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1569         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1570         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1571         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1572         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1573         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1574         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1575         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1576         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1577         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1578         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1579         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1580         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1581         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1582         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1583         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1584         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1585         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1586         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1587         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1588         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1589         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1590         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1591         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1592         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1593         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1594         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1595         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1596         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1597         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1598         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1599         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1600         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1601         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1602         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1603         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1604         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1605         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1606         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1607
1608         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1609         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1610         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1611         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1612         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1613         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1614         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1615         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1616         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1617         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1618         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1619         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1620
1621         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1622         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1623         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1624         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1625         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1626         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1627         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1628         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1629         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1630         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1631         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1632         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1633
1634         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1635         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1636         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1637         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1638         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1639         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1640         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1641         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1642         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1643         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1644         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1645         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1646
1647         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1648         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1649         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1650         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1651         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1652         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1653         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1654         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1655         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1656         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1657         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1658         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1659
1660         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1661         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1662         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1663         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1664         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1665         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1666         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1667         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1668         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1669         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1670         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1671         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1672
1673         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1674         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1675         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1676         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1677         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1678         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1679         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1680         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1681         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1682         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1683         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1684         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1685
1686         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1687                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1688                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1689                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1690                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1691                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1692                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1693
1694                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1695                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1696                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1697                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1698                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1699                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1700                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1701                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1702
1703                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1704                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1705         }
1706
1707         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1708                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1709                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1710                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1711                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1712         }
1713
1714         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1715                 /*
1716                  * Workaround for Bug H2 #2441 :
1717                  * "ST.NOP set trace event illegal opcode"
1718                  */
1719                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1720
1721                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1722                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1723                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1724                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1725
1726                 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1727                                 ICACHE_FETCH_LINE_NUM, 2);
1728         }
1729
1730         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1731         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1732                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1733
1734         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1735         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1736                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1737
1738         /*
1739          * Workaround for H2 #HW-23 bug
1740          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1741          * This limitation is still large enough to not affect Gen4 bandwidth.
1742          * We need to only limit that DMA channel because the user can only read
1743          * from Host using DMA CH 1
1744          */
1745         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1746
1747         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1748
1749         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1750 }
1751
1752 static void goya_init_mme_qman(struct hl_device *hdev)
1753 {
1754         u32 mtr_base_lo, mtr_base_hi;
1755         u32 so_base_lo, so_base_hi;
1756         u32 gic_base_lo, gic_base_hi;
1757         u64 qman_base_addr;
1758
1759         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1760         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1761         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1762         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1763
1764         gic_base_lo =
1765                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1766         gic_base_hi =
1767                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1768
1769         qman_base_addr = hdev->asic_prop.sram_base_address +
1770                                 MME_QMAN_BASE_OFFSET;
1771
1772         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1773         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1774         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1775         WREG32(mmMME_QM_PQ_PI, 0);
1776         WREG32(mmMME_QM_PQ_CI, 0);
1777         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1778         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1779         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1780         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1781
1782         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1783         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1784         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1785         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1786
1787         /* QMAN CQ has 8 cache lines */
1788         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1789
1790         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1791         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1792
1793         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1794
1795         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1796
1797         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1798
1799         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1800 }
1801
1802 static void goya_init_mme_cmdq(struct hl_device *hdev)
1803 {
1804         u32 mtr_base_lo, mtr_base_hi;
1805         u32 so_base_lo, so_base_hi;
1806         u32 gic_base_lo, gic_base_hi;
1807
1808         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1809         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1810         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1811         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1812
1813         gic_base_lo =
1814                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1815         gic_base_hi =
1816                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1817
1818         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1819         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1820         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1821         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1822
1823         /* CMDQ CQ has 20 cache lines */
1824         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1825
1826         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1827         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1828
1829         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1830
1831         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1832
1833         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1834
1835         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1836 }
1837
1838 void goya_init_mme_qmans(struct hl_device *hdev)
1839 {
1840         struct goya_device *goya = hdev->asic_specific;
1841         u32 so_base_lo, so_base_hi;
1842
1843         if (goya->hw_cap_initialized & HW_CAP_MME)
1844                 return;
1845
1846         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1847         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1848
1849         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1850         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1851
1852         goya_init_mme_qman(hdev);
1853         goya_init_mme_cmdq(hdev);
1854
1855         goya->hw_cap_initialized |= HW_CAP_MME;
1856 }
1857
1858 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1859 {
1860         u32 mtr_base_lo, mtr_base_hi;
1861         u32 so_base_lo, so_base_hi;
1862         u32 gic_base_lo, gic_base_hi;
1863         u64 qman_base_addr;
1864         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1865
1866         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1867         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1868         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1869         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1870
1871         gic_base_lo =
1872                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1873         gic_base_hi =
1874                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1875
1876         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1877
1878         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1879         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1880         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1881         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1882         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1883         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1884         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1885         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1886         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1887
1888         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1889         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1890         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1891         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1892
1893         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1894
1895         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1896         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1897
1898         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1899                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1900
1901         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1902
1903         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1904
1905         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1906 }
1907
1908 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1909 {
1910         u32 mtr_base_lo, mtr_base_hi;
1911         u32 so_base_lo, so_base_hi;
1912         u32 gic_base_lo, gic_base_hi;
1913         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1914
1915         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1916         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1917         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1918         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1919
1920         gic_base_lo =
1921                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1922         gic_base_hi =
1923                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1924
1925         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1926         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1927         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1928         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1929
1930         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1931
1932         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1933         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1934
1935         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1936                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1937
1938         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1939
1940         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1941
1942         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1943 }
1944
1945 void goya_init_tpc_qmans(struct hl_device *hdev)
1946 {
1947         struct goya_device *goya = hdev->asic_specific;
1948         u32 so_base_lo, so_base_hi;
1949         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1950                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1951         int i;
1952
1953         if (goya->hw_cap_initialized & HW_CAP_TPC)
1954                 return;
1955
1956         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1957         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1958
1959         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1960                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1961                                 so_base_lo);
1962                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1963                                 so_base_hi);
1964         }
1965
1966         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1967         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1968         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1969         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1970         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1971         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1972         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1973         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1974
1975         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1976                 goya_init_tpc_cmdq(hdev, i);
1977
1978         goya->hw_cap_initialized |= HW_CAP_TPC;
1979 }
1980
1981 /*
1982  * goya_disable_internal_queues - Disable internal queues
1983  *
1984  * @hdev: pointer to hl_device structure
1985  *
1986  */
1987 static void goya_disable_internal_queues(struct hl_device *hdev)
1988 {
1989         struct goya_device *goya = hdev->asic_specific;
1990
1991         if (!(goya->hw_cap_initialized & HW_CAP_MME))
1992                 goto disable_tpc;
1993
1994         WREG32(mmMME_QM_GLBL_CFG0, 0);
1995         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1996
1997 disable_tpc:
1998         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
1999                 return;
2000
2001         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2002         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2003
2004         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2005         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2006
2007         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2008         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2009
2010         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2011         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2012
2013         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2014         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2015
2016         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2017         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2018
2019         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2020         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2021
2022         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2023         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2024 }
2025
2026 /*
2027  * goya_stop_internal_queues - Stop internal queues
2028  *
2029  * @hdev: pointer to hl_device structure
2030  *
2031  * Returns 0 on success
2032  *
2033  */
2034 static int goya_stop_internal_queues(struct hl_device *hdev)
2035 {
2036         struct goya_device *goya = hdev->asic_specific;
2037         int rc, retval = 0;
2038
2039         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2040                 goto stop_tpc;
2041
2042         /*
2043          * Each queue (QMAN) is a separate H/W logic. That means that each
2044          * QMAN can be stopped independently and failure to stop one does NOT
2045          * mandate we should not try to stop other QMANs
2046          */
2047
2048         rc = goya_stop_queue(hdev,
2049                         mmMME_QM_GLBL_CFG1,
2050                         mmMME_QM_CP_STS,
2051                         mmMME_QM_GLBL_STS0);
2052
2053         if (rc) {
2054                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
2055                 retval = -EIO;
2056         }
2057
2058         rc = goya_stop_queue(hdev,
2059                         mmMME_CMDQ_GLBL_CFG1,
2060                         mmMME_CMDQ_CP_STS,
2061                         mmMME_CMDQ_GLBL_STS0);
2062
2063         if (rc) {
2064                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2065                 retval = -EIO;
2066         }
2067
2068 stop_tpc:
2069         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2070                 return retval;
2071
2072         rc = goya_stop_queue(hdev,
2073                         mmTPC0_QM_GLBL_CFG1,
2074                         mmTPC0_QM_CP_STS,
2075                         mmTPC0_QM_GLBL_STS0);
2076
2077         if (rc) {
2078                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2079                 retval = -EIO;
2080         }
2081
2082         rc = goya_stop_queue(hdev,
2083                         mmTPC0_CMDQ_GLBL_CFG1,
2084                         mmTPC0_CMDQ_CP_STS,
2085                         mmTPC0_CMDQ_GLBL_STS0);
2086
2087         if (rc) {
2088                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2089                 retval = -EIO;
2090         }
2091
2092         rc = goya_stop_queue(hdev,
2093                         mmTPC1_QM_GLBL_CFG1,
2094                         mmTPC1_QM_CP_STS,
2095                         mmTPC1_QM_GLBL_STS0);
2096
2097         if (rc) {
2098                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2099                 retval = -EIO;
2100         }
2101
2102         rc = goya_stop_queue(hdev,
2103                         mmTPC1_CMDQ_GLBL_CFG1,
2104                         mmTPC1_CMDQ_CP_STS,
2105                         mmTPC1_CMDQ_GLBL_STS0);
2106
2107         if (rc) {
2108                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2109                 retval = -EIO;
2110         }
2111
2112         rc = goya_stop_queue(hdev,
2113                         mmTPC2_QM_GLBL_CFG1,
2114                         mmTPC2_QM_CP_STS,
2115                         mmTPC2_QM_GLBL_STS0);
2116
2117         if (rc) {
2118                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2119                 retval = -EIO;
2120         }
2121
2122         rc = goya_stop_queue(hdev,
2123                         mmTPC2_CMDQ_GLBL_CFG1,
2124                         mmTPC2_CMDQ_CP_STS,
2125                         mmTPC2_CMDQ_GLBL_STS0);
2126
2127         if (rc) {
2128                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2129                 retval = -EIO;
2130         }
2131
2132         rc = goya_stop_queue(hdev,
2133                         mmTPC3_QM_GLBL_CFG1,
2134                         mmTPC3_QM_CP_STS,
2135                         mmTPC3_QM_GLBL_STS0);
2136
2137         if (rc) {
2138                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2139                 retval = -EIO;
2140         }
2141
2142         rc = goya_stop_queue(hdev,
2143                         mmTPC3_CMDQ_GLBL_CFG1,
2144                         mmTPC3_CMDQ_CP_STS,
2145                         mmTPC3_CMDQ_GLBL_STS0);
2146
2147         if (rc) {
2148                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2149                 retval = -EIO;
2150         }
2151
2152         rc = goya_stop_queue(hdev,
2153                         mmTPC4_QM_GLBL_CFG1,
2154                         mmTPC4_QM_CP_STS,
2155                         mmTPC4_QM_GLBL_STS0);
2156
2157         if (rc) {
2158                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2159                 retval = -EIO;
2160         }
2161
2162         rc = goya_stop_queue(hdev,
2163                         mmTPC4_CMDQ_GLBL_CFG1,
2164                         mmTPC4_CMDQ_CP_STS,
2165                         mmTPC4_CMDQ_GLBL_STS0);
2166
2167         if (rc) {
2168                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2169                 retval = -EIO;
2170         }
2171
2172         rc = goya_stop_queue(hdev,
2173                         mmTPC5_QM_GLBL_CFG1,
2174                         mmTPC5_QM_CP_STS,
2175                         mmTPC5_QM_GLBL_STS0);
2176
2177         if (rc) {
2178                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2179                 retval = -EIO;
2180         }
2181
2182         rc = goya_stop_queue(hdev,
2183                         mmTPC5_CMDQ_GLBL_CFG1,
2184                         mmTPC5_CMDQ_CP_STS,
2185                         mmTPC5_CMDQ_GLBL_STS0);
2186
2187         if (rc) {
2188                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2189                 retval = -EIO;
2190         }
2191
2192         rc = goya_stop_queue(hdev,
2193                         mmTPC6_QM_GLBL_CFG1,
2194                         mmTPC6_QM_CP_STS,
2195                         mmTPC6_QM_GLBL_STS0);
2196
2197         if (rc) {
2198                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2199                 retval = -EIO;
2200         }
2201
2202         rc = goya_stop_queue(hdev,
2203                         mmTPC6_CMDQ_GLBL_CFG1,
2204                         mmTPC6_CMDQ_CP_STS,
2205                         mmTPC6_CMDQ_GLBL_STS0);
2206
2207         if (rc) {
2208                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2209                 retval = -EIO;
2210         }
2211
2212         rc = goya_stop_queue(hdev,
2213                         mmTPC7_QM_GLBL_CFG1,
2214                         mmTPC7_QM_CP_STS,
2215                         mmTPC7_QM_GLBL_STS0);
2216
2217         if (rc) {
2218                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2219                 retval = -EIO;
2220         }
2221
2222         rc = goya_stop_queue(hdev,
2223                         mmTPC7_CMDQ_GLBL_CFG1,
2224                         mmTPC7_CMDQ_CP_STS,
2225                         mmTPC7_CMDQ_GLBL_STS0);
2226
2227         if (rc) {
2228                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2229                 retval = -EIO;
2230         }
2231
2232         return retval;
2233 }
2234
2235 static void goya_dma_stall(struct hl_device *hdev)
2236 {
2237         struct goya_device *goya = hdev->asic_specific;
2238
2239         if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2240                 return;
2241
2242         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2243         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2244         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2245         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2246         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2247 }
2248
2249 static void goya_tpc_stall(struct hl_device *hdev)
2250 {
2251         struct goya_device *goya = hdev->asic_specific;
2252
2253         if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2254                 return;
2255
2256         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2257         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2258         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2259         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2260         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2261         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2262         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2263         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2264 }
2265
2266 static void goya_mme_stall(struct hl_device *hdev)
2267 {
2268         struct goya_device *goya = hdev->asic_specific;
2269
2270         if (!(goya->hw_cap_initialized & HW_CAP_MME))
2271                 return;
2272
2273         WREG32(mmMME_STALL, 0xFFFFFFFF);
2274 }
2275
2276 static int goya_enable_msix(struct hl_device *hdev)
2277 {
2278         struct goya_device *goya = hdev->asic_specific;
2279         int cq_cnt = hdev->asic_prop.completion_queues_count;
2280         int rc, i, irq_cnt_init, irq;
2281
2282         if (goya->hw_cap_initialized & HW_CAP_MSIX)
2283                 return 0;
2284
2285         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2286                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2287         if (rc < 0) {
2288                 dev_err(hdev->dev,
2289                         "MSI-X: Failed to enable support -- %d/%d\n",
2290                         GOYA_MSIX_ENTRIES, rc);
2291                 return rc;
2292         }
2293
2294         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2295                 irq = pci_irq_vector(hdev->pdev, i);
2296                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2297                                 &hdev->completion_queue[i]);
2298                 if (rc) {
2299                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2300                         goto free_irqs;
2301                 }
2302         }
2303
2304         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2305
2306         rc = request_irq(irq, hl_irq_handler_eq, 0,
2307                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2308                         &hdev->event_queue);
2309         if (rc) {
2310                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2311                 goto free_irqs;
2312         }
2313
2314         goya->hw_cap_initialized |= HW_CAP_MSIX;
2315         return 0;
2316
2317 free_irqs:
2318         for (i = 0 ; i < irq_cnt_init ; i++)
2319                 free_irq(pci_irq_vector(hdev->pdev, i),
2320                         &hdev->completion_queue[i]);
2321
2322         pci_free_irq_vectors(hdev->pdev);
2323         return rc;
2324 }
2325
2326 static void goya_sync_irqs(struct hl_device *hdev)
2327 {
2328         struct goya_device *goya = hdev->asic_specific;
2329         int i;
2330
2331         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2332                 return;
2333
2334         /* Wait for all pending IRQs to be finished */
2335         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2336                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2337
2338         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2339 }
2340
2341 static void goya_disable_msix(struct hl_device *hdev)
2342 {
2343         struct goya_device *goya = hdev->asic_specific;
2344         int i, irq;
2345
2346         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2347                 return;
2348
2349         goya_sync_irqs(hdev);
2350
2351         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2352         free_irq(irq, &hdev->event_queue);
2353
2354         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2355                 irq = pci_irq_vector(hdev->pdev, i);
2356                 free_irq(irq, &hdev->completion_queue[i]);
2357         }
2358
2359         pci_free_irq_vectors(hdev->pdev);
2360
2361         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2362 }
2363
2364 static void goya_enable_timestamp(struct hl_device *hdev)
2365 {
2366         /* Disable the timestamp counter */
2367         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2368
2369         /* Zero the lower/upper parts of the 64-bit counter */
2370         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2371         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2372
2373         /* Enable the counter */
2374         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2375 }
2376
2377 static void goya_disable_timestamp(struct hl_device *hdev)
2378 {
2379         /* Disable the timestamp counter */
2380         WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2381 }
2382
2383 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2384 {
2385         u32 wait_timeout_ms;
2386
2387         dev_info(hdev->dev,
2388                 "Halting compute engines and disabling interrupts\n");
2389
2390         if (hdev->pldm)
2391                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2392         else
2393                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2394
2395         goya_stop_external_queues(hdev);
2396         goya_stop_internal_queues(hdev);
2397
2398         msleep(wait_timeout_ms);
2399
2400         goya_dma_stall(hdev);
2401         goya_tpc_stall(hdev);
2402         goya_mme_stall(hdev);
2403
2404         msleep(wait_timeout_ms);
2405
2406         goya_disable_external_queues(hdev);
2407         goya_disable_internal_queues(hdev);
2408
2409         goya_disable_timestamp(hdev);
2410
2411         if (hard_reset) {
2412                 goya_disable_msix(hdev);
2413                 goya_mmu_remove_device_cpu_mappings(hdev);
2414         } else {
2415                 goya_sync_irqs(hdev);
2416         }
2417 }
2418
2419 /*
2420  * goya_load_firmware_to_device() - Load LINUX FW code to device.
2421  * @hdev: Pointer to hl_device structure.
2422  *
2423  * Copy LINUX fw code from firmware file to HBM BAR.
2424  *
2425  * Return: 0 on success, non-zero for failure.
2426  */
2427 static int goya_load_firmware_to_device(struct hl_device *hdev)
2428 {
2429         void __iomem *dst;
2430
2431         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2432
2433         return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2434 }
2435
2436 /*
2437  * goya_load_boot_fit_to_device() - Load boot fit to device.
2438  * @hdev: Pointer to hl_device structure.
2439  *
2440  * Copy boot fit file to SRAM BAR.
2441  *
2442  * Return: 0 on success, non-zero for failure.
2443  */
2444 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2445 {
2446         void __iomem *dst;
2447
2448         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2449
2450         return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2451 }
2452
2453 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2454 {
2455         struct dynamic_fw_load_mgr *dynamic_loader;
2456         struct cpu_dyn_regs *dyn_regs;
2457
2458         dynamic_loader = &hdev->fw_loader.dynamic_loader;
2459
2460         /*
2461          * here we update initial values for few specific dynamic regs (as
2462          * before reading the first descriptor from FW those value has to be
2463          * hard-coded) in later stages of the protocol those values will be
2464          * updated automatically by reading the FW descriptor so data there
2465          * will always be up-to-date
2466          */
2467         dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2468         dyn_regs->kmd_msg_to_cpu =
2469                                 cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2470         dyn_regs->cpu_cmd_status_to_host =
2471                                 cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2472
2473         dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2474 }
2475
2476 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2477 {
2478         struct static_fw_load_mgr *static_loader;
2479
2480         static_loader = &hdev->fw_loader.static_loader;
2481
2482         static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2483         static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2484         static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2485         static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2486         static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2487         static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2488         static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2489         static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2490         static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2491         static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2492         static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2493         static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2494 }
2495
2496 static void goya_init_firmware_loader(struct hl_device *hdev)
2497 {
2498         struct asic_fixed_properties *prop = &hdev->asic_prop;
2499         struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2500
2501         /* fill common fields */
2502         fw_loader->linux_loaded = false;
2503         fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2504         fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2505         fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2506         fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2507         fw_loader->skip_bmc = false;
2508         fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2509         fw_loader->dram_bar_id = DDR_BAR_ID;
2510
2511         if (prop->dynamic_fw_load)
2512                 goya_init_dynamic_firmware_loader(hdev);
2513         else
2514                 goya_init_static_firmware_loader(hdev);
2515 }
2516
2517 static int goya_init_cpu(struct hl_device *hdev)
2518 {
2519         struct goya_device *goya = hdev->asic_specific;
2520         int rc;
2521
2522         if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2523                 return 0;
2524
2525         if (goya->hw_cap_initialized & HW_CAP_CPU)
2526                 return 0;
2527
2528         /*
2529          * Before pushing u-boot/linux to device, need to set the ddr bar to
2530          * base address of dram
2531          */
2532         if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2533                 dev_err(hdev->dev,
2534                         "failed to map DDR bar to DRAM base address\n");
2535                 return -EIO;
2536         }
2537
2538         rc = hl_fw_init_cpu(hdev);
2539
2540         if (rc)
2541                 return rc;
2542
2543         goya->hw_cap_initialized |= HW_CAP_CPU;
2544
2545         return 0;
2546 }
2547
2548 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2549                                                 u64 phys_addr)
2550 {
2551         u32 status, timeout_usec;
2552         int rc;
2553
2554         if (hdev->pldm)
2555                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2556         else
2557                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2558
2559         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2560         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2561         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2562
2563         rc = hl_poll_timeout(
2564                 hdev,
2565                 MMU_ASID_BUSY,
2566                 status,
2567                 !(status & 0x80000000),
2568                 1000,
2569                 timeout_usec);
2570
2571         if (rc) {
2572                 dev_err(hdev->dev,
2573                         "Timeout during MMU hop0 config of asid %d\n", asid);
2574                 return rc;
2575         }
2576
2577         return 0;
2578 }
2579
2580 int goya_mmu_init(struct hl_device *hdev)
2581 {
2582         struct asic_fixed_properties *prop = &hdev->asic_prop;
2583         struct goya_device *goya = hdev->asic_specific;
2584         u64 hop0_addr;
2585         int rc, i;
2586
2587         if (!hdev->mmu_enable)
2588                 return 0;
2589
2590         if (goya->hw_cap_initialized & HW_CAP_MMU)
2591                 return 0;
2592
2593         hdev->dram_default_page_mapping = true;
2594
2595         for (i = 0 ; i < prop->max_asid ; i++) {
2596                 hop0_addr = prop->mmu_pgt_addr +
2597                                 (i * prop->mmu_hop_table_size);
2598
2599                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2600                 if (rc) {
2601                         dev_err(hdev->dev,
2602                                 "failed to set hop0 addr for asid %d\n", i);
2603                         goto err;
2604                 }
2605         }
2606
2607         goya->hw_cap_initialized |= HW_CAP_MMU;
2608
2609         /* init MMU cache manage page */
2610         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2611                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2612         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2613
2614         /* Remove follower feature due to performance bug */
2615         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2616                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2617
2618         hdev->asic_funcs->mmu_invalidate_cache(hdev, true,
2619                                         VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK);
2620
2621         WREG32(mmMMU_MMU_ENABLE, 1);
2622         WREG32(mmMMU_SPI_MASK, 0xF);
2623
2624         return 0;
2625
2626 err:
2627         return rc;
2628 }
2629
2630 /*
2631  * goya_hw_init - Goya hardware initialization code
2632  *
2633  * @hdev: pointer to hl_device structure
2634  *
2635  * Returns 0 on success
2636  *
2637  */
2638 static int goya_hw_init(struct hl_device *hdev)
2639 {
2640         struct asic_fixed_properties *prop = &hdev->asic_prop;
2641         int rc;
2642
2643         /* Perform read from the device to make sure device is up */
2644         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2645
2646         /*
2647          * Let's mark in the H/W that we have reached this point. We check
2648          * this value in the reset_before_init function to understand whether
2649          * we need to reset the chip before doing H/W init. This register is
2650          * cleared by the H/W upon H/W reset
2651          */
2652         WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2653
2654         rc = goya_init_cpu(hdev);
2655         if (rc) {
2656                 dev_err(hdev->dev, "failed to initialize CPU\n");
2657                 return rc;
2658         }
2659
2660         goya_tpc_mbist_workaround(hdev);
2661
2662         goya_init_golden_registers(hdev);
2663
2664         /*
2665          * After CPU initialization is finished, change DDR bar mapping inside
2666          * iATU to point to the start address of the MMU page tables
2667          */
2668         if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2669                         ~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2670                 dev_err(hdev->dev,
2671                         "failed to map DDR bar to MMU page tables\n");
2672                 return -EIO;
2673         }
2674
2675         rc = goya_mmu_init(hdev);
2676         if (rc)
2677                 return rc;
2678
2679         goya_init_security(hdev);
2680
2681         goya_init_dma_qmans(hdev);
2682
2683         goya_init_mme_qmans(hdev);
2684
2685         goya_init_tpc_qmans(hdev);
2686
2687         goya_enable_timestamp(hdev);
2688
2689         /* MSI-X must be enabled before CPU queues are initialized */
2690         rc = goya_enable_msix(hdev);
2691         if (rc)
2692                 goto disable_queues;
2693
2694         /* Perform read from the device to flush all MSI-X configuration */
2695         RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2696
2697         return 0;
2698
2699 disable_queues:
2700         goya_disable_internal_queues(hdev);
2701         goya_disable_external_queues(hdev);
2702
2703         return rc;
2704 }
2705
2706 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2707 {
2708         struct goya_device *goya = hdev->asic_specific;
2709         u32 reset_timeout_ms, cpu_timeout_ms, status;
2710
2711         if (hdev->pldm) {
2712                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2713                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2714         } else {
2715                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2716                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2717         }
2718
2719         if (hard_reset) {
2720                 /* I don't know what is the state of the CPU so make sure it is
2721                  * stopped in any means necessary
2722                  */
2723                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2724                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2725                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2726
2727                 msleep(cpu_timeout_ms);
2728
2729                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2730                 goya_disable_clk_rlx(hdev);
2731                 goya_set_pll_refclk(hdev);
2732
2733                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2734                 dev_info(hdev->dev,
2735                         "Issued HARD reset command, going to wait %dms\n",
2736                         reset_timeout_ms);
2737         } else {
2738                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2739                 dev_info(hdev->dev,
2740                         "Issued SOFT reset command, going to wait %dms\n",
2741                         reset_timeout_ms);
2742         }
2743
2744         /*
2745          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2746          * itself is in reset. In either reset we need to wait until the reset
2747          * is deasserted
2748          */
2749         msleep(reset_timeout_ms);
2750
2751         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2752         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2753                 dev_err(hdev->dev,
2754                         "Timeout while waiting for device to reset 0x%x\n",
2755                         status);
2756
2757         if (!hard_reset && goya) {
2758                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2759                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2760                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2761                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2762                 return;
2763         }
2764
2765         /* Chicken bit to re-initiate boot sequencer flow */
2766         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2767                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2768         /* Move boot manager FSM to pre boot sequencer init state */
2769         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2770                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2771
2772         if (goya) {
2773                 goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2774                                 HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2775                                 HW_CAP_DMA | HW_CAP_MME |
2776                                 HW_CAP_MMU | HW_CAP_TPC_MBIST |
2777                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2778
2779                 memset(goya->events_stat, 0, sizeof(goya->events_stat));
2780         }
2781 }
2782
2783 int goya_suspend(struct hl_device *hdev)
2784 {
2785         int rc;
2786
2787         rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
2788         if (rc)
2789                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2790
2791         return rc;
2792 }
2793
2794 int goya_resume(struct hl_device *hdev)
2795 {
2796         return goya_init_iatu(hdev);
2797 }
2798
2799 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2800                         void *cpu_addr, dma_addr_t dma_addr, size_t size)
2801 {
2802         int rc;
2803
2804         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2805                         VM_DONTCOPY | VM_NORESERVE;
2806
2807         rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2808                                 (dma_addr - HOST_PHYS_BASE), size);
2809         if (rc)
2810                 dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2811
2812         return rc;
2813 }
2814
2815 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2816 {
2817         u32 db_reg_offset, db_value;
2818
2819         switch (hw_queue_id) {
2820         case GOYA_QUEUE_ID_DMA_0:
2821                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2822                 break;
2823
2824         case GOYA_QUEUE_ID_DMA_1:
2825                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2826                 break;
2827
2828         case GOYA_QUEUE_ID_DMA_2:
2829                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2830                 break;
2831
2832         case GOYA_QUEUE_ID_DMA_3:
2833                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2834                 break;
2835
2836         case GOYA_QUEUE_ID_DMA_4:
2837                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2838                 break;
2839
2840         case GOYA_QUEUE_ID_CPU_PQ:
2841                 db_reg_offset = mmCPU_IF_PF_PQ_PI;
2842                 break;
2843
2844         case GOYA_QUEUE_ID_MME:
2845                 db_reg_offset = mmMME_QM_PQ_PI;
2846                 break;
2847
2848         case GOYA_QUEUE_ID_TPC0:
2849                 db_reg_offset = mmTPC0_QM_PQ_PI;
2850                 break;
2851
2852         case GOYA_QUEUE_ID_TPC1:
2853                 db_reg_offset = mmTPC1_QM_PQ_PI;
2854                 break;
2855
2856         case GOYA_QUEUE_ID_TPC2:
2857                 db_reg_offset = mmTPC2_QM_PQ_PI;
2858                 break;
2859
2860         case GOYA_QUEUE_ID_TPC3:
2861                 db_reg_offset = mmTPC3_QM_PQ_PI;
2862                 break;
2863
2864         case GOYA_QUEUE_ID_TPC4:
2865                 db_reg_offset = mmTPC4_QM_PQ_PI;
2866                 break;
2867
2868         case GOYA_QUEUE_ID_TPC5:
2869                 db_reg_offset = mmTPC5_QM_PQ_PI;
2870                 break;
2871
2872         case GOYA_QUEUE_ID_TPC6:
2873                 db_reg_offset = mmTPC6_QM_PQ_PI;
2874                 break;
2875
2876         case GOYA_QUEUE_ID_TPC7:
2877                 db_reg_offset = mmTPC7_QM_PQ_PI;
2878                 break;
2879
2880         default:
2881                 /* Should never get here */
2882                 dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2883                         hw_queue_id);
2884                 return;
2885         }
2886
2887         db_value = pi;
2888
2889         /* ring the doorbell */
2890         WREG32(db_reg_offset, db_value);
2891
2892         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2893                 /* make sure device CPU will read latest data from host */
2894                 mb();
2895                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2896                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2897         }
2898 }
2899
2900 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2901 {
2902         /* The QMANs are on the SRAM so need to copy to IO space */
2903         memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2904 }
2905
2906 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2907                                         dma_addr_t *dma_handle, gfp_t flags)
2908 {
2909         void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2910                                                 dma_handle, flags);
2911
2912         /* Shift to the device's base physical address of host memory */
2913         if (kernel_addr)
2914                 *dma_handle += HOST_PHYS_BASE;
2915
2916         return kernel_addr;
2917 }
2918
2919 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2920                                         void *cpu_addr, dma_addr_t dma_handle)
2921 {
2922         /* Cancel the device's base physical address of host memory */
2923         dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
2924
2925         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
2926 }
2927
2928 int goya_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size)
2929 {
2930         return 0;
2931 }
2932
2933 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2934                                 dma_addr_t *dma_handle, u16 *queue_len)
2935 {
2936         void *base;
2937         u32 offset;
2938
2939         *dma_handle = hdev->asic_prop.sram_base_address;
2940
2941         base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2942
2943         switch (queue_id) {
2944         case GOYA_QUEUE_ID_MME:
2945                 offset = MME_QMAN_BASE_OFFSET;
2946                 *queue_len = MME_QMAN_LENGTH;
2947                 break;
2948         case GOYA_QUEUE_ID_TPC0:
2949                 offset = TPC0_QMAN_BASE_OFFSET;
2950                 *queue_len = TPC_QMAN_LENGTH;
2951                 break;
2952         case GOYA_QUEUE_ID_TPC1:
2953                 offset = TPC1_QMAN_BASE_OFFSET;
2954                 *queue_len = TPC_QMAN_LENGTH;
2955                 break;
2956         case GOYA_QUEUE_ID_TPC2:
2957                 offset = TPC2_QMAN_BASE_OFFSET;
2958                 *queue_len = TPC_QMAN_LENGTH;
2959                 break;
2960         case GOYA_QUEUE_ID_TPC3:
2961                 offset = TPC3_QMAN_BASE_OFFSET;
2962                 *queue_len = TPC_QMAN_LENGTH;
2963                 break;
2964         case GOYA_QUEUE_ID_TPC4:
2965                 offset = TPC4_QMAN_BASE_OFFSET;
2966                 *queue_len = TPC_QMAN_LENGTH;
2967                 break;
2968         case GOYA_QUEUE_ID_TPC5:
2969                 offset = TPC5_QMAN_BASE_OFFSET;
2970                 *queue_len = TPC_QMAN_LENGTH;
2971                 break;
2972         case GOYA_QUEUE_ID_TPC6:
2973                 offset = TPC6_QMAN_BASE_OFFSET;
2974                 *queue_len = TPC_QMAN_LENGTH;
2975                 break;
2976         case GOYA_QUEUE_ID_TPC7:
2977                 offset = TPC7_QMAN_BASE_OFFSET;
2978                 *queue_len = TPC_QMAN_LENGTH;
2979                 break;
2980         default:
2981                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2982                 return NULL;
2983         }
2984
2985         base += offset;
2986         *dma_handle += offset;
2987
2988         return base;
2989 }
2990
2991 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
2992 {
2993         struct packet_msg_prot *fence_pkt;
2994         u32 *fence_ptr;
2995         dma_addr_t fence_dma_addr;
2996         struct hl_cb *cb;
2997         u32 tmp, timeout;
2998         int rc;
2999
3000         if (hdev->pldm)
3001                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3002         else
3003                 timeout = HL_DEVICE_TIMEOUT_USEC;
3004
3005         if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3006                 dev_err_ratelimited(hdev->dev,
3007                         "Can't send driver job on QMAN0 because the device is not idle\n");
3008                 return -EBUSY;
3009         }
3010
3011         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3012                                                         &fence_dma_addr);
3013         if (!fence_ptr) {
3014                 dev_err(hdev->dev,
3015                         "Failed to allocate fence memory for QMAN0\n");
3016                 return -ENOMEM;
3017         }
3018
3019         goya_qman0_set_security(hdev, true);
3020
3021         cb = job->patched_cb;
3022
3023         fence_pkt = cb->kernel_address +
3024                         job->job_cb_size - sizeof(struct packet_msg_prot);
3025
3026         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3027                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3028                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3029         fence_pkt->ctl = cpu_to_le32(tmp);
3030         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3031         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3032
3033         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3034                                         job->job_cb_size, cb->bus_address);
3035         if (rc) {
3036                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3037                 goto free_fence_ptr;
3038         }
3039
3040         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3041                                 (tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3042                                 timeout, true);
3043
3044         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3045
3046         if (rc == -ETIMEDOUT) {
3047                 dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3048                 goto free_fence_ptr;
3049         }
3050
3051 free_fence_ptr:
3052         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3053                                         fence_dma_addr);
3054
3055         goya_qman0_set_security(hdev, false);
3056
3057         return rc;
3058 }
3059
3060 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3061                                 u32 timeout, u64 *result)
3062 {
3063         struct goya_device *goya = hdev->asic_specific;
3064
3065         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3066                 if (result)
3067                         *result = 0;
3068                 return 0;
3069         }
3070
3071         if (!timeout)
3072                 timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3073
3074         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3075                                         timeout, result);
3076 }
3077
3078 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3079 {
3080         struct packet_msg_prot *fence_pkt;
3081         dma_addr_t pkt_dma_addr;
3082         u32 fence_val, tmp;
3083         dma_addr_t fence_dma_addr;
3084         u32 *fence_ptr;
3085         int rc;
3086
3087         fence_val = GOYA_QMAN0_FENCE_VAL;
3088
3089         fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL,
3090                                                         &fence_dma_addr);
3091         if (!fence_ptr) {
3092                 dev_err(hdev->dev,
3093                         "Failed to allocate memory for H/W queue %d testing\n",
3094                         hw_queue_id);
3095                 return -ENOMEM;
3096         }
3097
3098         *fence_ptr = 0;
3099
3100         fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev,
3101                                         sizeof(struct packet_msg_prot),
3102                                         GFP_KERNEL, &pkt_dma_addr);
3103         if (!fence_pkt) {
3104                 dev_err(hdev->dev,
3105                         "Failed to allocate packet for H/W queue %d testing\n",
3106                         hw_queue_id);
3107                 rc = -ENOMEM;
3108                 goto free_fence_ptr;
3109         }
3110
3111         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3112                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3113                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3114         fence_pkt->ctl = cpu_to_le32(tmp);
3115         fence_pkt->value = cpu_to_le32(fence_val);
3116         fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3117
3118         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3119                                         sizeof(struct packet_msg_prot),
3120                                         pkt_dma_addr);
3121         if (rc) {
3122                 dev_err(hdev->dev,
3123                         "Failed to send fence packet to H/W queue %d\n",
3124                         hw_queue_id);
3125                 goto free_pkt;
3126         }
3127
3128         rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3129                                         1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3130
3131         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3132
3133         if (rc == -ETIMEDOUT) {
3134                 dev_err(hdev->dev,
3135                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3136                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3137                 rc = -EIO;
3138         }
3139
3140 free_pkt:
3141         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt,
3142                                         pkt_dma_addr);
3143 free_fence_ptr:
3144         hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr,
3145                                         fence_dma_addr);
3146         return rc;
3147 }
3148
3149 int goya_test_cpu_queue(struct hl_device *hdev)
3150 {
3151         struct goya_device *goya = hdev->asic_specific;
3152
3153         /*
3154          * check capability here as send_cpu_message() won't update the result
3155          * value if no capability
3156          */
3157         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3158                 return 0;
3159
3160         return hl_fw_test_cpu_queue(hdev);
3161 }
3162
3163 int goya_test_queues(struct hl_device *hdev)
3164 {
3165         int i, rc, ret_val = 0;
3166
3167         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3168                 rc = goya_test_queue(hdev, i);
3169                 if (rc)
3170                         ret_val = -EINVAL;
3171         }
3172
3173         return ret_val;
3174 }
3175
3176 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3177                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3178 {
3179         void *kernel_addr;
3180
3181         if (size > GOYA_DMA_POOL_BLK_SIZE)
3182                 return NULL;
3183
3184         kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3185
3186         /* Shift to the device's base physical address of host memory */
3187         if (kernel_addr)
3188                 *dma_handle += HOST_PHYS_BASE;
3189
3190         return kernel_addr;
3191 }
3192
3193 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3194                                 dma_addr_t dma_addr)
3195 {
3196         /* Cancel the device's base physical address of host memory */
3197         dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3198
3199         dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3200 }
3201
3202 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3203                                         dma_addr_t *dma_handle)
3204 {
3205         void *vaddr;
3206
3207         vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3208         *dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3209                         VA_CPU_ACCESSIBLE_MEM_ADDR;
3210
3211         return vaddr;
3212 }
3213
3214 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3215                                         void *vaddr)
3216 {
3217         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3218 }
3219
3220 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl,
3221                                 int nents, enum dma_data_direction dir)
3222 {
3223         struct scatterlist *sg;
3224         int i;
3225
3226         if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir))
3227                 return -ENOMEM;
3228
3229         /* Shift to the device's base physical address of host memory */
3230         for_each_sg(sgl, sg, nents, i)
3231                 sg->dma_address += HOST_PHYS_BASE;
3232
3233         return 0;
3234 }
3235
3236 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl,
3237                                 int nents, enum dma_data_direction dir)
3238 {
3239         struct scatterlist *sg;
3240         int i;
3241
3242         /* Cancel the device's base physical address of host memory */
3243         for_each_sg(sgl, sg, nents, i)
3244                 sg->dma_address -= HOST_PHYS_BASE;
3245
3246         dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir);
3247 }
3248
3249 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3250 {
3251         struct scatterlist *sg, *sg_next_iter;
3252         u32 count, dma_desc_cnt;
3253         u64 len, len_next;
3254         dma_addr_t addr, addr_next;
3255
3256         dma_desc_cnt = 0;
3257
3258         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3259
3260                 len = sg_dma_len(sg);
3261                 addr = sg_dma_address(sg);
3262
3263                 if (len == 0)
3264                         break;
3265
3266                 while ((count + 1) < sgt->nents) {
3267                         sg_next_iter = sg_next(sg);
3268                         len_next = sg_dma_len(sg_next_iter);
3269                         addr_next = sg_dma_address(sg_next_iter);
3270
3271                         if (len_next == 0)
3272                                 break;
3273
3274                         if ((addr + len == addr_next) &&
3275                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3276                                 len += len_next;
3277                                 count++;
3278                                 sg = sg_next_iter;
3279                         } else {
3280                                 break;
3281                         }
3282                 }
3283
3284                 dma_desc_cnt++;
3285         }
3286
3287         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3288 }
3289
3290 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3291                                 struct hl_cs_parser *parser,
3292                                 struct packet_lin_dma *user_dma_pkt,
3293                                 u64 addr, enum dma_data_direction dir)
3294 {
3295         struct hl_userptr *userptr;
3296         int rc;
3297
3298         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3299                         parser->job_userptr_list, &userptr))
3300                 goto already_pinned;
3301
3302         userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3303         if (!userptr)
3304                 return -ENOMEM;
3305
3306         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3307                                 userptr);
3308         if (rc)
3309                 goto free_userptr;
3310
3311         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3312
3313         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3314                                         userptr->sgt->nents, dir);
3315         if (rc) {
3316                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3317                 goto unpin_memory;
3318         }
3319
3320         userptr->dma_mapped = true;
3321         userptr->dir = dir;
3322
3323 already_pinned:
3324         parser->patched_cb_size +=
3325                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3326
3327         return 0;
3328
3329 unpin_memory:
3330         list_del(&userptr->job_node);
3331         hl_unpin_host_memory(hdev, userptr);
3332 free_userptr:
3333         kfree(userptr);
3334         return rc;
3335 }
3336
3337 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3338                                 struct hl_cs_parser *parser,
3339                                 struct packet_lin_dma *user_dma_pkt)
3340 {
3341         u64 device_memory_addr, addr;
3342         enum dma_data_direction dir;
3343         enum goya_dma_direction user_dir;
3344         bool sram_addr = true;
3345         bool skip_host_mem_pin = false;
3346         bool user_memset;
3347         u32 ctl;
3348         int rc = 0;
3349
3350         ctl = le32_to_cpu(user_dma_pkt->ctl);
3351
3352         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3353                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3354
3355         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3356                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3357
3358         switch (user_dir) {
3359         case DMA_HOST_TO_DRAM:
3360                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3361                 dir = DMA_TO_DEVICE;
3362                 sram_addr = false;
3363                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3364                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3365                 if (user_memset)
3366                         skip_host_mem_pin = true;
3367                 break;
3368
3369         case DMA_DRAM_TO_HOST:
3370                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3371                 dir = DMA_FROM_DEVICE;
3372                 sram_addr = false;
3373                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3374                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3375                 break;
3376
3377         case DMA_HOST_TO_SRAM:
3378                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3379                 dir = DMA_TO_DEVICE;
3380                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3381                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3382                 if (user_memset)
3383                         skip_host_mem_pin = true;
3384                 break;
3385
3386         case DMA_SRAM_TO_HOST:
3387                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3388                 dir = DMA_FROM_DEVICE;
3389                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3390                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3391                 break;
3392         default:
3393                 dev_err(hdev->dev, "DMA direction is undefined\n");
3394                 return -EFAULT;
3395         }
3396
3397         if (sram_addr) {
3398                 if (!hl_mem_area_inside_range(device_memory_addr,
3399                                 le32_to_cpu(user_dma_pkt->tsize),
3400                                 hdev->asic_prop.sram_user_base_address,
3401                                 hdev->asic_prop.sram_end_address)) {
3402
3403                         dev_err(hdev->dev,
3404                                 "SRAM address 0x%llx + 0x%x is invalid\n",
3405                                 device_memory_addr,
3406                                 user_dma_pkt->tsize);
3407                         return -EFAULT;
3408                 }
3409         } else {
3410                 if (!hl_mem_area_inside_range(device_memory_addr,
3411                                 le32_to_cpu(user_dma_pkt->tsize),
3412                                 hdev->asic_prop.dram_user_base_address,
3413                                 hdev->asic_prop.dram_end_address)) {
3414
3415                         dev_err(hdev->dev,
3416                                 "DRAM address 0x%llx + 0x%x is invalid\n",
3417                                 device_memory_addr,
3418                                 user_dma_pkt->tsize);
3419                         return -EFAULT;
3420                 }
3421         }
3422
3423         if (skip_host_mem_pin)
3424                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3425         else {
3426                 if ((dir == DMA_TO_DEVICE) &&
3427                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3428                         dev_err(hdev->dev,
3429                                 "Can't DMA from host on queue other then 1\n");
3430                         return -EFAULT;
3431                 }
3432
3433                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3434                                                 addr, dir);
3435         }
3436
3437         return rc;
3438 }
3439
3440 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3441                                 struct hl_cs_parser *parser,
3442                                 struct packet_lin_dma *user_dma_pkt)
3443 {
3444         u64 sram_memory_addr, dram_memory_addr;
3445         enum goya_dma_direction user_dir;
3446         u32 ctl;
3447
3448         ctl = le32_to_cpu(user_dma_pkt->ctl);
3449         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3450                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3451
3452         if (user_dir == DMA_DRAM_TO_SRAM) {
3453                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3454                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3455                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3456         } else {
3457                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3458                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3459                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3460         }
3461
3462         if (!hl_mem_area_inside_range(sram_memory_addr,
3463                                 le32_to_cpu(user_dma_pkt->tsize),
3464                                 hdev->asic_prop.sram_user_base_address,
3465                                 hdev->asic_prop.sram_end_address)) {
3466                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3467                         sram_memory_addr, user_dma_pkt->tsize);
3468                 return -EFAULT;
3469         }
3470
3471         if (!hl_mem_area_inside_range(dram_memory_addr,
3472                                 le32_to_cpu(user_dma_pkt->tsize),
3473                                 hdev->asic_prop.dram_user_base_address,
3474                                 hdev->asic_prop.dram_end_address)) {
3475                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3476                         dram_memory_addr, user_dma_pkt->tsize);
3477                 return -EFAULT;
3478         }
3479
3480         parser->patched_cb_size += sizeof(*user_dma_pkt);
3481
3482         return 0;
3483 }
3484
3485 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3486                                 struct hl_cs_parser *parser,
3487                                 struct packet_lin_dma *user_dma_pkt)
3488 {
3489         enum goya_dma_direction user_dir;
3490         u32 ctl;
3491         int rc;
3492
3493         dev_dbg(hdev->dev, "DMA packet details:\n");
3494         dev_dbg(hdev->dev, "source == 0x%llx\n",
3495                 le64_to_cpu(user_dma_pkt->src_addr));
3496         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3497                 le64_to_cpu(user_dma_pkt->dst_addr));
3498         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3499
3500         ctl = le32_to_cpu(user_dma_pkt->ctl);
3501         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3502                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3503
3504         /*
3505          * Special handling for DMA with size 0. The H/W has a bug where
3506          * this can cause the QMAN DMA to get stuck, so block it here.
3507          */
3508         if (user_dma_pkt->tsize == 0) {
3509                 dev_err(hdev->dev,
3510                         "Got DMA with size 0, might reset the device\n");
3511                 return -EINVAL;
3512         }
3513
3514         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3515                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3516         else
3517                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3518
3519         return rc;
3520 }
3521
3522 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3523                                 struct hl_cs_parser *parser,
3524                                 struct packet_lin_dma *user_dma_pkt)
3525 {
3526         dev_dbg(hdev->dev, "DMA packet details:\n");
3527         dev_dbg(hdev->dev, "source == 0x%llx\n",
3528                 le64_to_cpu(user_dma_pkt->src_addr));
3529         dev_dbg(hdev->dev, "destination == 0x%llx\n",
3530                 le64_to_cpu(user_dma_pkt->dst_addr));
3531         dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3532
3533         /*
3534          * WA for HW-23.
3535          * We can't allow user to read from Host using QMANs other than 1.
3536          * PMMU and HPMMU addresses are equal, check only one of them.
3537          */
3538         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3539                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3540                                 le32_to_cpu(user_dma_pkt->tsize),
3541                                 hdev->asic_prop.pmmu.start_addr,
3542                                 hdev->asic_prop.pmmu.end_addr)) {
3543                 dev_err(hdev->dev,
3544                         "Can't DMA from host on queue other then 1\n");
3545                 return -EFAULT;
3546         }
3547
3548         if (user_dma_pkt->tsize == 0) {
3549                 dev_err(hdev->dev,
3550                         "Got DMA with size 0, might reset the device\n");
3551                 return -EINVAL;
3552         }
3553
3554         parser->patched_cb_size += sizeof(*user_dma_pkt);
3555
3556         return 0;
3557 }
3558
3559 static int goya_validate_wreg32(struct hl_device *hdev,
3560                                 struct hl_cs_parser *parser,
3561                                 struct packet_wreg32 *wreg_pkt)
3562 {
3563         struct goya_device *goya = hdev->asic_specific;
3564         u32 sob_start_addr, sob_end_addr;
3565         u16 reg_offset;
3566
3567         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3568                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3569
3570         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3571         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3572         dev_dbg(hdev->dev, "value      == 0x%x\n",
3573                 le32_to_cpu(wreg_pkt->value));
3574
3575         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3576                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3577                         reg_offset);
3578                 return -EPERM;
3579         }
3580
3581         /*
3582          * With MMU, DMA channels are not secured, so it doesn't matter where
3583          * the WR COMP will be written to because it will go out with
3584          * non-secured property
3585          */
3586         if (goya->hw_cap_initialized & HW_CAP_MMU)
3587                 return 0;
3588
3589         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3590         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3591
3592         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3593                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3594
3595                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3596                         wreg_pkt->value);
3597                 return -EPERM;
3598         }
3599
3600         return 0;
3601 }
3602
3603 static int goya_validate_cb(struct hl_device *hdev,
3604                         struct hl_cs_parser *parser, bool is_mmu)
3605 {
3606         u32 cb_parsed_length = 0;
3607         int rc = 0;
3608
3609         parser->patched_cb_size = 0;
3610
3611         /* cb_user_size is more than 0 so loop will always be executed */
3612         while (cb_parsed_length < parser->user_cb_size) {
3613                 enum packet_id pkt_id;
3614                 u16 pkt_size;
3615                 struct goya_packet *user_pkt;
3616
3617                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3618
3619                 pkt_id = (enum packet_id) (
3620                                 (le64_to_cpu(user_pkt->header) &
3621                                 PACKET_HEADER_PACKET_ID_MASK) >>
3622                                         PACKET_HEADER_PACKET_ID_SHIFT);
3623
3624                 if (!validate_packet_id(pkt_id)) {
3625                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3626                         rc = -EINVAL;
3627                         break;
3628                 }
3629
3630                 pkt_size = goya_packet_sizes[pkt_id];
3631                 cb_parsed_length += pkt_size;
3632                 if (cb_parsed_length > parser->user_cb_size) {
3633                         dev_err(hdev->dev,
3634                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3635                         rc = -EINVAL;
3636                         break;
3637                 }
3638
3639                 switch (pkt_id) {
3640                 case PACKET_WREG_32:
3641                         /*
3642                          * Although it is validated after copy in patch_cb(),
3643                          * need to validate here as well because patch_cb() is
3644                          * not called in MMU path while this function is called
3645                          */
3646                         rc = goya_validate_wreg32(hdev,
3647                                 parser, (struct packet_wreg32 *) user_pkt);
3648                         parser->patched_cb_size += pkt_size;
3649                         break;
3650
3651                 case PACKET_WREG_BULK:
3652                         dev_err(hdev->dev,
3653                                 "User not allowed to use WREG_BULK\n");
3654                         rc = -EPERM;
3655                         break;
3656
3657                 case PACKET_MSG_PROT:
3658                         dev_err(hdev->dev,
3659                                 "User not allowed to use MSG_PROT\n");
3660                         rc = -EPERM;
3661                         break;
3662
3663                 case PACKET_CP_DMA:
3664                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3665                         rc = -EPERM;
3666                         break;
3667
3668                 case PACKET_STOP:
3669                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3670                         rc = -EPERM;
3671                         break;
3672
3673                 case PACKET_LIN_DMA:
3674                         if (is_mmu)
3675                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3676                                         (struct packet_lin_dma *) user_pkt);
3677                         else
3678                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3679                                         (struct packet_lin_dma *) user_pkt);
3680                         break;
3681
3682                 case PACKET_MSG_LONG:
3683                 case PACKET_MSG_SHORT:
3684                 case PACKET_FENCE:
3685                 case PACKET_NOP:
3686                         parser->patched_cb_size += pkt_size;
3687                         break;
3688
3689                 default:
3690                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3691                                 pkt_id);
3692                         rc = -EINVAL;
3693                         break;
3694                 }
3695
3696                 if (rc)
3697                         break;
3698         }
3699
3700         /*
3701          * The new CB should have space at the end for two MSG_PROT packets:
3702          * 1. A packet that will act as a completion packet
3703          * 2. A packet that will generate MSI-X interrupt
3704          */
3705         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3706
3707         return rc;
3708 }
3709
3710 static int goya_patch_dma_packet(struct hl_device *hdev,
3711                                 struct hl_cs_parser *parser,
3712                                 struct packet_lin_dma *user_dma_pkt,
3713                                 struct packet_lin_dma *new_dma_pkt,
3714                                 u32 *new_dma_pkt_size)
3715 {
3716         struct hl_userptr *userptr;
3717         struct scatterlist *sg, *sg_next_iter;
3718         u32 count, dma_desc_cnt;
3719         u64 len, len_next;
3720         dma_addr_t dma_addr, dma_addr_next;
3721         enum goya_dma_direction user_dir;
3722         u64 device_memory_addr, addr;
3723         enum dma_data_direction dir;
3724         struct sg_table *sgt;
3725         bool skip_host_mem_pin = false;
3726         bool user_memset;
3727         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3728
3729         ctl = le32_to_cpu(user_dma_pkt->ctl);
3730
3731         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3732                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3733
3734         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3735                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3736
3737         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3738                         (user_dma_pkt->tsize == 0)) {
3739                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3740                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3741                 return 0;
3742         }
3743
3744         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3745                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3746                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3747                 dir = DMA_TO_DEVICE;
3748                 if (user_memset)
3749                         skip_host_mem_pin = true;
3750         } else {
3751                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3752                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3753                 dir = DMA_FROM_DEVICE;
3754         }
3755
3756         if ((!skip_host_mem_pin) &&
3757                 (hl_userptr_is_pinned(hdev, addr,
3758                         le32_to_cpu(user_dma_pkt->tsize),
3759                         parser->job_userptr_list, &userptr) == false)) {
3760                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3761                                 addr, user_dma_pkt->tsize);
3762                 return -EFAULT;
3763         }
3764
3765         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3766                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3767                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3768                 return 0;
3769         }
3770
3771         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3772
3773         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3774
3775         sgt = userptr->sgt;
3776         dma_desc_cnt = 0;
3777
3778         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3779                 len = sg_dma_len(sg);
3780                 dma_addr = sg_dma_address(sg);
3781
3782                 if (len == 0)
3783                         break;
3784
3785                 while ((count + 1) < sgt->nents) {
3786                         sg_next_iter = sg_next(sg);
3787                         len_next = sg_dma_len(sg_next_iter);
3788                         dma_addr_next = sg_dma_address(sg_next_iter);
3789
3790                         if (len_next == 0)
3791                                 break;
3792
3793                         if ((dma_addr + len == dma_addr_next) &&
3794                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3795                                 len += len_next;
3796                                 count++;
3797                                 sg = sg_next_iter;
3798                         } else {
3799                                 break;
3800                         }
3801                 }
3802
3803                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3804                 if (likely(dma_desc_cnt))
3805                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3806                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3807                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3808                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3809                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3810
3811                 if (dir == DMA_TO_DEVICE) {
3812                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3813                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3814                 } else {
3815                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3816                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3817                 }
3818
3819                 if (!user_memset)
3820                         device_memory_addr += len;
3821                 dma_desc_cnt++;
3822                 new_dma_pkt++;
3823         }
3824
3825         if (!dma_desc_cnt) {
3826                 dev_err(hdev->dev,
3827                         "Error of 0 SG entries when patching DMA packet\n");
3828                 return -EFAULT;
3829         }
3830
3831         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3832         new_dma_pkt--;
3833         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3834
3835         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3836
3837         return 0;
3838 }
3839
3840 static int goya_patch_cb(struct hl_device *hdev,
3841                                 struct hl_cs_parser *parser)
3842 {
3843         u32 cb_parsed_length = 0;
3844         u32 cb_patched_cur_length = 0;
3845         int rc = 0;
3846
3847         /* cb_user_size is more than 0 so loop will always be executed */
3848         while (cb_parsed_length < parser->user_cb_size) {
3849                 enum packet_id pkt_id;
3850                 u16 pkt_size;
3851                 u32 new_pkt_size = 0;
3852                 struct goya_packet *user_pkt, *kernel_pkt;
3853
3854                 user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3855                 kernel_pkt = parser->patched_cb->kernel_address +
3856                                         cb_patched_cur_length;
3857
3858                 pkt_id = (enum packet_id) (
3859                                 (le64_to_cpu(user_pkt->header) &
3860                                 PACKET_HEADER_PACKET_ID_MASK) >>
3861                                         PACKET_HEADER_PACKET_ID_SHIFT);
3862
3863                 if (!validate_packet_id(pkt_id)) {
3864                         dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3865                         rc = -EINVAL;
3866                         break;
3867                 }
3868
3869                 pkt_size = goya_packet_sizes[pkt_id];
3870                 cb_parsed_length += pkt_size;
3871                 if (cb_parsed_length > parser->user_cb_size) {
3872                         dev_err(hdev->dev,
3873                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3874                         rc = -EINVAL;
3875                         break;
3876                 }
3877
3878                 switch (pkt_id) {
3879                 case PACKET_LIN_DMA:
3880                         rc = goya_patch_dma_packet(hdev, parser,
3881                                         (struct packet_lin_dma *) user_pkt,
3882                                         (struct packet_lin_dma *) kernel_pkt,
3883                                         &new_pkt_size);
3884                         cb_patched_cur_length += new_pkt_size;
3885                         break;
3886
3887                 case PACKET_WREG_32:
3888                         memcpy(kernel_pkt, user_pkt, pkt_size);
3889                         cb_patched_cur_length += pkt_size;
3890                         rc = goya_validate_wreg32(hdev, parser,
3891                                         (struct packet_wreg32 *) kernel_pkt);
3892                         break;
3893
3894                 case PACKET_WREG_BULK:
3895                         dev_err(hdev->dev,
3896                                 "User not allowed to use WREG_BULK\n");
3897                         rc = -EPERM;
3898                         break;
3899
3900                 case PACKET_MSG_PROT:
3901                         dev_err(hdev->dev,
3902                                 "User not allowed to use MSG_PROT\n");
3903                         rc = -EPERM;
3904                         break;
3905
3906                 case PACKET_CP_DMA:
3907                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3908                         rc = -EPERM;
3909                         break;
3910
3911                 case PACKET_STOP:
3912                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3913                         rc = -EPERM;
3914                         break;
3915
3916                 case PACKET_MSG_LONG:
3917                 case PACKET_MSG_SHORT:
3918                 case PACKET_FENCE:
3919                 case PACKET_NOP:
3920                         memcpy(kernel_pkt, user_pkt, pkt_size);
3921                         cb_patched_cur_length += pkt_size;
3922                         break;
3923
3924                 default:
3925                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3926                                 pkt_id);
3927                         rc = -EINVAL;
3928                         break;
3929                 }
3930
3931                 if (rc)
3932                         break;
3933         }
3934
3935         return rc;
3936 }
3937
3938 static int goya_parse_cb_mmu(struct hl_device *hdev,
3939                 struct hl_cs_parser *parser)
3940 {
3941         u64 patched_cb_handle;
3942         u32 patched_cb_size;
3943         struct hl_cb *user_cb;
3944         int rc;
3945
3946         /*
3947          * The new CB should have space at the end for two MSG_PROT pkt:
3948          * 1. A packet that will act as a completion packet
3949          * 2. A packet that will generate MSI-X interrupt
3950          */
3951         parser->patched_cb_size = parser->user_cb_size +
3952                         sizeof(struct packet_msg_prot) * 2;
3953
3954         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
3955                                 parser->patched_cb_size, false, false,
3956                                 &patched_cb_handle);
3957
3958         if (rc) {
3959                 dev_err(hdev->dev,
3960                         "Failed to allocate patched CB for DMA CS %d\n",
3961                         rc);
3962                 return rc;
3963         }
3964
3965         patched_cb_handle >>= PAGE_SHIFT;
3966         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3967                                 (u32) patched_cb_handle);
3968         /* hl_cb_get should never fail here */
3969         if (!parser->patched_cb) {
3970                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
3971                         (u32) patched_cb_handle);
3972                 rc = -EFAULT;
3973                 goto out;
3974         }
3975
3976         /*
3977          * The check that parser->user_cb_size <= parser->user_cb->size was done
3978          * in validate_queue_index().
3979          */
3980         memcpy(parser->patched_cb->kernel_address,
3981                 parser->user_cb->kernel_address,
3982                 parser->user_cb_size);
3983
3984         patched_cb_size = parser->patched_cb_size;
3985
3986         /* validate patched CB instead of user CB */
3987         user_cb = parser->user_cb;
3988         parser->user_cb = parser->patched_cb;
3989         rc = goya_validate_cb(hdev, parser, true);
3990         parser->user_cb = user_cb;
3991
3992         if (rc) {
3993                 hl_cb_put(parser->patched_cb);
3994                 goto out;
3995         }
3996
3997         if (patched_cb_size != parser->patched_cb_size) {
3998                 dev_err(hdev->dev, "user CB size mismatch\n");
3999                 hl_cb_put(parser->patched_cb);
4000                 rc = -EINVAL;
4001                 goto out;
4002         }
4003
4004 out:
4005         /*
4006          * Always call cb destroy here because we still have 1 reference
4007          * to it by calling cb_get earlier. After the job will be completed,
4008          * cb_put will release it, but here we want to remove it from the
4009          * idr
4010          */
4011         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4012                                         patched_cb_handle << PAGE_SHIFT);
4013
4014         return rc;
4015 }
4016
4017 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4018                                 struct hl_cs_parser *parser)
4019 {
4020         u64 patched_cb_handle;
4021         int rc;
4022
4023         rc = goya_validate_cb(hdev, parser, false);
4024
4025         if (rc)
4026                 goto free_userptr;
4027
4028         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, hdev->kernel_ctx,
4029                                 parser->patched_cb_size, false, false,
4030                                 &patched_cb_handle);
4031         if (rc) {
4032                 dev_err(hdev->dev,
4033                         "Failed to allocate patched CB for DMA CS %d\n", rc);
4034                 goto free_userptr;
4035         }
4036
4037         patched_cb_handle >>= PAGE_SHIFT;
4038         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
4039                                 (u32) patched_cb_handle);
4040         /* hl_cb_get should never fail here */
4041         if (!parser->patched_cb) {
4042                 dev_crit(hdev->dev, "DMA CB handle invalid 0x%x\n",
4043                         (u32) patched_cb_handle);
4044                 rc = -EFAULT;
4045                 goto out;
4046         }
4047
4048         rc = goya_patch_cb(hdev, parser);
4049
4050         if (rc)
4051                 hl_cb_put(parser->patched_cb);
4052
4053 out:
4054         /*
4055          * Always call cb destroy here because we still have 1 reference
4056          * to it by calling cb_get earlier. After the job will be completed,
4057          * cb_put will release it, but here we want to remove it from the
4058          * idr
4059          */
4060         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
4061                                 patched_cb_handle << PAGE_SHIFT);
4062
4063 free_userptr:
4064         if (rc)
4065                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
4066         return rc;
4067 }
4068
4069 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4070                                         struct hl_cs_parser *parser)
4071 {
4072         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4073         struct goya_device *goya = hdev->asic_specific;
4074
4075         if (goya->hw_cap_initialized & HW_CAP_MMU)
4076                 return 0;
4077
4078         /* For internal queue jobs, just check if CB address is valid */
4079         if (hl_mem_area_inside_range(
4080                         (u64) (uintptr_t) parser->user_cb,
4081                         parser->user_cb_size,
4082                         asic_prop->sram_user_base_address,
4083                         asic_prop->sram_end_address))
4084                 return 0;
4085
4086         if (hl_mem_area_inside_range(
4087                         (u64) (uintptr_t) parser->user_cb,
4088                         parser->user_cb_size,
4089                         asic_prop->dram_user_base_address,
4090                         asic_prop->dram_end_address))
4091                 return 0;
4092
4093         dev_err(hdev->dev,
4094                 "Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4095                 parser->user_cb, parser->user_cb_size);
4096
4097         return -EFAULT;
4098 }
4099
4100 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4101 {
4102         struct goya_device *goya = hdev->asic_specific;
4103
4104         if (parser->queue_type == QUEUE_TYPE_INT)
4105                 return goya_parse_cb_no_ext_queue(hdev, parser);
4106
4107         if (goya->hw_cap_initialized & HW_CAP_MMU)
4108                 return goya_parse_cb_mmu(hdev, parser);
4109         else
4110                 return goya_parse_cb_no_mmu(hdev, parser);
4111 }
4112
4113 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4114                                 u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec,
4115                                 bool eb)
4116 {
4117         struct packet_msg_prot *cq_pkt;
4118         u32 tmp;
4119
4120         cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4121
4122         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4123                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
4124                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4125         cq_pkt->ctl = cpu_to_le32(tmp);
4126         cq_pkt->value = cpu_to_le32(cq_val);
4127         cq_pkt->addr = cpu_to_le64(cq_addr);
4128
4129         cq_pkt++;
4130
4131         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4132                         (1 << GOYA_PKT_CTL_MB_SHIFT);
4133         cq_pkt->ctl = cpu_to_le32(tmp);
4134         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4135         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4136 }
4137
4138 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4139 {
4140         WREG32(mmCPU_EQ_CI, val);
4141 }
4142
4143 void goya_restore_phase_topology(struct hl_device *hdev)
4144 {
4145
4146 }
4147
4148 static void goya_clear_sm_regs(struct hl_device *hdev)
4149 {
4150         int i, num_of_sob_in_longs, num_of_mon_in_longs;
4151
4152         num_of_sob_in_longs =
4153                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4154
4155         num_of_mon_in_longs =
4156                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4157
4158         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4159                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4160
4161         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4162                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4163
4164         /* Flush all WREG to prevent race */
4165         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4166 }
4167
4168 /*
4169  * goya_debugfs_read32 - read a 32bit value from a given device or a host mapped
4170  *                       address.
4171  *
4172  * @hdev:       pointer to hl_device structure
4173  * @addr:       device or host mapped address
4174  * @val:        returned value
4175  *
4176  * In case of DDR address that is not mapped into the default aperture that
4177  * the DDR bar exposes, the function will configure the iATU so that the DDR
4178  * bar will be positioned at a base address that allows reading from the
4179  * required address. Configuring the iATU during normal operation can
4180  * lead to undefined behavior and therefore, should be done with extreme care
4181  *
4182  */
4183 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr,
4184                         bool user_address, u32 *val)
4185 {
4186         struct asic_fixed_properties *prop = &hdev->asic_prop;
4187         u64 ddr_bar_addr, host_phys_end;
4188         int rc = 0;
4189
4190         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4191
4192         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4193                 *val = RREG32(addr - CFG_BASE);
4194
4195         } else if ((addr >= SRAM_BASE_ADDR) &&
4196                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4197
4198                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4199                                 (addr - SRAM_BASE_ADDR));
4200
4201         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4202
4203                 u64 bar_base_addr = DRAM_PHYS_BASE +
4204                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4205
4206                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4207                 if (ddr_bar_addr != U64_MAX) {
4208                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
4209                                                 (addr - bar_base_addr));
4210
4211                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4212                                                         ddr_bar_addr);
4213                 }
4214                 if (ddr_bar_addr == U64_MAX)
4215                         rc = -EIO;
4216
4217         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4218                         user_address && !iommu_present(&pci_bus_type)) {
4219                 *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE);
4220
4221         } else {
4222                 rc = -EFAULT;
4223         }
4224
4225         return rc;
4226 }
4227
4228 /*
4229  * goya_debugfs_write32 - write a 32bit value to a given device or a host mapped
4230  *                        address.
4231  *
4232  * @hdev:       pointer to hl_device structure
4233  * @addr:       device or host mapped address
4234  * @val:        returned value
4235  *
4236  * In case of DDR address that is not mapped into the default aperture that
4237  * the DDR bar exposes, the function will configure the iATU so that the DDR
4238  * bar will be positioned at a base address that allows writing to the
4239  * required address. Configuring the iATU during normal operation can
4240  * lead to undefined behavior and therefore, should be done with extreme care
4241  *
4242  */
4243 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr,
4244                         bool user_address, u32 val)
4245 {
4246         struct asic_fixed_properties *prop = &hdev->asic_prop;
4247         u64 ddr_bar_addr, host_phys_end;
4248         int rc = 0;
4249
4250         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4251
4252         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4253                 WREG32(addr - CFG_BASE, val);
4254
4255         } else if ((addr >= SRAM_BASE_ADDR) &&
4256                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4257
4258                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4259                                         (addr - SRAM_BASE_ADDR));
4260
4261         } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) {
4262
4263                 u64 bar_base_addr = DRAM_PHYS_BASE +
4264                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4265
4266                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4267                 if (ddr_bar_addr != U64_MAX) {
4268                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4269                                                 (addr - bar_base_addr));
4270
4271                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4272                                                         ddr_bar_addr);
4273                 }
4274                 if (ddr_bar_addr == U64_MAX)
4275                         rc = -EIO;
4276
4277         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4278                         user_address && !iommu_present(&pci_bus_type)) {
4279                 *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4280
4281         } else {
4282                 rc = -EFAULT;
4283         }
4284
4285         return rc;
4286 }
4287
4288 static int goya_debugfs_read64(struct hl_device *hdev, u64 addr,
4289                         bool user_address, u64 *val)
4290 {
4291         struct asic_fixed_properties *prop = &hdev->asic_prop;
4292         u64 ddr_bar_addr, host_phys_end;
4293         int rc = 0;
4294
4295         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4296
4297         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4298                 u32 val_l = RREG32(addr - CFG_BASE);
4299                 u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
4300
4301                 *val = (((u64) val_h) << 32) | val_l;
4302
4303         } else if ((addr >= SRAM_BASE_ADDR) &&
4304                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4305
4306                 *val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4307                                 (addr - SRAM_BASE_ADDR));
4308
4309         } else if (addr <=
4310                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4311
4312                 u64 bar_base_addr = DRAM_PHYS_BASE +
4313                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4314
4315                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4316                 if (ddr_bar_addr != U64_MAX) {
4317                         *val = readq(hdev->pcie_bar[DDR_BAR_ID] +
4318                                                 (addr - bar_base_addr));
4319
4320                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4321                                                         ddr_bar_addr);
4322                 }
4323                 if (ddr_bar_addr == U64_MAX)
4324                         rc = -EIO;
4325
4326         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4327                         user_address && !iommu_present(&pci_bus_type)) {
4328                 *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
4329
4330         } else {
4331                 rc = -EFAULT;
4332         }
4333
4334         return rc;
4335 }
4336
4337 static int goya_debugfs_write64(struct hl_device *hdev, u64 addr,
4338                                 bool user_address, u64 val)
4339 {
4340         struct asic_fixed_properties *prop = &hdev->asic_prop;
4341         u64 ddr_bar_addr, host_phys_end;
4342         int rc = 0;
4343
4344         host_phys_end = HOST_PHYS_BASE + HOST_PHYS_SIZE;
4345
4346         if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
4347                 WREG32(addr - CFG_BASE, lower_32_bits(val));
4348                 WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
4349
4350         } else if ((addr >= SRAM_BASE_ADDR) &&
4351                         (addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
4352
4353                 writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4354                                         (addr - SRAM_BASE_ADDR));
4355
4356         } else if (addr <=
4357                    DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) {
4358
4359                 u64 bar_base_addr = DRAM_PHYS_BASE +
4360                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4361
4362                 ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
4363                 if (ddr_bar_addr != U64_MAX) {
4364                         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4365                                                 (addr - bar_base_addr));
4366
4367                         ddr_bar_addr = goya_set_ddr_bar_base(hdev,
4368                                                         ddr_bar_addr);
4369                 }
4370                 if (ddr_bar_addr == U64_MAX)
4371                         rc = -EIO;
4372
4373         } else if (addr >= HOST_PHYS_BASE && addr < host_phys_end &&
4374                         user_address && !iommu_present(&pci_bus_type)) {
4375                 *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
4376
4377         } else {
4378                 rc = -EFAULT;
4379         }
4380
4381         return rc;
4382 }
4383
4384 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size,
4385                                 void *blob_addr)
4386 {
4387         dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4388         return -EPERM;
4389 }
4390
4391 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4392 {
4393         struct goya_device *goya = hdev->asic_specific;
4394
4395         if (hdev->hard_reset_pending)
4396                 return U64_MAX;
4397
4398         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4399                         (addr - goya->ddr_bar_cur_addr));
4400 }
4401
4402 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4403 {
4404         struct goya_device *goya = hdev->asic_specific;
4405
4406         if (hdev->hard_reset_pending)
4407                 return;
4408
4409         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4410                         (addr - goya->ddr_bar_cur_addr));
4411 }
4412
4413 static const char *_goya_get_event_desc(u16 event_type)
4414 {
4415         switch (event_type) {
4416         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4417                 return "PCIe_if";
4418         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4419         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4420         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4421         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4422         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4423         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4424         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4425         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4426                 return "TPC%d_ecc";
4427         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4428                 return "MME_ecc";
4429         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4430                 return "MME_ecc_ext";
4431         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4432                 return "MMU_ecc";
4433         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4434                 return "DMA_macro";
4435         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4436                 return "DMA_ecc";
4437         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4438                 return "CPU_if_ecc";
4439         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4440                 return "PSOC_mem";
4441         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4442                 return "PSOC_coresight";
4443         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4444                 return "SRAM%d";
4445         case GOYA_ASYNC_EVENT_ID_GIC500:
4446                 return "GIC500";
4447         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4448                 return "PLL%d";
4449         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4450                 return "AXI_ecc";
4451         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4452                 return "L2_ram_ecc";
4453         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4454                 return "PSOC_gpio_05_sw_reset";
4455         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4456                 return "PSOC_gpio_10_vrhot_icrit";
4457         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4458                 return "PCIe_dec";
4459         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4460         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4461         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4462         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4463         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4464         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4465         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4466         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4467                 return "TPC%d_dec";
4468         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4469                 return "MME_wacs";
4470         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4471                 return "MME_wacsd";
4472         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4473                 return "CPU_axi_splitter";
4474         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4475                 return "PSOC_axi_dec";
4476         case GOYA_ASYNC_EVENT_ID_PSOC:
4477                 return "PSOC";
4478         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4479         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4480         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4481         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4482         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4483         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4484         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4485         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4486                 return "TPC%d_krn_err";
4487         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4488                 return "TPC%d_cq";
4489         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4490                 return "TPC%d_qm";
4491         case GOYA_ASYNC_EVENT_ID_MME_QM:
4492                 return "MME_qm";
4493         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4494                 return "MME_cq";
4495         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4496                 return "DMA%d_qm";
4497         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4498                 return "DMA%d_ch";
4499         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4500         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4501         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4502         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4503         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4504         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4505         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4506         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4507                 return "TPC%d_bmon_spmu";
4508         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4509                 return "DMA_bm_ch%d";
4510         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4511                 return "POWER_ENV_S";
4512         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4513                 return "POWER_ENV_E";
4514         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4515                 return "THERMAL_ENV_S";
4516         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4517                 return "THERMAL_ENV_E";
4518         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4519                 return "QUEUE_OUT_OF_SYNC";
4520         default:
4521                 return "N/A";
4522         }
4523 }
4524
4525 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4526 {
4527         u8 index;
4528
4529         switch (event_type) {
4530         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4531         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4532         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4533         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4534         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4535         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4536         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4537         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4538                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4539                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4540                 break;
4541         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4542                 index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4543                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4544                 break;
4545         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4546                 index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4547                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4548                 break;
4549         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4550         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4551         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4552         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4553         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4554         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4555         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4556         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4557                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4558                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4559                 break;
4560         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4561         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4562         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4563         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4564         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4565         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4566         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4567         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4568                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4569                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4570                 break;
4571         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4572                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4573                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4574                 break;
4575         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4576                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4577                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4578                 break;
4579         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4580                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4581                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4582                 break;
4583         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4584                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4585                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4586                 break;
4587         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4588         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4589         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4590         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4591         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4592         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4593         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4594         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4595                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4596                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4597                 break;
4598         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4599                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4600                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4601                 break;
4602         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4603                 snprintf(desc, size, _goya_get_event_desc(event_type));
4604                 break;
4605         default:
4606                 snprintf(desc, size, _goya_get_event_desc(event_type));
4607                 break;
4608         }
4609 }
4610
4611 static void goya_print_razwi_info(struct hl_device *hdev)
4612 {
4613         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4614                 dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4615                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4616         }
4617
4618         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4619                 dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4620                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4621         }
4622
4623         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4624                 dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4625                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4626         }
4627
4628         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4629                 dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4630                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4631         }
4632 }
4633
4634 static void goya_print_mmu_error_info(struct hl_device *hdev)
4635 {
4636         struct goya_device *goya = hdev->asic_specific;
4637         u64 addr;
4638         u32 val;
4639
4640         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4641                 return;
4642
4643         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4644         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4645                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4646                 addr <<= 32;
4647                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4648
4649                 dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4650                                         addr);
4651
4652                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4653         }
4654 }
4655
4656 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4657                                         struct cpucp_pkt_sync_err *sync_err)
4658 {
4659         struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4660
4661         dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%u\n",
4662                         sync_err->pi, sync_err->ci, q->pi, atomic_read(&q->ci));
4663 }
4664
4665 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4666                                 bool razwi)
4667 {
4668         char desc[20] = "";
4669
4670         goya_get_event_desc(event_type, desc, sizeof(desc));
4671         dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4672                 event_type, desc);
4673
4674         if (razwi) {
4675                 goya_print_razwi_info(hdev);
4676                 goya_print_mmu_error_info(hdev);
4677         }
4678 }
4679
4680 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4681                 size_t irq_arr_size)
4682 {
4683         struct cpucp_unmask_irq_arr_packet *pkt;
4684         size_t total_pkt_size;
4685         u64 result;
4686         int rc;
4687         int irq_num_entries, irq_arr_index;
4688         __le32 *goya_irq_arr;
4689
4690         total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4691                         irq_arr_size;
4692
4693         /* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4694         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4695
4696         /* total_pkt_size is casted to u16 later on */
4697         if (total_pkt_size > USHRT_MAX) {
4698                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4699                 return -EINVAL;
4700         }
4701
4702         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4703         if (!pkt)
4704                 return -ENOMEM;
4705
4706         irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4707         pkt->length = cpu_to_le32(irq_num_entries);
4708
4709         /* We must perform any necessary endianness conversation on the irq
4710          * array being passed to the goya hardware
4711          */
4712         for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4713                         irq_arr_index < irq_num_entries ; irq_arr_index++)
4714                 goya_irq_arr[irq_arr_index] =
4715                                 cpu_to_le32(irq_arr[irq_arr_index]);
4716
4717         pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4718                                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4719
4720         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4721                                                 total_pkt_size, 0, &result);
4722
4723         if (rc)
4724                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4725
4726         kfree(pkt);
4727
4728         return rc;
4729 }
4730
4731 static int goya_soft_reset_late_init(struct hl_device *hdev)
4732 {
4733         /*
4734          * Unmask all IRQs since some could have been received
4735          * during the soft reset
4736          */
4737         return goya_unmask_irq_arr(hdev, goya_all_events,
4738                                         sizeof(goya_all_events));
4739 }
4740
4741 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4742 {
4743         struct cpucp_packet pkt;
4744         u64 result;
4745         int rc;
4746
4747         memset(&pkt, 0, sizeof(pkt));
4748
4749         pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4750                                 CPUCP_PKT_CTL_OPCODE_SHIFT);
4751         pkt.value = cpu_to_le64(event_type);
4752
4753         rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4754                                                 0, &result);
4755
4756         if (rc)
4757                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4758
4759         return rc;
4760 }
4761
4762 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4763 {
4764         switch (event_type) {
4765         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4766                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_POWER;
4767                 dev_info_ratelimited(hdev->dev,
4768                         "Clock throttling due to power consumption\n");
4769                 break;
4770         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4771                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_POWER;
4772                 dev_info_ratelimited(hdev->dev,
4773                         "Power envelop is safe, back to optimal clock\n");
4774                 break;
4775         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4776                 hdev->clk_throttling_reason |= HL_CLK_THROTTLE_THERMAL;
4777                 dev_info_ratelimited(hdev->dev,
4778                         "Clock throttling due to overheating\n");
4779                 break;
4780         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4781                 hdev->clk_throttling_reason &= ~HL_CLK_THROTTLE_THERMAL;
4782                 dev_info_ratelimited(hdev->dev,
4783                         "Thermal envelop is safe, back to optimal clock\n");
4784                 break;
4785
4786         default:
4787                 dev_err(hdev->dev, "Received invalid clock change event %d\n",
4788                         event_type);
4789                 break;
4790         }
4791 }
4792
4793 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4794 {
4795         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4796         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4797                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4798         struct goya_device *goya = hdev->asic_specific;
4799
4800         if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4801                 dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4802                                 event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4803                 return;
4804         }
4805
4806         goya->events_stat[event_type]++;
4807         goya->events_stat_aggregate[event_type]++;
4808
4809         switch (event_type) {
4810         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4811         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4812         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4813         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4814         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4815         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4816         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4817         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4818         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4819         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4820         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4821         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4822         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4823         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4824         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4825         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4826         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4827         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4828         case GOYA_ASYNC_EVENT_ID_GIC500:
4829         case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4830         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4831         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4832         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4833                 goya_print_irq_info(hdev, event_type, false);
4834                 if (hdev->hard_reset_on_fw_events)
4835                         hl_device_reset(hdev, HL_RESET_HARD);
4836                 break;
4837
4838         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4839         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4840         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4841         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4842         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4843         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4844         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4845         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4846         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4847         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4848         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4849         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4850         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4851         case GOYA_ASYNC_EVENT_ID_PSOC:
4852         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4853         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4854         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4855         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4856         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4857         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4858         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4859         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4860         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4861         case GOYA_ASYNC_EVENT_ID_MME_QM:
4862         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4863         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4864         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4865                 goya_print_irq_info(hdev, event_type, true);
4866                 goya_unmask_irq(hdev, event_type);
4867                 break;
4868
4869         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4870         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4871         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4872         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4873         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4874         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4875         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4876         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4877         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4878         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4879                 goya_print_irq_info(hdev, event_type, false);
4880                 goya_unmask_irq(hdev, event_type);
4881                 break;
4882
4883         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4884         case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4885         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4886         case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4887                 goya_print_clk_change_info(hdev, event_type);
4888                 goya_unmask_irq(hdev, event_type);
4889                 break;
4890
4891         case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4892                 goya_print_irq_info(hdev, event_type, false);
4893                 goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4894                 if (hdev->hard_reset_on_fw_events)
4895                         hl_device_reset(hdev, HL_RESET_HARD);
4896                 else
4897                         hl_fw_unmask_irq(hdev, event_type);
4898                 break;
4899
4900         default:
4901                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4902                                 event_type);
4903                 break;
4904         }
4905 }
4906
4907 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4908 {
4909         struct goya_device *goya = hdev->asic_specific;
4910
4911         if (aggregate) {
4912                 *size = (u32) sizeof(goya->events_stat_aggregate);
4913                 return goya->events_stat_aggregate;
4914         }
4915
4916         *size = (u32) sizeof(goya->events_stat);
4917         return goya->events_stat;
4918 }
4919
4920 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4921                                 u64 val, bool is_dram)
4922 {
4923         struct packet_lin_dma *lin_dma_pkt;
4924         struct hl_cs_job *job;
4925         u32 cb_size, ctl;
4926         struct hl_cb *cb;
4927         int rc, lin_dma_pkts_cnt;
4928
4929         lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4930         cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4931                                                 sizeof(struct packet_msg_prot);
4932         cb = hl_cb_kernel_create(hdev, cb_size, false);
4933         if (!cb)
4934                 return -ENOMEM;
4935
4936         lin_dma_pkt = cb->kernel_address;
4937
4938         do {
4939                 memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4940
4941                 ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4942                                 (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4943                                 (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4944                                 (1 << GOYA_PKT_CTL_RB_SHIFT) |
4945                                 (1 << GOYA_PKT_CTL_MB_SHIFT));
4946                 ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4947                                 GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4948                 lin_dma_pkt->ctl = cpu_to_le32(ctl);
4949
4950                 lin_dma_pkt->src_addr = cpu_to_le64(val);
4951                 lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4952                 if (lin_dma_pkts_cnt > 1)
4953                         lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4954                 else
4955                         lin_dma_pkt->tsize = cpu_to_le32(size);
4956
4957                 size -= SZ_2G;
4958                 addr += SZ_2G;
4959                 lin_dma_pkt++;
4960         } while (--lin_dma_pkts_cnt);
4961
4962         job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4963         if (!job) {
4964                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4965                 rc = -ENOMEM;
4966                 goto release_cb;
4967         }
4968
4969         job->id = 0;
4970         job->user_cb = cb;
4971         atomic_inc(&job->user_cb->cs_cnt);
4972         job->user_cb_size = cb_size;
4973         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4974         job->patched_cb = job->user_cb;
4975         job->job_cb_size = job->user_cb_size;
4976
4977         hl_debugfs_add_job(hdev, job);
4978
4979         rc = goya_send_job_on_qman0(hdev, job);
4980
4981         hl_debugfs_remove_job(hdev, job);
4982         kfree(job);
4983         atomic_dec(&cb->cs_cnt);
4984
4985 release_cb:
4986         hl_cb_put(cb);
4987         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4988
4989         return rc;
4990 }
4991
4992 int goya_context_switch(struct hl_device *hdev, u32 asid)
4993 {
4994         struct asic_fixed_properties *prop = &hdev->asic_prop;
4995         u64 addr = prop->sram_base_address, sob_addr;
4996         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4997         u64 val = 0x7777777777777777ull;
4998         int rc, dma_id;
4999         u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
5000                                         mmDMA_CH_0_WR_COMP_ADDR_LO;
5001
5002         rc = goya_memset_device_memory(hdev, addr, size, val, false);
5003         if (rc) {
5004                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
5005                 return rc;
5006         }
5007
5008         /* we need to reset registers that the user is allowed to change */
5009         sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
5010         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
5011
5012         for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
5013                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
5014                                                         (dma_id - 1) * 4;
5015                 WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
5016                                                 lower_32_bits(sob_addr));
5017         }
5018
5019         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
5020
5021         goya_clear_sm_regs(hdev);
5022
5023         return 0;
5024 }
5025
5026 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
5027 {
5028         struct asic_fixed_properties *prop = &hdev->asic_prop;
5029         struct goya_device *goya = hdev->asic_specific;
5030         u64 addr = prop->mmu_pgt_addr;
5031         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
5032                         MMU_CACHE_MNG_SIZE;
5033
5034         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5035                 return 0;
5036
5037         return goya_memset_device_memory(hdev, addr, size, 0, true);
5038 }
5039
5040 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
5041 {
5042         struct goya_device *goya = hdev->asic_specific;
5043         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
5044         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
5045         u64 val = 0x9999999999999999ull;
5046
5047         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5048                 return 0;
5049
5050         return goya_memset_device_memory(hdev, addr, size, val, true);
5051 }
5052
5053 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
5054 {
5055         struct asic_fixed_properties *prop = &hdev->asic_prop;
5056         struct goya_device *goya = hdev->asic_specific;
5057         s64 off, cpu_off;
5058         int rc;
5059
5060         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5061                 return 0;
5062
5063         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
5064                 rc = hl_mmu_map_page(hdev->kernel_ctx,
5065                         prop->dram_base_address + off,
5066                         prop->dram_base_address + off, PAGE_SIZE_2MB,
5067                         (off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
5068                 if (rc) {
5069                         dev_err(hdev->dev, "Map failed for address 0x%llx\n",
5070                                 prop->dram_base_address + off);
5071                         goto unmap;
5072                 }
5073         }
5074
5075         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5076                 rc = hl_mmu_map_page(hdev->kernel_ctx,
5077                         VA_CPU_ACCESSIBLE_MEM_ADDR,
5078                         hdev->cpu_accessible_dma_address,
5079                         PAGE_SIZE_2MB, true);
5080
5081                 if (rc) {
5082                         dev_err(hdev->dev,
5083                                 "Map failed for CPU accessible memory\n");
5084                         off -= PAGE_SIZE_2MB;
5085                         goto unmap;
5086                 }
5087         } else {
5088                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
5089                         rc = hl_mmu_map_page(hdev->kernel_ctx,
5090                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5091                                 hdev->cpu_accessible_dma_address + cpu_off,
5092                                 PAGE_SIZE_4KB, true);
5093                         if (rc) {
5094                                 dev_err(hdev->dev,
5095                                         "Map failed for CPU accessible memory\n");
5096                                 cpu_off -= PAGE_SIZE_4KB;
5097                                 goto unmap_cpu;
5098                         }
5099                 }
5100         }
5101
5102         goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
5103         goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
5104         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
5105         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
5106
5107         /* Make sure configuration is flushed to device */
5108         RREG32(mmCPU_IF_AWUSER_OVR_EN);
5109
5110         goya->device_cpu_mmu_mappings_done = true;
5111
5112         return 0;
5113
5114 unmap_cpu:
5115         for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
5116                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5117                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5118                                 PAGE_SIZE_4KB, true))
5119                         dev_warn_ratelimited(hdev->dev,
5120                                 "failed to unmap address 0x%llx\n",
5121                                 VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5122 unmap:
5123         for (; off >= 0 ; off -= PAGE_SIZE_2MB)
5124                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5125                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5126                                 true))
5127                         dev_warn_ratelimited(hdev->dev,
5128                                 "failed to unmap address 0x%llx\n",
5129                                 prop->dram_base_address + off);
5130
5131         return rc;
5132 }
5133
5134 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
5135 {
5136         struct asic_fixed_properties *prop = &hdev->asic_prop;
5137         struct goya_device *goya = hdev->asic_specific;
5138         u32 off, cpu_off;
5139
5140         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5141                 return;
5142
5143         if (!goya->device_cpu_mmu_mappings_done)
5144                 return;
5145
5146         WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
5147         WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
5148
5149         if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
5150                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5151                                 VA_CPU_ACCESSIBLE_MEM_ADDR,
5152                                 PAGE_SIZE_2MB, true))
5153                         dev_warn(hdev->dev,
5154                                 "Failed to unmap CPU accessible memory\n");
5155         } else {
5156                 for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
5157                         if (hl_mmu_unmap_page(hdev->kernel_ctx,
5158                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
5159                                         PAGE_SIZE_4KB,
5160                                         (cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5161                                 dev_warn_ratelimited(hdev->dev,
5162                                         "failed to unmap address 0x%llx\n",
5163                                         VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5164         }
5165
5166         for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5167                 if (hl_mmu_unmap_page(hdev->kernel_ctx,
5168                                 prop->dram_base_address + off, PAGE_SIZE_2MB,
5169                                 (off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5170                         dev_warn_ratelimited(hdev->dev,
5171                                         "Failed to unmap address 0x%llx\n",
5172                                         prop->dram_base_address + off);
5173
5174         goya->device_cpu_mmu_mappings_done = false;
5175 }
5176
5177 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5178 {
5179         struct goya_device *goya = hdev->asic_specific;
5180         int i;
5181
5182         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5183                 return;
5184
5185         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5186                 dev_crit(hdev->dev, "asid %u is too big\n", asid);
5187                 return;
5188         }
5189
5190         /* zero the MMBP and ASID bits and then set the ASID */
5191         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5192                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5193 }
5194
5195 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5196                                         u32 flags)
5197 {
5198         struct goya_device *goya = hdev->asic_specific;
5199         u32 status, timeout_usec;
5200         int rc;
5201
5202         if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5203                 hdev->hard_reset_pending)
5204                 return 0;
5205
5206         /* no need in L1 only invalidation in Goya */
5207         if (!is_hard)
5208                 return 0;
5209
5210         if (hdev->pldm)
5211                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5212         else
5213                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5214
5215         /* L0 & L1 invalidation */
5216         WREG32(mmSTLB_INV_ALL_START, 1);
5217
5218         rc = hl_poll_timeout(
5219                 hdev,
5220                 mmSTLB_INV_ALL_START,
5221                 status,
5222                 !status,
5223                 1000,
5224                 timeout_usec);
5225
5226         if (rc) {
5227                 dev_err_ratelimited(hdev->dev,
5228                                         "MMU cache invalidation timeout\n");
5229                 hl_device_reset(hdev, HL_RESET_HARD);
5230         }
5231
5232         return rc;
5233 }
5234
5235 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5236                                                 bool is_hard, u32 flags,
5237                                                 u32 asid, u64 va, u64 size)
5238 {
5239         /* Treat as invalidate all because there is no range invalidation
5240          * in Goya
5241          */
5242         return hdev->asic_funcs->mmu_invalidate_cache(hdev, is_hard, flags);
5243 }
5244
5245 int goya_send_heartbeat(struct hl_device *hdev)
5246 {
5247         struct goya_device *goya = hdev->asic_specific;
5248
5249         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5250                 return 0;
5251
5252         return hl_fw_send_heartbeat(hdev);
5253 }
5254
5255 int goya_cpucp_info_get(struct hl_device *hdev)
5256 {
5257         struct goya_device *goya = hdev->asic_specific;
5258         struct asic_fixed_properties *prop = &hdev->asic_prop;
5259         u64 dram_size;
5260         int rc;
5261
5262         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5263                 return 0;
5264
5265         rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5266                                         mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5267                                         mmCPU_BOOT_ERR1);
5268         if (rc)
5269                 return rc;
5270
5271         dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5272         if (dram_size) {
5273                 if ((!is_power_of_2(dram_size)) ||
5274                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5275                         dev_err(hdev->dev,
5276                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
5277                                 dram_size);
5278                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
5279                 }
5280
5281                 prop->dram_size = dram_size;
5282                 prop->dram_end_address = prop->dram_base_address + dram_size;
5283         }
5284
5285         if (!strlen(prop->cpucp_info.card_name))
5286                 strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5287                                 CARD_NAME_MAX_LEN);
5288
5289         return 0;
5290 }
5291
5292 static void goya_set_clock_gating(struct hl_device *hdev)
5293 {
5294         /* clock gating not supported in Goya */
5295 }
5296
5297 static void goya_disable_clock_gating(struct hl_device *hdev)
5298 {
5299         /* clock gating not supported in Goya */
5300 }
5301
5302 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr,
5303                                         u8 mask_len, struct seq_file *s)
5304 {
5305         const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5306         const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5307         unsigned long *mask = (unsigned long *)mask_arr;
5308         u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5309                 mme_arch_sts;
5310         bool is_idle = true, is_eng_idle;
5311         u64 offset;
5312         int i;
5313
5314         if (s)
5315                 seq_puts(s, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
5316                                 "---  -------  ------------  -------------\n");
5317
5318         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5319
5320         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5321                 qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5322                 dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5323                 is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5324                                 IS_DMA_IDLE(dma_core_sts0);
5325                 is_idle &= is_eng_idle;
5326
5327                 if (mask && !is_eng_idle)
5328                         set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5329                 if (s)
5330                         seq_printf(s, dma_fmt, i, is_eng_idle ? "Y" : "N",
5331                                         qm_glbl_sts0, dma_core_sts0);
5332         }
5333
5334         if (s)
5335                 seq_puts(s,
5336                         "\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
5337                         "---  -------  ------------  --------------  ----------\n");
5338
5339         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5340
5341         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5342                 qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5343                 cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5344                 tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5345                 is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5346                                 IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5347                                 IS_TPC_IDLE(tpc_cfg_sts);
5348                 is_idle &= is_eng_idle;
5349
5350                 if (mask && !is_eng_idle)
5351                         set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5352                 if (s)
5353                         seq_printf(s, fmt, i, is_eng_idle ? "Y" : "N",
5354                                 qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5355         }
5356
5357         if (s)
5358                 seq_puts(s,
5359                         "\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
5360                         "---  -------  ------------  --------------  -----------\n");
5361
5362         qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5363         cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5364         mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5365         is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5366                         IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5367                         IS_MME_IDLE(mme_arch_sts);
5368         is_idle &= is_eng_idle;
5369
5370         if (mask && !is_eng_idle)
5371                 set_bit(GOYA_ENGINE_ID_MME_0, mask);
5372         if (s) {
5373                 seq_printf(s, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5374                                 cmdq_glbl_sts0, mme_arch_sts);
5375                 seq_puts(s, "\n");
5376         }
5377
5378         return is_idle;
5379 }
5380
5381 static void goya_hw_queues_lock(struct hl_device *hdev)
5382         __acquires(&goya->hw_queues_lock)
5383 {
5384         struct goya_device *goya = hdev->asic_specific;
5385
5386         spin_lock(&goya->hw_queues_lock);
5387 }
5388
5389 static void goya_hw_queues_unlock(struct hl_device *hdev)
5390         __releases(&goya->hw_queues_lock)
5391 {
5392         struct goya_device *goya = hdev->asic_specific;
5393
5394         spin_unlock(&goya->hw_queues_lock);
5395 }
5396
5397 static u32 goya_get_pci_id(struct hl_device *hdev)
5398 {
5399         return hdev->pdev->device;
5400 }
5401
5402 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5403                                 size_t max_size)
5404 {
5405         struct goya_device *goya = hdev->asic_specific;
5406
5407         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5408                 return 0;
5409
5410         return hl_fw_get_eeprom_data(hdev, data, max_size);
5411 }
5412
5413 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5414 {
5415
5416 }
5417
5418 static int goya_ctx_init(struct hl_ctx *ctx)
5419 {
5420         if (ctx->asid != HL_KERNEL_ASID_ID)
5421                 goya_mmu_prepare(ctx->hdev, ctx->asid);
5422
5423         return 0;
5424 }
5425
5426 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5427 {
5428         return cq_idx;
5429 }
5430
5431 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5432 {
5433         return 0;
5434 }
5435
5436 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5437 {
5438         return 0;
5439 }
5440
5441 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5442                                 u32 size, bool eb)
5443 {
5444         return 0;
5445 }
5446
5447 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5448                 struct hl_gen_wait_properties *prop)
5449 {
5450         return 0;
5451 }
5452
5453 static void goya_reset_sob(struct hl_device *hdev, void *data)
5454 {
5455
5456 }
5457
5458 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5459 {
5460
5461 }
5462
5463 static void goya_set_dma_mask_from_fw(struct hl_device *hdev)
5464 {
5465         if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) ==
5466                                                         HL_POWER9_HOST_MAGIC) {
5467                 dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n");
5468                 hdev->power9_64bit_dma_enable = 1;
5469                 hdev->dma_mask = 64;
5470         } else {
5471                 dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n");
5472                 hdev->power9_64bit_dma_enable = 0;
5473                 hdev->dma_mask = 48;
5474         }
5475 }
5476
5477 u64 goya_get_device_time(struct hl_device *hdev)
5478 {
5479         u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5480
5481         return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5482 }
5483
5484 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5485 {
5486         return 0;
5487 }
5488
5489 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5490                 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5491                 u32 collective_engine_id, u32 encaps_signal_offset)
5492 {
5493         return -EINVAL;
5494 }
5495
5496 static void goya_ctx_fini(struct hl_ctx *ctx)
5497 {
5498
5499 }
5500
5501 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5502                         u32 *block_size, u32 *block_id)
5503 {
5504         return -EPERM;
5505 }
5506
5507 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5508                                 u32 block_id, u32 block_size)
5509 {
5510         return -EPERM;
5511 }
5512
5513 static void goya_enable_events_from_fw(struct hl_device *hdev)
5514 {
5515         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5516                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5517 }
5518
5519 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5520 {
5521         switch (pll_idx) {
5522         case HL_GOYA_CPU_PLL: return CPU_PLL;
5523         case HL_GOYA_PCI_PLL: return PCI_PLL;
5524         case HL_GOYA_MME_PLL: return MME_PLL;
5525         case HL_GOYA_TPC_PLL: return TPC_PLL;
5526         case HL_GOYA_IC_PLL: return IC_PLL;
5527         case HL_GOYA_MC_PLL: return MC_PLL;
5528         case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5529         default: return -EINVAL;
5530         }
5531 }
5532
5533 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5534                                 struct hl_sync_to_engine_map *map)
5535 {
5536         /* Not implemented */
5537         return 0;
5538 }
5539
5540 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5541 {
5542         /* Not implemented */
5543         return 0;
5544 }
5545
5546 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5547                                 struct hl_device *hdev,
5548                                 struct hl_mon_state_dump *mon)
5549 {
5550         /* Not implemented */
5551         return 0;
5552 }
5553
5554
5555 static int goya_print_fences_single_engine(
5556         struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5557         enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5558         size_t *size, size_t *offset)
5559 {
5560         /* Not implemented */
5561         return 0;
5562 }
5563
5564
5565 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5566         .monitor_valid = goya_monitor_valid,
5567         .print_single_monitor = goya_print_single_monitor,
5568         .gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5569         .print_fences_single_engine = goya_print_fences_single_engine,
5570 };
5571
5572 static void goya_state_dump_init(struct hl_device *hdev)
5573 {
5574         /* Not implemented */
5575         hdev->state_dump_specs.props = goya_state_dump_specs_props;
5576         hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5577 }
5578
5579 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5580 {
5581         return 0;
5582 }
5583
5584 static u32 *goya_get_stream_master_qid_arr(void)
5585 {
5586         return NULL;
5587 }
5588
5589 static const struct hl_asic_funcs goya_funcs = {
5590         .early_init = goya_early_init,
5591         .early_fini = goya_early_fini,
5592         .late_init = goya_late_init,
5593         .late_fini = goya_late_fini,
5594         .sw_init = goya_sw_init,
5595         .sw_fini = goya_sw_fini,
5596         .hw_init = goya_hw_init,
5597         .hw_fini = goya_hw_fini,
5598         .halt_engines = goya_halt_engines,
5599         .suspend = goya_suspend,
5600         .resume = goya_resume,
5601         .mmap = goya_mmap,
5602         .ring_doorbell = goya_ring_doorbell,
5603         .pqe_write = goya_pqe_write,
5604         .asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5605         .asic_dma_free_coherent = goya_dma_free_coherent,
5606         .scrub_device_mem = goya_scrub_device_mem,
5607         .get_int_queue_base = goya_get_int_queue_base,
5608         .test_queues = goya_test_queues,
5609         .asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5610         .asic_dma_pool_free = goya_dma_pool_free,
5611         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5612         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5613         .hl_dma_unmap_sg = goya_dma_unmap_sg,
5614         .cs_parser = goya_cs_parser,
5615         .asic_dma_map_sg = goya_dma_map_sg,
5616         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
5617         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
5618         .update_eq_ci = goya_update_eq_ci,
5619         .context_switch = goya_context_switch,
5620         .restore_phase_topology = goya_restore_phase_topology,
5621         .debugfs_read32 = goya_debugfs_read32,
5622         .debugfs_write32 = goya_debugfs_write32,
5623         .debugfs_read64 = goya_debugfs_read64,
5624         .debugfs_write64 = goya_debugfs_write64,
5625         .debugfs_read_dma = goya_debugfs_read_dma,
5626         .add_device_attr = goya_add_device_attr,
5627         .handle_eqe = goya_handle_eqe,
5628         .set_pll_profile = goya_set_pll_profile,
5629         .get_events_stat = goya_get_events_stat,
5630         .read_pte = goya_read_pte,
5631         .write_pte = goya_write_pte,
5632         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
5633         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5634         .send_heartbeat = goya_send_heartbeat,
5635         .set_clock_gating = goya_set_clock_gating,
5636         .disable_clock_gating = goya_disable_clock_gating,
5637         .debug_coresight = goya_debug_coresight,
5638         .is_device_idle = goya_is_device_idle,
5639         .soft_reset_late_init = goya_soft_reset_late_init,
5640         .hw_queues_lock = goya_hw_queues_lock,
5641         .hw_queues_unlock = goya_hw_queues_unlock,
5642         .get_pci_id = goya_get_pci_id,
5643         .get_eeprom_data = goya_get_eeprom_data,
5644         .send_cpu_message = goya_send_cpu_message,
5645         .pci_bars_map = goya_pci_bars_map,
5646         .init_iatu = goya_init_iatu,
5647         .rreg = hl_rreg,
5648         .wreg = hl_wreg,
5649         .halt_coresight = goya_halt_coresight,
5650         .ctx_init = goya_ctx_init,
5651         .ctx_fini = goya_ctx_fini,
5652         .get_clk_rate = goya_get_clk_rate,
5653         .get_queue_id_for_cq = goya_get_queue_id_for_cq,
5654         .load_firmware_to_device = goya_load_firmware_to_device,
5655         .load_boot_fit_to_device = goya_load_boot_fit_to_device,
5656         .get_signal_cb_size = goya_get_signal_cb_size,
5657         .get_wait_cb_size = goya_get_wait_cb_size,
5658         .gen_signal_cb = goya_gen_signal_cb,
5659         .gen_wait_cb = goya_gen_wait_cb,
5660         .reset_sob = goya_reset_sob,
5661         .reset_sob_group = goya_reset_sob_group,
5662         .set_dma_mask_from_fw = goya_set_dma_mask_from_fw,
5663         .get_device_time = goya_get_device_time,
5664         .collective_wait_init_cs = goya_collective_wait_init_cs,
5665         .collective_wait_create_jobs = goya_collective_wait_create_jobs,
5666         .scramble_addr = hl_mmu_scramble_addr,
5667         .descramble_addr = hl_mmu_descramble_addr,
5668         .ack_protection_bits_errors = goya_ack_protection_bits_errors,
5669         .get_hw_block_id = goya_get_hw_block_id,
5670         .hw_block_mmap = goya_block_mmap,
5671         .enable_events_from_fw = goya_enable_events_from_fw,
5672         .map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5673         .init_firmware_loader = goya_init_firmware_loader,
5674         .init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5675         .state_dump_init = goya_state_dump_init,
5676         .get_sob_addr = &goya_get_sob_addr,
5677         .set_pci_memory_regions = goya_set_pci_memory_regions,
5678         .get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5679 };
5680
5681 /*
5682  * goya_set_asic_funcs - set Goya function pointers
5683  *
5684  * @*hdev: pointer to hl_device structure
5685  *
5686  */
5687 void goya_set_asic_funcs(struct hl_device *hdev)
5688 {
5689         hdev->asic_funcs = &goya_funcs;
5690 }