1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/rtsx_pci.h>
28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
32 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38 u8 driving_3v3[4][3] = {
44 u8 driving_1v8[4][3] = {
50 u8 (*driving)[3], drive_sel;
52 if (voltage == OUTPUT_3V3) {
53 driving = driving_3v3;
54 drive_sel = pcr->sd30_drive_sel_3v3;
56 driving = driving_1v8;
57 drive_sel = pcr->sd30_drive_sel_1v8;
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
61 0xFF, driving[drive_sel][0]);
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
63 0xFF, driving[drive_sel][1]);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
65 0xFF, driving[drive_sel][2]);
68 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
72 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
73 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75 if (!rtsx_vendor_setting_valid(reg)) {
76 pcr_dbg(pcr, "skip fetch vendor setting\n");
80 pcr->aspm_en = rtsx_reg_to_aspm(reg);
81 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
82 pcr->card_drive_sel &= 0x3F;
83 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
85 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
86 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
87 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
88 if (rtsx_reg_check_reverse_socket(reg))
89 pcr->flags |= PCR_REVERSE_SOCKET;
92 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
94 /* Set relink_time to 0 */
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
99 if (pm_state == HOST_ENTER_S3)
100 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
101 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
103 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
106 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
108 struct rtsx_cr_option *option = &(pcr->option);
111 if (CHK_PCI_PID(pcr, PID_524A))
112 rtsx_pci_read_config_dword(pcr,
113 PCR_ASPM_SETTING_REG1, &lval);
115 rtsx_pci_read_config_dword(pcr,
116 PCR_ASPM_SETTING_REG2, &lval);
118 if (lval & ASPM_L1_1_EN_MASK)
119 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
121 if (lval & ASPM_L1_2_EN_MASK)
122 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
124 if (lval & PM_L1_1_EN_MASK)
125 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
127 if (lval & PM_L1_2_EN_MASK)
128 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
130 if (option->ltr_en) {
133 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
134 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
135 option->ltr_enabled = true;
136 option->ltr_active = true;
137 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
139 option->ltr_enabled = false;
144 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
146 struct rtsx_cr_option *option = &(pcr->option);
148 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
149 | PM_L1_1_EN | PM_L1_2_EN))
150 option->force_clkreq_0 = false;
152 option->force_clkreq_0 = true;
157 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
159 struct rtsx_cr_option *option = &(pcr->option);
161 rts5249_init_from_cfg(pcr);
162 rts5249_init_from_hw(pcr);
164 rtsx_pci_init_cmd(pcr);
166 /* Rest L1SUB Config */
167 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
168 /* Configure GPIO as output */
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
170 /* Reset ASPM state to default value */
171 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
172 /* Switch LDO3318 source from DV33 to card_3v3 */
173 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
175 /* LED shine disabled, set initial shine cycle period */
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
177 /* Configure driving */
178 rts5249_fill_driving(pcr, OUTPUT_3V3);
179 if (pcr->flags & PCR_REVERSE_SOCKET)
180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
182 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
185 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
186 * to drive low, and we forcibly request clock.
188 if (option->force_clkreq_0)
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
190 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
193 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
195 return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
198 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
202 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
206 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
207 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
208 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
209 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
210 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
217 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
218 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
219 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
223 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
224 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
225 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
226 PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
230 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
231 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
232 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
233 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
237 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
238 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
239 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
240 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
241 PHY_FLD4_BER_CHK_EN);
244 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
245 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
248 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
249 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
252 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
253 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
258 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
259 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
260 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
261 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
264 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
266 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
269 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
271 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
274 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
276 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
279 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
281 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
284 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
287 struct rtsx_cr_option *option = &pcr->option;
290 rtsx_pci_enable_ocp(pcr);
292 rtsx_pci_init_cmd(pcr);
293 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
294 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
295 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
296 LDO3318_PWR_MASK, 0x02);
297 err = rtsx_pci_send_cmd(pcr, 100);
303 rtsx_pci_init_cmd(pcr);
304 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
305 SD_POWER_MASK, SD_VCC_POWER_ON);
306 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
307 LDO3318_PWR_MASK, 0x06);
308 return rtsx_pci_send_cmd(pcr, 100);
311 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
313 struct rtsx_cr_option *option = &pcr->option;
316 rtsx_pci_disable_ocp(pcr);
318 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
320 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
324 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
331 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
332 PHY_TUNE_VOLTAGE_3V3);
337 append = PHY_TUNE_D18_1V8;
338 if (CHK_PCI_PID(pcr, 0x5249)) {
339 err = rtsx_pci_update_phy(pcr, PHY_BACR,
340 PHY_BACR_BASIC_MASK, 0);
343 append = PHY_TUNE_D18_1V7;
346 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
352 pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
357 rtsx_pci_init_cmd(pcr);
358 rts5249_fill_driving(pcr, voltage);
359 return rtsx_pci_send_cmd(pcr, 100);
362 static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
364 struct rtsx_cr_option *option = &pcr->option;
367 if (pcr->aspm_enabled == enable)
370 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
373 rtsx_pci_update_cfg_byte(pcr,
374 pcr->pcie_cap + PCI_EXP_LNKCTL,
376 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
377 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
380 val = FORCE_ASPM_CTL0;
381 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
384 pcr->aspm_enabled = enable;
387 static const struct pcr_ops rts5249_pcr_ops = {
388 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
389 .extra_init_hw = rts5249_extra_init_hw,
390 .optimize_phy = rts5249_optimize_phy,
391 .turn_on_led = rtsx_base_turn_on_led,
392 .turn_off_led = rtsx_base_turn_off_led,
393 .enable_auto_blink = rtsx_base_enable_auto_blink,
394 .disable_auto_blink = rtsx_base_disable_auto_blink,
395 .card_power_on = rtsx_base_card_power_on,
396 .card_power_off = rtsx_base_card_power_off,
397 .switch_output_voltage = rtsx_base_switch_output_voltage,
398 .force_power_down = rtsx_base_force_power_down,
399 .set_aspm = rts5249_set_aspm,
402 /* SD Pull Control Enable:
403 * SD_DAT[3:0] ==> pull up
407 * SD_CLK ==> pull down
409 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
410 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
411 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
412 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
413 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
417 /* SD Pull Control Disable:
418 * SD_DAT[3:0] ==> pull down
420 * SD_WP ==> pull down
421 * SD_CMD ==> pull down
422 * SD_CLK ==> pull down
424 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
425 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
426 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
427 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
428 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
432 /* MS Pull Control Enable:
434 * others ==> pull down
436 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
437 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
438 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
439 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
443 /* MS Pull Control Disable:
445 * others ==> pull down
447 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
448 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
449 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
450 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
454 void rts5249_init_params(struct rtsx_pcr *pcr)
456 struct rtsx_cr_option *option = &(pcr->option);
458 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
460 pcr->ops = &rts5249_pcr_ops;
463 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
464 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
465 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
466 pcr->aspm_en = ASPM_L1_EN;
467 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
468 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
470 pcr->ic_version = rts5249_get_ic_version(pcr);
471 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
472 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
473 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
474 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
476 pcr->reg_pm_ctrl3 = PM_CTRL3;
478 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
479 | LTR_L1SS_PWR_GATE_EN);
480 option->ltr_en = true;
482 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
483 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
484 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
485 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
486 option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
487 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
488 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
489 option->ltr_l1off_snooze_sspwrgate =
490 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
493 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
495 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
497 return __rtsx_pci_write_phy_register(pcr, addr, val);
500 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
502 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
504 return __rtsx_pci_read_phy_register(pcr, addr, val);
507 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
511 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
512 D3_DELINK_MODE_EN, 0x00);
516 rtsx_pci_write_phy_register(pcr, PHY_PCR,
517 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
518 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
519 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
520 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
522 if (is_version(pcr, 0x524A, IC_VER_A)) {
523 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
524 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
525 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
526 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
527 PHY_SSCCR2_TIME2_WIDTH);
528 rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
529 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
530 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
531 rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
532 PHY_ANA1D_DEBUG_ADDR);
533 rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
534 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
535 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
536 PHY_DIG1E_RCLK_TX_EN_KEEP |
537 PHY_DIG1E_RCLK_TX_TERM_KEEP |
538 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
539 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
540 PHY_DIG1E_RX_EN_KEEP);
543 rtsx_pci_write_phy_register(pcr, PHY_ANA08,
544 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
545 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
550 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
552 rts5249_extra_init_hw(pcr);
554 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
555 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
556 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
557 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
559 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
560 if (is_version(pcr, 0x524A, IC_VER_A)) {
561 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
562 LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
563 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
564 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
565 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
566 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
567 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
568 LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
569 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
570 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
571 rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
572 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
578 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
580 struct rtsx_cr_option *option = &(pcr->option);
582 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
583 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
584 int aspm_L1_1, aspm_L1_2;
587 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
588 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
591 /* Run, latency: 60us */
593 val = option->ltr_l1off_snooze_sspwrgate;
595 /* L1off, latency: 300us */
597 val = option->ltr_l1off_sspwrgate;
600 if (aspm_L1_1 || aspm_L1_2) {
601 if (rtsx_check_dev_flag(pcr,
602 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
604 val &= ~L1OFF_MBIAS2_EN_5250;
606 val |= L1OFF_MBIAS2_EN_5250;
609 rtsx_set_l1off_sub(pcr, val);
612 static const struct pcr_ops rts524a_pcr_ops = {
613 .write_phy = rts524a_write_phy,
614 .read_phy = rts524a_read_phy,
615 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
616 .extra_init_hw = rts524a_extra_init_hw,
617 .optimize_phy = rts524a_optimize_phy,
618 .turn_on_led = rtsx_base_turn_on_led,
619 .turn_off_led = rtsx_base_turn_off_led,
620 .enable_auto_blink = rtsx_base_enable_auto_blink,
621 .disable_auto_blink = rtsx_base_disable_auto_blink,
622 .card_power_on = rtsx_base_card_power_on,
623 .card_power_off = rtsx_base_card_power_off,
624 .switch_output_voltage = rtsx_base_switch_output_voltage,
625 .force_power_down = rtsx_base_force_power_down,
626 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
627 .set_aspm = rts5249_set_aspm,
630 void rts524a_init_params(struct rtsx_pcr *pcr)
632 rts5249_init_params(pcr);
633 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
634 pcr->option.ltr_l1off_snooze_sspwrgate =
635 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
637 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
638 pcr->ops = &rts524a_pcr_ops;
640 pcr->option.ocp_en = 1;
641 if (pcr->option.ocp_en)
642 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
643 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
644 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
648 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
650 rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
651 LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
652 return rtsx_base_card_power_on(pcr, card);
655 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
659 rtsx_pci_write_register(pcr, LDO_CONFIG2,
660 LDO_D3318_MASK, LDO_D3318_33V);
661 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
664 rtsx_pci_write_register(pcr, LDO_CONFIG2,
665 LDO_D3318_MASK, LDO_D3318_18V);
666 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
673 rtsx_pci_init_cmd(pcr);
674 rts5249_fill_driving(pcr, voltage);
675 return rtsx_pci_send_cmd(pcr, 100);
678 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
682 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
683 D3_DELINK_MODE_EN, 0x00);
687 rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
688 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
689 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
690 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
692 rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
693 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
696 if (is_version(pcr, 0x525A, IC_VER_A))
697 rtsx_pci_write_phy_register(pcr, _PHY_REV0,
698 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
699 _PHY_REV0_CDR_RX_IDLE_BYPASS);
704 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
706 rts5249_extra_init_hw(pcr);
708 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
709 if (is_version(pcr, 0x525A, IC_VER_A)) {
710 rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
711 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
712 rtsx_pci_write_register(pcr, RREF_CFG,
713 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
714 rtsx_pci_write_register(pcr, LDO_VIO_CFG,
715 LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
716 rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
717 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
718 rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
719 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
720 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
721 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
722 rtsx_pci_write_register(pcr, OOBS_CONFIG,
723 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
729 static const struct pcr_ops rts525a_pcr_ops = {
730 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
731 .extra_init_hw = rts525a_extra_init_hw,
732 .optimize_phy = rts525a_optimize_phy,
733 .turn_on_led = rtsx_base_turn_on_led,
734 .turn_off_led = rtsx_base_turn_off_led,
735 .enable_auto_blink = rtsx_base_enable_auto_blink,
736 .disable_auto_blink = rtsx_base_disable_auto_blink,
737 .card_power_on = rts525a_card_power_on,
738 .card_power_off = rtsx_base_card_power_off,
739 .switch_output_voltage = rts525a_switch_output_voltage,
740 .force_power_down = rtsx_base_force_power_down,
741 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
742 .set_aspm = rts5249_set_aspm,
745 void rts525a_init_params(struct rtsx_pcr *pcr)
747 rts5249_init_params(pcr);
748 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
749 pcr->option.ltr_l1off_snooze_sspwrgate =
750 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
752 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
753 pcr->ops = &rts525a_pcr_ops;
755 pcr->option.ocp_en = 1;
756 if (pcr->option.ocp_en)
757 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
758 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
759 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;