drivers/mfd/qcom-pm8xxx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   4  */
   5
   6 #define pr_fmt(fmt) "%s: " fmt, __func__
   7
   8 #include <linux/kernel.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/irqchip/chained_irq.h>
  11 #include <linux/irq.h>
  12 #include <linux/irqdomain.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/ssbi.h>
  18 #include <linux/regmap.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/mfd/core.h>
  21
  22 #define SSBI_REG_ADDR_IRQ_BASE          0x1BB
  23
  24 #define SSBI_REG_ADDR_IRQ_ROOT          (SSBI_REG_ADDR_IRQ_BASE + 0)
  25 #define SSBI_REG_ADDR_IRQ_M_STATUS1     (SSBI_REG_ADDR_IRQ_BASE + 1)
  26 #define SSBI_REG_ADDR_IRQ_M_STATUS2     (SSBI_REG_ADDR_IRQ_BASE + 2)
  27 #define SSBI_REG_ADDR_IRQ_M_STATUS3     (SSBI_REG_ADDR_IRQ_BASE + 3)
  28 #define SSBI_REG_ADDR_IRQ_M_STATUS4     (SSBI_REG_ADDR_IRQ_BASE + 4)
  29 #define SSBI_REG_ADDR_IRQ_BLK_SEL       (SSBI_REG_ADDR_IRQ_BASE + 5)
  30 #define SSBI_REG_ADDR_IRQ_IT_STATUS     (SSBI_REG_ADDR_IRQ_BASE + 6)
  31 #define SSBI_REG_ADDR_IRQ_CONFIG        (SSBI_REG_ADDR_IRQ_BASE + 7)
  32 #define SSBI_REG_ADDR_IRQ_RT_STATUS     (SSBI_REG_ADDR_IRQ_BASE + 8)
  33
  34 #define PM8821_SSBI_REG_ADDR_IRQ_BASE   0x100
  35 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
  36 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
  37 #define PM8821_SSBI_REG(m, b, offset) \
  38                         ((m == 0) ? \
  39                         (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
  40                         (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
  41 #define PM8821_SSBI_ADDR_IRQ_ROOT(m, b)         PM8821_SSBI_REG(m, b, 0x0)
  42 #define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)        PM8821_SSBI_REG(m, b, 0x01)
  43 #define PM8821_SSBI_ADDR_IRQ_MASK(m, b)         PM8821_SSBI_REG(m, b, 0x08)
  44 #define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)    PM8821_SSBI_REG(m, b, 0x0f)
  45
  46 #define PM8821_BLOCKS_PER_MASTER        7
  47
  48 #define PM_IRQF_LVL_SEL                 0x01    /* level select */
  49 #define PM_IRQF_MASK_FE                 0x02    /* mask falling edge */
  50 #define PM_IRQF_MASK_RE                 0x04    /* mask rising edge */
  51 #define PM_IRQF_CLR                     0x08    /* clear interrupt */
  52 #define PM_IRQF_BITS_MASK               0x70
  53 #define PM_IRQF_BITS_SHIFT              4
  54 #define PM_IRQF_WRITE                   0x80
  55
  56 #define PM_IRQF_MASK_ALL                (PM_IRQF_MASK_FE | \
  57                                         PM_IRQF_MASK_RE)
  58
  59 #define REG_HWREV               0x002  /* PMIC4 revision */
  60 #define REG_HWREV_2             0x0E8  /* PMIC4 revision 2 */
  61
  62 #define PM8XXX_NR_IRQS          256
  63 #define PM8821_NR_IRQS          112
  64
  65 struct pm_irq_data {
  66         int num_irqs;
  67         struct irq_chip *irq_chip;
  68         void (*irq_handler)(struct irq_desc *desc);
  69 };
  70
  71 struct pm_irq_chip {
  72         struct regmap           *regmap;
  73         spinlock_t              pm_irq_lock;
  74         struct irq_domain       *irqdomain;
  75         unsigned int            num_blocks;
  76         unsigned int            num_masters;
  77         const struct pm_irq_data *pm_irq_data;
  78         /* MUST BE AT THE END OF THIS STRUCT */
  79         u8                      config[];
  80 };
  81
  82 static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
  83                                  unsigned int *ip)
  84 {
  85         int     rc;
  86
  87         spin_lock(&chip->pm_irq_lock);
  88         rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
  89         if (rc) {
  90                 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
  91                 goto bail;
  92         }
  93
  94         rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
  95         if (rc)
  96                 pr_err("Failed Reading Status rc=%d\n", rc);
  97 bail:
  98         spin_unlock(&chip->pm_irq_lock);
  99         return rc;
 100 }
 101
 102 static int
 103 pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
 104 {
 105         int     rc;
 106
 107         spin_lock(&chip->pm_irq_lock);
 108         rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
 109         if (rc) {
 110                 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
 111                 goto bail;
 112         }
 113
 114         cp |= PM_IRQF_WRITE;
 115         rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
 116         if (rc)
 117                 pr_err("Failed Configuring IRQ rc=%d\n", rc);
 118 bail:
 119         spin_unlock(&chip->pm_irq_lock);
 120         return rc;
 121 }
 122
 123 static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
 124 {
 125         int pmirq, irq, i, ret = 0;
 126         unsigned int bits;
 127
 128         ret = pm8xxx_read_block_irq(chip, block, &bits);
 129         if (ret) {
 130                 pr_err("Failed reading %d block ret=%d", block, ret);
 131                 return ret;
 132         }
 133         if (!bits) {
 134                 pr_err("block bit set in master but no irqs: %d", block);
 135                 return 0;
 136         }
 137
 138         /* Check IRQ bits */
 139         for (i = 0; i < 8; i++) {
 140                 if (bits & (1 << i)) {
 141                         pmirq = block * 8 + i;
 142                         irq = irq_find_mapping(chip->irqdomain, pmirq);
 143                         generic_handle_irq(irq);
 144                 }
 145         }
 146         return 0;
 147 }
 148
 149 static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
 150 {
 151         unsigned int blockbits;
 152         int block_number, i, ret = 0;
 153
 154         ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
 155                           &blockbits);
 156         if (ret) {
 157                 pr_err("Failed to read master %d ret=%d\n", master, ret);
 158                 return ret;
 159         }
 160         if (!blockbits) {
 161                 pr_err("master bit set in root but no blocks: %d", master);
 162                 return 0;
 163         }
 164
 165         for (i = 0; i < 8; i++)
 166                 if (blockbits & (1 << i)) {
 167                         block_number = master * 8 + i;  /* block # */
 168                         ret |= pm8xxx_irq_block_handler(chip, block_number);
 169                 }
 170         return ret;
 171 }
 172
 173 static void pm8xxx_irq_handler(struct irq_desc *desc)
 174 {
 175         struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
 176         struct irq_chip *irq_chip = irq_desc_get_chip(desc);
 177         unsigned int root;
 178         int     i, ret, masters = 0;
 179
 180         chained_irq_enter(irq_chip, desc);
 181
 182         ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
 183         if (ret) {
 184                 pr_err("Can't read root status ret=%d\n", ret);
 185                 return;
 186         }
 187
 188         /* on pm8xxx series masters start from bit 1 of the root */
 189         masters = root >> 1;
 190
 191         /* Read allowed masters for blocks. */
 192         for (i = 0; i < chip->num_masters; i++)
 193                 if (masters & (1 << i))
 194                         pm8xxx_irq_master_handler(chip, i);
 195
 196         chained_irq_exit(irq_chip, desc);
 197 }
 198
 199 static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
 200                                      int master, int block)
 201 {
 202         int pmirq, irq, i, ret;
 203         unsigned int bits;
 204
 205         ret = regmap_read(chip->regmap,
 206                           PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
 207         if (ret) {
 208                 pr_err("Reading block %d failed ret=%d", block, ret);
 209                 return;
 210         }
 211
 212         /* Convert block offset to global block number */
 213         block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
 214
 215         /* Check IRQ bits */
 216         for (i = 0; i < 8; i++) {
 217                 if (bits & BIT(i)) {
 218                         pmirq = block * 8 + i;
 219                         irq = irq_find_mapping(chip->irqdomain, pmirq);
 220                         generic_handle_irq(irq);
 221                 }
 222         }
 223 }
 224
 225 static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
 226                                              int master, u8 master_val)
 227 {
 228         int block;
 229
 230         for (block = 1; block < 8; block++)
 231                 if (master_val & BIT(block))
 232                         pm8821_irq_block_handler(chip, master, block);
 233 }
 234
 235 static void pm8821_irq_handler(struct irq_desc *desc)
 236 {
 237         struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
 238         struct irq_chip *irq_chip = irq_desc_get_chip(desc);
 239         unsigned int master;
 240         int ret;
 241
 242         chained_irq_enter(irq_chip, desc);
 243         ret = regmap_read(chip->regmap,
 244                           PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
 245         if (ret) {
 246                 pr_err("Failed to read master 0 ret=%d\n", ret);
 247                 goto done;
 248         }
 249
 250         /* bits 1 through 7 marks the first 7 blocks in master 0 */
 251         if (master & GENMASK(7, 1))
 252                 pm8821_irq_master_handler(chip, 0, master);
 253
 254         /* bit 0 marks if master 1 contains any bits */
 255         if (!(master & BIT(0)))
 256                 goto done;
 257
 258         ret = regmap_read(chip->regmap,
 259                           PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
 260         if (ret) {
 261                 pr_err("Failed to read master 1 ret=%d\n", ret);
 262                 goto done;
 263         }
 264
 265         pm8821_irq_master_handler(chip, 1, master);
 266
 267 done:
 268         chained_irq_exit(irq_chip, desc);
 269 }
 270
 271 static void pm8xxx_irq_mask_ack(struct irq_data *d)
 272 {
 273         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 274         unsigned int pmirq = irqd_to_hwirq(d);
 275         u8      block, config;
 276
 277         block = pmirq / 8;
 278
 279         config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
 280         pm8xxx_config_irq(chip, block, config);
 281 }
 282
 283 static void pm8xxx_irq_unmask(struct irq_data *d)
 284 {
 285         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 286         unsigned int pmirq = irqd_to_hwirq(d);
 287         u8      block, config;
 288
 289         block = pmirq / 8;
 290
 291         config = chip->config[pmirq];
 292         pm8xxx_config_irq(chip, block, config);
 293 }
 294
 295 static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 296 {
 297         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 298         unsigned int pmirq = irqd_to_hwirq(d);
 299         int irq_bit;
 300         u8 block, config;
 301
 302         block = pmirq / 8;
 303         irq_bit  = pmirq % 8;
 304
 305         chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
 306                                                         | PM_IRQF_MASK_ALL;
 307         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 308                 if (flow_type & IRQF_TRIGGER_RISING)
 309                         chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
 310                 if (flow_type & IRQF_TRIGGER_FALLING)
 311                         chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
 312         } else {
 313                 chip->config[pmirq] |= PM_IRQF_LVL_SEL;
 314
 315                 if (flow_type & IRQF_TRIGGER_HIGH)
 316                         chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
 317                 else
 318                         chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
 319         }
 320
 321         config = chip->config[pmirq] | PM_IRQF_CLR;
 322         return pm8xxx_config_irq(chip, block, config);
 323 }
 324
 325 static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
 326                                         enum irqchip_irq_state which,
 327                                         bool *state)
 328 {
 329         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 330         unsigned int pmirq = irqd_to_hwirq(d);
 331         unsigned int bits;
 332         int irq_bit;
 333         u8 block;
 334         int rc;
 335
 336         if (which != IRQCHIP_STATE_LINE_LEVEL)
 337                 return -EINVAL;
 338
 339         block = pmirq / 8;
 340         irq_bit = pmirq % 8;
 341
 342         spin_lock(&chip->pm_irq_lock);
 343         rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
 344         if (rc) {
 345                 pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
 346                 goto bail;
 347         }
 348
 349         rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
 350         if (rc) {
 351                 pr_err("Failed Reading Status rc=%d\n", rc);
 352                 goto bail;
 353         }
 354
 355         *state = !!(bits & BIT(irq_bit));
 356 bail:
 357         spin_unlock(&chip->pm_irq_lock);
 358
 359         return rc;
 360 }
 361
 362 static struct irq_chip pm8xxx_irq_chip = {
 363         .name           = "pm8xxx",
 364         .irq_mask_ack   = pm8xxx_irq_mask_ack,
 365         .irq_unmask     = pm8xxx_irq_unmask,
 366         .irq_set_type   = pm8xxx_irq_set_type,
 367         .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
 368         .flags          = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
 369 };
 370
 371 static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
 372                                   struct irq_domain *domain, unsigned int irq,
 373                                   irq_hw_number_t hwirq, unsigned int type)
 374 {
 375         irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
 376                             chip, handle_level_irq, NULL, NULL);
 377         irq_set_noprobe(irq);
 378 }
 379
 380 static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 381                                    unsigned int nr_irqs, void *data)
 382 {
 383         struct pm_irq_chip *chip = domain->host_data;
 384         struct irq_fwspec *fwspec = data;
 385         irq_hw_number_t hwirq;
 386         unsigned int type;
 387         int ret, i;
 388
 389         ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
 390         if (ret)
 391                 return ret;
 392
 393         for (i = 0; i < nr_irqs; i++)
 394                 pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
 395
 396         return 0;
 397 }
 398
 399 static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
 400         .alloc = pm8xxx_irq_domain_alloc,
 401         .free = irq_domain_free_irqs_common,
 402         .translate = irq_domain_translate_twocell,
 403 };
 404
 405 static void pm8821_irq_mask_ack(struct irq_data *d)
 406 {
 407         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 408         unsigned int pmirq = irqd_to_hwirq(d);
 409         u8 block, master;
 410         int irq_bit, rc;
 411
 412         block = pmirq / 8;
 413         master = block / PM8821_BLOCKS_PER_MASTER;
 414         irq_bit = pmirq % 8;
 415         block %= PM8821_BLOCKS_PER_MASTER;
 416
 417         rc = regmap_update_bits(chip->regmap,
 418                                 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
 419                                 BIT(irq_bit), BIT(irq_bit));
 420         if (rc) {
 421                 pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
 422                 return;
 423         }
 424
 425         rc = regmap_update_bits(chip->regmap,
 426                                 PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
 427                                 BIT(irq_bit), BIT(irq_bit));
 428         if (rc)
 429                 pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
 430 }
 431
 432 static void pm8821_irq_unmask(struct irq_data *d)
 433 {
 434         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 435         unsigned int pmirq = irqd_to_hwirq(d);
 436         int irq_bit, rc;
 437         u8 block, master;
 438
 439         block = pmirq / 8;
 440         master = block / PM8821_BLOCKS_PER_MASTER;
 441         irq_bit = pmirq % 8;
 442         block %= PM8821_BLOCKS_PER_MASTER;
 443
 444         rc = regmap_update_bits(chip->regmap,
 445                                 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
 446                                 BIT(irq_bit), ~BIT(irq_bit));
 447         if (rc)
 448                 pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
 449
 450 }
 451
 452 static int pm8821_irq_get_irqchip_state(struct irq_data *d,
 453                                         enum irqchip_irq_state which,
 454                                         bool *state)
 455 {
 456         struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
 457         int rc, pmirq = irqd_to_hwirq(d);
 458         u8 block, irq_bit, master;
 459         unsigned int bits;
 460
 461         block = pmirq / 8;
 462         master = block / PM8821_BLOCKS_PER_MASTER;
 463         irq_bit = pmirq % 8;
 464         block %= PM8821_BLOCKS_PER_MASTER;
 465
 466         rc = regmap_read(chip->regmap,
 467                 PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
 468         if (rc) {
 469                 pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
 470                 return rc;
 471         }
 472
 473         *state = !!(bits & BIT(irq_bit));
 474
 475         return rc;
 476 }
 477
 478 static struct irq_chip pm8821_irq_chip = {
 479         .name           = "pm8821",
 480         .irq_mask_ack   = pm8821_irq_mask_ack,
 481         .irq_unmask     = pm8821_irq_unmask,
 482         .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
 483         .flags          = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
 484 };
 485
 486 static const struct regmap_config ssbi_regmap_config = {
 487         .reg_bits = 16,
 488         .val_bits = 8,
 489         .max_register = 0x3ff,
 490         .fast_io = true,
 491         .reg_read = ssbi_reg_read,
 492         .reg_write = ssbi_reg_write
 493 };
 494
 495 static const struct pm_irq_data pm8xxx_data = {
 496         .num_irqs = PM8XXX_NR_IRQS,
 497         .irq_chip = &pm8xxx_irq_chip,
 498         .irq_handler = pm8xxx_irq_handler,
 499 };
 500
 501 static const struct pm_irq_data pm8821_data = {
 502         .num_irqs = PM8821_NR_IRQS,
 503         .irq_chip = &pm8821_irq_chip,
 504         .irq_handler = pm8821_irq_handler,
 505 };
 506
 507 static const struct of_device_id pm8xxx_id_table[] = {
 508         { .compatible = "qcom,pm8018", .data = &pm8xxx_data},
 509         { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
 510         { .compatible = "qcom,pm8821", .data = &pm8821_data},
 511         { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
 512         { }
 513 };
 514 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
 515
 516 static int pm8xxx_probe(struct platform_device *pdev)
 517 {
 518         const struct pm_irq_data *data;
 519         struct regmap *regmap;
 520         int irq, rc;
 521         unsigned int val;
 522         u32 rev;
 523         struct pm_irq_chip *chip;
 524
 525         data = of_device_get_match_data(&pdev->dev);
 526         if (!data) {
 527                 dev_err(&pdev->dev, "No matching driver data found\n");
 528                 return -EINVAL;
 529         }
 530
 531         irq = platform_get_irq(pdev, 0);
 532         if (irq < 0)
 533                 return irq;
 534
 535         regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
 536                                   &ssbi_regmap_config);
 537         if (IS_ERR(regmap))
 538                 return PTR_ERR(regmap);
 539
 540         /* Read PMIC chip revision */
 541         rc = regmap_read(regmap, REG_HWREV, &val);
 542         if (rc) {
 543                 pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
 544                 return rc;
 545         }
 546         pr_info("PMIC revision 1: %02X\n", val);
 547         rev = val;
 548
 549         /* Read PMIC chip revision 2 */
 550         rc = regmap_read(regmap, REG_HWREV_2, &val);
 551         if (rc) {
 552                 pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
 553                         REG_HWREV_2, rc);
 554                 return rc;
 555         }
 556         pr_info("PMIC revision 2: %02X\n", val);
 557         rev |= val << BITS_PER_BYTE;
 558
 559         chip = devm_kzalloc(&pdev->dev,
 560                             struct_size(chip, config, data->num_irqs),
 561                             GFP_KERNEL);
 562         if (!chip)
 563                 return -ENOMEM;
 564
 565         platform_set_drvdata(pdev, chip);
 566         chip->regmap = regmap;
 567         chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
 568         chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
 569         chip->pm_irq_data = data;
 570         spin_lock_init(&chip->pm_irq_lock);
 571
 572         chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
 573                                                 data->num_irqs,
 574                                                 &pm8xxx_irq_domain_ops,
 575                                                 chip);
 576         if (!chip->irqdomain)
 577                 return -ENODEV;
 578
 579         irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
 580         irq_set_irq_wake(irq, 1);
 581
 582         rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 583         if (rc) {
 584                 irq_set_chained_handler_and_data(irq, NULL, NULL);
 585                 irq_domain_remove(chip->irqdomain);
 586         }
 587
 588         return rc;
 589 }
 590
 591 static int pm8xxx_remove_child(struct device *dev, void *unused)
 592 {
 593         platform_device_unregister(to_platform_device(dev));
 594         return 0;
 595 }
 596
 597 static int pm8xxx_remove(struct platform_device *pdev)
 598 {
 599         int irq = platform_get_irq(pdev, 0);
 600         struct pm_irq_chip *chip = platform_get_drvdata(pdev);
 601
 602         device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
 603         irq_set_chained_handler_and_data(irq, NULL, NULL);
 604         irq_domain_remove(chip->irqdomain);
 605
 606         return 0;
 607 }
 608
 609 static struct platform_driver pm8xxx_driver = {
 610         .probe          = pm8xxx_probe,
 611         .remove         = pm8xxx_remove,
 612         .driver         = {
 613                 .name   = "pm8xxx-core",
 614                 .of_match_table = pm8xxx_id_table,
 615         },
 616 };
 617
 618 static int __init pm8xxx_init(void)
 619 {
 620         return platform_driver_register(&pm8xxx_driver);
 621 }
 622 subsys_initcall(pm8xxx_init);
 623
 624 static void __exit pm8xxx_exit(void)
 625 {
 626         platform_driver_unregister(&pm8xxx_driver);
 627 }
 628 module_exit(pm8xxx_exit);
 629
 630 MODULE_LICENSE("GPL v2");
 631 MODULE_DESCRIPTION("PMIC 8xxx core driver");
 632 MODULE_VERSION("1.0");
 633 MODULE_ALIAS("platform:pm8xxx-core");