drivers/memory/renesas-rpc-if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RPC-IF core driver
   4  *
   5  * Copyright (C) 2018-2019 Renesas Solutions Corp.
   6  * Copyright (C) 2019 Macronix International Co., Ltd.
   7  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/of.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18
  19 #include <memory/renesas-rpc-if.h>
  20
  21 #define RPCIF_CMNCR             0x0000  /* R/W */
  22 #define RPCIF_CMNCR_MD          BIT(31)
  23 #define RPCIF_CMNCR_SFDE        BIT(24) /* undocumented but must be set */
  24 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
  25 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
  26 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
  27 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
  28 #define RPCIF_CMNCR_MOIIO_HIZ   (RPCIF_CMNCR_MOIIO0(3) | \
  29                                  RPCIF_CMNCR_MOIIO1(3) | \
  30                                  RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
  31 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* undocumented */
  32 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* undocumented */
  33 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
  34 #define RPCIF_CMNCR_IOFV_HIZ    (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
  35                                  RPCIF_CMNCR_IO3FV(3))
  36 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
  37
  38 #define RPCIF_SSLDR             0x0004  /* R/W */
  39 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
  40 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
  41 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
  42
  43 #define RPCIF_DRCR              0x000C  /* R/W */
  44 #define RPCIF_DRCR_SSLN         BIT(24)
  45 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
  46 #define RPCIF_DRCR_RCF          BIT(9)
  47 #define RPCIF_DRCR_RBE          BIT(8)
  48 #define RPCIF_DRCR_SSLE         BIT(0)
  49
  50 #define RPCIF_DRCMR             0x0010  /* R/W */
  51 #define RPCIF_DRCMR_CMD(c)      (((c) & 0xFF) << 16)
  52 #define RPCIF_DRCMR_OCMD(c)     (((c) & 0xFF) << 0)
  53
  54 #define RPCIF_DREAR             0x0014  /* R/W */
  55 #define RPCIF_DREAR_EAV(c)      (((c) & 0xF) << 16)
  56 #define RPCIF_DREAR_EAC(c)      (((c) & 0x7) << 0)
  57
  58 #define RPCIF_DROPR             0x0018  /* R/W */
  59
  60 #define RPCIF_DRENR             0x001C  /* R/W */
  61 #define RPCIF_DRENR_CDB(o)      (u32)((((o) & 0x3) << 30))
  62 #define RPCIF_DRENR_OCDB(o)     (((o) & 0x3) << 28)
  63 #define RPCIF_DRENR_ADB(o)      (((o) & 0x3) << 24)
  64 #define RPCIF_DRENR_OPDB(o)     (((o) & 0x3) << 20)
  65 #define RPCIF_DRENR_DRDB(o)     (((o) & 0x3) << 16)
  66 #define RPCIF_DRENR_DME         BIT(15)
  67 #define RPCIF_DRENR_CDE         BIT(14)
  68 #define RPCIF_DRENR_OCDE        BIT(12)
  69 #define RPCIF_DRENR_ADE(v)      (((v) & 0xF) << 8)
  70 #define RPCIF_DRENR_OPDE(v)     (((v) & 0xF) << 4)
  71
  72 #define RPCIF_SMCR              0x0020  /* R/W */
  73 #define RPCIF_SMCR_SSLKP        BIT(8)
  74 #define RPCIF_SMCR_SPIRE        BIT(2)
  75 #define RPCIF_SMCR_SPIWE        BIT(1)
  76 #define RPCIF_SMCR_SPIE         BIT(0)
  77
  78 #define RPCIF_SMCMR             0x0024  /* R/W */
  79 #define RPCIF_SMCMR_CMD(c)      (((c) & 0xFF) << 16)
  80 #define RPCIF_SMCMR_OCMD(c)     (((c) & 0xFF) << 0)
  81
  82 #define RPCIF_SMADR             0x0028  /* R/W */
  83
  84 #define RPCIF_SMOPR             0x002C  /* R/W */
  85 #define RPCIF_SMOPR_OPD3(o)     (((o) & 0xFF) << 24)
  86 #define RPCIF_SMOPR_OPD2(o)     (((o) & 0xFF) << 16)
  87 #define RPCIF_SMOPR_OPD1(o)     (((o) & 0xFF) << 8)
  88 #define RPCIF_SMOPR_OPD0(o)     (((o) & 0xFF) << 0)
  89
  90 #define RPCIF_SMENR             0x0030  /* R/W */
  91 #define RPCIF_SMENR_CDB(o)      (((o) & 0x3) << 30)
  92 #define RPCIF_SMENR_OCDB(o)     (((o) & 0x3) << 28)
  93 #define RPCIF_SMENR_ADB(o)      (((o) & 0x3) << 24)
  94 #define RPCIF_SMENR_OPDB(o)     (((o) & 0x3) << 20)
  95 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
  96 #define RPCIF_SMENR_DME         BIT(15)
  97 #define RPCIF_SMENR_CDE         BIT(14)
  98 #define RPCIF_SMENR_OCDE        BIT(12)
  99 #define RPCIF_SMENR_ADE(v)      (((v) & 0xF) << 8)
 100 #define RPCIF_SMENR_OPDE(v)     (((v) & 0xF) << 4)
 101 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
 102
 103 #define RPCIF_SMRDR0            0x0038  /* R */
 104 #define RPCIF_SMRDR1            0x003C  /* R */
 105 #define RPCIF_SMWDR0            0x0040  /* W */
 106 #define RPCIF_SMWDR1            0x0044  /* W */
 107
 108 #define RPCIF_CMNSR             0x0048  /* R */
 109 #define RPCIF_CMNSR_SSLF        BIT(1)
 110 #define RPCIF_CMNSR_TEND        BIT(0)
 111
 112 #define RPCIF_DRDMCR            0x0058  /* R/W */
 113 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 114
 115 #define RPCIF_DRDRENR           0x005C  /* R/W */
 116 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
 117 #define RPCIF_DRDRENR_ADDRE     BIT(8)
 118 #define RPCIF_DRDRENR_OPDRE     BIT(4)
 119 #define RPCIF_DRDRENR_DRDRE     BIT(0)
 120
 121 #define RPCIF_SMDMCR            0x0060  /* R/W */
 122 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
 123
 124 #define RPCIF_SMDRENR           0x0064  /* R/W */
 125 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
 126 #define RPCIF_SMDRENR_ADDRE     BIT(8)
 127 #define RPCIF_SMDRENR_OPDRE     BIT(4)
 128 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
 129
 130 #define RPCIF_PHYCNT            0x007C  /* R/W */
 131 #define RPCIF_PHYCNT_CAL        BIT(31)
 132 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
 133 #define RPCIF_PHYCNT_EXDS       BIT(21)
 134 #define RPCIF_PHYCNT_OCT        BIT(20)
 135 #define RPCIF_PHYCNT_DDRCAL     BIT(19)
 136 #define RPCIF_PHYCNT_HS         BIT(18)
 137 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15)
 138 #define RPCIF_PHYCNT_WBUF2      BIT(4)
 139 #define RPCIF_PHYCNT_WBUF       BIT(2)
 140 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
 141
 142 #define RPCIF_PHYOFFSET1        0x0080  /* R/W */
 143 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 144
 145 #define RPCIF_PHYOFFSET2        0x0084  /* R/W */
 146 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 147
 148 #define RPCIF_PHYINT            0x0088  /* R/W */
 149 #define RPCIF_PHYINT_WPVAL      BIT(1)
 150
 151 #define RPCIF_DIRMAP_SIZE       0x4000000
 152
 153 static const struct regmap_range rpcif_volatile_ranges[] = {
 154         regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
 155         regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
 156         regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
 157 };
 158
 159 static const struct regmap_access_table rpcif_volatile_table = {
 160         .yes_ranges     = rpcif_volatile_ranges,
 161         .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
 162 };
 163
 164 static const struct regmap_config rpcif_regmap_config = {
 165         .reg_bits       = 32,
 166         .val_bits       = 32,
 167         .reg_stride     = 4,
 168         .fast_io        = true,
 169         .max_register   = RPCIF_PHYINT,
 170         .volatile_table = &rpcif_volatile_table,
 171 };
 172
 173 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
 174 {
 175         struct platform_device *pdev = to_platform_device(dev);
 176         struct resource *res;
 177         void __iomem *base;
 178
 179         rpc->dev = dev;
 180
 181         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 182         base = devm_ioremap_resource(&pdev->dev, res);
 183         if (IS_ERR(base))
 184                 return PTR_ERR(base);
 185
 186         rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 187                                             &rpcif_regmap_config);
 188         if (IS_ERR(rpc->regmap)) {
 189                 dev_err(&pdev->dev,
 190                         "failed to init regmap for rpcif, error %ld\n",
 191                         PTR_ERR(rpc->regmap));
 192                 return  PTR_ERR(rpc->regmap);
 193         }
 194
 195         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
 196         rpc->size = resource_size(res);
 197         rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
 198         if (IS_ERR(rpc->dirmap))
 199                 rpc->dirmap = NULL;
 200
 201         rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 202
 203         return PTR_ERR_OR_ZERO(rpc->rstc);
 204 }
 205 EXPORT_SYMBOL(rpcif_sw_init);
 206
 207 void rpcif_enable_rpm(struct rpcif *rpc)
 208 {
 209         pm_runtime_enable(rpc->dev);
 210 }
 211 EXPORT_SYMBOL(rpcif_enable_rpm);
 212
 213 void rpcif_disable_rpm(struct rpcif *rpc)
 214 {
 215         pm_runtime_put_sync(rpc->dev);
 216 }
 217 EXPORT_SYMBOL(rpcif_disable_rpm);
 218
 219 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
 220 {
 221         u32 dummy;
 222
 223         pm_runtime_get_sync(rpc->dev);
 224
 225         /*
 226          * NOTE: The 0x260 are undocumented bits, but they must be set.
 227          *       RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
 228          *       0x0 : the delay is biggest,
 229          *       0x1 : the delay is 2nd biggest,
 230          *       On H3 ES1.x, the value should be 0, while on others,
 231          *       the value should be 7.
 232          */
 233         regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
 234                      RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
 235
 236         /*
 237          * NOTE: The 0x1511144 are undocumented bits, but they must be set
 238          *       for RPCIF_PHYOFFSET1.
 239          *       The 0x31 are undocumented bits, but they must be set
 240          *       for RPCIF_PHYOFFSET2.
 241          */
 242         regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
 243                      RPCIF_PHYOFFSET1_DDRTMG(3));
 244         regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
 245                      RPCIF_PHYOFFSET2_OCTTMG(4));
 246
 247         if (hyperflash)
 248                 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
 249                                    RPCIF_PHYINT_WPVAL, 0);
 250
 251         regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
 252                      RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
 253                      RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 254         /* Set RCF after BSZ update */
 255         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 256         /* Dummy read according to spec */
 257         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 258         regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
 259                      RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
 260
 261         pm_runtime_put(rpc->dev);
 262
 263         rpc->bus_size = hyperflash ? 2 : 1;
 264 }
 265 EXPORT_SYMBOL(rpcif_hw_init);
 266
 267 static int wait_msg_xfer_end(struct rpcif *rpc)
 268 {
 269         u32 sts;
 270
 271         return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
 272                                         sts & RPCIF_CMNSR_TEND, 0,
 273                                         USEC_PER_SEC);
 274 }
 275
 276 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
 277 {
 278         if (rpc->bus_size == 2)
 279                 nbytes /= 2;
 280         nbytes = clamp(nbytes, 1U, 4U);
 281         return GENMASK(3, 4 - nbytes);
 282 }
 283
 284 static u8 rpcif_bit_size(u8 buswidth)
 285 {
 286         return buswidth > 4 ? 2 : ilog2(buswidth);
 287 }
 288
 289 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
 290                    size_t *len)
 291 {
 292         rpc->smcr = 0;
 293         rpc->smadr = 0;
 294         rpc->enable = 0;
 295         rpc->command = 0;
 296         rpc->option = 0;
 297         rpc->dummy = 0;
 298         rpc->ddr = 0;
 299         rpc->xferlen = 0;
 300
 301         if (op->cmd.buswidth) {
 302                 rpc->enable  = RPCIF_SMENR_CDE |
 303                         RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
 304                 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
 305                 if (op->cmd.ddr)
 306                         rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
 307         }
 308         if (op->ocmd.buswidth) {
 309                 rpc->enable  |= RPCIF_SMENR_OCDE |
 310                         RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
 311                 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
 312         }
 313
 314         if (op->addr.buswidth) {
 315                 rpc->enable |=
 316                         RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
 317                 if (op->addr.nbytes == 4)
 318                         rpc->enable |= RPCIF_SMENR_ADE(0xF);
 319                 else
 320                         rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
 321                                                 2, 3 - op->addr.nbytes));
 322                 if (op->addr.ddr)
 323                         rpc->ddr |= RPCIF_SMDRENR_ADDRE;
 324
 325                 if (offs && len)
 326                         rpc->smadr = *offs;
 327                 else
 328                         rpc->smadr = op->addr.val;
 329         }
 330
 331         if (op->dummy.buswidth) {
 332                 rpc->enable |= RPCIF_SMENR_DME;
 333                 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
 334                                                 op->dummy.buswidth);
 335         }
 336
 337         if (op->option.buswidth) {
 338                 rpc->enable |= RPCIF_SMENR_OPDE(
 339                         rpcif_bits_set(rpc, op->option.nbytes)) |
 340                         RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
 341                 if (op->option.ddr)
 342                         rpc->ddr |= RPCIF_SMDRENR_OPDRE;
 343                 rpc->option = op->option.val;
 344         }
 345
 346         rpc->dir = op->data.dir;
 347         if (op->data.buswidth) {
 348                 u32 nbytes;
 349
 350                 rpc->buffer = op->data.buf.in;
 351                 switch (op->data.dir) {
 352                 case RPCIF_DATA_IN:
 353                         rpc->smcr = RPCIF_SMCR_SPIRE;
 354                         break;
 355                 case RPCIF_DATA_OUT:
 356                         rpc->smcr = RPCIF_SMCR_SPIWE;
 357                         break;
 358                 default:
 359                         break;
 360                 }
 361                 if (op->data.ddr)
 362                         rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
 363
 364                 if (offs && len)
 365                         nbytes = *len;
 366                 else
 367                         nbytes = op->data.nbytes;
 368                 rpc->xferlen = nbytes;
 369
 370                 rpc->enable |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)) |
 371                         RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
 372         }
 373 }
 374 EXPORT_SYMBOL(rpcif_prepare);
 375
 376 int rpcif_manual_xfer(struct rpcif *rpc)
 377 {
 378         u32 smenr, smcr, pos = 0, max = 4;
 379         int ret = 0;
 380
 381         if (rpc->bus_size == 2)
 382                 max = 8;
 383
 384         pm_runtime_get_sync(rpc->dev);
 385
 386         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
 387                            RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
 388         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 389                            RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
 390         regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
 391         regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
 392         regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
 393         regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
 394         smenr = rpc->enable;
 395
 396         switch (rpc->dir) {
 397         case RPCIF_DATA_OUT:
 398                 while (pos < rpc->xferlen) {
 399                         u32 nbytes = rpc->xferlen - pos;
 400                         u32 data[2];
 401
 402                         smcr = rpc->smcr | RPCIF_SMCR_SPIE;
 403                         if (nbytes > max) {
 404                                 nbytes = max;
 405                                 smcr |= RPCIF_SMCR_SSLKP;
 406                         }
 407
 408                         memcpy(data, rpc->buffer + pos, nbytes);
 409                         if (nbytes > 4) {
 410                                 regmap_write(rpc->regmap, RPCIF_SMWDR1,
 411                                              data[0]);
 412                                 regmap_write(rpc->regmap, RPCIF_SMWDR0,
 413                                              data[1]);
 414                         } else if (nbytes > 2) {
 415                                 regmap_write(rpc->regmap, RPCIF_SMWDR0,
 416                                              data[0]);
 417                         } else  {
 418                                 regmap_write(rpc->regmap, RPCIF_SMWDR0,
 419                                              data[0] << 16);
 420                         }
 421
 422                         regmap_write(rpc->regmap, RPCIF_SMADR,
 423                                      rpc->smadr + pos);
 424                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 425                         regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
 426                         ret = wait_msg_xfer_end(rpc);
 427                         if (ret)
 428                                 goto err_out;
 429
 430                         pos += nbytes;
 431                         smenr = rpc->enable &
 432                                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
 433                 }
 434                 break;
 435         case RPCIF_DATA_IN:
 436                 /*
 437                  * RPC-IF spoils the data for the commands without an address
 438                  * phase (like RDID) in the manual mode, so we'll have to work
 439                  * around this issue by using the external address space read
 440                  * mode instead.
 441                  */
 442                 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
 443                         u32 dummy;
 444
 445                         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 446                                            RPCIF_CMNCR_MD, 0);
 447                         regmap_write(rpc->regmap, RPCIF_DRCR,
 448                                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
 449                         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 450                         regmap_write(rpc->regmap, RPCIF_DREAR,
 451                                      RPCIF_DREAR_EAC(1));
 452                         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 453                         regmap_write(rpc->regmap, RPCIF_DRENR,
 454                                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
 455                         regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
 456                         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 457                         memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
 458                         regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
 459                         /* Dummy read according to spec */
 460                         regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
 461                         break;
 462                 }
 463                 while (pos < rpc->xferlen) {
 464                         u32 nbytes = rpc->xferlen - pos;
 465                         u32 data[2];
 466
 467                         if (nbytes > max)
 468                                 nbytes = max;
 469
 470                         regmap_write(rpc->regmap, RPCIF_SMADR,
 471                                      rpc->smadr + pos);
 472                         regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
 473                         regmap_write(rpc->regmap, RPCIF_SMCR,
 474                                      rpc->smcr | RPCIF_SMCR_SPIE);
 475                         ret = wait_msg_xfer_end(rpc);
 476                         if (ret)
 477                                 goto err_out;
 478
 479                         if (nbytes > 4) {
 480                                 regmap_read(rpc->regmap, RPCIF_SMRDR1,
 481                                             &data[0]);
 482                                 regmap_read(rpc->regmap, RPCIF_SMRDR0,
 483                                             &data[1]);
 484                         } else if (nbytes > 2) {
 485                                 regmap_read(rpc->regmap, RPCIF_SMRDR0,
 486                                             &data[0]);
 487                         } else  {
 488                                 regmap_read(rpc->regmap, RPCIF_SMRDR0,
 489                                             &data[0]);
 490                                 data[0] >>= 16;
 491                         }
 492                         memcpy(rpc->buffer + pos, data, nbytes);
 493
 494                         pos += nbytes;
 495                 }
 496                 break;
 497         default:
 498                 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
 499                 regmap_write(rpc->regmap, RPCIF_SMCR,
 500                              rpc->smcr | RPCIF_SMCR_SPIE);
 501                 ret = wait_msg_xfer_end(rpc);
 502                 if (ret)
 503                         goto err_out;
 504         }
 505
 506 exit:
 507         pm_runtime_put(rpc->dev);
 508         return ret;
 509
 510 err_out:
 511         ret = reset_control_reset(rpc->rstc);
 512         rpcif_hw_init(rpc, rpc->bus_size == 2);
 513         goto exit;
 514 }
 515 EXPORT_SYMBOL(rpcif_manual_xfer);
 516
 517 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
 518 {
 519         loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
 520         size_t size = RPCIF_DIRMAP_SIZE - from;
 521
 522         if (len > size)
 523                 len = size;
 524
 525         pm_runtime_get_sync(rpc->dev);
 526
 527         regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
 528         regmap_write(rpc->regmap, RPCIF_DRCR, 0);
 529         regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
 530         regmap_write(rpc->regmap, RPCIF_DREAR,
 531                      RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
 532         regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
 533         regmap_write(rpc->regmap, RPCIF_DRENR,
 534                      rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
 535         regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
 536         regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
 537
 538         memcpy_fromio(buf, rpc->dirmap + from, len);
 539
 540         pm_runtime_put(rpc->dev);
 541
 542         return len;
 543 }
 544 EXPORT_SYMBOL(rpcif_dirmap_read);
 545
 546 static int rpcif_probe(struct platform_device *pdev)
 547 {
 548         struct platform_device *vdev;
 549         struct device_node *flash;
 550         const char *name;
 551
 552         flash = of_get_next_child(pdev->dev.of_node, NULL);
 553         if (!flash) {
 554                 dev_warn(&pdev->dev, "no flash node found\n");
 555                 return -ENODEV;
 556         }
 557
 558         if (of_device_is_compatible(flash, "jedec,spi-nor")) {
 559                 name = "rpc-if-spi";
 560         } else if (of_device_is_compatible(flash, "cfi-flash")) {
 561                 name = "rpc-if-hyperflash";
 562         } else  {
 563                 dev_warn(&pdev->dev, "unknown flash type\n");
 564                 return -ENODEV;
 565         }
 566
 567         vdev = platform_device_alloc(name, pdev->id);
 568         if (!vdev)
 569                 return -ENOMEM;
 570         vdev->dev.parent = &pdev->dev;
 571         platform_set_drvdata(pdev, vdev);
 572         return platform_device_add(vdev);
 573 }
 574
 575 static int rpcif_remove(struct platform_device *pdev)
 576 {
 577         struct platform_device *vdev = platform_get_drvdata(pdev);
 578
 579         platform_device_unregister(vdev);
 580
 581         return 0;
 582 }
 583
 584 static const struct of_device_id rpcif_of_match[] = {
 585         { .compatible = "renesas,rcar-gen3-rpc-if", },
 586         {},
 587 };
 588 MODULE_DEVICE_TABLE(of, rpcif_of_match);
 589
 590 static struct platform_driver rpcif_driver = {
 591         .probe  = rpcif_probe,
 592         .remove = rpcif_remove,
 593         .driver = {
 594                 .name = "rpc-if",
 595                 .of_match_table = rpcif_of_match,
 596         },
 597 };
 598 module_platform_driver(rpcif_driver);
 599
 600 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
 601 MODULE_LICENSE("GPL v2");