drivers/memory/omap-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPMC support functions
   4  *
   5  * Copyright (C) 2005-2006 Nokia Corporation
   6  *
   7  * Author: Juha Yrjola
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  */
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/ioport.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio/driver.h>
  21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  22 #include <linux/gpio/machine.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/omap-gpmc.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/sizes.h>
  33
  34 #include <linux/platform_data/mtd-nand-omap2.h>
  35
  36 #define DEVICE_NAME             "omap-gpmc"
  37
  38 /* GPMC register offsets */
  39 #define GPMC_REVISION           0x00
  40 #define GPMC_SYSCONFIG          0x10
  41 #define GPMC_SYSSTATUS          0x14
  42 #define GPMC_IRQSTATUS          0x18
  43 #define GPMC_IRQENABLE          0x1c
  44 #define GPMC_TIMEOUT_CONTROL    0x40
  45 #define GPMC_ERR_ADDRESS        0x44
  46 #define GPMC_ERR_TYPE           0x48
  47 #define GPMC_CONFIG             0x50
  48 #define GPMC_STATUS             0x54
  49 #define GPMC_PREFETCH_CONFIG1   0x1e0
  50 #define GPMC_PREFETCH_CONFIG2   0x1e4
  51 #define GPMC_PREFETCH_CONTROL   0x1ec
  52 #define GPMC_PREFETCH_STATUS    0x1f0
  53 #define GPMC_ECC_CONFIG         0x1f4
  54 #define GPMC_ECC_CONTROL        0x1f8
  55 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  56 #define GPMC_ECC1_RESULT        0x200
  57 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  58 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  59 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  60 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  64
  65 /* GPMC ECC control settings */
  66 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  67 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  68 #define GPMC_ECC_CTRL_ECCREG1           0x001
  69 #define GPMC_ECC_CTRL_ECCREG2           0x002
  70 #define GPMC_ECC_CTRL_ECCREG3           0x003
  71 #define GPMC_ECC_CTRL_ECCREG4           0x004
  72 #define GPMC_ECC_CTRL_ECCREG5           0x005
  73 #define GPMC_ECC_CTRL_ECCREG6           0x006
  74 #define GPMC_ECC_CTRL_ECCREG7           0x007
  75 #define GPMC_ECC_CTRL_ECCREG8           0x008
  76 #define GPMC_ECC_CTRL_ECCREG9           0x009
  77
  78 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  79
  80 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  81
  82 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  83 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  84 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  88
  89 #define GPMC_CS0_OFFSET         0x60
  90 #define GPMC_CS_SIZE            0x30
  91 #define GPMC_BCH_SIZE           0x10
  92
  93 /*
  94  * The first 1MB of GPMC address space is typically mapped to
  95  * the internal ROM. Never allocate the first page, to
  96  * facilitate bug detection; even if we didn't boot from ROM.
  97  * As GPMC minimum partition size is 16MB we can only start from
  98  * there.
  99  */
 100 #define GPMC_MEM_START          0x1000000
 101 #define GPMC_MEM_END            0x3FFFFFFF
 102
 103 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 104 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 105
 106 #define CS_NUM_SHIFT            24
 107 #define ENABLE_PREFETCH         (0x1 << 7)
 108 #define DMA_MPU_MODE            2
 109
 110 #define GPMC_REVISION_MAJOR(l)          (((l) >> 4) & 0xf)
 111 #define GPMC_REVISION_MINOR(l)          ((l) & 0xf)
 112
 113 #define GPMC_HAS_WR_ACCESS              0x1
 114 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 115 #define GPMC_HAS_MUX_AAD                0x4
 116
 117 #define GPMC_NR_WAITPINS                4
 118
 119 #define GPMC_CS_CONFIG1         0x00
 120 #define GPMC_CS_CONFIG2         0x04
 121 #define GPMC_CS_CONFIG3         0x08
 122 #define GPMC_CS_CONFIG4         0x0c
 123 #define GPMC_CS_CONFIG5         0x10
 124 #define GPMC_CS_CONFIG6         0x14
 125 #define GPMC_CS_CONFIG7         0x18
 126 #define GPMC_CS_NAND_COMMAND    0x1c
 127 #define GPMC_CS_NAND_ADDRESS    0x20
 128 #define GPMC_CS_NAND_DATA       0x24
 129
 130 /* Control Commands */
 131 #define GPMC_CONFIG_RDY_BSY     0x00000001
 132 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 133 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 134
 135 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 136 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 137 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 138 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 139 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 140 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 141 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 142 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
 143 /** CLKACTIVATIONTIME Max Ticks */
 144 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 145 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
 146 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 147 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 148 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 149 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 150 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
 151 /** WAITMONITORINGTIME Max Ticks */
 152 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 153 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
 154 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
 155 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 156 /** DEVICESIZE Max Value */
 157 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 158 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
 159 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 160 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
 161 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 162 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
 163 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 164 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 165 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 166 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 167
 168 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 169 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 170 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 171 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 172 /* All CONFIG7 bits except reserved bits */
 173 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 174                                          GPMC_CONFIG7_CSVALID_MASK |     \
 175                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 176
 177 #define GPMC_DEVICETYPE_NOR             0
 178 #define GPMC_DEVICETYPE_NAND            2
 179 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 180 #define WR_RD_PIN_MONITORING            0x00600000
 181
 182 /* ECC commands */
 183 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 184 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 185 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 186
 187 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 188
 189 enum gpmc_clk_domain {
 190         GPMC_CD_FCLK,
 191         GPMC_CD_CLK
 192 };
 193
 194 struct gpmc_cs_data {
 195         const char *name;
 196
 197 #define GPMC_CS_RESERVED        (1 << 0)
 198         u32 flags;
 199
 200         struct resource mem;
 201 };
 202
 203 /* Structure to save gpmc cs context */
 204 struct gpmc_cs_config {
 205         u32 config1;
 206         u32 config2;
 207         u32 config3;
 208         u32 config4;
 209         u32 config5;
 210         u32 config6;
 211         u32 config7;
 212         int is_valid;
 213 };
 214
 215 /*
 216  * Structure to save/restore gpmc context
 217  * to support core off on OMAP3
 218  */
 219 struct omap3_gpmc_regs {
 220         u32 sysconfig;
 221         u32 irqenable;
 222         u32 timeout_ctrl;
 223         u32 config;
 224         u32 prefetch_config1;
 225         u32 prefetch_config2;
 226         u32 prefetch_control;
 227         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 228 };
 229
 230 struct gpmc_device {
 231         struct device *dev;
 232         int irq;
 233         struct irq_chip irq_chip;
 234         struct gpio_chip gpio_chip;
 235         int nirqs;
 236 };
 237
 238 static struct irq_domain *gpmc_irq_domain;
 239
 240 static struct resource  gpmc_mem_root;
 241 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 242 static DEFINE_SPINLOCK(gpmc_mem_lock);
 243 /* Define chip-selects as reserved by default until probe completes */
 244 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 245 static unsigned int gpmc_nr_waitpins;
 246 static unsigned int gpmc_capability;
 247 static void __iomem *gpmc_base;
 248
 249 static struct clk *gpmc_l3_clk;
 250
 251 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 252
 253 static void gpmc_write_reg(int idx, u32 val)
 254 {
 255         writel_relaxed(val, gpmc_base + idx);
 256 }
 257
 258 static u32 gpmc_read_reg(int idx)
 259 {
 260         return readl_relaxed(gpmc_base + idx);
 261 }
 262
 263 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 264 {
 265         void __iomem *reg_addr;
 266
 267         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 268         writel_relaxed(val, reg_addr);
 269 }
 270
 271 static u32 gpmc_cs_read_reg(int cs, int idx)
 272 {
 273         void __iomem *reg_addr;
 274
 275         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 276         return readl_relaxed(reg_addr);
 277 }
 278
 279 /* TODO: Add support for gpmc_fck to clock framework and use it */
 280 static unsigned long gpmc_get_fclk_period(void)
 281 {
 282         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 283
 284         rate /= 1000;
 285         rate = 1000000000 / rate;       /* In picoseconds */
 286
 287         return rate;
 288 }
 289
 290 /**
 291  * gpmc_get_clk_period - get period of selected clock domain in ps
 292  * @cs: Chip Select Region.
 293  * @cd: Clock Domain.
 294  *
 295  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 296  * prior to calling this function with GPMC_CD_CLK.
 297  */
 298 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 299 {
 300         unsigned long tick_ps = gpmc_get_fclk_period();
 301         u32 l;
 302         int div;
 303
 304         switch (cd) {
 305         case GPMC_CD_CLK:
 306                 /* get current clk divider */
 307                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 308                 div = (l & 0x03) + 1;
 309                 /* get GPMC_CLK period */
 310                 tick_ps *= div;
 311                 break;
 312         case GPMC_CD_FCLK:
 313         default:
 314                 break;
 315         }
 316
 317         return tick_ps;
 318 }
 319
 320 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 321                                          enum gpmc_clk_domain cd)
 322 {
 323         unsigned long tick_ps;
 324
 325         /* Calculate in picosecs to yield more exact results */
 326         tick_ps = gpmc_get_clk_period(cs, cd);
 327
 328         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 329 }
 330
 331 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 332 {
 333         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 334 }
 335
 336 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 337 {
 338         unsigned long tick_ps;
 339
 340         /* Calculate in picosecs to yield more exact results */
 341         tick_ps = gpmc_get_fclk_period();
 342
 343         return (time_ps + tick_ps - 1) / tick_ps;
 344 }
 345
 346 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 347                                          enum gpmc_clk_domain cd)
 348 {
 349         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 350 }
 351
 352 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 353 {
 354         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 355 }
 356
 357 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 358 {
 359         return ticks * gpmc_get_fclk_period();
 360 }
 361
 362 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 363 {
 364         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 365
 366         return ticks * gpmc_get_fclk_period();
 367 }
 368
 369 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 370 {
 371         u32 l;
 372
 373         l = gpmc_cs_read_reg(cs, reg);
 374         if (value)
 375                 l |= mask;
 376         else
 377                 l &= ~mask;
 378         gpmc_cs_write_reg(cs, reg, l);
 379 }
 380
 381 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 382 {
 383         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 384                            GPMC_CONFIG1_TIME_PARA_GRAN,
 385                            p->time_para_granularity);
 386         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 387                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 388         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 389                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 391                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 393                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 395                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 396                            p->cycle2cyclesamecsen);
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 398                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 399                            p->cycle2cyclediffcsen);
 400 }
 401
 402 #ifdef CONFIG_OMAP_GPMC_DEBUG
 403 /**
 404  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 405  * @cs:      Chip Select Region
 406  * @reg:     GPMC_CS_CONFIGn register offset.
 407  * @st_bit:  Start Bit
 408  * @end_bit: End Bit. Must be >= @st_bit.
 409  * @max:     Maximum parameter value (before optional @shift).
 410  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 411  * @name:    DTS node name, w/o "gpmc,"
 412  * @cd:      Clock Domain of timing parameter.
 413  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 414  * @raw:     Raw Format Option.
 415  *           raw format:  gpmc,name = <value>
 416  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 417  *           Where x ns -- y ns result in the same tick value.
 418  *           When @max is exceeded, "invalid" is printed inside comment.
 419  * @noval:   Parameter values equal to 0 are not printed.
 420  * @return:  Specified timing parameter (after optional @shift).
 421  *
 422  */
 423 static int get_gpmc_timing_reg(
 424         /* timing specifiers */
 425         int cs, int reg, int st_bit, int end_bit, int max,
 426         const char *name, const enum gpmc_clk_domain cd,
 427         /* value transform */
 428         int shift,
 429         /* format specifiers */
 430         bool raw, bool noval)
 431 {
 432         u32 l;
 433         int nr_bits;
 434         int mask;
 435         bool invalid;
 436
 437         l = gpmc_cs_read_reg(cs, reg);
 438         nr_bits = end_bit - st_bit + 1;
 439         mask = (1 << nr_bits) - 1;
 440         l = (l >> st_bit) & mask;
 441         if (!max)
 442                 max = mask;
 443         invalid = l > max;
 444         if (shift)
 445                 l = (shift << l);
 446         if (noval && (l == 0))
 447                 return 0;
 448         if (!raw) {
 449                 /* DTS tick format for timings in ns */
 450                 unsigned int time_ns;
 451                 unsigned int time_ns_min = 0;
 452
 453                 if (l)
 454                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 455                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 456                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 457                         name, time_ns, time_ns_min, time_ns, l,
 458                         invalid ? "; invalid " : " ");
 459         } else {
 460                 /* raw format */
 461                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 462                         invalid ? " /* invalid */" : "");
 463         }
 464
 465         return l;
 466 }
 467
 468 #define GPMC_PRINT_CONFIG(cs, config) \
 469         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 470                 gpmc_cs_read_reg(cs, config))
 471 #define GPMC_GET_RAW(reg, st, end, field) \
 472         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 473 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 474         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 475 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 476         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 477 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 479 #define GPMC_GET_TICKS(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 481 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 483 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 485
 486 static void gpmc_show_regs(int cs, const char *desc)
 487 {
 488         pr_info("gpmc cs%i %s:\n", cs, desc);
 489         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 490         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 491         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 492         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 495 }
 496
 497 /*
 498  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 499  * see commit c9fb809.
 500  */
 501 static void gpmc_cs_show_timings(int cs, const char *desc)
 502 {
 503         gpmc_show_regs(cs, desc);
 504
 505         pr_info("gpmc cs%i access configuration:\n", cs);
 506         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 507         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 508         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 509                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 510         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 511         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 512         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 513         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 514                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 515                                "burst-length");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 521
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 523
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 525
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 528
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 531
 532         pr_info("gpmc cs%i timings configuration:\n", cs);
 533         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 534         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 535         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 536
 537         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 540         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 541                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 542                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 543                                 "adv-aad-mux-rd-off-ns");
 544                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 545                                 "adv-aad-mux-wr-off-ns");
 546         }
 547
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 549         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 550         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 551                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 552                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 553         }
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 556
 557         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 558         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 560
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 562
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 565
 566         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 567                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 568                               "wait-monitoring-ns", GPMC_CD_CLK);
 569         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 570                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 571                               "clk-activation-ns", GPMC_CD_FCLK);
 572
 573         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 574         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 575 }
 576 #else
 577 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 578 {
 579 }
 580 #endif
 581
 582 /**
 583  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 584  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 585  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 586  *
 587  * @cs:      Chip Select Region.
 588  * @reg:     GPMC_CS_CONFIGn register offset.
 589  * @st_bit:  Start Bit
 590  * @end_bit: End Bit. Must be >= @st_bit.
 591  * @max:     Maximum parameter value.
 592  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 593  * @time:    Timing parameter in ns.
 594  * @cd:      Timing parameter clock domain.
 595  * @name:    Timing parameter name.
 596  * @return:  0 on success, -1 on error.
 597  */
 598 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 599                                int time, enum gpmc_clk_domain cd, const char *name)
 600 {
 601         u32 l;
 602         int ticks, mask, nr_bits;
 603
 604         if (time == 0)
 605                 ticks = 0;
 606         else
 607                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 608         nr_bits = end_bit - st_bit + 1;
 609         mask = (1 << nr_bits) - 1;
 610
 611         if (!max)
 612                 max = mask;
 613
 614         if (ticks > max) {
 615                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 616                        __func__, cs, name, time, ticks, max);
 617
 618                 return -1;
 619         }
 620
 621         l = gpmc_cs_read_reg(cs, reg);
 622 #ifdef CONFIG_OMAP_GPMC_DEBUG
 623         pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 624                 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 625                         (l >> st_bit) & mask, time);
 626 #endif
 627         l &= ~(mask << st_bit);
 628         l |= ticks << st_bit;
 629         gpmc_cs_write_reg(cs, reg, l);
 630
 631         return 0;
 632 }
 633
 634 /**
 635  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 636  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 637  * read  --> don't sample bus too early
 638  * write --> data is longer on bus
 639  *
 640  * Formula:
 641  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 642  *                    / waitmonitoring_ticks)
 643  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 644  * div <= 0 check.
 645  *
 646  * @wait_monitoring: WAITMONITORINGTIME in ns.
 647  * @return:          -1 on failure to scale, else proper divider > 0.
 648  */
 649 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 650 {
 651         int div = gpmc_ns_to_ticks(wait_monitoring);
 652
 653         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 654         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 655
 656         if (div > 4)
 657                 return -1;
 658         if (div <= 0)
 659                 div = 1;
 660
 661         return div;
 662 }
 663
 664 /**
 665  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 666  * @sync_clk: GPMC_CLK period in ps.
 667  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 668  *            Else, returns -1.
 669  */
 670 int gpmc_calc_divider(unsigned int sync_clk)
 671 {
 672         int div = gpmc_ps_to_ticks(sync_clk);
 673
 674         if (div > 4)
 675                 return -1;
 676         if (div <= 0)
 677                 div = 1;
 678
 679         return div;
 680 }
 681
 682 /**
 683  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 684  * @cs:     Chip Select Region.
 685  * @t:      GPMC timing parameters.
 686  * @s:      GPMC timing settings.
 687  * @return: 0 on success, -1 on error.
 688  */
 689 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 690                         const struct gpmc_settings *s)
 691 {
 692         int div, ret;
 693         u32 l;
 694
 695         div = gpmc_calc_divider(t->sync_clk);
 696         if (div < 0)
 697                 return -EINVAL;
 698
 699         /*
 700          * See if we need to change the divider for waitmonitoringtime.
 701          *
 702          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 703          * pure asynchronous accesses, i.e. both read and write asynchronous.
 704          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 705          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 706          *
 707          * This statement must not change div to scale async WAITMONITORINGTIME
 708          * to protect mixed synchronous and asynchronous accesses.
 709          *
 710          * We raise an error later if WAITMONITORINGTIME does not fit.
 711          */
 712         if (!s->sync_read && !s->sync_write &&
 713             (s->wait_on_read || s->wait_on_write)
 714            ) {
 715                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 716                 if (div < 0) {
 717                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 718                                __func__,
 719                                t->wait_monitoring
 720                                );
 721                         return -ENXIO;
 722                 }
 723         }
 724
 725         ret = 0;
 726         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 727                                    GPMC_CD_FCLK, "cs_on");
 728         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 729                                    GPMC_CD_FCLK, "cs_rd_off");
 730         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 731                                    GPMC_CD_FCLK, "cs_wr_off");
 732         if (ret)
 733                 return -ENXIO;
 734
 735         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 736                                    GPMC_CD_FCLK, "adv_on");
 737         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 738                                    GPMC_CD_FCLK, "adv_rd_off");
 739         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 740                                    GPMC_CD_FCLK, "adv_wr_off");
 741         if (ret)
 742                 return -ENXIO;
 743
 744         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 745                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 746                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 747                                            "adv_aad_mux_on");
 748                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 749                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 750                                            "adv_aad_mux_rd_off");
 751                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 752                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 753                                            "adv_aad_mux_wr_off");
 754                 if (ret)
 755                         return -ENXIO;
 756         }
 757
 758         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 759                                    GPMC_CD_FCLK, "oe_on");
 760         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 761                                    GPMC_CD_FCLK, "oe_off");
 762         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 763                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 764                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 765                                            "oe_aad_mux_on");
 766                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 767                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 768                                            "oe_aad_mux_off");
 769         }
 770         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 771                                    GPMC_CD_FCLK, "we_on");
 772         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 773                                    GPMC_CD_FCLK, "we_off");
 774         if (ret)
 775                 return -ENXIO;
 776
 777         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 778                                    GPMC_CD_FCLK, "rd_cycle");
 779         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 780                                    GPMC_CD_FCLK, "wr_cycle");
 781         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 782                                    GPMC_CD_FCLK, "access");
 783         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 784                                    t->page_burst_access, GPMC_CD_FCLK,
 785                                    "page_burst_access");
 786         if (ret)
 787                 return -ENXIO;
 788
 789         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 790                                    t->bus_turnaround, GPMC_CD_FCLK,
 791                                    "bus_turnaround");
 792         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 793                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 794                                    "cycle2cycle_delay");
 795         if (ret)
 796                 return -ENXIO;
 797
 798         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 799                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 800                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 801                                            "wr_data_mux_bus");
 802                 if (ret)
 803                         return -ENXIO;
 804         }
 805         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 806                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 807                                            t->wr_access, GPMC_CD_FCLK,
 808                                            "wr_access");
 809                 if (ret)
 810                         return -ENXIO;
 811         }
 812
 813         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 814         l &= ~0x03;
 815         l |= (div - 1);
 816         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 817
 818         ret = 0;
 819         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 820                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 821                                    t->wait_monitoring, GPMC_CD_CLK,
 822                                    "wait_monitoring");
 823         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 824                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 825                                    t->clk_activation, GPMC_CD_FCLK,
 826                                    "clk_activation");
 827         if (ret)
 828                 return -ENXIO;
 829
 830 #ifdef CONFIG_OMAP_GPMC_DEBUG
 831         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 832                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 833 #endif
 834
 835         gpmc_cs_bool_timings(cs, &t->bool_timings);
 836         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 837
 838         return 0;
 839 }
 840
 841 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 842 {
 843         u32 l;
 844         u32 mask;
 845
 846         /*
 847          * Ensure that base address is aligned on a
 848          * boundary equal to or greater than size.
 849          */
 850         if (base & (size - 1))
 851                 return -EINVAL;
 852
 853         base >>= GPMC_CHUNK_SHIFT;
 854         mask = (1 << GPMC_SECTION_SHIFT) - size;
 855         mask >>= GPMC_CHUNK_SHIFT;
 856         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 857
 858         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 859         l &= ~GPMC_CONFIG7_MASK;
 860         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 861         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 862         l |= GPMC_CONFIG7_CSVALID;
 863         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 864
 865         return 0;
 866 }
 867
 868 static void gpmc_cs_enable_mem(int cs)
 869 {
 870         u32 l;
 871
 872         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 873         l |= GPMC_CONFIG7_CSVALID;
 874         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 875 }
 876
 877 static void gpmc_cs_disable_mem(int cs)
 878 {
 879         u32 l;
 880
 881         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 882         l &= ~GPMC_CONFIG7_CSVALID;
 883         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 884 }
 885
 886 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 887 {
 888         u32 l;
 889         u32 mask;
 890
 891         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 892         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 893         mask = (l >> 8) & 0x0f;
 894         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 895 }
 896
 897 static int gpmc_cs_mem_enabled(int cs)
 898 {
 899         u32 l;
 900
 901         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 902         return l & GPMC_CONFIG7_CSVALID;
 903 }
 904
 905 static void gpmc_cs_set_reserved(int cs, int reserved)
 906 {
 907         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 908
 909         gpmc->flags |= GPMC_CS_RESERVED;
 910 }
 911
 912 static bool gpmc_cs_reserved(int cs)
 913 {
 914         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 915
 916         return gpmc->flags & GPMC_CS_RESERVED;
 917 }
 918
 919 static unsigned long gpmc_mem_align(unsigned long size)
 920 {
 921         int order;
 922
 923         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 924         order = GPMC_CHUNK_SHIFT - 1;
 925         do {
 926                 size >>= 1;
 927                 order++;
 928         } while (size);
 929         size = 1 << order;
 930         return size;
 931 }
 932
 933 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 934 {
 935         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 936         struct resource *res = &gpmc->mem;
 937         int r;
 938
 939         size = gpmc_mem_align(size);
 940         spin_lock(&gpmc_mem_lock);
 941         res->start = base;
 942         res->end = base + size - 1;
 943         r = request_resource(&gpmc_mem_root, res);
 944         spin_unlock(&gpmc_mem_lock);
 945
 946         return r;
 947 }
 948
 949 static int gpmc_cs_delete_mem(int cs)
 950 {
 951         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 952         struct resource *res = &gpmc->mem;
 953         int r;
 954
 955         spin_lock(&gpmc_mem_lock);
 956         r = release_resource(res);
 957         res->start = 0;
 958         res->end = 0;
 959         spin_unlock(&gpmc_mem_lock);
 960
 961         return r;
 962 }
 963
 964 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 965 {
 966         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 967         struct resource *res = &gpmc->mem;
 968         int r = -1;
 969
 970         if (cs >= gpmc_cs_num) {
 971                 pr_err("%s: requested chip-select is disabled\n", __func__);
 972                 return -ENODEV;
 973         }
 974         size = gpmc_mem_align(size);
 975         if (size > (1 << GPMC_SECTION_SHIFT))
 976                 return -ENOMEM;
 977
 978         spin_lock(&gpmc_mem_lock);
 979         if (gpmc_cs_reserved(cs)) {
 980                 r = -EBUSY;
 981                 goto out;
 982         }
 983         if (gpmc_cs_mem_enabled(cs))
 984                 r = adjust_resource(res, res->start & ~(size - 1), size);
 985         if (r < 0)
 986                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 987                                       size, NULL, NULL);
 988         if (r < 0)
 989                 goto out;
 990
 991         /* Disable CS while changing base address and size mask */
 992         gpmc_cs_disable_mem(cs);
 993
 994         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 995         if (r < 0) {
 996                 release_resource(res);
 997                 goto out;
 998         }
 999
1000         /* Enable CS */
1001         gpmc_cs_enable_mem(cs);
1002         *base = res->start;
1003         gpmc_cs_set_reserved(cs, 1);
1004 out:
1005         spin_unlock(&gpmc_mem_lock);
1006         return r;
1007 }
1008 EXPORT_SYMBOL(gpmc_cs_request);
1009
1010 void gpmc_cs_free(int cs)
1011 {
1012         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1013         struct resource *res = &gpmc->mem;
1014
1015         spin_lock(&gpmc_mem_lock);
1016         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1017                 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1018                 spin_unlock(&gpmc_mem_lock);
1019                 return;
1020         }
1021         gpmc_cs_disable_mem(cs);
1022         if (res->flags)
1023                 release_resource(res);
1024         gpmc_cs_set_reserved(cs, 0);
1025         spin_unlock(&gpmc_mem_lock);
1026 }
1027 EXPORT_SYMBOL(gpmc_cs_free);
1028
1029 /**
1030  * gpmc_configure - write request to configure gpmc
1031  * @cmd: command type
1032  * @wval: value to write
1033  * @return status of the operation
1034  */
1035 int gpmc_configure(int cmd, int wval)
1036 {
1037         u32 regval;
1038
1039         switch (cmd) {
1040         case GPMC_CONFIG_WP:
1041                 regval = gpmc_read_reg(GPMC_CONFIG);
1042                 if (wval)
1043                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1044                 else
1045                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1046                 gpmc_write_reg(GPMC_CONFIG, regval);
1047                 break;
1048
1049         default:
1050                 pr_err("%s: command not supported\n", __func__);
1051                 return -EINVAL;
1052         }
1053
1054         return 0;
1055 }
1056 EXPORT_SYMBOL(gpmc_configure);
1057
1058 static bool gpmc_nand_writebuffer_empty(void)
1059 {
1060         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1061                 return true;
1062
1063         return false;
1064 }
1065
1066 static struct gpmc_nand_ops nand_ops = {
1067         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1068 };
1069
1070 /**
1071  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1072  * @reg: the GPMC NAND register map exclusive for NAND use.
1073  * @cs: GPMC chip select number on which the NAND sits. The
1074  *      register map returned will be specific to this chip select.
1075  *
1076  * Returns NULL on error e.g. invalid cs.
1077  */
1078 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1079 {
1080         int i;
1081
1082         if (cs >= gpmc_cs_num)
1083                 return NULL;
1084
1085         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1086                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1087         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1088                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1089         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1090                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1091         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1092         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1093         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1094         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1095         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1096         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1097         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1098         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1099
1100         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1101                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1102                                            GPMC_BCH_SIZE * i;
1103                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1104                                            GPMC_BCH_SIZE * i;
1105                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1106                                            GPMC_BCH_SIZE * i;
1107                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1108                                            GPMC_BCH_SIZE * i;
1109                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1110                                            i * GPMC_BCH_SIZE;
1111                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1112                                            i * GPMC_BCH_SIZE;
1113                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1114                                            i * GPMC_BCH_SIZE;
1115         }
1116
1117         return &nand_ops;
1118 }
1119 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1120
1121 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1122                                                 struct gpmc_settings *s,
1123                                                 int freq, int latency)
1124 {
1125         struct gpmc_device_timings dev_t;
1126         const int t_cer  = 15;
1127         const int t_avdp = 12;
1128         const int t_cez  = 20; /* max of t_cez, t_oez */
1129         const int t_wpl  = 40;
1130         const int t_wph  = 30;
1131         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1132
1133         switch (freq) {
1134         case 104:
1135                 min_gpmc_clk_period = 9600; /* 104 MHz */
1136                 t_ces   = 3;
1137                 t_avds  = 4;
1138                 t_avdh  = 2;
1139                 t_ach   = 3;
1140                 t_aavdh = 6;
1141                 t_rdyo  = 6;
1142                 break;
1143         case 83:
1144                 min_gpmc_clk_period = 12000; /* 83 MHz */
1145                 t_ces   = 5;
1146                 t_avds  = 4;
1147                 t_avdh  = 2;
1148                 t_ach   = 6;
1149                 t_aavdh = 6;
1150                 t_rdyo  = 9;
1151                 break;
1152         case 66:
1153                 min_gpmc_clk_period = 15000; /* 66 MHz */
1154                 t_ces   = 6;
1155                 t_avds  = 5;
1156                 t_avdh  = 2;
1157                 t_ach   = 6;
1158                 t_aavdh = 6;
1159                 t_rdyo  = 11;
1160                 break;
1161         default:
1162                 min_gpmc_clk_period = 18500; /* 54 MHz */
1163                 t_ces   = 7;
1164                 t_avds  = 7;
1165                 t_avdh  = 7;
1166                 t_ach   = 9;
1167                 t_aavdh = 7;
1168                 t_rdyo  = 15;
1169                 break;
1170         }
1171
1172         /* Set synchronous read timings */
1173         memset(&dev_t, 0, sizeof(dev_t));
1174
1175         if (!s->sync_write) {
1176                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1177                 dev_t.t_wpl = t_wpl * 1000;
1178                 dev_t.t_wph = t_wph * 1000;
1179                 dev_t.t_aavdh = t_aavdh * 1000;
1180         }
1181         dev_t.ce_xdelay = true;
1182         dev_t.avd_xdelay = true;
1183         dev_t.oe_xdelay = true;
1184         dev_t.we_xdelay = true;
1185         dev_t.clk = min_gpmc_clk_period;
1186         dev_t.t_bacc = dev_t.clk;
1187         dev_t.t_ces = t_ces * 1000;
1188         dev_t.t_avds = t_avds * 1000;
1189         dev_t.t_avdh = t_avdh * 1000;
1190         dev_t.t_ach = t_ach * 1000;
1191         dev_t.cyc_iaa = (latency + 1);
1192         dev_t.t_cez_r = t_cez * 1000;
1193         dev_t.t_cez_w = dev_t.t_cez_r;
1194         dev_t.cyc_aavdh_oe = 1;
1195         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1196
1197         gpmc_calc_timings(t, s, &dev_t);
1198 }
1199
1200 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1201                                   int latency,
1202                                   struct gpmc_onenand_info *info)
1203 {
1204         int ret;
1205         struct gpmc_timings gpmc_t;
1206         struct gpmc_settings gpmc_s;
1207
1208         gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1209
1210         info->sync_read = gpmc_s.sync_read;
1211         info->sync_write = gpmc_s.sync_write;
1212         info->burst_len = gpmc_s.burst_len;
1213
1214         if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1215                 return 0;
1216
1217         gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1218
1219         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1220         if (ret < 0)
1221                 return ret;
1222
1223         return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1224 }
1225 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1226
1227 int gpmc_get_client_irq(unsigned int irq_config)
1228 {
1229         if (!gpmc_irq_domain) {
1230                 pr_warn("%s called before GPMC IRQ domain available\n",
1231                         __func__);
1232                 return 0;
1233         }
1234
1235         /* we restrict this to NAND IRQs only */
1236         if (irq_config >= GPMC_NR_NAND_IRQS)
1237                 return 0;
1238
1239         return irq_create_mapping(gpmc_irq_domain, irq_config);
1240 }
1241
1242 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1243 {
1244         u32 regval;
1245
1246         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1247         if (hwirq >= GPMC_NR_NAND_IRQS)
1248                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1249
1250         regval = gpmc_read_reg(GPMC_IRQENABLE);
1251         if (endis)
1252                 regval |= BIT(hwirq);
1253         else
1254                 regval &= ~BIT(hwirq);
1255         gpmc_write_reg(GPMC_IRQENABLE, regval);
1256
1257         return 0;
1258 }
1259
1260 static void gpmc_irq_disable(struct irq_data *p)
1261 {
1262         gpmc_irq_endis(p->hwirq, false);
1263 }
1264
1265 static void gpmc_irq_enable(struct irq_data *p)
1266 {
1267         gpmc_irq_endis(p->hwirq, true);
1268 }
1269
1270 static void gpmc_irq_mask(struct irq_data *d)
1271 {
1272         gpmc_irq_endis(d->hwirq, false);
1273 }
1274
1275 static void gpmc_irq_unmask(struct irq_data *d)
1276 {
1277         gpmc_irq_endis(d->hwirq, true);
1278 }
1279
1280 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1281 {
1282         u32 regval;
1283
1284         /* NAND IRQs polarity is not configurable */
1285         if (hwirq < GPMC_NR_NAND_IRQS)
1286                 return;
1287
1288         /* WAITPIN starts at BIT 8 */
1289         hwirq += 8 - GPMC_NR_NAND_IRQS;
1290
1291         regval = gpmc_read_reg(GPMC_CONFIG);
1292         if (rising_edge)
1293                 regval &= ~BIT(hwirq);
1294         else
1295                 regval |= BIT(hwirq);
1296
1297         gpmc_write_reg(GPMC_CONFIG, regval);
1298 }
1299
1300 static void gpmc_irq_ack(struct irq_data *d)
1301 {
1302         unsigned int hwirq = d->hwirq;
1303
1304         /* skip reserved bits */
1305         if (hwirq >= GPMC_NR_NAND_IRQS)
1306                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1307
1308         /* Setting bit to 1 clears (or Acks) the interrupt */
1309         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1310 }
1311
1312 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1313 {
1314         /* can't set type for NAND IRQs */
1315         if (d->hwirq < GPMC_NR_NAND_IRQS)
1316                 return -EINVAL;
1317
1318         /* We can support either rising or falling edge at a time */
1319         if (trigger == IRQ_TYPE_EDGE_FALLING)
1320                 gpmc_irq_edge_config(d->hwirq, false);
1321         else if (trigger == IRQ_TYPE_EDGE_RISING)
1322                 gpmc_irq_edge_config(d->hwirq, true);
1323         else
1324                 return -EINVAL;
1325
1326         return 0;
1327 }
1328
1329 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1330                         irq_hw_number_t hw)
1331 {
1332         struct gpmc_device *gpmc = d->host_data;
1333
1334         irq_set_chip_data(virq, gpmc);
1335         if (hw < GPMC_NR_NAND_IRQS) {
1336                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1337                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1338                                          handle_simple_irq);
1339         } else {
1340                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1341                                          handle_edge_irq);
1342         }
1343
1344         return 0;
1345 }
1346
1347 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1348         .map    = gpmc_irq_map,
1349         .xlate  = irq_domain_xlate_twocell,
1350 };
1351
1352 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1353 {
1354         int hwirq, virq;
1355         u32 regval, regvalx;
1356         struct gpmc_device *gpmc = data;
1357
1358         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1359         regvalx = regval;
1360
1361         if (!regval)
1362                 return IRQ_NONE;
1363
1364         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1365                 /* skip reserved status bits */
1366                 if (hwirq == GPMC_NR_NAND_IRQS)
1367                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1368
1369                 if (regvalx & BIT(hwirq)) {
1370                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1371                         if (!virq) {
1372                                 dev_warn(gpmc->dev,
1373                                          "spurious irq detected hwirq %d, virq %d\n",
1374                                          hwirq, virq);
1375                         }
1376
1377                         generic_handle_irq(virq);
1378                 }
1379         }
1380
1381         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1382
1383         return IRQ_HANDLED;
1384 }
1385
1386 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1387 {
1388         u32 regval;
1389         int rc;
1390
1391         /* Disable interrupts */
1392         gpmc_write_reg(GPMC_IRQENABLE, 0);
1393
1394         /* clear interrupts */
1395         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1396         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1397
1398         gpmc->irq_chip.name = "gpmc";
1399         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1400         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1401         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1402         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1403         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1404         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1405
1406         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1407                                                 gpmc->nirqs,
1408                                                 &gpmc_irq_domain_ops,
1409                                                 gpmc);
1410         if (!gpmc_irq_domain) {
1411                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1412                 return -ENODEV;
1413         }
1414
1415         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1416         if (rc) {
1417                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1418                         gpmc->irq, rc);
1419                 irq_domain_remove(gpmc_irq_domain);
1420                 gpmc_irq_domain = NULL;
1421         }
1422
1423         return rc;
1424 }
1425
1426 static int gpmc_free_irq(struct gpmc_device *gpmc)
1427 {
1428         int hwirq;
1429
1430         free_irq(gpmc->irq, gpmc);
1431
1432         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1433                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1434
1435         irq_domain_remove(gpmc_irq_domain);
1436         gpmc_irq_domain = NULL;
1437
1438         return 0;
1439 }
1440
1441 static void gpmc_mem_exit(void)
1442 {
1443         int cs;
1444
1445         for (cs = 0; cs < gpmc_cs_num; cs++) {
1446                 if (!gpmc_cs_mem_enabled(cs))
1447                         continue;
1448                 gpmc_cs_delete_mem(cs);
1449         }
1450 }
1451
1452 static void gpmc_mem_init(void)
1453 {
1454         int cs;
1455
1456         gpmc_mem_root.start = GPMC_MEM_START;
1457         gpmc_mem_root.end = GPMC_MEM_END;
1458
1459         /* Reserve all regions that has been set up by bootloader */
1460         for (cs = 0; cs < gpmc_cs_num; cs++) {
1461                 u32 base, size;
1462
1463                 if (!gpmc_cs_mem_enabled(cs))
1464                         continue;
1465                 gpmc_cs_get_memconf(cs, &base, &size);
1466                 if (gpmc_cs_insert_mem(cs, base, size)) {
1467                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1468                                 __func__, cs, base, base + size);
1469                         gpmc_cs_disable_mem(cs);
1470                 }
1471         }
1472 }
1473
1474 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1475 {
1476         u32 temp;
1477         int div;
1478
1479         div = gpmc_calc_divider(sync_clk);
1480         temp = gpmc_ps_to_ticks(time_ps);
1481         temp = (temp + div - 1) / div;
1482         return gpmc_ticks_to_ps(temp * div);
1483 }
1484
1485 /* XXX: can the cycles be avoided ? */
1486 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1487                                        struct gpmc_device_timings *dev_t,
1488                                        bool mux)
1489 {
1490         u32 temp;
1491
1492         /* adv_rd_off */
1493         temp = dev_t->t_avdp_r;
1494         /* XXX: mux check required ? */
1495         if (mux) {
1496                 /* XXX: t_avdp not to be required for sync, only added for tusb
1497                  * this indirectly necessitates requirement of t_avdp_r and
1498                  * t_avdp_w instead of having a single t_avdp
1499                  */
1500                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1501                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1502         }
1503         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1504
1505         /* oe_on */
1506         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1507         if (mux) {
1508                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1509                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1510                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1511         }
1512         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1513
1514         /* access */
1515         /* XXX: any scope for improvement ?, by combining oe_on
1516          * and clk_activation, need to check whether
1517          * access = clk_activation + round to sync clk ?
1518          */
1519         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1520         temp += gpmc_t->clk_activation;
1521         if (dev_t->cyc_oe)
1522                 temp = max_t(u32, temp, gpmc_t->oe_on +
1523                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1524         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1525
1526         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1527         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1528
1529         /* rd_cycle */
1530         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1531         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1532                                                         gpmc_t->access;
1533         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1534         if (dev_t->t_ce_rdyz)
1535                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1536         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1537
1538         return 0;
1539 }
1540
1541 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1542                                         struct gpmc_device_timings *dev_t,
1543                                         bool mux)
1544 {
1545         u32 temp;
1546
1547         /* adv_wr_off */
1548         temp = dev_t->t_avdp_w;
1549         if (mux) {
1550                 temp = max_t(u32, temp,
1551                         gpmc_t->clk_activation + dev_t->t_avdh);
1552                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1553         }
1554         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1555
1556         /* wr_data_mux_bus */
1557         temp = max_t(u32, dev_t->t_weasu,
1558                         gpmc_t->clk_activation + dev_t->t_rdyo);
1559         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1560          * and in that case remember to handle we_on properly
1561          */
1562         if (mux) {
1563                 temp = max_t(u32, temp,
1564                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1565                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1566                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1567         }
1568         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1569
1570         /* we_on */
1571         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1572                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1573         else
1574                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1575
1576         /* wr_access */
1577         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1578         gpmc_t->wr_access = gpmc_t->access;
1579
1580         /* we_off */
1581         temp = gpmc_t->we_on + dev_t->t_wpl;
1582         temp = max_t(u32, temp,
1583                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1584         temp = max_t(u32, temp,
1585                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1586         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1587
1588         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1589                                                         dev_t->t_wph);
1590
1591         /* wr_cycle */
1592         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1593         temp += gpmc_t->wr_access;
1594         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1595         if (dev_t->t_ce_rdyz)
1596                 temp = max_t(u32, temp,
1597                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1598         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1599
1600         return 0;
1601 }
1602
1603 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1604                                         struct gpmc_device_timings *dev_t,
1605                                         bool mux)
1606 {
1607         u32 temp;
1608
1609         /* adv_rd_off */
1610         temp = dev_t->t_avdp_r;
1611         if (mux)
1612                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1613         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1614
1615         /* oe_on */
1616         temp = dev_t->t_oeasu;
1617         if (mux)
1618                 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1619         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1620
1621         /* access */
1622         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1623                      gpmc_t->oe_on + dev_t->t_oe);
1624         temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1625         temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1626         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1627
1628         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1629         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1630
1631         /* rd_cycle */
1632         temp = max_t(u32, dev_t->t_rd_cycle,
1633                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1634         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1635         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1636
1637         return 0;
1638 }
1639
1640 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1641                                          struct gpmc_device_timings *dev_t,
1642                                          bool mux)
1643 {
1644         u32 temp;
1645
1646         /* adv_wr_off */
1647         temp = dev_t->t_avdp_w;
1648         if (mux)
1649                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1650         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1651
1652         /* wr_data_mux_bus */
1653         temp = dev_t->t_weasu;
1654         if (mux) {
1655                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1656                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1657                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1658         }
1659         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1660
1661         /* we_on */
1662         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1663                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1664         else
1665                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1666
1667         /* we_off */
1668         temp = gpmc_t->we_on + dev_t->t_wpl;
1669         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1670
1671         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1672                                                         dev_t->t_wph);
1673
1674         /* wr_cycle */
1675         temp = max_t(u32, dev_t->t_wr_cycle,
1676                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1677         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1678
1679         return 0;
1680 }
1681
1682 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1683                         struct gpmc_device_timings *dev_t)
1684 {
1685         u32 temp;
1686
1687         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1688                                                 gpmc_get_fclk_period();
1689
1690         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1691                                         dev_t->t_bacc,
1692                                         gpmc_t->sync_clk);
1693
1694         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1695         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1696
1697         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1698                 return 0;
1699
1700         if (dev_t->ce_xdelay)
1701                 gpmc_t->bool_timings.cs_extra_delay = true;
1702         if (dev_t->avd_xdelay)
1703                 gpmc_t->bool_timings.adv_extra_delay = true;
1704         if (dev_t->oe_xdelay)
1705                 gpmc_t->bool_timings.oe_extra_delay = true;
1706         if (dev_t->we_xdelay)
1707                 gpmc_t->bool_timings.we_extra_delay = true;
1708
1709         return 0;
1710 }
1711
1712 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1713                                     struct gpmc_device_timings *dev_t,
1714                                     bool sync)
1715 {
1716         u32 temp;
1717
1718         /* cs_on */
1719         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1720
1721         /* adv_on */
1722         temp = dev_t->t_avdasu;
1723         if (dev_t->t_ce_avd)
1724                 temp = max_t(u32, temp,
1725                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1726         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1727
1728         if (sync)
1729                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1730
1731         return 0;
1732 }
1733
1734 /*
1735  * TODO: remove this function once all peripherals are confirmed to
1736  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1737  * has to be modified to handle timings in ps instead of ns
1738  */
1739 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1740 {
1741         t->cs_on /= 1000;
1742         t->cs_rd_off /= 1000;
1743         t->cs_wr_off /= 1000;
1744         t->adv_on /= 1000;
1745         t->adv_rd_off /= 1000;
1746         t->adv_wr_off /= 1000;
1747         t->we_on /= 1000;
1748         t->we_off /= 1000;
1749         t->oe_on /= 1000;
1750         t->oe_off /= 1000;
1751         t->page_burst_access /= 1000;
1752         t->access /= 1000;
1753         t->rd_cycle /= 1000;
1754         t->wr_cycle /= 1000;
1755         t->bus_turnaround /= 1000;
1756         t->cycle2cycle_delay /= 1000;
1757         t->wait_monitoring /= 1000;
1758         t->clk_activation /= 1000;
1759         t->wr_access /= 1000;
1760         t->wr_data_mux_bus /= 1000;
1761 }
1762
1763 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1764                       struct gpmc_settings *gpmc_s,
1765                       struct gpmc_device_timings *dev_t)
1766 {
1767         bool mux = false, sync = false;
1768
1769         if (gpmc_s) {
1770                 mux = gpmc_s->mux_add_data ? true : false;
1771                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1772         }
1773
1774         memset(gpmc_t, 0, sizeof(*gpmc_t));
1775
1776         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1777
1778         if (gpmc_s && gpmc_s->sync_read)
1779                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1780         else
1781                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1782
1783         if (gpmc_s && gpmc_s->sync_write)
1784                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1785         else
1786                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1787
1788         /* TODO: remove, see function definition */
1789         gpmc_convert_ps_to_ns(gpmc_t);
1790
1791         return 0;
1792 }
1793
1794 /**
1795  * gpmc_cs_program_settings - programs non-timing related settings
1796  * @cs:         GPMC chip-select to program
1797  * @p:          pointer to GPMC settings structure
1798  *
1799  * Programs non-timing related settings for a GPMC chip-select, such as
1800  * bus-width, burst configuration, etc. Function should be called once
1801  * for each chip-select that is being used and must be called before
1802  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1803  * register will be initialised to zero by this function. Returns 0 on
1804  * success and appropriate negative error code on failure.
1805  */
1806 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1807 {
1808         u32 config1;
1809
1810         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1811                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1812                 return -EINVAL;
1813         }
1814
1815         /* Address-data multiplexing not supported for NAND devices */
1816         if (p->device_nand && p->mux_add_data) {
1817                 pr_err("%s: invalid configuration!\n", __func__);
1818                 return -EINVAL;
1819         }
1820
1821         if ((p->mux_add_data > GPMC_MUX_AD) ||
1822             ((p->mux_add_data == GPMC_MUX_AAD) &&
1823              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1824                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1825                 return -EINVAL;
1826         }
1827
1828         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1829         if (p->burst_read || p->burst_write) {
1830                 switch (p->burst_len) {
1831                 case GPMC_BURST_4:
1832                 case GPMC_BURST_8:
1833                 case GPMC_BURST_16:
1834                         break;
1835                 default:
1836                         pr_err("%s: invalid page/burst-length (%d)\n",
1837                                __func__, p->burst_len);
1838                         return -EINVAL;
1839                 }
1840         }
1841
1842         if (p->wait_pin > gpmc_nr_waitpins) {
1843                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1844                 return -EINVAL;
1845         }
1846
1847         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1848
1849         if (p->sync_read)
1850                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1851         if (p->sync_write)
1852                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1853         if (p->wait_on_read)
1854                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1855         if (p->wait_on_write)
1856                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1857         if (p->wait_on_read || p->wait_on_write)
1858                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1859         if (p->device_nand)
1860                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1861         if (p->mux_add_data)
1862                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1863         if (p->burst_read)
1864                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1865         if (p->burst_write)
1866                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1867         if (p->burst_read || p->burst_write) {
1868                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1869                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1870         }
1871
1872         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1873
1874         return 0;
1875 }
1876
1877 #ifdef CONFIG_OF
1878 static const struct of_device_id gpmc_dt_ids[] = {
1879         { .compatible = "ti,omap2420-gpmc" },
1880         { .compatible = "ti,omap2430-gpmc" },
1881         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1882         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1883         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1884         { }
1885 };
1886
1887 static void gpmc_cs_set_name(int cs, const char *name)
1888 {
1889         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1890
1891         gpmc->name = name;
1892 }
1893
1894 static const char *gpmc_cs_get_name(int cs)
1895 {
1896         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1897
1898         return gpmc->name;
1899 }
1900
1901 /**
1902  * gpmc_cs_remap - remaps a chip-select physical base address
1903  * @cs:         chip-select to remap
1904  * @base:       physical base address to re-map chip-select to
1905  *
1906  * Re-maps a chip-select to a new physical base address specified by
1907  * "base". Returns 0 on success and appropriate negative error code
1908  * on failure.
1909  */
1910 static int gpmc_cs_remap(int cs, u32 base)
1911 {
1912         int ret;
1913         u32 old_base, size;
1914
1915         if (cs >= gpmc_cs_num) {
1916                 pr_err("%s: requested chip-select is disabled\n", __func__);
1917                 return -ENODEV;
1918         }
1919
1920         /*
1921          * Make sure we ignore any device offsets from the GPMC partition
1922          * allocated for the chip select and that the new base confirms
1923          * to the GPMC 16MB minimum granularity.
1924          */
1925         base &= ~(SZ_16M - 1);
1926
1927         gpmc_cs_get_memconf(cs, &old_base, &size);
1928         if (base == old_base)
1929                 return 0;
1930
1931         ret = gpmc_cs_delete_mem(cs);
1932         if (ret < 0)
1933                 return ret;
1934
1935         ret = gpmc_cs_insert_mem(cs, base, size);
1936         if (ret < 0)
1937                 return ret;
1938
1939         ret = gpmc_cs_set_memconf(cs, base, size);
1940
1941         return ret;
1942 }
1943
1944 /**
1945  * gpmc_read_settings_dt - read gpmc settings from device-tree
1946  * @np:         pointer to device-tree node for a gpmc child device
1947  * @p:          pointer to gpmc settings structure
1948  *
1949  * Reads the GPMC settings for a GPMC child device from device-tree and
1950  * stores them in the GPMC settings structure passed. The GPMC settings
1951  * structure is initialised to zero by this function and so any
1952  * previously stored settings will be cleared.
1953  */
1954 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1955 {
1956         memset(p, 0, sizeof(struct gpmc_settings));
1957
1958         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1959         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1960         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1961         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1962
1963         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1964                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1965                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1966                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1967                 if (!p->burst_read && !p->burst_write)
1968                         pr_warn("%s: page/burst-length set but not used!\n",
1969                                 __func__);
1970         }
1971
1972         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1973                 p->wait_on_read = of_property_read_bool(np,
1974                                                         "gpmc,wait-on-read");
1975                 p->wait_on_write = of_property_read_bool(np,
1976                                                          "gpmc,wait-on-write");
1977                 if (!p->wait_on_read && !p->wait_on_write)
1978                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1979                                  __func__);
1980         }
1981 }
1982
1983 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1984                                                 struct gpmc_timings *gpmc_t)
1985 {
1986         struct gpmc_bool_timings *p;
1987
1988         if (!np || !gpmc_t)
1989                 return;
1990
1991         memset(gpmc_t, 0, sizeof(*gpmc_t));
1992
1993         /* minimum clock period for syncronous mode */
1994         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1995
1996         /* chip select timtings */
1997         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1998         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1999         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2000
2001         /* ADV signal timings */
2002         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2003         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2004         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2005         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2006                              &gpmc_t->adv_aad_mux_on);
2007         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2008                              &gpmc_t->adv_aad_mux_rd_off);
2009         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2010                              &gpmc_t->adv_aad_mux_wr_off);
2011
2012         /* WE signal timings */
2013         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2014         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2015
2016         /* OE signal timings */
2017         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2018         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2019         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2020                              &gpmc_t->oe_aad_mux_on);
2021         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2022                              &gpmc_t->oe_aad_mux_off);
2023
2024         /* access and cycle timings */
2025         of_property_read_u32(np, "gpmc,page-burst-access-ns",
2026                              &gpmc_t->page_burst_access);
2027         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2028         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2029         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2030         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2031                              &gpmc_t->bus_turnaround);
2032         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2033                              &gpmc_t->cycle2cycle_delay);
2034         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2035                              &gpmc_t->wait_monitoring);
2036         of_property_read_u32(np, "gpmc,clk-activation-ns",
2037                              &gpmc_t->clk_activation);
2038
2039         /* only applicable to OMAP3+ */
2040         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2041         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2042                              &gpmc_t->wr_data_mux_bus);
2043
2044         /* bool timing parameters */
2045         p = &gpmc_t->bool_timings;
2046
2047         p->cycle2cyclediffcsen =
2048                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2049         p->cycle2cyclesamecsen =
2050                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2051         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2052         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2053         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2054         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2055         p->time_para_granularity =
2056                 of_property_read_bool(np, "gpmc,time-para-granularity");
2057 }
2058
2059 /**
2060  * gpmc_probe_generic_child - configures the gpmc for a child device
2061  * @pdev:       pointer to gpmc platform device
2062  * @child:      pointer to device-tree node for child device
2063  *
2064  * Allocates and configures a GPMC chip-select for a child device.
2065  * Returns 0 on success and appropriate negative error code on failure.
2066  */
2067 static int gpmc_probe_generic_child(struct platform_device *pdev,
2068                                 struct device_node *child)
2069 {
2070         struct gpmc_settings gpmc_s;
2071         struct gpmc_timings gpmc_t;
2072         struct resource res;
2073         unsigned long base;
2074         const char *name;
2075         int ret, cs;
2076         u32 val;
2077         struct gpio_desc *waitpin_desc = NULL;
2078         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2079
2080         if (of_property_read_u32(child, "reg", &cs) < 0) {
2081                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2082                         child);
2083                 return -ENODEV;
2084         }
2085
2086         if (of_address_to_resource(child, 0, &res) < 0) {
2087                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2088                         child);
2089                 return -ENODEV;
2090         }
2091
2092         /*
2093          * Check if we have multiple instances of the same device
2094          * on a single chip select. If so, use the already initialized
2095          * timings.
2096          */
2097         name = gpmc_cs_get_name(cs);
2098         if (name && of_node_name_eq(child, name))
2099                 goto no_timings;
2100
2101         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2102         if (ret < 0) {
2103                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2104                 return ret;
2105         }
2106         gpmc_cs_set_name(cs, child->full_name);
2107
2108         gpmc_read_settings_dt(child, &gpmc_s);
2109         gpmc_read_timings_dt(child, &gpmc_t);
2110
2111         /*
2112          * For some GPMC devices we still need to rely on the bootloader
2113          * timings because the devices can be connected via FPGA.
2114          * REVISIT: Add timing support from slls644g.pdf.
2115          */
2116         if (!gpmc_t.cs_rd_off) {
2117                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2118                         cs);
2119                 gpmc_cs_show_timings(cs,
2120                                      "please add GPMC bootloader timings to .dts");
2121                 goto no_timings;
2122         }
2123
2124         /* CS must be disabled while making changes to gpmc configuration */
2125         gpmc_cs_disable_mem(cs);
2126
2127         /*
2128          * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2129          * location in the gpmc address space. When booting with
2130          * device-tree we want the NOR flash to be mapped to the
2131          * location specified in the device-tree blob. So remap the
2132          * CS to this location. Once DT migration is complete should
2133          * just make gpmc_cs_request() map a specific address.
2134          */
2135         ret = gpmc_cs_remap(cs, res.start);
2136         if (ret < 0) {
2137                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2138                         cs, &res.start);
2139                 if (res.start < GPMC_MEM_START) {
2140                         dev_info(&pdev->dev,
2141                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2142                                  cs, GPMC_MEM_START);
2143                 } else if (res.end > GPMC_MEM_END) {
2144                         dev_info(&pdev->dev,
2145                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2146                                  cs, GPMC_MEM_END);
2147                 }
2148                 goto err;
2149         }
2150
2151         if (of_node_name_eq(child, "nand")) {
2152                 /* Warn about older DT blobs with no compatible property */
2153                 if (!of_property_read_bool(child, "compatible")) {
2154                         dev_warn(&pdev->dev,
2155                                  "Incompatible NAND node: missing compatible");
2156                         ret = -EINVAL;
2157                         goto err;
2158                 }
2159         }
2160
2161         if (of_node_name_eq(child, "onenand")) {
2162                 /* Warn about older DT blobs with no compatible property */
2163                 if (!of_property_read_bool(child, "compatible")) {
2164                         dev_warn(&pdev->dev,
2165                                  "Incompatible OneNAND node: missing compatible");
2166                         ret = -EINVAL;
2167                         goto err;
2168                 }
2169         }
2170
2171         if (of_device_is_compatible(child, "ti,omap2-nand")) {
2172                 /* NAND specific setup */
2173                 val = 8;
2174                 of_property_read_u32(child, "nand-bus-width", &val);
2175                 switch (val) {
2176                 case 8:
2177                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2178                         break;
2179                 case 16:
2180                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2181                         break;
2182                 default:
2183                         dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2184                                 child);
2185                         ret = -EINVAL;
2186                         goto err;
2187                 }
2188
2189                 /* disable write protect */
2190                 gpmc_configure(GPMC_CONFIG_WP, 0);
2191                 gpmc_s.device_nand = true;
2192         } else {
2193                 ret = of_property_read_u32(child, "bank-width",
2194                                            &gpmc_s.device_width);
2195                 if (ret < 0 && !gpmc_s.device_width) {
2196                         dev_err(&pdev->dev,
2197                                 "%pOF has no 'gpmc,device-width' property\n",
2198                                 child);
2199                         goto err;
2200                 }
2201         }
2202
2203         /* Reserve wait pin if it is required and valid */
2204         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2205                 unsigned int wait_pin = gpmc_s.wait_pin;
2206
2207                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2208                                                          wait_pin, "WAITPIN",
2209                                                          GPIO_ACTIVE_HIGH,
2210                                                          GPIOD_IN);
2211                 if (IS_ERR(waitpin_desc)) {
2212                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2213                         ret = PTR_ERR(waitpin_desc);
2214                         goto err;
2215                 }
2216         }
2217
2218         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2219
2220         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2221         if (ret < 0)
2222                 goto err_cs;
2223
2224         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2225         if (ret) {
2226                 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2227                         child);
2228                 goto err_cs;
2229         }
2230
2231         /* Clear limited address i.e. enable A26-A11 */
2232         val = gpmc_read_reg(GPMC_CONFIG);
2233         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2234         gpmc_write_reg(GPMC_CONFIG, val);
2235
2236         /* Enable CS region */
2237         gpmc_cs_enable_mem(cs);
2238
2239 no_timings:
2240
2241         /* create platform device, NULL on error or when disabled */
2242         if (!of_platform_device_create(child, NULL, &pdev->dev))
2243                 goto err_child_fail;
2244
2245         /* is child a common bus? */
2246         if (of_match_node(of_default_bus_match_table, child))
2247                 /* create children and other common bus children */
2248                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2249                         goto err_child_fail;
2250
2251         return 0;
2252
2253 err_child_fail:
2254
2255         dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2256         ret = -ENODEV;
2257
2258 err_cs:
2259         gpiochip_free_own_desc(waitpin_desc);
2260 err:
2261         gpmc_cs_free(cs);
2262
2263         return ret;
2264 }
2265
2266 static int gpmc_probe_dt(struct platform_device *pdev)
2267 {
2268         int ret;
2269         const struct of_device_id *of_id =
2270                 of_match_device(gpmc_dt_ids, &pdev->dev);
2271
2272         if (!of_id)
2273                 return 0;
2274
2275         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2276                                    &gpmc_cs_num);
2277         if (ret < 0) {
2278                 pr_err("%s: number of chip-selects not defined\n", __func__);
2279                 return ret;
2280         } else if (gpmc_cs_num < 1) {
2281                 pr_err("%s: all chip-selects are disabled\n", __func__);
2282                 return -EINVAL;
2283         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2284                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2285                                          __func__, GPMC_CS_NUM);
2286                 return -EINVAL;
2287         }
2288
2289         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2290                                    &gpmc_nr_waitpins);
2291         if (ret < 0) {
2292                 pr_err("%s: number of wait pins not found!\n", __func__);
2293                 return ret;
2294         }
2295
2296         return 0;
2297 }
2298
2299 static void gpmc_probe_dt_children(struct platform_device *pdev)
2300 {
2301         int ret;
2302         struct device_node *child;
2303
2304         for_each_available_child_of_node(pdev->dev.of_node, child) {
2305                 ret = gpmc_probe_generic_child(pdev, child);
2306                 if (ret) {
2307                         dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2308                                 child, ret);
2309                 }
2310         }
2311 }
2312 #else
2313 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2314 {
2315         memset(p, 0, sizeof(*p));
2316 }
2317 static int gpmc_probe_dt(struct platform_device *pdev)
2318 {
2319         return 0;
2320 }
2321
2322 static void gpmc_probe_dt_children(struct platform_device *pdev)
2323 {
2324 }
2325 #endif /* CONFIG_OF */
2326
2327 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2328 {
2329         return 1;       /* we're input only */
2330 }
2331
2332 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2333                                      unsigned int offset)
2334 {
2335         return 0;       /* we're input only */
2336 }
2337
2338 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2339                                       unsigned int offset, int value)
2340 {
2341         return -EINVAL; /* we're input only */
2342 }
2343
2344 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2345                           int value)
2346 {
2347 }
2348
2349 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2350 {
2351         u32 reg;
2352
2353         offset += 8;
2354
2355         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2356
2357         return !!reg;
2358 }
2359
2360 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2361 {
2362         int ret;
2363
2364         gpmc->gpio_chip.parent = gpmc->dev;
2365         gpmc->gpio_chip.owner = THIS_MODULE;
2366         gpmc->gpio_chip.label = DEVICE_NAME;
2367         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2368         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2369         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2370         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2371         gpmc->gpio_chip.set = gpmc_gpio_set;
2372         gpmc->gpio_chip.get = gpmc_gpio_get;
2373         gpmc->gpio_chip.base = -1;
2374
2375         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2376         if (ret < 0) {
2377                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2378                 return ret;
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int gpmc_probe(struct platform_device *pdev)
2385 {
2386         int rc;
2387         u32 l;
2388         struct resource *res;
2389         struct gpmc_device *gpmc;
2390
2391         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2392         if (!gpmc)
2393                 return -ENOMEM;
2394
2395         gpmc->dev = &pdev->dev;
2396         platform_set_drvdata(pdev, gpmc);
2397
2398         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2399         if (!res)
2400                 return -ENOENT;
2401
2402         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2403         if (IS_ERR(gpmc_base))
2404                 return PTR_ERR(gpmc_base);
2405
2406         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2407         if (!res) {
2408                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2409                 return -ENOENT;
2410         }
2411
2412         gpmc->irq = res->start;
2413
2414         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2415         if (IS_ERR(gpmc_l3_clk)) {
2416                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2417                 return PTR_ERR(gpmc_l3_clk);
2418         }
2419
2420         if (!clk_get_rate(gpmc_l3_clk)) {
2421                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2422                 return -EINVAL;
2423         }
2424
2425         if (pdev->dev.of_node) {
2426                 rc = gpmc_probe_dt(pdev);
2427                 if (rc)
2428                         return rc;
2429         } else {
2430                 gpmc_cs_num = GPMC_CS_NUM;
2431                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2432         }
2433
2434         pm_runtime_enable(&pdev->dev);
2435         pm_runtime_get_sync(&pdev->dev);
2436
2437         l = gpmc_read_reg(GPMC_REVISION);
2438
2439         /*
2440          * FIXME: Once device-tree migration is complete the below flags
2441          * should be populated based upon the device-tree compatible
2442          * string. For now just use the IP revision. OMAP3+ devices have
2443          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2444          * devices support the addr-addr-data multiplex protocol.
2445          *
2446          * GPMC IP revisions:
2447          * - OMAP24xx                   = 2.0
2448          * - OMAP3xxx                   = 5.0
2449          * - OMAP44xx/54xx/AM335x       = 6.0
2450          */
2451         if (GPMC_REVISION_MAJOR(l) > 0x4)
2452                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2453         if (GPMC_REVISION_MAJOR(l) > 0x5)
2454                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2455         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2456                  GPMC_REVISION_MINOR(l));
2457
2458         gpmc_mem_init();
2459         rc = gpmc_gpio_init(gpmc);
2460         if (rc)
2461                 goto gpio_init_failed;
2462
2463         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2464         rc = gpmc_setup_irq(gpmc);
2465         if (rc) {
2466                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2467                 goto gpio_init_failed;
2468         }
2469
2470         gpmc_probe_dt_children(pdev);
2471
2472         return 0;
2473
2474 gpio_init_failed:
2475         gpmc_mem_exit();
2476         pm_runtime_put_sync(&pdev->dev);
2477         pm_runtime_disable(&pdev->dev);
2478
2479         return rc;
2480 }
2481
2482 static int gpmc_remove(struct platform_device *pdev)
2483 {
2484         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2485
2486         gpmc_free_irq(gpmc);
2487         gpmc_mem_exit();
2488         pm_runtime_put_sync(&pdev->dev);
2489         pm_runtime_disable(&pdev->dev);
2490
2491         return 0;
2492 }
2493
2494 #ifdef CONFIG_PM_SLEEP
2495 static int gpmc_suspend(struct device *dev)
2496 {
2497         omap3_gpmc_save_context();
2498         pm_runtime_put_sync(dev);
2499         return 0;
2500 }
2501
2502 static int gpmc_resume(struct device *dev)
2503 {
2504         pm_runtime_get_sync(dev);
2505         omap3_gpmc_restore_context();
2506         return 0;
2507 }
2508 #endif
2509
2510 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2511
2512 static struct platform_driver gpmc_driver = {
2513         .probe          = gpmc_probe,
2514         .remove         = gpmc_remove,
2515         .driver         = {
2516                 .name   = DEVICE_NAME,
2517                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2518                 .pm     = &gpmc_pm_ops,
2519         },
2520 };
2521
2522 static __init int gpmc_init(void)
2523 {
2524         return platform_driver_register(&gpmc_driver);
2525 }
2526 postcore_initcall(gpmc_init);
2527
2528 static struct omap3_gpmc_regs gpmc_context;
2529
2530 void omap3_gpmc_save_context(void)
2531 {
2532         int i;
2533
2534         if (!gpmc_base)
2535                 return;
2536
2537         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2538         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2539         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2540         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2541         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2542         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2543         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2544         for (i = 0; i < gpmc_cs_num; i++) {
2545                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2546                 if (gpmc_context.cs_context[i].is_valid) {
2547                         gpmc_context.cs_context[i].config1 =
2548                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2549                         gpmc_context.cs_context[i].config2 =
2550                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2551                         gpmc_context.cs_context[i].config3 =
2552                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2553                         gpmc_context.cs_context[i].config4 =
2554                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2555                         gpmc_context.cs_context[i].config5 =
2556                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2557                         gpmc_context.cs_context[i].config6 =
2558                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2559                         gpmc_context.cs_context[i].config7 =
2560                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2561                 }
2562         }
2563 }
2564
2565 void omap3_gpmc_restore_context(void)
2566 {
2567         int i;
2568
2569         if (!gpmc_base)
2570                 return;
2571
2572         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2573         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2574         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2575         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2576         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2577         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2578         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2579         for (i = 0; i < gpmc_cs_num; i++) {
2580                 if (gpmc_context.cs_context[i].is_valid) {
2581                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2582                                 gpmc_context.cs_context[i].config1);
2583                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2584                                 gpmc_context.cs_context[i].config2);
2585                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2586                                 gpmc_context.cs_context[i].config3);
2587                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2588                                 gpmc_context.cs_context[i].config4);
2589                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2590                                 gpmc_context.cs_context[i].config5);
2591                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2592                                 gpmc_context.cs_context[i].config6);
2593                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2594                                 gpmc_context.cs_context[i].config7);
2595                 }
2596         }
2597 }