drivers/irqchip/qcom-pdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/soc/qcom/irq.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21
  22 #define PDC_MAX_IRQS            168
  23 #define PDC_MAX_GPIO_IRQS       256
  24
  25 #define CLEAR_INTR(reg, intr)   (reg & ~(1 << intr))
  26 #define ENABLE_INTR(reg, intr)  (reg | (1 << intr))
  27
  28 #define IRQ_ENABLE_BANK         0x10
  29 #define IRQ_i_CFG               0x110
  30
  31 #define PDC_NO_PARENT_IRQ       ~0UL
  32
  33 struct pdc_pin_region {
  34         u32 pin_base;
  35         u32 parent_base;
  36         u32 cnt;
  37 };
  38
  39 static DEFINE_RAW_SPINLOCK(pdc_lock);
  40 static void __iomem *pdc_base;
  41 static struct pdc_pin_region *pdc_region;
  42 static int pdc_region_cnt;
  43
  44 static void pdc_reg_write(int reg, u32 i, u32 val)
  45 {
  46         writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  47 }
  48
  49 static u32 pdc_reg_read(int reg, u32 i)
  50 {
  51         return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  52 }
  53
  54 static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
  55                                           enum irqchip_irq_state which,
  56                                           bool *state)
  57 {
  58         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  59                 return 0;
  60
  61         return irq_chip_get_parent_state(d, which, state);
  62 }
  63
  64 static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
  65                                           enum irqchip_irq_state which,
  66                                           bool value)
  67 {
  68         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  69                 return 0;
  70
  71         return irq_chip_set_parent_state(d, which, value);
  72 }
  73
  74 static void pdc_enable_intr(struct irq_data *d, bool on)
  75 {
  76         int pin_out = d->hwirq;
  77         u32 index, mask;
  78         u32 enable;
  79
  80         index = pin_out / 32;
  81         mask = pin_out % 32;
  82
  83         raw_spin_lock(&pdc_lock);
  84         enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  85         enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
  86         pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  87         raw_spin_unlock(&pdc_lock);
  88 }
  89
  90 static void qcom_pdc_gic_disable(struct irq_data *d)
  91 {
  92         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  93                 return;
  94
  95         pdc_enable_intr(d, false);
  96         irq_chip_disable_parent(d);
  97 }
  98
  99 static void qcom_pdc_gic_enable(struct irq_data *d)
 100 {
 101         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 102                 return;
 103
 104         pdc_enable_intr(d, true);
 105         irq_chip_enable_parent(d);
 106 }
 107
 108 static void qcom_pdc_gic_mask(struct irq_data *d)
 109 {
 110         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 111                 return;
 112
 113         irq_chip_mask_parent(d);
 114 }
 115
 116 static void qcom_pdc_gic_unmask(struct irq_data *d)
 117 {
 118         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 119                 return;
 120
 121         irq_chip_unmask_parent(d);
 122 }
 123
 124 /*
 125  * GIC does not handle falling edge or active low. To allow falling edge and
 126  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
 127  * falling edge into a rising edge and active low into an active high.
 128  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
 129  * set as per the table below.
 130  * Level sensitive active low    LOW
 131  * Rising edge sensitive         NOT USED
 132  * Falling edge sensitive        LOW
 133  * Dual Edge sensitive           NOT USED
 134  * Level sensitive active High   HIGH
 135  * Falling Edge sensitive        NOT USED
 136  * Rising edge sensitive         HIGH
 137  * Dual Edge sensitive           HIGH
 138  */
 139 enum pdc_irq_config_bits {
 140         PDC_LEVEL_LOW           = 0b000,
 141         PDC_EDGE_FALLING        = 0b010,
 142         PDC_LEVEL_HIGH          = 0b100,
 143         PDC_EDGE_RISING         = 0b110,
 144         PDC_EDGE_DUAL           = 0b111,
 145 };
 146
 147 /**
 148  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 149  *
 150  * @d: the interrupt data
 151  * @type: the interrupt type
 152  *
 153  * If @type is edge triggered, forward that as Rising edge as PDC
 154  * takes care of converting falling edge to rising edge signal
 155  * If @type is level, then forward that as level high as PDC
 156  * takes care of converting falling edge to rising edge signal
 157  */
 158 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 159 {
 160         int pin_out = d->hwirq;
 161         enum pdc_irq_config_bits pdc_type;
 162
 163         if (pin_out == GPIO_NO_WAKE_IRQ)
 164                 return 0;
 165
 166         switch (type) {
 167         case IRQ_TYPE_EDGE_RISING:
 168                 pdc_type = PDC_EDGE_RISING;
 169                 break;
 170         case IRQ_TYPE_EDGE_FALLING:
 171                 pdc_type = PDC_EDGE_FALLING;
 172                 type = IRQ_TYPE_EDGE_RISING;
 173                 break;
 174         case IRQ_TYPE_EDGE_BOTH:
 175                 pdc_type = PDC_EDGE_DUAL;
 176                 type = IRQ_TYPE_EDGE_RISING;
 177                 break;
 178         case IRQ_TYPE_LEVEL_HIGH:
 179                 pdc_type = PDC_LEVEL_HIGH;
 180                 break;
 181         case IRQ_TYPE_LEVEL_LOW:
 182                 pdc_type = PDC_LEVEL_LOW;
 183                 type = IRQ_TYPE_LEVEL_HIGH;
 184                 break;
 185         default:
 186                 WARN_ON(1);
 187                 return -EINVAL;
 188         }
 189
 190         pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
 191
 192         return irq_chip_set_type_parent(d, type);
 193 }
 194
 195 static struct irq_chip qcom_pdc_gic_chip = {
 196         .name                   = "PDC",
 197         .irq_eoi                = irq_chip_eoi_parent,
 198         .irq_mask               = qcom_pdc_gic_mask,
 199         .irq_unmask             = qcom_pdc_gic_unmask,
 200         .irq_disable            = qcom_pdc_gic_disable,
 201         .irq_enable             = qcom_pdc_gic_enable,
 202         .irq_get_irqchip_state  = qcom_pdc_gic_get_irqchip_state,
 203         .irq_set_irqchip_state  = qcom_pdc_gic_set_irqchip_state,
 204         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 205         .irq_set_type           = qcom_pdc_gic_set_type,
 206         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 207                                   IRQCHIP_SET_TYPE_MASKED |
 208                                   IRQCHIP_SKIP_SET_WAKE |
 209                                   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
 210         .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
 211         .irq_set_affinity       = irq_chip_set_affinity_parent,
 212 };
 213
 214 static irq_hw_number_t get_parent_hwirq(int pin)
 215 {
 216         int i;
 217         struct pdc_pin_region *region;
 218
 219         for (i = 0; i < pdc_region_cnt; i++) {
 220                 region = &pdc_region[i];
 221                 if (pin >= region->pin_base &&
 222                     pin < region->pin_base + region->cnt)
 223                         return (region->parent_base + pin - region->pin_base);
 224         }
 225
 226         return PDC_NO_PARENT_IRQ;
 227 }
 228
 229 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
 230                               unsigned long *hwirq, unsigned int *type)
 231 {
 232         if (is_of_node(fwspec->fwnode)) {
 233                 if (fwspec->param_count != 2)
 234                         return -EINVAL;
 235
 236                 *hwirq = fwspec->param[0];
 237                 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
 238                 return 0;
 239         }
 240
 241         return -EINVAL;
 242 }
 243
 244 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 245                           unsigned int nr_irqs, void *data)
 246 {
 247         struct irq_fwspec *fwspec = data;
 248         struct irq_fwspec parent_fwspec;
 249         irq_hw_number_t hwirq, parent_hwirq;
 250         unsigned int type;
 251         int ret;
 252
 253         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 254         if (ret)
 255                 return ret;
 256
 257         ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 258                                              &qcom_pdc_gic_chip, NULL);
 259         if (ret)
 260                 return ret;
 261
 262         parent_hwirq = get_parent_hwirq(hwirq);
 263         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 264                 return 0;
 265
 266         if (type & IRQ_TYPE_EDGE_BOTH)
 267                 type = IRQ_TYPE_EDGE_RISING;
 268
 269         if (type & IRQ_TYPE_LEVEL_MASK)
 270                 type = IRQ_TYPE_LEVEL_HIGH;
 271
 272         parent_fwspec.fwnode      = domain->parent->fwnode;
 273         parent_fwspec.param_count = 3;
 274         parent_fwspec.param[0]    = 0;
 275         parent_fwspec.param[1]    = parent_hwirq;
 276         parent_fwspec.param[2]    = type;
 277
 278         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 279                                             &parent_fwspec);
 280 }
 281
 282 static const struct irq_domain_ops qcom_pdc_ops = {
 283         .translate      = qcom_pdc_translate,
 284         .alloc          = qcom_pdc_alloc,
 285         .free           = irq_domain_free_irqs_common,
 286 };
 287
 288 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
 289                                unsigned int nr_irqs, void *data)
 290 {
 291         struct irq_fwspec *fwspec = data;
 292         struct irq_fwspec parent_fwspec;
 293         irq_hw_number_t hwirq, parent_hwirq;
 294         unsigned int type;
 295         int ret;
 296
 297         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 298         if (ret)
 299                 return ret;
 300
 301         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 302                                             &qcom_pdc_gic_chip, NULL);
 303         if (ret)
 304                 return ret;
 305
 306         if (hwirq == GPIO_NO_WAKE_IRQ)
 307                 return 0;
 308
 309         parent_hwirq = get_parent_hwirq(hwirq);
 310         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 311                 return 0;
 312
 313         if (type & IRQ_TYPE_EDGE_BOTH)
 314                 type = IRQ_TYPE_EDGE_RISING;
 315
 316         if (type & IRQ_TYPE_LEVEL_MASK)
 317                 type = IRQ_TYPE_LEVEL_HIGH;
 318
 319         parent_fwspec.fwnode      = domain->parent->fwnode;
 320         parent_fwspec.param_count = 3;
 321         parent_fwspec.param[0]    = 0;
 322         parent_fwspec.param[1]    = parent_hwirq;
 323         parent_fwspec.param[2]    = type;
 324
 325         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 326                                             &parent_fwspec);
 327 }
 328
 329 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
 330                                        struct irq_fwspec *fwspec,
 331                                        enum irq_domain_bus_token bus_token)
 332 {
 333         return bus_token == DOMAIN_BUS_WAKEUP;
 334 }
 335
 336 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
 337         .select         = qcom_pdc_gpio_domain_select,
 338         .alloc          = qcom_pdc_gpio_alloc,
 339         .free           = irq_domain_free_irqs_common,
 340 };
 341
 342 static int pdc_setup_pin_mapping(struct device_node *np)
 343 {
 344         int ret, n, i;
 345         u32 irq_index, reg_index, val;
 346
 347         n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
 348         if (n <= 0 || n % 3)
 349                 return -EINVAL;
 350
 351         pdc_region_cnt = n / 3;
 352         pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
 353         if (!pdc_region) {
 354                 pdc_region_cnt = 0;
 355                 return -ENOMEM;
 356         }
 357
 358         for (n = 0; n < pdc_region_cnt; n++) {
 359                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 360                                                  n * 3 + 0,
 361                                                  &pdc_region[n].pin_base);
 362                 if (ret)
 363                         return ret;
 364                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 365                                                  n * 3 + 1,
 366                                                  &pdc_region[n].parent_base);
 367                 if (ret)
 368                         return ret;
 369                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 370                                                  n * 3 + 2,
 371                                                  &pdc_region[n].cnt);
 372                 if (ret)
 373                         return ret;
 374
 375                 for (i = 0; i < pdc_region[n].cnt; i++) {
 376                         reg_index = (i + pdc_region[n].pin_base) >> 5;
 377                         irq_index = (i + pdc_region[n].pin_base) & 0x1f;
 378                         val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
 379                         val &= ~BIT(irq_index);
 380                         pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
 381                 }
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 388 {
 389         struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 390         int ret;
 391
 392         pdc_base = of_iomap(node, 0);
 393         if (!pdc_base) {
 394                 pr_err("%pOF: unable to map PDC registers\n", node);
 395                 return -ENXIO;
 396         }
 397
 398         parent_domain = irq_find_host(parent);
 399         if (!parent_domain) {
 400                 pr_err("%pOF: unable to find PDC's parent domain\n", node);
 401                 ret = -ENXIO;
 402                 goto fail;
 403         }
 404
 405         ret = pdc_setup_pin_mapping(node);
 406         if (ret) {
 407                 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
 408                 goto fail;
 409         }
 410
 411         pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
 412                                                  of_fwnode_handle(node),
 413                                                  &qcom_pdc_ops, NULL);
 414         if (!pdc_domain) {
 415                 pr_err("%pOF: GIC domain add failed\n", node);
 416                 ret = -ENOMEM;
 417                 goto fail;
 418         }
 419
 420         pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
 421                                         IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
 422                                         PDC_MAX_GPIO_IRQS,
 423                                         of_fwnode_handle(node),
 424                                         &qcom_pdc_gpio_ops, NULL);
 425         if (!pdc_gpio_domain) {
 426                 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
 427                 ret = -ENOMEM;
 428                 goto remove;
 429         }
 430
 431         irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
 432
 433         return 0;
 434
 435 remove:
 436         irq_domain_remove(pdc_domain);
 437 fail:
 438         kfree(pdc_region);
 439         iounmap(pdc_base);
 440         return ret;
 441 }
 442
 443 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);