drivers/irqchip/qcom-pdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/irq.h>
  10 #include <linux/irqchip.h>
  11 #include <linux/irqdomain.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/soc/qcom/irq.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21
  22 #define PDC_MAX_IRQS            168
  23 #define PDC_MAX_GPIO_IRQS       256
  24
  25 #define CLEAR_INTR(reg, intr)   (reg & ~(1 << intr))
  26 #define ENABLE_INTR(reg, intr)  (reg | (1 << intr))
  27
  28 #define IRQ_ENABLE_BANK         0x10
  29 #define IRQ_i_CFG               0x110
  30
  31 #define PDC_NO_PARENT_IRQ       ~0UL
  32
  33 struct pdc_pin_region {
  34         u32 pin_base;
  35         u32 parent_base;
  36         u32 cnt;
  37 };
  38
  39 static DEFINE_RAW_SPINLOCK(pdc_lock);
  40 static void __iomem *pdc_base;
  41 static struct pdc_pin_region *pdc_region;
  42 static int pdc_region_cnt;
  43
  44 static void pdc_reg_write(int reg, u32 i, u32 val)
  45 {
  46         writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
  47 }
  48
  49 static u32 pdc_reg_read(int reg, u32 i)
  50 {
  51         return readl_relaxed(pdc_base + reg + i * sizeof(u32));
  52 }
  53
  54 static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d,
  55                                           enum irqchip_irq_state which,
  56                                           bool *state)
  57 {
  58         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  59                 return 0;
  60
  61         return irq_chip_get_parent_state(d, which, state);
  62 }
  63
  64 static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d,
  65                                           enum irqchip_irq_state which,
  66                                           bool value)
  67 {
  68         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  69                 return 0;
  70
  71         return irq_chip_set_parent_state(d, which, value);
  72 }
  73
  74 static void pdc_enable_intr(struct irq_data *d, bool on)
  75 {
  76         int pin_out = d->hwirq;
  77         u32 index, mask;
  78         u32 enable;
  79
  80         index = pin_out / 32;
  81         mask = pin_out % 32;
  82
  83         raw_spin_lock(&pdc_lock);
  84         enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
  85         enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
  86         pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
  87         raw_spin_unlock(&pdc_lock);
  88 }
  89
  90 static void qcom_pdc_gic_disable(struct irq_data *d)
  91 {
  92         if (d->hwirq == GPIO_NO_WAKE_IRQ)
  93                 return;
  94
  95         pdc_enable_intr(d, false);
  96         irq_chip_disable_parent(d);
  97 }
  98
  99 static void qcom_pdc_gic_enable(struct irq_data *d)
 100 {
 101         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 102                 return;
 103
 104         pdc_enable_intr(d, true);
 105         irq_chip_enable_parent(d);
 106 }
 107
 108 static void qcom_pdc_gic_mask(struct irq_data *d)
 109 {
 110         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 111                 return;
 112
 113         irq_chip_mask_parent(d);
 114 }
 115
 116 static void qcom_pdc_gic_unmask(struct irq_data *d)
 117 {
 118         if (d->hwirq == GPIO_NO_WAKE_IRQ)
 119                 return;
 120
 121         irq_chip_unmask_parent(d);
 122 }
 123
 124 /*
 125  * GIC does not handle falling edge or active low. To allow falling edge and
 126  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
 127  * falling edge into a rising edge and active low into an active high.
 128  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
 129  * set as per the table below.
 130  * Level sensitive active low    LOW
 131  * Rising edge sensitive         NOT USED
 132  * Falling edge sensitive        LOW
 133  * Dual Edge sensitive           NOT USED
 134  * Level sensitive active High   HIGH
 135  * Falling Edge sensitive        NOT USED
 136  * Rising edge sensitive         HIGH
 137  * Dual Edge sensitive           HIGH
 138  */
 139 enum pdc_irq_config_bits {
 140         PDC_LEVEL_LOW           = 0b000,
 141         PDC_EDGE_FALLING        = 0b010,
 142         PDC_LEVEL_HIGH          = 0b100,
 143         PDC_EDGE_RISING         = 0b110,
 144         PDC_EDGE_DUAL           = 0b111,
 145 };
 146
 147 /**
 148  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
 149  *
 150  * @d: the interrupt data
 151  * @type: the interrupt type
 152  *
 153  * If @type is edge triggered, forward that as Rising edge as PDC
 154  * takes care of converting falling edge to rising edge signal
 155  * If @type is level, then forward that as level high as PDC
 156  * takes care of converting falling edge to rising edge signal
 157  */
 158 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 159 {
 160         int pin_out = d->hwirq;
 161         enum pdc_irq_config_bits pdc_type;
 162         enum pdc_irq_config_bits old_pdc_type;
 163         int ret;
 164
 165         if (pin_out == GPIO_NO_WAKE_IRQ)
 166                 return 0;
 167
 168         switch (type) {
 169         case IRQ_TYPE_EDGE_RISING:
 170                 pdc_type = PDC_EDGE_RISING;
 171                 break;
 172         case IRQ_TYPE_EDGE_FALLING:
 173                 pdc_type = PDC_EDGE_FALLING;
 174                 type = IRQ_TYPE_EDGE_RISING;
 175                 break;
 176         case IRQ_TYPE_EDGE_BOTH:
 177                 pdc_type = PDC_EDGE_DUAL;
 178                 type = IRQ_TYPE_EDGE_RISING;
 179                 break;
 180         case IRQ_TYPE_LEVEL_HIGH:
 181                 pdc_type = PDC_LEVEL_HIGH;
 182                 break;
 183         case IRQ_TYPE_LEVEL_LOW:
 184                 pdc_type = PDC_LEVEL_LOW;
 185                 type = IRQ_TYPE_LEVEL_HIGH;
 186                 break;
 187         default:
 188                 WARN_ON(1);
 189                 return -EINVAL;
 190         }
 191
 192         old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out);
 193         pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
 194
 195         ret = irq_chip_set_type_parent(d, type);
 196         if (ret)
 197                 return ret;
 198
 199         /*
 200          * When we change types the PDC can give a phantom interrupt.
 201          * Clear it.  Specifically the phantom shows up when reconfiguring
 202          * polarity of interrupt without changing the state of the signal
 203          * but let's be consistent and clear it always.
 204          *
 205          * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
 206          * interrupt will be cleared before the rest of the system sees it.
 207          */
 208         if (old_pdc_type != pdc_type)
 209                 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
 210
 211         return 0;
 212 }
 213
 214 static struct irq_chip qcom_pdc_gic_chip = {
 215         .name                   = "PDC",
 216         .irq_eoi                = irq_chip_eoi_parent,
 217         .irq_mask               = qcom_pdc_gic_mask,
 218         .irq_unmask             = qcom_pdc_gic_unmask,
 219         .irq_disable            = qcom_pdc_gic_disable,
 220         .irq_enable             = qcom_pdc_gic_enable,
 221         .irq_get_irqchip_state  = qcom_pdc_gic_get_irqchip_state,
 222         .irq_set_irqchip_state  = qcom_pdc_gic_set_irqchip_state,
 223         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 224         .irq_set_type           = qcom_pdc_gic_set_type,
 225         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
 226                                   IRQCHIP_SET_TYPE_MASKED |
 227                                   IRQCHIP_SKIP_SET_WAKE |
 228                                   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
 229         .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
 230         .irq_set_affinity       = irq_chip_set_affinity_parent,
 231 };
 232
 233 static irq_hw_number_t get_parent_hwirq(int pin)
 234 {
 235         int i;
 236         struct pdc_pin_region *region;
 237
 238         for (i = 0; i < pdc_region_cnt; i++) {
 239                 region = &pdc_region[i];
 240                 if (pin >= region->pin_base &&
 241                     pin < region->pin_base + region->cnt)
 242                         return (region->parent_base + pin - region->pin_base);
 243         }
 244
 245         return PDC_NO_PARENT_IRQ;
 246 }
 247
 248 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
 249                               unsigned long *hwirq, unsigned int *type)
 250 {
 251         if (is_of_node(fwspec->fwnode)) {
 252                 if (fwspec->param_count != 2)
 253                         return -EINVAL;
 254
 255                 *hwirq = fwspec->param[0];
 256                 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
 257                 return 0;
 258         }
 259
 260         return -EINVAL;
 261 }
 262
 263 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 264                           unsigned int nr_irqs, void *data)
 265 {
 266         struct irq_fwspec *fwspec = data;
 267         struct irq_fwspec parent_fwspec;
 268         irq_hw_number_t hwirq, parent_hwirq;
 269         unsigned int type;
 270         int ret;
 271
 272         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 273         if (ret)
 274                 return ret;
 275
 276         ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 277                                              &qcom_pdc_gic_chip, NULL);
 278         if (ret)
 279                 return ret;
 280
 281         parent_hwirq = get_parent_hwirq(hwirq);
 282         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 283                 return 0;
 284
 285         if (type & IRQ_TYPE_EDGE_BOTH)
 286                 type = IRQ_TYPE_EDGE_RISING;
 287
 288         if (type & IRQ_TYPE_LEVEL_MASK)
 289                 type = IRQ_TYPE_LEVEL_HIGH;
 290
 291         parent_fwspec.fwnode      = domain->parent->fwnode;
 292         parent_fwspec.param_count = 3;
 293         parent_fwspec.param[0]    = 0;
 294         parent_fwspec.param[1]    = parent_hwirq;
 295         parent_fwspec.param[2]    = type;
 296
 297         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 298                                             &parent_fwspec);
 299 }
 300
 301 static const struct irq_domain_ops qcom_pdc_ops = {
 302         .translate      = qcom_pdc_translate,
 303         .alloc          = qcom_pdc_alloc,
 304         .free           = irq_domain_free_irqs_common,
 305 };
 306
 307 static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
 308                                unsigned int nr_irqs, void *data)
 309 {
 310         struct irq_fwspec *fwspec = data;
 311         struct irq_fwspec parent_fwspec;
 312         irq_hw_number_t hwirq, parent_hwirq;
 313         unsigned int type;
 314         int ret;
 315
 316         ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 317         if (ret)
 318                 return ret;
 319
 320         ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 321                                             &qcom_pdc_gic_chip, NULL);
 322         if (ret)
 323                 return ret;
 324
 325         if (hwirq == GPIO_NO_WAKE_IRQ)
 326                 return 0;
 327
 328         parent_hwirq = get_parent_hwirq(hwirq);
 329         if (parent_hwirq == PDC_NO_PARENT_IRQ)
 330                 return 0;
 331
 332         if (type & IRQ_TYPE_EDGE_BOTH)
 333                 type = IRQ_TYPE_EDGE_RISING;
 334
 335         if (type & IRQ_TYPE_LEVEL_MASK)
 336                 type = IRQ_TYPE_LEVEL_HIGH;
 337
 338         parent_fwspec.fwnode      = domain->parent->fwnode;
 339         parent_fwspec.param_count = 3;
 340         parent_fwspec.param[0]    = 0;
 341         parent_fwspec.param[1]    = parent_hwirq;
 342         parent_fwspec.param[2]    = type;
 343
 344         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 345                                             &parent_fwspec);
 346 }
 347
 348 static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
 349                                        struct irq_fwspec *fwspec,
 350                                        enum irq_domain_bus_token bus_token)
 351 {
 352         return bus_token == DOMAIN_BUS_WAKEUP;
 353 }
 354
 355 static const struct irq_domain_ops qcom_pdc_gpio_ops = {
 356         .select         = qcom_pdc_gpio_domain_select,
 357         .alloc          = qcom_pdc_gpio_alloc,
 358         .free           = irq_domain_free_irqs_common,
 359 };
 360
 361 static int pdc_setup_pin_mapping(struct device_node *np)
 362 {
 363         int ret, n, i;
 364         u32 irq_index, reg_index, val;
 365
 366         n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
 367         if (n <= 0 || n % 3)
 368                 return -EINVAL;
 369
 370         pdc_region_cnt = n / 3;
 371         pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
 372         if (!pdc_region) {
 373                 pdc_region_cnt = 0;
 374                 return -ENOMEM;
 375         }
 376
 377         for (n = 0; n < pdc_region_cnt; n++) {
 378                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 379                                                  n * 3 + 0,
 380                                                  &pdc_region[n].pin_base);
 381                 if (ret)
 382                         return ret;
 383                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 384                                                  n * 3 + 1,
 385                                                  &pdc_region[n].parent_base);
 386                 if (ret)
 387                         return ret;
 388                 ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
 389                                                  n * 3 + 2,
 390                                                  &pdc_region[n].cnt);
 391                 if (ret)
 392                         return ret;
 393
 394                 for (i = 0; i < pdc_region[n].cnt; i++) {
 395                         reg_index = (i + pdc_region[n].pin_base) >> 5;
 396                         irq_index = (i + pdc_region[n].pin_base) & 0x1f;
 397                         val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
 398                         val &= ~BIT(irq_index);
 399                         pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
 400                 }
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 407 {
 408         struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 409         int ret;
 410
 411         pdc_base = of_iomap(node, 0);
 412         if (!pdc_base) {
 413                 pr_err("%pOF: unable to map PDC registers\n", node);
 414                 return -ENXIO;
 415         }
 416
 417         parent_domain = irq_find_host(parent);
 418         if (!parent_domain) {
 419                 pr_err("%pOF: unable to find PDC's parent domain\n", node);
 420                 ret = -ENXIO;
 421                 goto fail;
 422         }
 423
 424         ret = pdc_setup_pin_mapping(node);
 425         if (ret) {
 426                 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
 427                 goto fail;
 428         }
 429
 430         pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS,
 431                                                  of_fwnode_handle(node),
 432                                                  &qcom_pdc_ops, NULL);
 433         if (!pdc_domain) {
 434                 pr_err("%pOF: GIC domain add failed\n", node);
 435                 ret = -ENOMEM;
 436                 goto fail;
 437         }
 438
 439         pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
 440                                         IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
 441                                         PDC_MAX_GPIO_IRQS,
 442                                         of_fwnode_handle(node),
 443                                         &qcom_pdc_gpio_ops, NULL);
 444         if (!pdc_gpio_domain) {
 445                 pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);
 446                 ret = -ENOMEM;
 447                 goto remove;
 448         }
 449
 450         irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
 451
 452         return 0;
 453
 454 remove:
 455         irq_domain_remove(pdc_domain);
 456 fail:
 457         kfree(pdc_region);
 458         iounmap(pdc_base);
 459         return ret;
 460 }
 461
 462 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);