drivers/iommu/mtk_iommu_v1.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * IOMMU API for MTK architected m4u v1 implementations
   4  *
   5  * Copyright (c) 2015-2016 MediaTek Inc.
   6  * Author: Honghui Zhang <honghui.zhang@mediatek.com>
   7  *
   8  * Based on driver/iommu/mtk_iommu.c
   9  */
  10 #include <linux/memblock.h>
  11 #include <linux/bug.h>
  12 #include <linux/clk.h>
  13 #include <linux/component.h>
  14 #include <linux/device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dma-iommu.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/iommu.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/list.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_iommu.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/spinlock.h>
  31 #include <asm/barrier.h>
  32 #include <asm/dma-iommu.h>
  33 #include <linux/init.h>
  34 #include <dt-bindings/memory/mt2701-larb-port.h>
  35 #include <soc/mediatek/smi.h>
  36 #include "mtk_iommu.h"
  37
  38 #define REG_MMU_PT_BASE_ADDR                    0x000
  39
  40 #define F_ALL_INVLD                             0x2
  41 #define F_MMU_INV_RANGE                         0x1
  42 #define F_INVLD_EN0                             BIT(0)
  43 #define F_INVLD_EN1                             BIT(1)
  44
  45 #define F_MMU_FAULT_VA_MSK                      0xfffff000
  46 #define MTK_PROTECT_PA_ALIGN                    128
  47
  48 #define REG_MMU_CTRL_REG                        0x210
  49 #define F_MMU_CTRL_COHERENT_EN                  BIT(8)
  50 #define REG_MMU_IVRP_PADDR                      0x214
  51 #define REG_MMU_INT_CONTROL                     0x220
  52 #define F_INT_TRANSLATION_FAULT                 BIT(0)
  53 #define F_INT_MAIN_MULTI_HIT_FAULT              BIT(1)
  54 #define F_INT_INVALID_PA_FAULT                  BIT(2)
  55 #define F_INT_ENTRY_REPLACEMENT_FAULT           BIT(3)
  56 #define F_INT_TABLE_WALK_FAULT                  BIT(4)
  57 #define F_INT_TLB_MISS_FAULT                    BIT(5)
  58 #define F_INT_PFH_DMA_FIFO_OVERFLOW             BIT(6)
  59 #define F_INT_MISS_DMA_FIFO_OVERFLOW            BIT(7)
  60
  61 #define F_MMU_TF_PROTECT_SEL(prot)              (((prot) & 0x3) << 5)
  62 #define F_INT_CLR_BIT                           BIT(12)
  63
  64 #define REG_MMU_FAULT_ST                        0x224
  65 #define REG_MMU_FAULT_VA                        0x228
  66 #define REG_MMU_INVLD_PA                        0x22C
  67 #define REG_MMU_INT_ID                          0x388
  68 #define REG_MMU_INVALIDATE                      0x5c0
  69 #define REG_MMU_INVLD_START_A                   0x5c4
  70 #define REG_MMU_INVLD_END_A                     0x5c8
  71
  72 #define REG_MMU_INV_SEL                         0x5d8
  73 #define REG_MMU_STANDARD_AXI_MODE               0x5e8
  74
  75 #define REG_MMU_DCM                             0x5f0
  76 #define F_MMU_DCM_ON                            BIT(1)
  77 #define REG_MMU_CPE_DONE                        0x60c
  78 #define F_DESC_VALID                            0x2
  79 #define F_DESC_NONSEC                           BIT(3)
  80 #define MT2701_M4U_TF_LARB(TF)                  (6 - (((TF) >> 13) & 0x7))
  81 #define MT2701_M4U_TF_PORT(TF)                  (((TF) >> 8) & 0xF)
  82 /* MTK generation one iommu HW only support 4K size mapping */
  83 #define MT2701_IOMMU_PAGE_SHIFT                 12
  84 #define MT2701_IOMMU_PAGE_SIZE                  (1UL << MT2701_IOMMU_PAGE_SHIFT)
  85
  86 /*
  87  * MTK m4u support 4GB iova address space, and only support 4K page
  88  * mapping. So the pagetable size should be exactly as 4M.
  89  */
  90 #define M2701_IOMMU_PGT_SIZE                    SZ_4M
  91
  92 struct mtk_iommu_domain {
  93         spinlock_t                      pgtlock; /* lock for page table */
  94         struct iommu_domain             domain;
  95         u32                             *pgt_va;
  96         dma_addr_t                      pgt_pa;
  97         struct mtk_iommu_data           *data;
  98 };
  99
 100 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 101 {
 102         return container_of(dom, struct mtk_iommu_domain, domain);
 103 }
 104
 105 static const int mt2701_m4u_in_larb[] = {
 106         LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
 107         LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
 108 };
 109
 110 static inline int mt2701_m4u_to_larb(int id)
 111 {
 112         int i;
 113
 114         for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
 115                 if ((id) >= mt2701_m4u_in_larb[i])
 116                         return i;
 117
 118         return 0;
 119 }
 120
 121 static inline int mt2701_m4u_to_port(int id)
 122 {
 123         int larb = mt2701_m4u_to_larb(id);
 124
 125         return id - mt2701_m4u_in_larb[larb];
 126 }
 127
 128 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 129 {
 130         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 131                         data->base + REG_MMU_INV_SEL);
 132         writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 133         wmb(); /* Make sure the tlb flush all done */
 134 }
 135
 136 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
 137                                 unsigned long iova, size_t size)
 138 {
 139         int ret;
 140         u32 tmp;
 141
 142         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 143                 data->base + REG_MMU_INV_SEL);
 144         writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
 145                 data->base + REG_MMU_INVLD_START_A);
 146         writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
 147                 data->base + REG_MMU_INVLD_END_A);
 148         writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
 149
 150         ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 151                                 tmp, tmp != 0, 10, 100000);
 152         if (ret) {
 153                 dev_warn(data->dev,
 154                          "Partial TLB flush timed out, falling back to full flush\n");
 155                 mtk_iommu_tlb_flush_all(data);
 156         }
 157         /* Clear the CPE status */
 158         writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 159 }
 160
 161 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 162 {
 163         struct mtk_iommu_data *data = dev_id;
 164         struct mtk_iommu_domain *dom = data->m4u_dom;
 165         u32 int_state, regval, fault_iova, fault_pa;
 166         unsigned int fault_larb, fault_port;
 167
 168         /* Read error information from registers */
 169         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
 170         fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
 171
 172         fault_iova &= F_MMU_FAULT_VA_MSK;
 173         fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
 174         regval = readl_relaxed(data->base + REG_MMU_INT_ID);
 175         fault_larb = MT2701_M4U_TF_LARB(regval);
 176         fault_port = MT2701_M4U_TF_PORT(regval);
 177
 178         /*
 179          * MTK v1 iommu HW could not determine whether the fault is read or
 180          * write fault, report as read fault.
 181          */
 182         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 183                         IOMMU_FAULT_READ))
 184                 dev_err_ratelimited(data->dev,
 185                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
 186                         int_state, fault_iova, fault_pa,
 187                         fault_larb, fault_port);
 188
 189         /* Interrupt clear */
 190         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
 191         regval |= F_INT_CLR_BIT;
 192         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 193
 194         mtk_iommu_tlb_flush_all(data);
 195
 196         return IRQ_HANDLED;
 197 }
 198
 199 static void mtk_iommu_config(struct mtk_iommu_data *data,
 200                              struct device *dev, bool enable)
 201 {
 202         struct mtk_smi_larb_iommu    *larb_mmu;
 203         unsigned int                 larbid, portid;
 204         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 205         int i;
 206
 207         for (i = 0; i < fwspec->num_ids; ++i) {
 208                 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
 209                 portid = mt2701_m4u_to_port(fwspec->ids[i]);
 210                 larb_mmu = &data->larb_imu[larbid];
 211
 212                 dev_dbg(dev, "%s iommu port: %d\n",
 213                         enable ? "enable" : "disable", portid);
 214
 215                 if (enable)
 216                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 217                 else
 218                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 219         }
 220 }
 221
 222 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
 223 {
 224         struct mtk_iommu_domain *dom = data->m4u_dom;
 225
 226         spin_lock_init(&dom->pgtlock);
 227
 228         dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 229                                          &dom->pgt_pa, GFP_KERNEL);
 230         if (!dom->pgt_va)
 231                 return -ENOMEM;
 232
 233         writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
 234
 235         dom->data = data;
 236
 237         return 0;
 238 }
 239
 240 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 241 {
 242         struct mtk_iommu_domain *dom;
 243
 244         if (type != IOMMU_DOMAIN_UNMANAGED)
 245                 return NULL;
 246
 247         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 248         if (!dom)
 249                 return NULL;
 250
 251         return &dom->domain;
 252 }
 253
 254 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 255 {
 256         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 257         struct mtk_iommu_data *data = dom->data;
 258
 259         dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
 260                         dom->pgt_va, dom->pgt_pa);
 261         kfree(to_mtk_domain(domain));
 262 }
 263
 264 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 265                                    struct device *dev)
 266 {
 267         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 268         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 269         struct dma_iommu_mapping *mtk_mapping;
 270         int ret;
 271
 272         /* Only allow the domain created internally. */
 273         mtk_mapping = data->mapping;
 274         if (mtk_mapping->domain != domain)
 275                 return 0;
 276
 277         if (!data->m4u_dom) {
 278                 data->m4u_dom = dom;
 279                 ret = mtk_iommu_domain_finalise(data);
 280                 if (ret) {
 281                         data->m4u_dom = NULL;
 282                         return ret;
 283                 }
 284         }
 285
 286         mtk_iommu_config(data, dev, true);
 287         return 0;
 288 }
 289
 290 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 291                                     struct device *dev)
 292 {
 293         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 294
 295         mtk_iommu_config(data, dev, false);
 296 }
 297
 298 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 299                          phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 300 {
 301         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 302         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 303         unsigned long flags;
 304         unsigned int i;
 305         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 306         u32 pabase = (u32)paddr;
 307         int map_size = 0;
 308
 309         spin_lock_irqsave(&dom->pgtlock, flags);
 310         for (i = 0; i < page_num; i++) {
 311                 if (pgt_base_iova[i]) {
 312                         memset(pgt_base_iova, 0, i * sizeof(u32));
 313                         break;
 314                 }
 315                 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
 316                 pabase += MT2701_IOMMU_PAGE_SIZE;
 317                 map_size += MT2701_IOMMU_PAGE_SIZE;
 318         }
 319
 320         spin_unlock_irqrestore(&dom->pgtlock, flags);
 321
 322         mtk_iommu_tlb_flush_range(dom->data, iova, size);
 323
 324         return map_size == size ? 0 : -EEXIST;
 325 }
 326
 327 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 328                               unsigned long iova, size_t size,
 329                               struct iommu_iotlb_gather *gather)
 330 {
 331         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 332         unsigned long flags;
 333         u32 *pgt_base_iova = dom->pgt_va + (iova  >> MT2701_IOMMU_PAGE_SHIFT);
 334         unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
 335
 336         spin_lock_irqsave(&dom->pgtlock, flags);
 337         memset(pgt_base_iova, 0, page_num * sizeof(u32));
 338         spin_unlock_irqrestore(&dom->pgtlock, flags);
 339
 340         mtk_iommu_tlb_flush_range(dom->data, iova, size);
 341
 342         return size;
 343 }
 344
 345 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 346                                           dma_addr_t iova)
 347 {
 348         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 349         unsigned long flags;
 350         phys_addr_t pa;
 351
 352         spin_lock_irqsave(&dom->pgtlock, flags);
 353         pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
 354         pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
 355         spin_unlock_irqrestore(&dom->pgtlock, flags);
 356
 357         return pa;
 358 }
 359
 360 static const struct iommu_ops mtk_iommu_ops;
 361
 362 /*
 363  * MTK generation one iommu HW only support one iommu domain, and all the client
 364  * sharing the same iova address space.
 365  */
 366 static int mtk_iommu_create_mapping(struct device *dev,
 367                                     struct of_phandle_args *args)
 368 {
 369         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 370         struct mtk_iommu_data *data;
 371         struct platform_device *m4updev;
 372         struct dma_iommu_mapping *mtk_mapping;
 373         int ret;
 374
 375         if (args->args_count != 1) {
 376                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 377                         args->args_count);
 378                 return -EINVAL;
 379         }
 380
 381         if (!fwspec) {
 382                 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
 383                 if (ret)
 384                         return ret;
 385                 fwspec = dev_iommu_fwspec_get(dev);
 386         } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
 387                 return -EINVAL;
 388         }
 389
 390         if (!dev_iommu_priv_get(dev)) {
 391                 /* Get the m4u device */
 392                 m4updev = of_find_device_by_node(args->np);
 393                 if (WARN_ON(!m4updev))
 394                         return -EINVAL;
 395
 396                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 397         }
 398
 399         ret = iommu_fwspec_add_ids(dev, args->args, 1);
 400         if (ret)
 401                 return ret;
 402
 403         data = dev_iommu_priv_get(dev);
 404         mtk_mapping = data->mapping;
 405         if (!mtk_mapping) {
 406                 /* MTK iommu support 4GB iova address space. */
 407                 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
 408                                                 0, 1ULL << 32);
 409                 if (IS_ERR(mtk_mapping))
 410                         return PTR_ERR(mtk_mapping);
 411
 412                 data->mapping = mtk_mapping;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int mtk_iommu_def_domain_type(struct device *dev)
 419 {
 420         return IOMMU_DOMAIN_UNMANAGED;
 421 }
 422
 423 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 424 {
 425         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 426         struct of_phandle_args iommu_spec;
 427         struct mtk_iommu_data *data;
 428         int err, idx = 0;
 429
 430         while (!of_parse_phandle_with_args(dev->of_node, "iommus",
 431                                            "#iommu-cells",
 432                                            idx, &iommu_spec)) {
 433
 434                 err = mtk_iommu_create_mapping(dev, &iommu_spec);
 435                 of_node_put(iommu_spec.np);
 436                 if (err)
 437                         return ERR_PTR(err);
 438
 439                 /* dev->iommu_fwspec might have changed */
 440                 fwspec = dev_iommu_fwspec_get(dev);
 441                 idx++;
 442         }
 443
 444         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 445                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 446
 447         data = dev_iommu_priv_get(dev);
 448
 449         return &data->iommu;
 450 }
 451
 452 static void mtk_iommu_probe_finalize(struct device *dev)
 453 {
 454         struct dma_iommu_mapping *mtk_mapping;
 455         struct mtk_iommu_data *data;
 456         int err;
 457
 458         data        = dev_iommu_priv_get(dev);
 459         mtk_mapping = data->mapping;
 460
 461         err = arm_iommu_attach_device(dev, mtk_mapping);
 462         if (err)
 463                 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
 464 }
 465
 466 static void mtk_iommu_release_device(struct device *dev)
 467 {
 468         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 469
 470         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 471                 return;
 472
 473         iommu_fwspec_free(dev);
 474 }
 475
 476 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 477 {
 478         u32 regval;
 479         int ret;
 480
 481         ret = clk_prepare_enable(data->bclk);
 482         if (ret) {
 483                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
 484                 return ret;
 485         }
 486
 487         regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
 488         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 489
 490         regval = F_INT_TRANSLATION_FAULT |
 491                 F_INT_MAIN_MULTI_HIT_FAULT |
 492                 F_INT_INVALID_PA_FAULT |
 493                 F_INT_ENTRY_REPLACEMENT_FAULT |
 494                 F_INT_TABLE_WALK_FAULT |
 495                 F_INT_TLB_MISS_FAULT |
 496                 F_INT_PFH_DMA_FIFO_OVERFLOW |
 497                 F_INT_MISS_DMA_FIFO_OVERFLOW;
 498         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
 499
 500         /* protect memory,hw will write here while translation fault */
 501         writel_relaxed(data->protect_base,
 502                         data->base + REG_MMU_IVRP_PADDR);
 503
 504         writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
 505
 506         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 507                              dev_name(data->dev), (void *)data)) {
 508                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 509                 clk_disable_unprepare(data->bclk);
 510                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 511                 return -ENODEV;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static const struct iommu_ops mtk_iommu_ops = {
 518         .domain_alloc   = mtk_iommu_domain_alloc,
 519         .domain_free    = mtk_iommu_domain_free,
 520         .attach_dev     = mtk_iommu_attach_device,
 521         .detach_dev     = mtk_iommu_detach_device,
 522         .map            = mtk_iommu_map,
 523         .unmap          = mtk_iommu_unmap,
 524         .iova_to_phys   = mtk_iommu_iova_to_phys,
 525         .probe_device   = mtk_iommu_probe_device,
 526         .probe_finalize = mtk_iommu_probe_finalize,
 527         .release_device = mtk_iommu_release_device,
 528         .def_domain_type = mtk_iommu_def_domain_type,
 529         .device_group   = generic_device_group,
 530         .pgsize_bitmap  = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
 531         .owner          = THIS_MODULE,
 532 };
 533
 534 static const struct of_device_id mtk_iommu_of_ids[] = {
 535         { .compatible = "mediatek,mt2701-m4u", },
 536         {}
 537 };
 538
 539 static const struct component_master_ops mtk_iommu_com_ops = {
 540         .bind           = mtk_iommu_bind,
 541         .unbind         = mtk_iommu_unbind,
 542 };
 543
 544 static int mtk_iommu_probe(struct platform_device *pdev)
 545 {
 546         struct mtk_iommu_data           *data;
 547         struct device                   *dev = &pdev->dev;
 548         struct resource                 *res;
 549         struct component_match          *match = NULL;
 550         void                            *protect;
 551         int                             larb_nr, ret, i;
 552
 553         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 554         if (!data)
 555                 return -ENOMEM;
 556
 557         data->dev = dev;
 558
 559         /* Protect memory. HW will access here while translation fault.*/
 560         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
 561                         GFP_KERNEL | GFP_DMA);
 562         if (!protect)
 563                 return -ENOMEM;
 564         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 565
 566         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 567         data->base = devm_ioremap_resource(dev, res);
 568         if (IS_ERR(data->base))
 569                 return PTR_ERR(data->base);
 570
 571         data->irq = platform_get_irq(pdev, 0);
 572         if (data->irq < 0)
 573                 return data->irq;
 574
 575         data->bclk = devm_clk_get(dev, "bclk");
 576         if (IS_ERR(data->bclk))
 577                 return PTR_ERR(data->bclk);
 578
 579         larb_nr = of_count_phandle_with_args(dev->of_node,
 580                                              "mediatek,larbs", NULL);
 581         if (larb_nr < 0)
 582                 return larb_nr;
 583
 584         for (i = 0; i < larb_nr; i++) {
 585                 struct device_node *larbnode;
 586                 struct platform_device *plarbdev;
 587
 588                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 589                 if (!larbnode)
 590                         return -EINVAL;
 591
 592                 if (!of_device_is_available(larbnode)) {
 593                         of_node_put(larbnode);
 594                         continue;
 595                 }
 596
 597                 plarbdev = of_find_device_by_node(larbnode);
 598                 if (!plarbdev) {
 599                         of_node_put(larbnode);
 600                         return -EPROBE_DEFER;
 601                 }
 602                 data->larb_imu[i].dev = &plarbdev->dev;
 603
 604                 component_match_add_release(dev, &match, release_of,
 605                                             compare_of, larbnode);
 606         }
 607
 608         platform_set_drvdata(pdev, data);
 609
 610         ret = mtk_iommu_hw_init(data);
 611         if (ret)
 612                 return ret;
 613
 614         ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
 615                                      dev_name(&pdev->dev));
 616         if (ret)
 617                 return ret;
 618
 619         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
 620         if (ret)
 621                 goto out_sysfs_remove;
 622
 623         if (!iommu_present(&platform_bus_type)) {
 624                 ret = bus_set_iommu(&platform_bus_type,  &mtk_iommu_ops);
 625                 if (ret)
 626                         goto out_dev_unreg;
 627         }
 628
 629         ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
 630         if (ret)
 631                 goto out_bus_set_null;
 632         return ret;
 633
 634 out_bus_set_null:
 635         bus_set_iommu(&platform_bus_type, NULL);
 636 out_dev_unreg:
 637         iommu_device_unregister(&data->iommu);
 638 out_sysfs_remove:
 639         iommu_device_sysfs_remove(&data->iommu);
 640         return ret;
 641 }
 642
 643 static int mtk_iommu_remove(struct platform_device *pdev)
 644 {
 645         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
 646
 647         iommu_device_sysfs_remove(&data->iommu);
 648         iommu_device_unregister(&data->iommu);
 649
 650         if (iommu_present(&platform_bus_type))
 651                 bus_set_iommu(&platform_bus_type, NULL);
 652
 653         clk_disable_unprepare(data->bclk);
 654         devm_free_irq(&pdev->dev, data->irq, data);
 655         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
 656         return 0;
 657 }
 658
 659 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 660 {
 661         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 662         struct mtk_iommu_suspend_reg *reg = &data->reg;
 663         void __iomem *base = data->base;
 664
 665         reg->standard_axi_mode = readl_relaxed(base +
 666                                                REG_MMU_STANDARD_AXI_MODE);
 667         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
 668         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 669         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
 670         return 0;
 671 }
 672
 673 static int __maybe_unused mtk_iommu_resume(struct device *dev)
 674 {
 675         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 676         struct mtk_iommu_suspend_reg *reg = &data->reg;
 677         void __iomem *base = data->base;
 678
 679         writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
 680         writel_relaxed(reg->standard_axi_mode,
 681                        base + REG_MMU_STANDARD_AXI_MODE);
 682         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
 683         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 684         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
 685         writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
 686         return 0;
 687 }
 688
 689 static const struct dev_pm_ops mtk_iommu_pm_ops = {
 690         SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
 691 };
 692
 693 static struct platform_driver mtk_iommu_driver = {
 694         .probe  = mtk_iommu_probe,
 695         .remove = mtk_iommu_remove,
 696         .driver = {
 697                 .name = "mtk-iommu-v1",
 698                 .of_match_table = mtk_iommu_of_ids,
 699                 .pm = &mtk_iommu_pm_ops,
 700         }
 701 };
 702 module_platform_driver(mtk_iommu_driver);
 703
 704 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
 705 MODULE_LICENSE("GPL v2");