drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <yong.wu@mediatek.com>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/bug.h>
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-direct.h>
  12 #include <linux/dma-iommu.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/iommu.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/list.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regmap.h>
  28 #include <linux/slab.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/soc/mediatek/infracfg.h>
  31 #include <asm/barrier.h>
  32 #include <soc/mediatek/smi.h>
  33
  34 #include "mtk_iommu.h"
  35
  36 #define REG_MMU_PT_BASE_ADDR                    0x000
  37 #define MMU_PT_ADDR_MASK                        GENMASK(31, 7)
  38
  39 #define REG_MMU_INVALIDATE                      0x020
  40 #define F_ALL_INVLD                             0x2
  41 #define F_MMU_INV_RANGE                         0x1
  42
  43 #define REG_MMU_INVLD_START_A                   0x024
  44 #define REG_MMU_INVLD_END_A                     0x028
  45
  46 #define REG_MMU_INV_SEL_GEN2                    0x02c
  47 #define REG_MMU_INV_SEL_GEN1                    0x038
  48 #define F_INVLD_EN0                             BIT(0)
  49 #define F_INVLD_EN1                             BIT(1)
  50
  51 #define REG_MMU_MISC_CTRL                       0x048
  52 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  53 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  54
  55 #define REG_MMU_DCM_DIS                         0x050
  56 #define REG_MMU_WR_LEN_CTRL                     0x054
  57 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  58
  59 #define REG_MMU_CTRL_REG                        0x110
  60 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  61 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  62 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  63
  64 #define REG_MMU_IVRP_PADDR                      0x114
  65
  66 #define REG_MMU_VLD_PA_RNG                      0x118
  67 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  68
  69 #define REG_MMU_INT_CONTROL0                    0x120
  70 #define F_L2_MULIT_HIT_EN                       BIT(0)
  71 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  72 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  73 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  74 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  75 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  76 #define F_INT_CLR_BIT                           BIT(12)
  77
  78 #define REG_MMU_INT_MAIN_CONTROL                0x124
  79                                                 /* mmu0 | mmu1 */
  80 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  81 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  82 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  83 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  84 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  85 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  86 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  87
  88 #define REG_MMU_CPE_DONE                        0x12C
  89
  90 #define REG_MMU_FAULT_ST1                       0x134
  91 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  92 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  93
  94 #define REG_MMU0_FAULT_VA                       0x13c
  95 #define F_MMU_INVAL_VA_31_12_MASK               GENMASK(31, 12)
  96 #define F_MMU_INVAL_VA_34_32_MASK               GENMASK(11, 9)
  97 #define F_MMU_INVAL_PA_34_32_MASK               GENMASK(8, 6)
  98 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
  99 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
 100
 101 #define REG_MMU0_INVLD_PA                       0x140
 102 #define REG_MMU1_FAULT_VA                       0x144
 103 #define REG_MMU1_INVLD_PA                       0x148
 104 #define REG_MMU0_INT_ID                         0x150
 105 #define REG_MMU1_INT_ID                         0x154
 106 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 107 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 108 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 109 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 110
 111 #define MTK_PROTECT_PA_ALIGN                    256
 112
 113 #define HAS_4GB_MODE                    BIT(0)
 114 /* HW will use the EMI clock if there isn't the "bclk". */
 115 #define HAS_BCLK                        BIT(1)
 116 #define HAS_VLD_PA_RNG                  BIT(2)
 117 #define RESET_AXI                       BIT(3)
 118 #define OUT_ORDER_WR_EN                 BIT(4)
 119 #define HAS_SUB_COMM                    BIT(5)
 120 #define WR_THROT_EN                     BIT(6)
 121 #define HAS_LEGACY_IVRP_PADDR           BIT(7)
 122 #define IOVA_34_EN                      BIT(8)
 123
 124 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
 125                 ((((pdata)->flags) & (_x)) == (_x))
 126
 127 struct mtk_iommu_domain {
 128         struct io_pgtable_cfg           cfg;
 129         struct io_pgtable_ops           *iop;
 130
 131         struct mtk_iommu_data           *data;
 132         struct iommu_domain             domain;
 133 };
 134
 135 static const struct iommu_ops mtk_iommu_ops;
 136
 137 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
 138
 139 #define MTK_IOMMU_TLB_ADDR(iova) ({                                     \
 140         dma_addr_t _addr = iova;                                        \
 141         ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
 142 })
 143
 144 /*
 145  * In M4U 4GB mode, the physical address is remapped as below:
 146  *
 147  * CPU Physical address:
 148  * ====================
 149  *
 150  * 0      1G       2G     3G       4G     5G
 151  * |---A---|---B---|---C---|---D---|---E---|
 152  * +--I/O--+------------Memory-------------+
 153  *
 154  * IOMMU output physical address:
 155  *  =============================
 156  *
 157  *                                 4G      5G     6G      7G      8G
 158  *                                 |---E---|---B---|---C---|---D---|
 159  *                                 +------------Memory-------------+
 160  *
 161  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 162  * bit32 of the CPU physical address always is needed to set, and for Region
 163  * 'E', the CPU physical address keep as is.
 164  * Additionally, The iommu consumers always use the CPU phyiscal address.
 165  */
 166 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 167
 168 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 169
 170 #define for_each_m4u(data)      list_for_each_entry(data, &m4ulist, list)
 171
 172 struct mtk_iommu_iova_region {
 173         dma_addr_t              iova_base;
 174         unsigned long long      size;
 175 };
 176
 177 static const struct mtk_iommu_iova_region single_domain[] = {
 178         {.iova_base = 0,                .size = SZ_4G},
 179 };
 180
 181 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
 182         { .iova_base = 0x0,             .size = SZ_4G},         /* disp: 0 ~ 4G */
 183         #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
 184         { .iova_base = SZ_4G,           .size = SZ_4G},         /* vdec: 4G ~ 8G */
 185         { .iova_base = SZ_4G * 2,       .size = SZ_4G},         /* CAM/MDP: 8G ~ 12G */
 186         { .iova_base = 0x240000000ULL,  .size = 0x4000000},     /* CCU0 */
 187         { .iova_base = 0x244000000ULL,  .size = 0x4000000},     /* CCU1 */
 188         #endif
 189 };
 190
 191 /*
 192  * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
 193  * for the performance.
 194  *
 195  * Here always return the mtk_iommu_data of the first probed M4U where the
 196  * iommu domain information is recorded.
 197  */
 198 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
 199 {
 200         struct mtk_iommu_data *data;
 201
 202         for_each_m4u(data)
 203                 return data;
 204
 205         return NULL;
 206 }
 207
 208 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 209 {
 210         return container_of(dom, struct mtk_iommu_domain, domain);
 211 }
 212
 213 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 214 {
 215         for_each_m4u(data) {
 216                 if (pm_runtime_get_if_in_use(data->dev) <= 0)
 217                         continue;
 218
 219                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 220                                data->base + data->plat_data->inv_sel_reg);
 221                 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 222                 wmb(); /* Make sure the tlb flush all done */
 223
 224                 pm_runtime_put(data->dev);
 225         }
 226 }
 227
 228 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 229                                            size_t granule,
 230                                            struct mtk_iommu_data *data)
 231 {
 232         bool has_pm = !!data->dev->pm_domain;
 233         unsigned long flags;
 234         int ret;
 235         u32 tmp;
 236
 237         for_each_m4u(data) {
 238                 if (has_pm) {
 239                         if (pm_runtime_get_if_in_use(data->dev) <= 0)
 240                                 continue;
 241                 }
 242
 243                 spin_lock_irqsave(&data->tlb_lock, flags);
 244                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 245                                data->base + data->plat_data->inv_sel_reg);
 246
 247                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova),
 248                                data->base + REG_MMU_INVLD_START_A);
 249                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
 250                                data->base + REG_MMU_INVLD_END_A);
 251                 writel_relaxed(F_MMU_INV_RANGE,
 252                                data->base + REG_MMU_INVALIDATE);
 253
 254                 /* tlb sync */
 255                 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 256                                                 tmp, tmp != 0, 10, 1000);
 257                 if (ret) {
 258                         dev_warn(data->dev,
 259                                  "Partial TLB flush timed out, falling back to full flush\n");
 260                         mtk_iommu_tlb_flush_all(data);
 261                 }
 262                 /* Clear the CPE status */
 263                 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 264                 spin_unlock_irqrestore(&data->tlb_lock, flags);
 265
 266                 if (has_pm)
 267                         pm_runtime_put(data->dev);
 268         }
 269 }
 270
 271 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 272 {
 273         struct mtk_iommu_data *data = dev_id;
 274         struct mtk_iommu_domain *dom = data->m4u_dom;
 275         unsigned int fault_larb, fault_port, sub_comm = 0;
 276         u32 int_state, regval, va34_32, pa34_32;
 277         u64 fault_iova, fault_pa;
 278         bool layer, write;
 279
 280         /* Read error info from registers */
 281         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
 282         if (int_state & F_REG_MMU0_FAULT_MASK) {
 283                 regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
 284                 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
 285                 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
 286         } else {
 287                 regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
 288                 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
 289                 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
 290         }
 291         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 292         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 293         if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
 294                 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
 295                 pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
 296                 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
 297                 fault_iova |= (u64)va34_32 << 32;
 298                 fault_pa |= (u64)pa34_32 << 32;
 299         }
 300
 301         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 302         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
 303                 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 304                 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 305         } else {
 306                 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 307         }
 308         fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 309
 310         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 311                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 312                 dev_err_ratelimited(
 313                         data->dev,
 314                         "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
 315                         int_state, fault_iova, fault_pa, fault_larb, fault_port,
 316                         layer, write ? "write" : "read");
 317         }
 318
 319         /* Interrupt clear */
 320         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
 321         regval |= F_INT_CLR_BIT;
 322         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 323
 324         mtk_iommu_tlb_flush_all(data);
 325
 326         return IRQ_HANDLED;
 327 }
 328
 329 static int mtk_iommu_get_domain_id(struct device *dev,
 330                                    const struct mtk_iommu_plat_data *plat_data)
 331 {
 332         const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
 333         const struct bus_dma_region *dma_rgn = dev->dma_range_map;
 334         int i, candidate = -1;
 335         dma_addr_t dma_end;
 336
 337         if (!dma_rgn || plat_data->iova_region_nr == 1)
 338                 return 0;
 339
 340         dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
 341         for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
 342                 /* Best fit. */
 343                 if (dma_rgn->dma_start == rgn->iova_base &&
 344                     dma_end == rgn->iova_base + rgn->size - 1)
 345                         return i;
 346                 /* ok if it is inside this region. */
 347                 if (dma_rgn->dma_start >= rgn->iova_base &&
 348                     dma_end < rgn->iova_base + rgn->size)
 349                         candidate = i;
 350         }
 351
 352         if (candidate >= 0)
 353                 return candidate;
 354         dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
 355                 &dma_rgn->dma_start, dma_rgn->size);
 356         return -EINVAL;
 357 }
 358
 359 static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
 360                              bool enable, unsigned int domid)
 361 {
 362         struct mtk_smi_larb_iommu    *larb_mmu;
 363         unsigned int                 larbid, portid;
 364         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 365         const struct mtk_iommu_iova_region *region;
 366         int i;
 367
 368         for (i = 0; i < fwspec->num_ids; ++i) {
 369                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 370                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 371
 372                 larb_mmu = &data->larb_imu[larbid];
 373
 374                 region = data->plat_data->iova_region + domid;
 375                 larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
 376
 377                 dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
 378                         enable ? "enable" : "disable", dev_name(larb_mmu->dev),
 379                         portid, domid, larb_mmu->bank[portid]);
 380
 381                 if (enable)
 382                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 383                 else
 384                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 385         }
 386 }
 387
 388 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 389                                      struct mtk_iommu_data *data,
 390                                      unsigned int domid)
 391 {
 392         const struct mtk_iommu_iova_region *region;
 393
 394         /* Use the exist domain as there is only one pgtable here. */
 395         if (data->m4u_dom) {
 396                 dom->iop = data->m4u_dom->iop;
 397                 dom->cfg = data->m4u_dom->cfg;
 398                 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
 399                 goto update_iova_region;
 400         }
 401
 402         dom->cfg = (struct io_pgtable_cfg) {
 403                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 404                         IO_PGTABLE_QUIRK_NO_PERMS |
 405                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 406                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 407                 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
 408                 .iommu_dev = data->dev,
 409         };
 410
 411         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
 412                 dom->cfg.oas = data->enable_4GB ? 33 : 32;
 413         else
 414                 dom->cfg.oas = 35;
 415
 416         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 417         if (!dom->iop) {
 418                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 419                 return -EINVAL;
 420         }
 421
 422         /* Update our support page sizes bitmap */
 423         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 424
 425 update_iova_region:
 426         /* Update the iova region for this domain */
 427         region = data->plat_data->iova_region + domid;
 428         dom->domain.geometry.aperture_start = region->iova_base;
 429         dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
 430         dom->domain.geometry.force_aperture = true;
 431         return 0;
 432 }
 433
 434 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 435 {
 436         struct mtk_iommu_domain *dom;
 437
 438         if (type != IOMMU_DOMAIN_DMA)
 439                 return NULL;
 440
 441         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 442         if (!dom)
 443                 return NULL;
 444
 445         if (iommu_get_dma_cookie(&dom->domain)) {
 446                 kfree(dom);
 447                 return NULL;
 448         }
 449
 450         return &dom->domain;
 451 }
 452
 453 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 454 {
 455         iommu_put_dma_cookie(domain);
 456         kfree(to_mtk_domain(domain));
 457 }
 458
 459 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 460                                    struct device *dev)
 461 {
 462         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 463         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 464         struct device *m4udev = data->dev;
 465         int ret, domid;
 466
 467         domid = mtk_iommu_get_domain_id(dev, data->plat_data);
 468         if (domid < 0)
 469                 return domid;
 470
 471         if (!dom->data) {
 472                 if (mtk_iommu_domain_finalise(dom, data, domid))
 473                         return -ENODEV;
 474                 dom->data = data;
 475         }
 476
 477         if (!data->m4u_dom) { /* Initialize the M4U HW */
 478                 ret = pm_runtime_resume_and_get(m4udev);
 479                 if (ret < 0)
 480                         return ret;
 481
 482                 ret = mtk_iommu_hw_init(data);
 483                 if (ret) {
 484                         pm_runtime_put(m4udev);
 485                         return ret;
 486                 }
 487                 data->m4u_dom = dom;
 488                 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
 489                        data->base + REG_MMU_PT_BASE_ADDR);
 490
 491                 pm_runtime_put(m4udev);
 492         }
 493
 494         mtk_iommu_config(data, dev, true, domid);
 495         return 0;
 496 }
 497
 498 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 499                                     struct device *dev)
 500 {
 501         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 502
 503         mtk_iommu_config(data, dev, false, 0);
 504 }
 505
 506 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 507                          phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 508 {
 509         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 510
 511         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 512         if (dom->data->enable_4GB)
 513                 paddr |= BIT_ULL(32);
 514
 515         /* Synchronize with the tlb_lock */
 516         return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
 517 }
 518
 519 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 520                               unsigned long iova, size_t size,
 521                               struct iommu_iotlb_gather *gather)
 522 {
 523         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 524         unsigned long end = iova + size - 1;
 525
 526         if (gather->start > iova)
 527                 gather->start = iova;
 528         if (gather->end < end)
 529                 gather->end = end;
 530         return dom->iop->unmap(dom->iop, iova, size, gather);
 531 }
 532
 533 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 534 {
 535         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 536
 537         mtk_iommu_tlb_flush_all(dom->data);
 538 }
 539
 540 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 541                                  struct iommu_iotlb_gather *gather)
 542 {
 543         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 544         size_t length = gather->end - gather->start + 1;
 545
 546         mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
 547                                        dom->data);
 548 }
 549
 550 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
 551                                size_t size)
 552 {
 553         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 554
 555         mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data);
 556 }
 557
 558 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 559                                           dma_addr_t iova)
 560 {
 561         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 562         phys_addr_t pa;
 563
 564         pa = dom->iop->iova_to_phys(dom->iop, iova);
 565         if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 566                 pa &= ~BIT_ULL(32);
 567
 568         return pa;
 569 }
 570
 571 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 572 {
 573         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 574         struct mtk_iommu_data *data;
 575
 576         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 577                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 578
 579         data = dev_iommu_priv_get(dev);
 580
 581         return &data->iommu;
 582 }
 583
 584 static void mtk_iommu_release_device(struct device *dev)
 585 {
 586         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 587
 588         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 589                 return;
 590
 591         iommu_fwspec_free(dev);
 592 }
 593
 594 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 595 {
 596         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 597         struct iommu_group *group;
 598         int domid;
 599
 600         if (!data)
 601                 return ERR_PTR(-ENODEV);
 602
 603         domid = mtk_iommu_get_domain_id(dev, data->plat_data);
 604         if (domid < 0)
 605                 return ERR_PTR(domid);
 606
 607         group = data->m4u_group[domid];
 608         if (!group) {
 609                 group = iommu_group_alloc();
 610                 if (!IS_ERR(group))
 611                         data->m4u_group[domid] = group;
 612         } else {
 613                 iommu_group_ref_get(group);
 614         }
 615         return group;
 616 }
 617
 618 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 619 {
 620         struct platform_device *m4updev;
 621
 622         if (args->args_count != 1) {
 623                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 624                         args->args_count);
 625                 return -EINVAL;
 626         }
 627
 628         if (!dev_iommu_priv_get(dev)) {
 629                 /* Get the m4u device */
 630                 m4updev = of_find_device_by_node(args->np);
 631                 if (WARN_ON(!m4updev))
 632                         return -EINVAL;
 633
 634                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 635         }
 636
 637         return iommu_fwspec_add_ids(dev, args->args, 1);
 638 }
 639
 640 static void mtk_iommu_get_resv_regions(struct device *dev,
 641                                        struct list_head *head)
 642 {
 643         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 644         unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i;
 645         const struct mtk_iommu_iova_region *resv, *curdom;
 646         struct iommu_resv_region *region;
 647         int prot = IOMMU_WRITE | IOMMU_READ;
 648
 649         if ((int)domid < 0)
 650                 return;
 651         curdom = data->plat_data->iova_region + domid;
 652         for (i = 0; i < data->plat_data->iova_region_nr; i++) {
 653                 resv = data->plat_data->iova_region + i;
 654
 655                 /* Only reserve when the region is inside the current domain */
 656                 if (resv->iova_base <= curdom->iova_base ||
 657                     resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
 658                         continue;
 659
 660                 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
 661                                                  prot, IOMMU_RESV_RESERVED);
 662                 if (!region)
 663                         return;
 664
 665                 list_add_tail(&region->list, head);
 666         }
 667 }
 668
 669 static const struct iommu_ops mtk_iommu_ops = {
 670         .domain_alloc   = mtk_iommu_domain_alloc,
 671         .domain_free    = mtk_iommu_domain_free,
 672         .attach_dev     = mtk_iommu_attach_device,
 673         .detach_dev     = mtk_iommu_detach_device,
 674         .map            = mtk_iommu_map,
 675         .unmap          = mtk_iommu_unmap,
 676         .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
 677         .iotlb_sync     = mtk_iommu_iotlb_sync,
 678         .iotlb_sync_map = mtk_iommu_sync_map,
 679         .iova_to_phys   = mtk_iommu_iova_to_phys,
 680         .probe_device   = mtk_iommu_probe_device,
 681         .release_device = mtk_iommu_release_device,
 682         .device_group   = mtk_iommu_device_group,
 683         .of_xlate       = mtk_iommu_of_xlate,
 684         .get_resv_regions = mtk_iommu_get_resv_regions,
 685         .put_resv_regions = generic_iommu_put_resv_regions,
 686         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 687         .owner          = THIS_MODULE,
 688 };
 689
 690 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 691 {
 692         u32 regval;
 693
 694         if (data->plat_data->m4u_plat == M4U_MT8173) {
 695                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
 696                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
 697         } else {
 698                 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
 699                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
 700         }
 701         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 702
 703         regval = F_L2_MULIT_HIT_EN |
 704                 F_TABLE_WALK_FAULT_INT_EN |
 705                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
 706                 F_MISS_FIFO_OVERFLOW_INT_EN |
 707                 F_PREFETCH_FIFO_ERR_INT_EN |
 708                 F_MISS_FIFO_ERR_INT_EN;
 709         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 710
 711         regval = F_INT_TRANSLATION_FAULT |
 712                 F_INT_MAIN_MULTI_HIT_FAULT |
 713                 F_INT_INVALID_PA_FAULT |
 714                 F_INT_ENTRY_REPLACEMENT_FAULT |
 715                 F_INT_TLB_MISS_FAULT |
 716                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
 717                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
 718         writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
 719
 720         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
 721                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
 722         else
 723                 regval = lower_32_bits(data->protect_base) |
 724                          upper_32_bits(data->protect_base);
 725         writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 726
 727         if (data->enable_4GB &&
 728             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
 729                 /*
 730                  * If 4GB mode is enabled, the validate PA range is from
 731                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
 732                  */
 733                 regval = F_MMU_VLD_PA_RNG(7, 4);
 734                 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
 735         }
 736         writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 737         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
 738                 /* write command throttling mode */
 739                 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
 740                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
 741                 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
 742         }
 743
 744         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
 745                 /* The register is called STANDARD_AXI_MODE in this case */
 746                 regval = 0;
 747         } else {
 748                 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
 749                 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
 750                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
 751                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
 752         }
 753         writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
 754
 755         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 756                              dev_name(data->dev), (void *)data)) {
 757                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 758                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 759                 return -ENODEV;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static const struct component_master_ops mtk_iommu_com_ops = {
 766         .bind           = mtk_iommu_bind,
 767         .unbind         = mtk_iommu_unbind,
 768 };
 769
 770 static int mtk_iommu_probe(struct platform_device *pdev)
 771 {
 772         struct mtk_iommu_data   *data;
 773         struct device           *dev = &pdev->dev;
 774         struct device_node      *larbnode, *smicomm_node;
 775         struct platform_device  *plarbdev;
 776         struct device_link      *link;
 777         struct resource         *res;
 778         resource_size_t         ioaddr;
 779         struct component_match  *match = NULL;
 780         struct regmap           *infracfg;
 781         void                    *protect;
 782         int                     i, larb_nr, ret;
 783         u32                     val;
 784         char                    *p;
 785
 786         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 787         if (!data)
 788                 return -ENOMEM;
 789         data->dev = dev;
 790         data->plat_data = of_device_get_match_data(dev);
 791
 792         /* Protect memory. HW will access here while translation fault.*/
 793         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
 794         if (!protect)
 795                 return -ENOMEM;
 796         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 797
 798         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
 799                 switch (data->plat_data->m4u_plat) {
 800                 case M4U_MT2712:
 801                         p = "mediatek,mt2712-infracfg";
 802                         break;
 803                 case M4U_MT8173:
 804                         p = "mediatek,mt8173-infracfg";
 805                         break;
 806                 default:
 807                         p = NULL;
 808                 }
 809
 810                 infracfg = syscon_regmap_lookup_by_compatible(p);
 811
 812                 if (IS_ERR(infracfg))
 813                         return PTR_ERR(infracfg);
 814
 815                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
 816                 if (ret)
 817                         return ret;
 818                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
 819         }
 820
 821         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 822         data->base = devm_ioremap_resource(dev, res);
 823         if (IS_ERR(data->base))
 824                 return PTR_ERR(data->base);
 825         ioaddr = res->start;
 826
 827         data->irq = platform_get_irq(pdev, 0);
 828         if (data->irq < 0)
 829                 return data->irq;
 830
 831         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
 832                 data->bclk = devm_clk_get(dev, "bclk");
 833                 if (IS_ERR(data->bclk))
 834                         return PTR_ERR(data->bclk);
 835         }
 836
 837         larb_nr = of_count_phandle_with_args(dev->of_node,
 838                                              "mediatek,larbs", NULL);
 839         if (larb_nr < 0)
 840                 return larb_nr;
 841
 842         for (i = 0; i < larb_nr; i++) {
 843                 u32 id;
 844
 845                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 846                 if (!larbnode)
 847                         return -EINVAL;
 848
 849                 if (!of_device_is_available(larbnode)) {
 850                         of_node_put(larbnode);
 851                         continue;
 852                 }
 853
 854                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
 855                 if (ret)/* The id is consecutive if there is no this property */
 856                         id = i;
 857
 858                 plarbdev = of_find_device_by_node(larbnode);
 859                 if (!plarbdev) {
 860                         of_node_put(larbnode);
 861                         return -EPROBE_DEFER;
 862                 }
 863                 data->larb_imu[id].dev = &plarbdev->dev;
 864
 865                 component_match_add_release(dev, &match, release_of,
 866                                             compare_of, larbnode);
 867         }
 868
 869         /* Get smi-common dev from the last larb. */
 870         smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
 871         if (!smicomm_node)
 872                 return -EINVAL;
 873
 874         plarbdev = of_find_device_by_node(smicomm_node);
 875         of_node_put(smicomm_node);
 876         data->smicomm_dev = &plarbdev->dev;
 877
 878         pm_runtime_enable(dev);
 879
 880         link = device_link_add(data->smicomm_dev, dev,
 881                         DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
 882         if (!link) {
 883                 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
 884                 ret = -EINVAL;
 885                 goto out_runtime_disable;
 886         }
 887
 888         platform_set_drvdata(pdev, data);
 889
 890         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
 891                                      "mtk-iommu.%pa", &ioaddr);
 892         if (ret)
 893                 goto out_link_remove;
 894
 895         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
 896         if (ret)
 897                 goto out_sysfs_remove;
 898
 899         spin_lock_init(&data->tlb_lock);
 900         list_add_tail(&data->list, &m4ulist);
 901
 902         if (!iommu_present(&platform_bus_type)) {
 903                 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
 904                 if (ret)
 905                         goto out_list_del;
 906         }
 907
 908         ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
 909         if (ret)
 910                 goto out_bus_set_null;
 911         return ret;
 912
 913 out_bus_set_null:
 914         bus_set_iommu(&platform_bus_type, NULL);
 915 out_list_del:
 916         list_del(&data->list);
 917         iommu_device_unregister(&data->iommu);
 918 out_sysfs_remove:
 919         iommu_device_sysfs_remove(&data->iommu);
 920 out_link_remove:
 921         device_link_remove(data->smicomm_dev, dev);
 922 out_runtime_disable:
 923         pm_runtime_disable(dev);
 924         return ret;
 925 }
 926
 927 static int mtk_iommu_remove(struct platform_device *pdev)
 928 {
 929         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
 930
 931         iommu_device_sysfs_remove(&data->iommu);
 932         iommu_device_unregister(&data->iommu);
 933
 934         if (iommu_present(&platform_bus_type))
 935                 bus_set_iommu(&platform_bus_type, NULL);
 936
 937         clk_disable_unprepare(data->bclk);
 938         device_link_remove(data->smicomm_dev, &pdev->dev);
 939         pm_runtime_disable(&pdev->dev);
 940         devm_free_irq(&pdev->dev, data->irq, data);
 941         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
 942         return 0;
 943 }
 944
 945 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
 946 {
 947         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 948         struct mtk_iommu_suspend_reg *reg = &data->reg;
 949         void __iomem *base = data->base;
 950
 951         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
 952         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
 953         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
 954         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 955         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 956         reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
 957         reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
 958         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
 959         clk_disable_unprepare(data->bclk);
 960         return 0;
 961 }
 962
 963 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
 964 {
 965         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 966         struct mtk_iommu_suspend_reg *reg = &data->reg;
 967         struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
 968         void __iomem *base = data->base;
 969         int ret;
 970
 971         ret = clk_prepare_enable(data->bclk);
 972         if (ret) {
 973                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 974                 return ret;
 975         }
 976
 977         /*
 978          * Uppon first resume, only enable the clk and return, since the values of the
 979          * registers are not yet set.
 980          */
 981         if (!m4u_dom)
 982                 return 0;
 983
 984         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
 985         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
 986         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
 987         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 988         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
 989         writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
 990         writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
 991         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
 992         writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
 993         return 0;
 994 }
 995
 996 static const struct dev_pm_ops mtk_iommu_pm_ops = {
 997         SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
 998         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 999                                      pm_runtime_force_resume)
1000 };
1001
1002 static const struct mtk_iommu_plat_data mt2712_data = {
1003         .m4u_plat     = M4U_MT2712,
1004         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
1005         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1006         .iova_region  = single_domain,
1007         .iova_region_nr = ARRAY_SIZE(single_domain),
1008         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1009 };
1010
1011 static const struct mtk_iommu_plat_data mt6779_data = {
1012         .m4u_plat      = M4U_MT6779,
1013         .flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
1014         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
1015         .iova_region   = single_domain,
1016         .iova_region_nr = ARRAY_SIZE(single_domain),
1017         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1018 };
1019
1020 static const struct mtk_iommu_plat_data mt8167_data = {
1021         .m4u_plat     = M4U_MT8167,
1022         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
1023         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1024         .iova_region  = single_domain,
1025         .iova_region_nr = ARRAY_SIZE(single_domain),
1026         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1027 };
1028
1029 static const struct mtk_iommu_plat_data mt8173_data = {
1030         .m4u_plat     = M4U_MT8173,
1031         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1032                         HAS_LEGACY_IVRP_PADDR,
1033         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1034         .iova_region  = single_domain,
1035         .iova_region_nr = ARRAY_SIZE(single_domain),
1036         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1037 };
1038
1039 static const struct mtk_iommu_plat_data mt8183_data = {
1040         .m4u_plat     = M4U_MT8183,
1041         .flags        = RESET_AXI,
1042         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1043         .iova_region  = single_domain,
1044         .iova_region_nr = ARRAY_SIZE(single_domain),
1045         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1046 };
1047
1048 static const struct mtk_iommu_plat_data mt8192_data = {
1049         .m4u_plat       = M4U_MT8192,
1050         .flags          = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
1051                           WR_THROT_EN | IOVA_34_EN,
1052         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1053         .iova_region    = mt8192_multi_dom,
1054         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1055         .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1056                            {0, 14, 16}, {0, 13, 18, 17}},
1057 };
1058
1059 static const struct of_device_id mtk_iommu_of_ids[] = {
1060         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1061         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1062         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1063         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1064         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1065         { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1066         {}
1067 };
1068
1069 static struct platform_driver mtk_iommu_driver = {
1070         .probe  = mtk_iommu_probe,
1071         .remove = mtk_iommu_remove,
1072         .driver = {
1073                 .name = "mtk-iommu",
1074                 .of_match_table = mtk_iommu_of_ids,
1075                 .pm = &mtk_iommu_pm_ops,
1076         }
1077 };
1078 module_platform_driver(mtk_iommu_driver);
1079
1080 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1081 MODULE_LICENSE("GPL v2");