drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <yong.wu@mediatek.com>
   5  */
   6 #include <linux/bug.h>
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/device.h>
  10 #include <linux/dma-iommu.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/iommu.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/list.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_iommu.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/soc/mediatek/infracfg.h>
  27 #include <asm/barrier.h>
  28 #include <soc/mediatek/smi.h>
  29
  30 #include "mtk_iommu.h"
  31
  32 #define REG_MMU_PT_BASE_ADDR                    0x000
  33 #define MMU_PT_ADDR_MASK                        GENMASK(31, 7)
  34
  35 #define REG_MMU_INVALIDATE                      0x020
  36 #define F_ALL_INVLD                             0x2
  37 #define F_MMU_INV_RANGE                         0x1
  38
  39 #define REG_MMU_INVLD_START_A                   0x024
  40 #define REG_MMU_INVLD_END_A                     0x028
  41
  42 #define REG_MMU_INV_SEL_GEN2                    0x02c
  43 #define REG_MMU_INV_SEL_GEN1                    0x038
  44 #define F_INVLD_EN0                             BIT(0)
  45 #define F_INVLD_EN1                             BIT(1)
  46
  47 #define REG_MMU_MISC_CTRL                       0x048
  48 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  49 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  50
  51 #define REG_MMU_DCM_DIS                         0x050
  52 #define REG_MMU_WR_LEN_CTRL                     0x054
  53 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  54
  55 #define REG_MMU_CTRL_REG                        0x110
  56 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  57 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  58 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  59
  60 #define REG_MMU_IVRP_PADDR                      0x114
  61
  62 #define REG_MMU_VLD_PA_RNG                      0x118
  63 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  64
  65 #define REG_MMU_INT_CONTROL0                    0x120
  66 #define F_L2_MULIT_HIT_EN                       BIT(0)
  67 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  68 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  69 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  70 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  71 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  72 #define F_INT_CLR_BIT                           BIT(12)
  73
  74 #define REG_MMU_INT_MAIN_CONTROL                0x124
  75                                                 /* mmu0 | mmu1 */
  76 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  77 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  78 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  79 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  80 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  81 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  82 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  83
  84 #define REG_MMU_CPE_DONE                        0x12C
  85
  86 #define REG_MMU_FAULT_ST1                       0x134
  87 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  88 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  89
  90 #define REG_MMU0_FAULT_VA                       0x13c
  91 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
  92 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
  93
  94 #define REG_MMU0_INVLD_PA                       0x140
  95 #define REG_MMU1_FAULT_VA                       0x144
  96 #define REG_MMU1_INVLD_PA                       0x148
  97 #define REG_MMU0_INT_ID                         0x150
  98 #define REG_MMU1_INT_ID                         0x154
  99 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 100 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 101 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 102 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 103
 104 #define MTK_PROTECT_PA_ALIGN                    256
 105
 106 /*
 107  * Get the local arbiter ID and the portid within the larb arbiter
 108  * from mtk_m4u_id which is defined by MTK_M4U_ID.
 109  */
 110 #define MTK_M4U_TO_LARB(id)             (((id) >> 5) & 0xf)
 111 #define MTK_M4U_TO_PORT(id)             ((id) & 0x1f)
 112
 113 #define HAS_4GB_MODE                    BIT(0)
 114 /* HW will use the EMI clock if there isn't the "bclk". */
 115 #define HAS_BCLK                        BIT(1)
 116 #define HAS_VLD_PA_RNG                  BIT(2)
 117 #define RESET_AXI                       BIT(3)
 118 #define OUT_ORDER_WR_EN                 BIT(4)
 119 #define HAS_SUB_COMM                    BIT(5)
 120 #define WR_THROT_EN                     BIT(6)
 121 #define HAS_LEGACY_IVRP_PADDR           BIT(7)
 122
 123 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
 124                 ((((pdata)->flags) & (_x)) == (_x))
 125
 126 struct mtk_iommu_domain {
 127         struct io_pgtable_cfg           cfg;
 128         struct io_pgtable_ops           *iop;
 129
 130         struct iommu_domain             domain;
 131 };
 132
 133 static const struct iommu_ops mtk_iommu_ops;
 134
 135 /*
 136  * In M4U 4GB mode, the physical address is remapped as below:
 137  *
 138  * CPU Physical address:
 139  * ====================
 140  *
 141  * 0      1G       2G     3G       4G     5G
 142  * |---A---|---B---|---C---|---D---|---E---|
 143  * +--I/O--+------------Memory-------------+
 144  *
 145  * IOMMU output physical address:
 146  *  =============================
 147  *
 148  *                                 4G      5G     6G      7G      8G
 149  *                                 |---E---|---B---|---C---|---D---|
 150  *                                 +------------Memory-------------+
 151  *
 152  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 153  * bit32 of the CPU physical address always is needed to set, and for Region
 154  * 'E', the CPU physical address keep as is.
 155  * Additionally, The iommu consumers always use the CPU phyiscal address.
 156  */
 157 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 158
 159 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 160
 161 #define for_each_m4u(data)      list_for_each_entry(data, &m4ulist, list)
 162
 163 /*
 164  * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
 165  * for the performance.
 166  *
 167  * Here always return the mtk_iommu_data of the first probed M4U where the
 168  * iommu domain information is recorded.
 169  */
 170 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
 171 {
 172         struct mtk_iommu_data *data;
 173
 174         for_each_m4u(data)
 175                 return data;
 176
 177         return NULL;
 178 }
 179
 180 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 181 {
 182         return container_of(dom, struct mtk_iommu_domain, domain);
 183 }
 184
 185 static void mtk_iommu_tlb_flush_all(void *cookie)
 186 {
 187         struct mtk_iommu_data *data = cookie;
 188
 189         for_each_m4u(data) {
 190                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 191                                data->base + data->plat_data->inv_sel_reg);
 192                 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
 193                 wmb(); /* Make sure the tlb flush all done */
 194         }
 195 }
 196
 197 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 198                                            size_t granule, void *cookie)
 199 {
 200         struct mtk_iommu_data *data = cookie;
 201         unsigned long flags;
 202         int ret;
 203         u32 tmp;
 204
 205         for_each_m4u(data) {
 206                 spin_lock_irqsave(&data->tlb_lock, flags);
 207                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 208                                data->base + data->plat_data->inv_sel_reg);
 209
 210                 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
 211                 writel_relaxed(iova + size - 1,
 212                                data->base + REG_MMU_INVLD_END_A);
 213                 writel_relaxed(F_MMU_INV_RANGE,
 214                                data->base + REG_MMU_INVALIDATE);
 215
 216                 /* tlb sync */
 217                 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
 218                                                 tmp, tmp != 0, 10, 1000);
 219                 if (ret) {
 220                         dev_warn(data->dev,
 221                                  "Partial TLB flush timed out, falling back to full flush\n");
 222                         mtk_iommu_tlb_flush_all(cookie);
 223                 }
 224                 /* Clear the CPE status */
 225                 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
 226                 spin_unlock_irqrestore(&data->tlb_lock, flags);
 227         }
 228 }
 229
 230 static void mtk_iommu_tlb_flush_page_nosync(struct iommu_iotlb_gather *gather,
 231                                             unsigned long iova, size_t granule,
 232                                             void *cookie)
 233 {
 234         struct mtk_iommu_data *data = cookie;
 235         struct iommu_domain *domain = &data->m4u_dom->domain;
 236
 237         iommu_iotlb_gather_add_page(domain, gather, iova, granule);
 238 }
 239
 240 static const struct iommu_flush_ops mtk_iommu_flush_ops = {
 241         .tlb_flush_all = mtk_iommu_tlb_flush_all,
 242         .tlb_flush_walk = mtk_iommu_tlb_flush_range_sync,
 243         .tlb_add_page = mtk_iommu_tlb_flush_page_nosync,
 244 };
 245
 246 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 247 {
 248         struct mtk_iommu_data *data = dev_id;
 249         struct mtk_iommu_domain *dom = data->m4u_dom;
 250         u32 int_state, regval, fault_iova, fault_pa;
 251         unsigned int fault_larb, fault_port, sub_comm = 0;
 252         bool layer, write;
 253
 254         /* Read error info from registers */
 255         int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
 256         if (int_state & F_REG_MMU0_FAULT_MASK) {
 257                 regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
 258                 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
 259                 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
 260         } else {
 261                 regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
 262                 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
 263                 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
 264         }
 265         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 266         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 267         fault_port = F_MMU_INT_ID_PORT_ID(regval);
 268         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
 269                 fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 270                 sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 271         } else {
 272                 fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 273         }
 274         fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 275
 276         if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
 277                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 278                 dev_err_ratelimited(
 279                         data->dev,
 280                         "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
 281                         int_state, fault_iova, fault_pa, fault_larb, fault_port,
 282                         layer, write ? "write" : "read");
 283         }
 284
 285         /* Interrupt clear */
 286         regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
 287         regval |= F_INT_CLR_BIT;
 288         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 289
 290         mtk_iommu_tlb_flush_all(data);
 291
 292         return IRQ_HANDLED;
 293 }
 294
 295 static void mtk_iommu_config(struct mtk_iommu_data *data,
 296                              struct device *dev, bool enable)
 297 {
 298         struct mtk_smi_larb_iommu    *larb_mmu;
 299         unsigned int                 larbid, portid;
 300         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 301         int i;
 302
 303         for (i = 0; i < fwspec->num_ids; ++i) {
 304                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 305                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 306                 larb_mmu = &data->larb_imu[larbid];
 307
 308                 dev_dbg(dev, "%s iommu port: %d\n",
 309                         enable ? "enable" : "disable", portid);
 310
 311                 if (enable)
 312                         larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 313                 else
 314                         larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 315         }
 316 }
 317
 318 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
 319 {
 320         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 321
 322         dom->cfg = (struct io_pgtable_cfg) {
 323                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 324                         IO_PGTABLE_QUIRK_NO_PERMS |
 325                         IO_PGTABLE_QUIRK_TLBI_ON_MAP |
 326                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 327                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 328                 .ias = 32,
 329                 .oas = 34,
 330                 .tlb = &mtk_iommu_flush_ops,
 331                 .iommu_dev = data->dev,
 332         };
 333
 334         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 335         if (!dom->iop) {
 336                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 337                 return -EINVAL;
 338         }
 339
 340         /* Update our support page sizes bitmap */
 341         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 342         return 0;
 343 }
 344
 345 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 346 {
 347         struct mtk_iommu_domain *dom;
 348
 349         if (type != IOMMU_DOMAIN_DMA)
 350                 return NULL;
 351
 352         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 353         if (!dom)
 354                 return NULL;
 355
 356         if (iommu_get_dma_cookie(&dom->domain))
 357                 goto  free_dom;
 358
 359         if (mtk_iommu_domain_finalise(dom))
 360                 goto  put_dma_cookie;
 361
 362         dom->domain.geometry.aperture_start = 0;
 363         dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
 364         dom->domain.geometry.force_aperture = true;
 365
 366         return &dom->domain;
 367
 368 put_dma_cookie:
 369         iommu_put_dma_cookie(&dom->domain);
 370 free_dom:
 371         kfree(dom);
 372         return NULL;
 373 }
 374
 375 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 376 {
 377         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 378
 379         free_io_pgtable_ops(dom->iop);
 380         iommu_put_dma_cookie(domain);
 381         kfree(to_mtk_domain(domain));
 382 }
 383
 384 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 385                                    struct device *dev)
 386 {
 387         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 388         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 389
 390         if (!data)
 391                 return -ENODEV;
 392
 393         /* Update the pgtable base address register of the M4U HW */
 394         if (!data->m4u_dom) {
 395                 data->m4u_dom = dom;
 396                 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
 397                        data->base + REG_MMU_PT_BASE_ADDR);
 398         }
 399
 400         mtk_iommu_config(data, dev, true);
 401         return 0;
 402 }
 403
 404 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 405                                     struct device *dev)
 406 {
 407         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 408
 409         if (!data)
 410                 return;
 411
 412         mtk_iommu_config(data, dev, false);
 413 }
 414
 415 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 416                          phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 417 {
 418         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 419         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 420
 421         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 422         if (data->enable_4GB)
 423                 paddr |= BIT_ULL(32);
 424
 425         /* Synchronize with the tlb_lock */
 426         return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
 427 }
 428
 429 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 430                               unsigned long iova, size_t size,
 431                               struct iommu_iotlb_gather *gather)
 432 {
 433         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 434
 435         return dom->iop->unmap(dom->iop, iova, size, gather);
 436 }
 437
 438 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 439 {
 440         mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data());
 441 }
 442
 443 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 444                                  struct iommu_iotlb_gather *gather)
 445 {
 446         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 447         size_t length = gather->end - gather->start;
 448
 449         if (gather->start == ULONG_MAX)
 450                 return;
 451
 452         mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
 453                                        data);
 454 }
 455
 456 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 457                                           dma_addr_t iova)
 458 {
 459         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 460         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 461         phys_addr_t pa;
 462
 463         pa = dom->iop->iova_to_phys(dom->iop, iova);
 464         if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 465                 pa &= ~BIT_ULL(32);
 466
 467         return pa;
 468 }
 469
 470 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 471 {
 472         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 473         struct mtk_iommu_data *data;
 474
 475         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 476                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 477
 478         data = dev_iommu_priv_get(dev);
 479
 480         return &data->iommu;
 481 }
 482
 483 static void mtk_iommu_release_device(struct device *dev)
 484 {
 485         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 486
 487         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 488                 return;
 489
 490         iommu_fwspec_free(dev);
 491 }
 492
 493 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 494 {
 495         struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
 496
 497         if (!data)
 498                 return ERR_PTR(-ENODEV);
 499
 500         /* All the client devices are in the same m4u iommu-group */
 501         if (!data->m4u_group) {
 502                 data->m4u_group = iommu_group_alloc();
 503                 if (IS_ERR(data->m4u_group))
 504                         dev_err(dev, "Failed to allocate M4U IOMMU group\n");
 505         } else {
 506                 iommu_group_ref_get(data->m4u_group);
 507         }
 508         return data->m4u_group;
 509 }
 510
 511 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 512 {
 513         struct platform_device *m4updev;
 514
 515         if (args->args_count != 1) {
 516                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 517                         args->args_count);
 518                 return -EINVAL;
 519         }
 520
 521         if (!dev_iommu_priv_get(dev)) {
 522                 /* Get the m4u device */
 523                 m4updev = of_find_device_by_node(args->np);
 524                 if (WARN_ON(!m4updev))
 525                         return -EINVAL;
 526
 527                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 528         }
 529
 530         return iommu_fwspec_add_ids(dev, args->args, 1);
 531 }
 532
 533 static const struct iommu_ops mtk_iommu_ops = {
 534         .domain_alloc   = mtk_iommu_domain_alloc,
 535         .domain_free    = mtk_iommu_domain_free,
 536         .attach_dev     = mtk_iommu_attach_device,
 537         .detach_dev     = mtk_iommu_detach_device,
 538         .map            = mtk_iommu_map,
 539         .unmap          = mtk_iommu_unmap,
 540         .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
 541         .iotlb_sync     = mtk_iommu_iotlb_sync,
 542         .iova_to_phys   = mtk_iommu_iova_to_phys,
 543         .probe_device   = mtk_iommu_probe_device,
 544         .release_device = mtk_iommu_release_device,
 545         .device_group   = mtk_iommu_device_group,
 546         .of_xlate       = mtk_iommu_of_xlate,
 547         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 548 };
 549
 550 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 551 {
 552         u32 regval;
 553         int ret;
 554
 555         ret = clk_prepare_enable(data->bclk);
 556         if (ret) {
 557                 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
 558                 return ret;
 559         }
 560
 561         if (data->plat_data->m4u_plat == M4U_MT8173) {
 562                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
 563                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
 564         } else {
 565                 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
 566                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
 567         }
 568         writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
 569
 570         regval = F_L2_MULIT_HIT_EN |
 571                 F_TABLE_WALK_FAULT_INT_EN |
 572                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
 573                 F_MISS_FIFO_OVERFLOW_INT_EN |
 574                 F_PREFETCH_FIFO_ERR_INT_EN |
 575                 F_MISS_FIFO_ERR_INT_EN;
 576         writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
 577
 578         regval = F_INT_TRANSLATION_FAULT |
 579                 F_INT_MAIN_MULTI_HIT_FAULT |
 580                 F_INT_INVALID_PA_FAULT |
 581                 F_INT_ENTRY_REPLACEMENT_FAULT |
 582                 F_INT_TLB_MISS_FAULT |
 583                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
 584                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
 585         writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
 586
 587         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
 588                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
 589         else
 590                 regval = lower_32_bits(data->protect_base) |
 591                          upper_32_bits(data->protect_base);
 592         writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
 593
 594         if (data->enable_4GB &&
 595             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
 596                 /*
 597                  * If 4GB mode is enabled, the validate PA range is from
 598                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
 599                  */
 600                 regval = F_MMU_VLD_PA_RNG(7, 4);
 601                 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
 602         }
 603         writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 604         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
 605                 /* write command throttling mode */
 606                 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
 607                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
 608                 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
 609         }
 610
 611         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
 612                 /* The register is called STANDARD_AXI_MODE in this case */
 613                 regval = 0;
 614         } else {
 615                 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
 616                 regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
 617                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
 618                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
 619         }
 620         writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
 621
 622         if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
 623                              dev_name(data->dev), (void *)data)) {
 624                 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
 625                 clk_disable_unprepare(data->bclk);
 626                 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
 627                 return -ENODEV;
 628         }
 629
 630         return 0;
 631 }
 632
 633 static const struct component_master_ops mtk_iommu_com_ops = {
 634         .bind           = mtk_iommu_bind,
 635         .unbind         = mtk_iommu_unbind,
 636 };
 637
 638 static int mtk_iommu_probe(struct platform_device *pdev)
 639 {
 640         struct mtk_iommu_data   *data;
 641         struct device           *dev = &pdev->dev;
 642         struct resource         *res;
 643         resource_size_t         ioaddr;
 644         struct component_match  *match = NULL;
 645         struct regmap           *infracfg;
 646         void                    *protect;
 647         int                     i, larb_nr, ret;
 648         u32                     val;
 649         char                    *p;
 650
 651         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 652         if (!data)
 653                 return -ENOMEM;
 654         data->dev = dev;
 655         data->plat_data = of_device_get_match_data(dev);
 656
 657         /* Protect memory. HW will access here while translation fault.*/
 658         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
 659         if (!protect)
 660                 return -ENOMEM;
 661         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
 662
 663         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
 664                 switch (data->plat_data->m4u_plat) {
 665                 case M4U_MT2712:
 666                         p = "mediatek,mt2712-infracfg";
 667                         break;
 668                 case M4U_MT8173:
 669                         p = "mediatek,mt8173-infracfg";
 670                         break;
 671                 default:
 672                         p = NULL;
 673                 }
 674
 675                 infracfg = syscon_regmap_lookup_by_compatible(p);
 676
 677                 if (IS_ERR(infracfg))
 678                         return PTR_ERR(infracfg);
 679
 680                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
 681                 if (ret)
 682                         return ret;
 683                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
 684         }
 685
 686         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 687         data->base = devm_ioremap_resource(dev, res);
 688         if (IS_ERR(data->base))
 689                 return PTR_ERR(data->base);
 690         ioaddr = res->start;
 691
 692         data->irq = platform_get_irq(pdev, 0);
 693         if (data->irq < 0)
 694                 return data->irq;
 695
 696         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
 697                 data->bclk = devm_clk_get(dev, "bclk");
 698                 if (IS_ERR(data->bclk))
 699                         return PTR_ERR(data->bclk);
 700         }
 701
 702         larb_nr = of_count_phandle_with_args(dev->of_node,
 703                                              "mediatek,larbs", NULL);
 704         if (larb_nr < 0)
 705                 return larb_nr;
 706
 707         for (i = 0; i < larb_nr; i++) {
 708                 struct device_node *larbnode;
 709                 struct platform_device *plarbdev;
 710                 u32 id;
 711
 712                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
 713                 if (!larbnode)
 714                         return -EINVAL;
 715
 716                 if (!of_device_is_available(larbnode)) {
 717                         of_node_put(larbnode);
 718                         continue;
 719                 }
 720
 721                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
 722                 if (ret)/* The id is consecutive if there is no this property */
 723                         id = i;
 724
 725                 plarbdev = of_find_device_by_node(larbnode);
 726                 if (!plarbdev) {
 727                         of_node_put(larbnode);
 728                         return -EPROBE_DEFER;
 729                 }
 730                 data->larb_imu[id].dev = &plarbdev->dev;
 731
 732                 component_match_add_release(dev, &match, release_of,
 733                                             compare_of, larbnode);
 734         }
 735
 736         platform_set_drvdata(pdev, data);
 737
 738         ret = mtk_iommu_hw_init(data);
 739         if (ret)
 740                 return ret;
 741
 742         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
 743                                      "mtk-iommu.%pa", &ioaddr);
 744         if (ret)
 745                 return ret;
 746
 747         iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
 748         iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode);
 749
 750         ret = iommu_device_register(&data->iommu);
 751         if (ret)
 752                 return ret;
 753
 754         spin_lock_init(&data->tlb_lock);
 755         list_add_tail(&data->list, &m4ulist);
 756
 757         if (!iommu_present(&platform_bus_type))
 758                 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
 759
 760         return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
 761 }
 762
 763 static int mtk_iommu_remove(struct platform_device *pdev)
 764 {
 765         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
 766
 767         iommu_device_sysfs_remove(&data->iommu);
 768         iommu_device_unregister(&data->iommu);
 769
 770         if (iommu_present(&platform_bus_type))
 771                 bus_set_iommu(&platform_bus_type, NULL);
 772
 773         clk_disable_unprepare(data->bclk);
 774         devm_free_irq(&pdev->dev, data->irq, data);
 775         component_master_del(&pdev->dev, &mtk_iommu_com_ops);
 776         return 0;
 777 }
 778
 779 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
 780 {
 781         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 782         struct mtk_iommu_suspend_reg *reg = &data->reg;
 783         void __iomem *base = data->base;
 784
 785         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
 786         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
 787         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
 788         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
 789         reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 790         reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
 791         reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
 792         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
 793         clk_disable_unprepare(data->bclk);
 794         return 0;
 795 }
 796
 797 static int __maybe_unused mtk_iommu_resume(struct device *dev)
 798 {
 799         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 800         struct mtk_iommu_suspend_reg *reg = &data->reg;
 801         struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
 802         void __iomem *base = data->base;
 803         int ret;
 804
 805         ret = clk_prepare_enable(data->bclk);
 806         if (ret) {
 807                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
 808                 return ret;
 809         }
 810         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
 811         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
 812         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
 813         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
 814         writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
 815         writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
 816         writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
 817         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
 818         if (m4u_dom)
 819                 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
 820                        base + REG_MMU_PT_BASE_ADDR);
 821         return 0;
 822 }
 823
 824 static const struct dev_pm_ops mtk_iommu_pm_ops = {
 825         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
 826 };
 827
 828 static const struct mtk_iommu_plat_data mt2712_data = {
 829         .m4u_plat     = M4U_MT2712,
 830         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
 831         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 832         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
 833 };
 834
 835 static const struct mtk_iommu_plat_data mt6779_data = {
 836         .m4u_plat      = M4U_MT6779,
 837         .flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
 838         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
 839         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
 840 };
 841
 842 static const struct mtk_iommu_plat_data mt8167_data = {
 843         .m4u_plat     = M4U_MT8167,
 844         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
 845         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 846         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
 847 };
 848
 849 static const struct mtk_iommu_plat_data mt8173_data = {
 850         .m4u_plat     = M4U_MT8173,
 851         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
 852                         HAS_LEGACY_IVRP_PADDR,
 853         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 854         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
 855 };
 856
 857 static const struct mtk_iommu_plat_data mt8183_data = {
 858         .m4u_plat     = M4U_MT8183,
 859         .flags        = RESET_AXI,
 860         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 861         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
 862 };
 863
 864 static const struct of_device_id mtk_iommu_of_ids[] = {
 865         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
 866         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
 867         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
 868         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
 869         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
 870         {}
 871 };
 872
 873 static struct platform_driver mtk_iommu_driver = {
 874         .probe  = mtk_iommu_probe,
 875         .remove = mtk_iommu_remove,
 876         .driver = {
 877                 .name = "mtk-iommu",
 878                 .of_match_table = mtk_iommu_of_ids,
 879                 .pm = &mtk_iommu_pm_ops,
 880         }
 881 };
 882
 883 static int __init mtk_iommu_init(void)
 884 {
 885         int ret;
 886
 887         ret = platform_driver_register(&mtk_iommu_driver);
 888         if (ret != 0)
 889                 pr_err("Failed to register MTK IOMMU driver\n");
 890
 891         return ret;
 892 }
 893
 894 subsys_initcall(mtk_iommu_init)