drivers/interconnect/qcom/sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  *
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/interconnect.h>
   9 #include <linux/interconnect-provider.h>
  10 #include <linux/module.h>
  11 #include <linux/of_platform.h>
  12 #include <dt-bindings/interconnect/qcom,sc7180.h>
  13
  14 #include "bcm-voter.h"
  15 #include "icc-rpmh.h"
  16 #include "sc7180.h"
  17
  18 DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
  19 DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
  20 DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
  21 DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  22 DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  23 DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
  24 DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
  25 DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
  26 DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
  27 DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  28 DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  29 DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  30 DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
  31 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  32 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  33 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
  34 DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
  35 DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
  36 DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
  37                 SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
  38 DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
  39 SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
  40 DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
  41 DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  42 DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  43 DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
  44 DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  45 DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
  46 DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  47 DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
  48 DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
  49 DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
  50 DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
  51 DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
  52 DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
  53 DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  54 DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  55 DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  56 DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
  57 DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  58 DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  59 DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
  60 DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
  61 DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
  62 DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
  63 DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
  64 DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
  65 DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
  66 DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
  67 DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
  68 DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
  69 DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
  70 DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
  71 DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
  72 DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
  73 DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
  74 DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
  75 DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
  76 DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
  77 DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
  78 DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
  79 DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
  80 DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
  81 DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
  82 DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
  83 DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
  84 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
  85 DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
  86 DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
  87 DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
  88 DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
  89 DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
  90 DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
  91 DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
  92 DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
  93 DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
  94 DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
  95 DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
  96 DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
  97 DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
  98 DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
  99 DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
 100 DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
 101 DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
 102 DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
 103 DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
 104 DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
 105 DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
 106 DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
 107 DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
 108 DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
 109 DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
 110 DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
 111 DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
 112 DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
 113 DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
 114 DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
 115 DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
 116 DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
 117 DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
 118 DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
 119 DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
 120 DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
 121 DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
 122 DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
 123 DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
 124 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
 125 DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
 126 DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
 127 DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
 128 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
 129 DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
 130 DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
 131 DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
 132 DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
 133 DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
 134 DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
 135 DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
 136 DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
 137 DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
 138 DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
 139 DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
 140 DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
 141 DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
 142 DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
 143 DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
 144 DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
 145 DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
 146 DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
 147 DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
 148 DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
 149 DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
 150 DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
 151 DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
 152 DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
 153 DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
 154 DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
 155 DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
 156 DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
 157
 158 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
 159 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
 160 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 161 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
 162 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
 163 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
 164 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
 165 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
 166 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
 167 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
 168 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
 169 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
 170 DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
 171 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
 172 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
 173 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
 174 DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
 175 DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
 176 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
 177 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
 178 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
 179 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
 180 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
 181 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
 182 DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
 183
 184 static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
 185         &bcm_cn1,
 186 };
 187
 188 static struct qcom_icc_node *aggre1_noc_nodes[] = {
 189         [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
 190         [MASTER_QSPI] = &qhm_qspi,
 191         [MASTER_QUP_0] = &qhm_qup_0,
 192         [MASTER_SDCC_2] = &xm_sdc2,
 193         [MASTER_EMMC] = &xm_emmc,
 194         [MASTER_UFS_MEM] = &xm_ufs_mem,
 195         [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
 196         [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
 197 };
 198
 199 static struct qcom_icc_desc sc7180_aggre1_noc = {
 200         .nodes = aggre1_noc_nodes,
 201         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 202         .bcms = aggre1_noc_bcms,
 203         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
 204 };
 205
 206 static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
 207         &bcm_ce0,
 208 };
 209
 210 static struct qcom_icc_node *aggre2_noc_nodes[] = {
 211         [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
 212         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
 213         [MASTER_QUP_1] = &qhm_qup_1,
 214         [MASTER_USB3] = &qhm_usb3,
 215         [MASTER_CRYPTO] = &qxm_crypto,
 216         [MASTER_IPA] = &qxm_ipa,
 217         [MASTER_QDSS_ETR] = &xm_qdss_etr,
 218         [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
 219         [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
 220 };
 221
 222 static struct qcom_icc_desc sc7180_aggre2_noc = {
 223         .nodes = aggre2_noc_nodes,
 224         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 225         .bcms = aggre2_noc_bcms,
 226         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
 227 };
 228
 229 static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
 230         &bcm_mm1,
 231 };
 232
 233 static struct qcom_icc_node *camnoc_virt_nodes[] = {
 234         [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
 235         [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
 236         [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
 237         [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
 238 };
 239
 240 static struct qcom_icc_desc sc7180_camnoc_virt = {
 241         .nodes = camnoc_virt_nodes,
 242         .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
 243         .bcms = camnoc_virt_bcms,
 244         .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
 245 };
 246
 247 static struct qcom_icc_bcm *compute_noc_bcms[] = {
 248         &bcm_co0,
 249         &bcm_co2,
 250         &bcm_co3,
 251 };
 252
 253 static struct qcom_icc_node *compute_noc_nodes[] = {
 254         [MASTER_NPU] = &qnm_npu,
 255         [MASTER_NPU_PROC] = &qxm_npu_dsp,
 256         [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
 257 };
 258
 259 static struct qcom_icc_desc sc7180_compute_noc = {
 260         .nodes = compute_noc_nodes,
 261         .num_nodes = ARRAY_SIZE(compute_noc_nodes),
 262         .bcms = compute_noc_bcms,
 263         .num_bcms = ARRAY_SIZE(compute_noc_bcms),
 264 };
 265
 266 static struct qcom_icc_bcm *config_noc_bcms[] = {
 267         &bcm_cn0,
 268         &bcm_cn1,
 269 };
 270
 271 static struct qcom_icc_node *config_noc_nodes[] = {
 272         [MASTER_SNOC_CNOC] = &qnm_snoc,
 273         [MASTER_QDSS_DAP] = &xm_qdss_dap,
 274         [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
 275         [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
 276         [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
 277         [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
 278         [SLAVE_AOP] = &qhs_aop,
 279         [SLAVE_AOSS] = &qhs_aoss,
 280         [SLAVE_BOOT_ROM] = &qhs_boot_rom,
 281         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
 282         [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
 283         [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
 284         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
 285         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
 286         [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
 287         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
 288         [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
 289         [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
 290         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
 291         [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
 292         [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
 293         [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
 294         [SLAVE_GLM] = &qhs_glm,
 295         [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
 296         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 297         [SLAVE_IPA_CFG] = &qhs_ipa,
 298         [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
 299         [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
 300         [SLAVE_NPU_CFG] = &qhs_npu_cfg,
 301         [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
 302         [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
 303         [SLAVE_PDM] = &qhs_pdm,
 304         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
 305         [SLAVE_PRNG] = &qhs_prng,
 306         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 307         [SLAVE_QM_CFG] = &qhs_qm_cfg,
 308         [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
 309         [SLAVE_QSPI_0] = &qhs_qspi,
 310         [SLAVE_QUP_0] = &qhs_qup0,
 311         [SLAVE_QUP_1] = &qhs_qup1,
 312         [SLAVE_SDCC_2] = &qhs_sdc2,
 313         [SLAVE_SECURITY] = &qhs_security,
 314         [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
 315         [SLAVE_TCSR] = &qhs_tcsr,
 316         [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
 317         [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
 318         [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
 319         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
 320         [SLAVE_USB3] = &qhs_usb3,
 321         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
 322         [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
 323         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
 324         [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
 325 };
 326
 327 static struct qcom_icc_desc sc7180_config_noc = {
 328         .nodes = config_noc_nodes,
 329         .num_nodes = ARRAY_SIZE(config_noc_nodes),
 330         .bcms = config_noc_bcms,
 331         .num_bcms = ARRAY_SIZE(config_noc_bcms),
 332 };
 333
 334 static struct qcom_icc_node *dc_noc_nodes[] = {
 335         [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
 336         [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
 337         [SLAVE_LLCC_CFG] = &qhs_llcc,
 338 };
 339
 340 static struct qcom_icc_desc sc7180_dc_noc = {
 341         .nodes = dc_noc_nodes,
 342         .num_nodes = ARRAY_SIZE(dc_noc_nodes),
 343 };
 344
 345 static struct qcom_icc_bcm *gem_noc_bcms[] = {
 346         &bcm_sh0,
 347         &bcm_sh2,
 348         &bcm_sh3,
 349         &bcm_sh4,
 350 };
 351
 352 static struct qcom_icc_node *gem_noc_nodes[] = {
 353         [MASTER_APPSS_PROC] = &acm_apps0,
 354         [MASTER_SYS_TCU] = &acm_sys_tcu,
 355         [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
 356         [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
 357         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
 358         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
 359         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
 360         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 361         [MASTER_GFX3D] = &qxm_gpu,
 362         [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
 363         [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
 364         [SLAVE_LLCC] = &qns_llcc,
 365         [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
 366 };
 367
 368 static struct qcom_icc_desc sc7180_gem_noc = {
 369         .nodes = gem_noc_nodes,
 370         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
 371         .bcms = gem_noc_bcms,
 372         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
 373 };
 374
 375 static struct qcom_icc_bcm *ipa_virt_bcms[] = {
 376         &bcm_ip0,
 377 };
 378
 379 static struct qcom_icc_node *ipa_virt_nodes[] = {
 380         [MASTER_IPA_CORE] = &ipa_core_master,
 381         [SLAVE_IPA_CORE] = &ipa_core_slave,
 382 };
 383
 384 static struct qcom_icc_desc sc7180_ipa_virt = {
 385         .nodes = ipa_virt_nodes,
 386         .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
 387         .bcms = ipa_virt_bcms,
 388         .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
 389 };
 390
 391 static struct qcom_icc_bcm *mc_virt_bcms[] = {
 392         &bcm_acv,
 393         &bcm_mc0,
 394 };
 395
 396 static struct qcom_icc_node *mc_virt_nodes[] = {
 397         [MASTER_LLCC] = &llcc_mc,
 398         [SLAVE_EBI1] = &ebi,
 399 };
 400
 401 static struct qcom_icc_desc sc7180_mc_virt = {
 402         .nodes = mc_virt_nodes,
 403         .num_nodes = ARRAY_SIZE(mc_virt_nodes),
 404         .bcms = mc_virt_bcms,
 405         .num_bcms = ARRAY_SIZE(mc_virt_bcms),
 406 };
 407
 408 static struct qcom_icc_bcm *mmss_noc_bcms[] = {
 409         &bcm_mm0,
 410         &bcm_mm1,
 411         &bcm_mm2,
 412 };
 413
 414 static struct qcom_icc_node *mmss_noc_nodes[] = {
 415         [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
 416         [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
 417         [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
 418         [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
 419         [MASTER_MDP0] = &qxm_mdp0,
 420         [MASTER_ROTATOR] = &qxm_rot,
 421         [MASTER_VIDEO_P0] = &qxm_venus0,
 422         [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
 423         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
 424         [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
 425         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 426 };
 427
 428 static struct qcom_icc_desc sc7180_mmss_noc = {
 429         .nodes = mmss_noc_nodes,
 430         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 431         .bcms = mmss_noc_bcms,
 432         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
 433 };
 434
 435 static struct qcom_icc_node *npu_noc_nodes[] = {
 436         [MASTER_NPU_SYS] = &amm_npu_sys,
 437         [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
 438         [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
 439         [SLAVE_NPU_CP] = &qhs_cp,
 440         [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
 441         [SLAVE_NPU_DPM] = &qhs_dpm,
 442         [SLAVE_ISENSE_CFG] = &qhs_isense,
 443         [SLAVE_NPU_LLM_CFG] = &qhs_llm,
 444         [SLAVE_NPU_TCM] = &qhs_tcm,
 445         [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
 446         [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
 447 };
 448
 449 static struct qcom_icc_desc sc7180_npu_noc = {
 450         .nodes = npu_noc_nodes,
 451         .num_nodes = ARRAY_SIZE(npu_noc_nodes),
 452 };
 453
 454 static struct qcom_icc_bcm *qup_virt_bcms[] = {
 455         &bcm_qup0,
 456 };
 457
 458 static struct qcom_icc_node *qup_virt_nodes[] = {
 459         [MASTER_QUP_CORE_0] = &qup_core_master_1,
 460         [MASTER_QUP_CORE_1] = &qup_core_master_2,
 461         [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
 462         [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
 463 };
 464
 465 static struct qcom_icc_desc sc7180_qup_virt = {
 466         .nodes = qup_virt_nodes,
 467         .num_nodes = ARRAY_SIZE(qup_virt_nodes),
 468         .bcms = qup_virt_bcms,
 469         .num_bcms = ARRAY_SIZE(qup_virt_bcms),
 470 };
 471
 472 static struct qcom_icc_bcm *system_noc_bcms[] = {
 473         &bcm_sn0,
 474         &bcm_sn1,
 475         &bcm_sn2,
 476         &bcm_sn3,
 477         &bcm_sn4,
 478         &bcm_sn7,
 479         &bcm_sn9,
 480         &bcm_sn12,
 481 };
 482
 483 static struct qcom_icc_node *system_noc_nodes[] = {
 484         [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
 485         [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
 486         [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
 487         [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
 488         [MASTER_PIMEM] = &qxm_pimem,
 489         [SLAVE_APPSS] = &qhs_apss,
 490         [SLAVE_SNOC_CNOC] = &qns_cnoc,
 491         [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
 492         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 493         [SLAVE_IMEM] = &qxs_imem,
 494         [SLAVE_PIMEM] = &qxs_pimem,
 495         [SLAVE_SERVICE_SNOC] = &srvc_snoc,
 496         [SLAVE_QDSS_STM] = &xs_qdss_stm,
 497         [SLAVE_TCU] = &xs_sys_tcu_cfg,
 498 };
 499
 500 static struct qcom_icc_desc sc7180_system_noc = {
 501         .nodes = system_noc_nodes,
 502         .num_nodes = ARRAY_SIZE(system_noc_nodes),
 503         .bcms = system_noc_bcms,
 504         .num_bcms = ARRAY_SIZE(system_noc_bcms),
 505 };
 506
 507 static int qnoc_probe(struct platform_device *pdev)
 508 {
 509         const struct qcom_icc_desc *desc;
 510         struct icc_onecell_data *data;
 511         struct icc_provider *provider;
 512         struct qcom_icc_node **qnodes;
 513         struct qcom_icc_provider *qp;
 514         struct icc_node *node;
 515         size_t num_nodes, i;
 516         int ret;
 517
 518         desc = device_get_match_data(&pdev->dev);
 519         if (!desc)
 520                 return -EINVAL;
 521
 522         qnodes = desc->nodes;
 523         num_nodes = desc->num_nodes;
 524
 525         qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
 526         if (!qp)
 527                 return -ENOMEM;
 528
 529         data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
 530         if (!data)
 531                 return -ENOMEM;
 532
 533         provider = &qp->provider;
 534         provider->dev = &pdev->dev;
 535         provider->set = qcom_icc_set;
 536         provider->pre_aggregate = qcom_icc_pre_aggregate;
 537         provider->aggregate = qcom_icc_aggregate;
 538         provider->xlate_extended = qcom_icc_xlate_extended;
 539         INIT_LIST_HEAD(&provider->nodes);
 540         provider->data = data;
 541
 542         qp->dev = &pdev->dev;
 543         qp->bcms = desc->bcms;
 544         qp->num_bcms = desc->num_bcms;
 545
 546         qp->voter = of_bcm_voter_get(qp->dev, NULL);
 547         if (IS_ERR(qp->voter))
 548                 return PTR_ERR(qp->voter);
 549
 550         ret = icc_provider_add(provider);
 551         if (ret) {
 552                 dev_err(&pdev->dev, "error adding interconnect provider\n");
 553                 return ret;
 554         }
 555
 556         for (i = 0; i < num_nodes; i++) {
 557                 size_t j;
 558
 559                 if (!qnodes[i])
 560                         continue;
 561
 562                 node = icc_node_create(qnodes[i]->id);
 563                 if (IS_ERR(node)) {
 564                         ret = PTR_ERR(node);
 565                         goto err;
 566                 }
 567
 568                 node->name = qnodes[i]->name;
 569                 node->data = qnodes[i];
 570                 icc_node_add(node, provider);
 571
 572                 for (j = 0; j < qnodes[i]->num_links; j++)
 573                         icc_link_create(node, qnodes[i]->links[j]);
 574
 575                 data->nodes[i] = node;
 576         }
 577         data->num_nodes = num_nodes;
 578
 579         for (i = 0; i < qp->num_bcms; i++)
 580                 qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
 581
 582         platform_set_drvdata(pdev, qp);
 583
 584         return 0;
 585 err:
 586         icc_nodes_remove(provider);
 587         icc_provider_del(provider);
 588         return ret;
 589 }
 590
 591 static int qnoc_remove(struct platform_device *pdev)
 592 {
 593         struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
 594
 595         icc_nodes_remove(&qp->provider);
 596         return icc_provider_del(&qp->provider);
 597 }
 598
 599 static const struct of_device_id qnoc_of_match[] = {
 600         { .compatible = "qcom,sc7180-aggre1-noc",
 601           .data = &sc7180_aggre1_noc},
 602         { .compatible = "qcom,sc7180-aggre2-noc",
 603           .data = &sc7180_aggre2_noc},
 604         { .compatible = "qcom,sc7180-camnoc-virt",
 605           .data = &sc7180_camnoc_virt},
 606         { .compatible = "qcom,sc7180-compute-noc",
 607           .data = &sc7180_compute_noc},
 608         { .compatible = "qcom,sc7180-config-noc",
 609           .data = &sc7180_config_noc},
 610         { .compatible = "qcom,sc7180-dc-noc",
 611           .data = &sc7180_dc_noc},
 612         { .compatible = "qcom,sc7180-gem-noc",
 613           .data = &sc7180_gem_noc},
 614         { .compatible = "qcom,sc7180-ipa-virt",
 615           .data = &sc7180_ipa_virt},
 616         { .compatible = "qcom,sc7180-mc-virt",
 617           .data = &sc7180_mc_virt},
 618         { .compatible = "qcom,sc7180-mmss-noc",
 619           .data = &sc7180_mmss_noc},
 620         { .compatible = "qcom,sc7180-npu-noc",
 621           .data = &sc7180_npu_noc},
 622         { .compatible = "qcom,sc7180-qup-virt",
 623           .data = &sc7180_qup_virt},
 624         { .compatible = "qcom,sc7180-system-noc",
 625           .data = &sc7180_system_noc},
 626         { }
 627 };
 628 MODULE_DEVICE_TABLE(of, qnoc_of_match);
 629
 630 static struct platform_driver qnoc_driver = {
 631         .probe = qnoc_probe,
 632         .remove = qnoc_remove,
 633         .driver = {
 634                 .name = "qnoc-sc7180",
 635                 .of_match_table = qnoc_of_match,
 636                 .sync_state = icc_sync_state,
 637         },
 638 };
 639 module_platform_driver(qnoc_driver);
 640
 641 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
 642 MODULE_LICENSE("GPL v2");