drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 113  * to kernel buffer
 114  *
 115  * @umem: User space memory where the WQ is
 116  * @buffer: buffer to copy to
 117  * @buflen: buffer length
 118  * @wqe_index: index of WQE to copy from
 119  * @wq_offset: offset to start of WQ
 120  * @wq_wqe_cnt: number of WQEs in WQ
 121  * @wq_wqe_shift: log2 of WQE size
 122  * @bcnt: number of bytes to copy
 123  * @bytes_copied: number of bytes to copy (return value)
 124  *
 125  * Copies from start of WQE bcnt or less bytes.
 126  * Does not gurantee to copy the entire WQE.
 127  *
 128  * Return: zero on success, or an error code.
 129  */
 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem,
 131                                         void *buffer,
 132                                         u32 buflen,
 133                                         int wqe_index,
 134                                         int wq_offset,
 135                                         int wq_wqe_cnt,
 136                                         int wq_wqe_shift,
 137                                         int bcnt,
 138                                         size_t *bytes_copied)
 139 {
 140         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 141         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 142         size_t copy_length;
 143         int ret;
 144
 145         /* don't copy more than requested, more than buffer length or
 146          * beyond WQ end
 147          */
 148         copy_length = min_t(u32, buflen, wq_end - offset);
 149         copy_length = min_t(u32, copy_length, bcnt);
 150
 151         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 152         if (ret)
 153                 return ret;
 154
 155         if (!ret && bytes_copied)
 156                 *bytes_copied = copy_length;
 157
 158         return 0;
 159 }
 160
 161 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp,
 162                              int wqe_index,
 163                              void *buffer,
 164                              int buflen,
 165                              size_t *bc)
 166 {
 167         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 168         struct ib_umem *umem = base->ubuffer.umem;
 169         struct mlx5_ib_wq *wq = &qp->sq;
 170         struct mlx5_wqe_ctrl_seg *ctrl;
 171         size_t bytes_copied;
 172         size_t bytes_copied2;
 173         size_t wqe_length;
 174         int ret;
 175         int ds;
 176
 177         if (buflen < sizeof(*ctrl))
 178                 return -EINVAL;
 179
 180         /* at first read as much as possible */
 181         ret = mlx5_ib_read_user_wqe_common(umem,
 182                                            buffer,
 183                                            buflen,
 184                                            wqe_index,
 185                                            wq->offset,
 186                                            wq->wqe_cnt,
 187                                            wq->wqe_shift,
 188                                            buflen,
 189                                            &bytes_copied);
 190         if (ret)
 191                 return ret;
 192
 193         /* we need at least control segment size to proceed */
 194         if (bytes_copied < sizeof(*ctrl))
 195                 return -EINVAL;
 196
 197         ctrl = buffer;
 198         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 199         wqe_length = ds * MLX5_WQE_DS_UNITS;
 200
 201         /* if we copied enough then we are done */
 202         if (bytes_copied >= wqe_length) {
 203                 *bc = bytes_copied;
 204                 return 0;
 205         }
 206
 207         /* otherwise this a wrapped around wqe
 208          * so read the remaining bytes starting
 209          * from  wqe_index 0
 210          */
 211         ret = mlx5_ib_read_user_wqe_common(umem,
 212                                            buffer + bytes_copied,
 213                                            buflen - bytes_copied,
 214                                            0,
 215                                            wq->offset,
 216                                            wq->wqe_cnt,
 217                                            wq->wqe_shift,
 218                                            wqe_length - bytes_copied,
 219                                            &bytes_copied2);
 220
 221         if (ret)
 222                 return ret;
 223         *bc = bytes_copied + bytes_copied2;
 224         return 0;
 225 }
 226
 227 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp,
 228                              int wqe_index,
 229                              void *buffer,
 230                              int buflen,
 231                              size_t *bc)
 232 {
 233         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 234         struct ib_umem *umem = base->ubuffer.umem;
 235         struct mlx5_ib_wq *wq = &qp->rq;
 236         size_t bytes_copied;
 237         int ret;
 238
 239         ret = mlx5_ib_read_user_wqe_common(umem,
 240                                            buffer,
 241                                            buflen,
 242                                            wqe_index,
 243                                            wq->offset,
 244                                            wq->wqe_cnt,
 245                                            wq->wqe_shift,
 246                                            buflen,
 247                                            &bytes_copied);
 248
 249         if (ret)
 250                 return ret;
 251         *bc = bytes_copied;
 252         return 0;
 253 }
 254
 255 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq,
 256                               int wqe_index,
 257                               void *buffer,
 258                               int buflen,
 259                               size_t *bc)
 260 {
 261         struct ib_umem *umem = srq->umem;
 262         size_t bytes_copied;
 263         int ret;
 264
 265         ret = mlx5_ib_read_user_wqe_common(umem,
 266                                            buffer,
 267                                            buflen,
 268                                            wqe_index,
 269                                            0,
 270                                            srq->msrq.max,
 271                                            srq->msrq.wqe_shift,
 272                                            buflen,
 273                                            &bytes_copied);
 274
 275         if (ret)
 276                 return ret;
 277         *bc = bytes_copied;
 278         return 0;
 279 }
 280
 281 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 282 {
 283         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 284         struct ib_event event;
 285
 286         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 287                 /* This event is only valid for trans_qps */
 288                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 289         }
 290
 291         if (ibqp->event_handler) {
 292                 event.device     = ibqp->device;
 293                 event.element.qp = ibqp;
 294                 switch (type) {
 295                 case MLX5_EVENT_TYPE_PATH_MIG:
 296                         event.event = IB_EVENT_PATH_MIG;
 297                         break;
 298                 case MLX5_EVENT_TYPE_COMM_EST:
 299                         event.event = IB_EVENT_COMM_EST;
 300                         break;
 301                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 302                         event.event = IB_EVENT_SQ_DRAINED;
 303                         break;
 304                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 305                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 306                         break;
 307                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 308                         event.event = IB_EVENT_QP_FATAL;
 309                         break;
 310                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 311                         event.event = IB_EVENT_PATH_MIG_ERR;
 312                         break;
 313                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 314                         event.event = IB_EVENT_QP_REQ_ERR;
 315                         break;
 316                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 317                         event.event = IB_EVENT_QP_ACCESS_ERR;
 318                         break;
 319                 default:
 320                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 321                         return;
 322                 }
 323
 324                 ibqp->event_handler(&event, ibqp->qp_context);
 325         }
 326 }
 327
 328 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 329                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 330 {
 331         int wqe_size;
 332         int wq_size;
 333
 334         /* Sanity check RQ size before proceeding */
 335         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 336                 return -EINVAL;
 337
 338         if (!has_rq) {
 339                 qp->rq.max_gs = 0;
 340                 qp->rq.wqe_cnt = 0;
 341                 qp->rq.wqe_shift = 0;
 342                 cap->max_recv_wr = 0;
 343                 cap->max_recv_sge = 0;
 344         } else {
 345                 if (ucmd) {
 346                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 347                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 348                                 return -EINVAL;
 349                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 350                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 351                                 return -EINVAL;
 352                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 353                         qp->rq.max_post = qp->rq.wqe_cnt;
 354                 } else {
 355                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 356                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 357                         wqe_size = roundup_pow_of_two(wqe_size);
 358                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 359                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 360                         qp->rq.wqe_cnt = wq_size / wqe_size;
 361                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 362                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 363                                             wqe_size,
 364                                             MLX5_CAP_GEN(dev->mdev,
 365                                                          max_wqe_sz_rq));
 366                                 return -EINVAL;
 367                         }
 368                         qp->rq.wqe_shift = ilog2(wqe_size);
 369                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 370                         qp->rq.max_post = qp->rq.wqe_cnt;
 371                 }
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int sq_overhead(struct ib_qp_init_attr *attr)
 378 {
 379         int size = 0;
 380
 381         switch (attr->qp_type) {
 382         case IB_QPT_XRC_INI:
 383                 size += sizeof(struct mlx5_wqe_xrc_seg);
 384                 /* fall through */
 385         case IB_QPT_RC:
 386                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 387                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 388                             sizeof(struct mlx5_wqe_raddr_seg),
 389                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 390                             sizeof(struct mlx5_mkey_seg) +
 391                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 392                             MLX5_IB_UMR_OCTOWORD);
 393                 break;
 394
 395         case IB_QPT_XRC_TGT:
 396                 return 0;
 397
 398         case IB_QPT_UC:
 399                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 400                         max(sizeof(struct mlx5_wqe_raddr_seg),
 401                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 402                             sizeof(struct mlx5_mkey_seg));
 403                 break;
 404
 405         case IB_QPT_UD:
 406                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 407                         size += sizeof(struct mlx5_wqe_eth_pad) +
 408                                 sizeof(struct mlx5_wqe_eth_seg);
 409                 /* fall through */
 410         case IB_QPT_SMI:
 411         case MLX5_IB_QPT_HW_GSI:
 412                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 413                         sizeof(struct mlx5_wqe_datagram_seg);
 414                 break;
 415
 416         case MLX5_IB_QPT_REG_UMR:
 417                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 418                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 419                         sizeof(struct mlx5_mkey_seg);
 420                 break;
 421
 422         default:
 423                 return -EINVAL;
 424         }
 425
 426         return size;
 427 }
 428
 429 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 430 {
 431         int inl_size = 0;
 432         int size;
 433
 434         size = sq_overhead(attr);
 435         if (size < 0)
 436                 return size;
 437
 438         if (attr->cap.max_inline_data) {
 439                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 440                         attr->cap.max_inline_data;
 441         }
 442
 443         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 444         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 445             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 446                         return MLX5_SIG_WQE_SIZE;
 447         else
 448                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 449 }
 450
 451 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 452 {
 453         int max_sge;
 454
 455         if (attr->qp_type == IB_QPT_RC)
 456                 max_sge = (min_t(int, wqe_size, 512) -
 457                            sizeof(struct mlx5_wqe_ctrl_seg) -
 458                            sizeof(struct mlx5_wqe_raddr_seg)) /
 459                         sizeof(struct mlx5_wqe_data_seg);
 460         else if (attr->qp_type == IB_QPT_XRC_INI)
 461                 max_sge = (min_t(int, wqe_size, 512) -
 462                            sizeof(struct mlx5_wqe_ctrl_seg) -
 463                            sizeof(struct mlx5_wqe_xrc_seg) -
 464                            sizeof(struct mlx5_wqe_raddr_seg)) /
 465                         sizeof(struct mlx5_wqe_data_seg);
 466         else
 467                 max_sge = (wqe_size - sq_overhead(attr)) /
 468                         sizeof(struct mlx5_wqe_data_seg);
 469
 470         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 471                      sizeof(struct mlx5_wqe_data_seg));
 472 }
 473
 474 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 475                         struct mlx5_ib_qp *qp)
 476 {
 477         int wqe_size;
 478         int wq_size;
 479
 480         if (!attr->cap.max_send_wr)
 481                 return 0;
 482
 483         wqe_size = calc_send_wqe(attr);
 484         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 485         if (wqe_size < 0)
 486                 return wqe_size;
 487
 488         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 489                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 490                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 491                 return -EINVAL;
 492         }
 493
 494         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 495                               sizeof(struct mlx5_wqe_inline_seg);
 496         attr->cap.max_inline_data = qp->max_inline_data;
 497
 498         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 499                 qp->signature_en = true;
 500
 501         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 502         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 503         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 504                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 505                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 506                             qp->sq.wqe_cnt,
 507                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 508                 return -ENOMEM;
 509         }
 510         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 511         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 512         if (qp->sq.max_gs < attr->cap.max_send_sge)
 513                 return -ENOMEM;
 514
 515         attr->cap.max_send_sge = qp->sq.max_gs;
 516         qp->sq.max_post = wq_size / wqe_size;
 517         attr->cap.max_send_wr = qp->sq.max_post;
 518
 519         return wq_size;
 520 }
 521
 522 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 523                             struct mlx5_ib_qp *qp,
 524                             struct mlx5_ib_create_qp *ucmd,
 525                             struct mlx5_ib_qp_base *base,
 526                             struct ib_qp_init_attr *attr)
 527 {
 528         int desc_sz = 1 << qp->sq.wqe_shift;
 529
 530         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 531                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 532                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 533                 return -EINVAL;
 534         }
 535
 536         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 537                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 538                              ucmd->sq_wqe_count);
 539                 return -EINVAL;
 540         }
 541
 542         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 543
 544         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 545                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 546                              qp->sq.wqe_cnt,
 547                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 548                 return -EINVAL;
 549         }
 550
 551         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 552             qp->flags & MLX5_IB_QP_UNDERLAY) {
 553                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 554                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 555         } else {
 556                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 557                                          (qp->sq.wqe_cnt << 6);
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int qp_has_rq(struct ib_qp_init_attr *attr)
 564 {
 565         if (attr->qp_type == IB_QPT_XRC_INI ||
 566             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 567             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 568             !attr->cap.max_recv_wr)
 569                 return 0;
 570
 571         return 1;
 572 }
 573
 574 enum {
 575         /* this is the first blue flame register in the array of bfregs assigned
 576          * to a processes. Since we do not use it for blue flame but rather
 577          * regular 64 bit doorbells, we do not need a lock for maintaiing
 578          * "odd/even" order
 579          */
 580         NUM_NON_BLUE_FLAME_BFREGS = 1,
 581 };
 582
 583 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 584 {
 585         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 586 }
 587
 588 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 589                          struct mlx5_bfreg_info *bfregi)
 590 {
 591         int n;
 592
 593         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 594             NUM_NON_BLUE_FLAME_BFREGS;
 595
 596         return n >= 0 ? n : 0;
 597 }
 598
 599 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 600                            struct mlx5_bfreg_info *bfregi)
 601 {
 602         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 603 }
 604
 605 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 606                           struct mlx5_bfreg_info *bfregi)
 607 {
 608         int med;
 609
 610         med = num_med_bfreg(dev, bfregi);
 611         return ++med;
 612 }
 613
 614 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 615                                   struct mlx5_bfreg_info *bfregi)
 616 {
 617         int i;
 618
 619         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 620                 if (!bfregi->count[i]) {
 621                         bfregi->count[i]++;
 622                         return i;
 623                 }
 624         }
 625
 626         return -ENOMEM;
 627 }
 628
 629 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 630                                  struct mlx5_bfreg_info *bfregi)
 631 {
 632         int minidx = first_med_bfreg(dev, bfregi);
 633         int i;
 634
 635         if (minidx < 0)
 636                 return minidx;
 637
 638         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 639                 if (bfregi->count[i] < bfregi->count[minidx])
 640                         minidx = i;
 641                 if (!bfregi->count[minidx])
 642                         break;
 643         }
 644
 645         bfregi->count[minidx]++;
 646         return minidx;
 647 }
 648
 649 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 650                        struct mlx5_bfreg_info *bfregi)
 651 {
 652         int bfregn = -ENOMEM;
 653
 654         mutex_lock(&bfregi->lock);
 655         if (bfregi->ver >= 2) {
 656                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 657                 if (bfregn < 0)
 658                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 659         }
 660
 661         if (bfregn < 0) {
 662                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 663                 bfregn = 0;
 664                 bfregi->count[bfregn]++;
 665         }
 666         mutex_unlock(&bfregi->lock);
 667
 668         return bfregn;
 669 }
 670
 671 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 672 {
 673         mutex_lock(&bfregi->lock);
 674         bfregi->count[bfregn]--;
 675         mutex_unlock(&bfregi->lock);
 676 }
 677
 678 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 679 {
 680         switch (state) {
 681         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 682         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 683         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 684         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 685         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 686         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 687         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 688         default:                return -1;
 689         }
 690 }
 691
 692 static int to_mlx5_st(enum ib_qp_type type)
 693 {
 694         switch (type) {
 695         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 696         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 697         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 698         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 699         case IB_QPT_XRC_INI:
 700         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 701         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 702         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 703         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 704         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 705         case IB_QPT_RAW_PACKET:
 706         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 707         case IB_QPT_MAX:
 708         default:                return -EINVAL;
 709         }
 710 }
 711
 712 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 713                              struct mlx5_ib_cq *recv_cq);
 714 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 715                                struct mlx5_ib_cq *recv_cq);
 716
 717 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 718                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 719                         bool dyn_bfreg)
 720 {
 721         unsigned int bfregs_per_sys_page;
 722         u32 index_of_sys_page;
 723         u32 offset;
 724
 725         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 726                                 MLX5_NON_FP_BFREGS_PER_UAR;
 727         index_of_sys_page = bfregn / bfregs_per_sys_page;
 728
 729         if (dyn_bfreg) {
 730                 index_of_sys_page += bfregi->num_static_sys_pages;
 731
 732                 if (index_of_sys_page >= bfregi->num_sys_pages)
 733                         return -EINVAL;
 734
 735                 if (bfregn > bfregi->num_dyn_bfregs ||
 736                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 737                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 738                         return -EINVAL;
 739                 }
 740         }
 741
 742         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 743         return bfregi->sys_pages[index_of_sys_page] + offset;
 744 }
 745
 746 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 747                             unsigned long addr, size_t size,
 748                             struct ib_umem **umem, int *npages, int *page_shift,
 749                             int *ncont, u32 *offset)
 750 {
 751         int err;
 752
 753         *umem = ib_umem_get(udata, addr, size, 0, 0);
 754         if (IS_ERR(*umem)) {
 755                 mlx5_ib_dbg(dev, "umem_get failed\n");
 756                 return PTR_ERR(*umem);
 757         }
 758
 759         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 760
 761         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 762         if (err) {
 763                 mlx5_ib_warn(dev, "bad offset\n");
 764                 goto err_umem;
 765         }
 766
 767         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 768                     addr, size, *npages, *page_shift, *ncont, *offset);
 769
 770         return 0;
 771
 772 err_umem:
 773         ib_umem_release(*umem);
 774         *umem = NULL;
 775
 776         return err;
 777 }
 778
 779 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 780                             struct mlx5_ib_rwq *rwq)
 781 {
 782         struct mlx5_ib_ucontext *context;
 783
 784         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 785                 atomic_dec(&dev->delay_drop.rqs_cnt);
 786
 787         context = to_mucontext(pd->uobject->context);
 788         mlx5_ib_db_unmap_user(context, &rwq->db);
 789         if (rwq->umem)
 790                 ib_umem_release(rwq->umem);
 791 }
 792
 793 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 794                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 795                           struct mlx5_ib_create_wq *ucmd)
 796 {
 797         int page_shift = 0;
 798         int npages;
 799         u32 offset = 0;
 800         int ncont = 0;
 801         int err;
 802
 803         if (!ucmd->buf_addr)
 804                 return -EINVAL;
 805
 806         rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
 807         if (IS_ERR(rwq->umem)) {
 808                 mlx5_ib_dbg(dev, "umem_get failed\n");
 809                 err = PTR_ERR(rwq->umem);
 810                 return err;
 811         }
 812
 813         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 814                            &ncont, NULL);
 815         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 816                                      &rwq->rq_page_offset);
 817         if (err) {
 818                 mlx5_ib_warn(dev, "bad offset\n");
 819                 goto err_umem;
 820         }
 821
 822         rwq->rq_num_pas = ncont;
 823         rwq->page_shift = page_shift;
 824         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 825         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 826
 827         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 828                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 829                     npages, page_shift, ncont, offset);
 830
 831         err = mlx5_ib_db_map_user(to_mucontext(pd->uobject->context), udata,
 832                                   ucmd->db_addr, &rwq->db);
 833         if (err) {
 834                 mlx5_ib_dbg(dev, "map failed\n");
 835                 goto err_umem;
 836         }
 837
 838         rwq->create_type = MLX5_WQ_USER;
 839         return 0;
 840
 841 err_umem:
 842         ib_umem_release(rwq->umem);
 843         return err;
 844 }
 845
 846 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 847                          struct mlx5_bfreg_info *bfregi, int bfregn)
 848 {
 849         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 850                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 851 }
 852
 853 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 854                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 855                           struct ib_qp_init_attr *attr,
 856                           u32 **in,
 857                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 858                           struct mlx5_ib_qp_base *base)
 859 {
 860         struct mlx5_ib_ucontext *context;
 861         struct mlx5_ib_create_qp ucmd;
 862         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 863         int page_shift = 0;
 864         int uar_index = 0;
 865         int npages;
 866         u32 offset = 0;
 867         int bfregn;
 868         int ncont = 0;
 869         __be64 *pas;
 870         void *qpc;
 871         int err;
 872         u16 uid;
 873
 874         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 875         if (err) {
 876                 mlx5_ib_dbg(dev, "copy failed\n");
 877                 return err;
 878         }
 879
 880         context = to_mucontext(pd->uobject->context);
 881         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 882                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 883                                                 ucmd.bfreg_index, true);
 884                 if (uar_index < 0)
 885                         return uar_index;
 886
 887                 bfregn = MLX5_IB_INVALID_BFREG;
 888         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 889                 /*
 890                  * TBD: should come from the verbs when we have the API
 891                  */
 892                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 893                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 894         }
 895         else {
 896                 bfregn = alloc_bfreg(dev, &context->bfregi);
 897                 if (bfregn < 0)
 898                         return bfregn;
 899         }
 900
 901         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 902         if (bfregn != MLX5_IB_INVALID_BFREG)
 903                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 904                                                 false);
 905
 906         qp->rq.offset = 0;
 907         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 908         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 909
 910         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 911         if (err)
 912                 goto err_bfreg;
 913
 914         if (ucmd.buf_addr && ubuffer->buf_size) {
 915                 ubuffer->buf_addr = ucmd.buf_addr;
 916                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 917                                        ubuffer->buf_size, &ubuffer->umem,
 918                                        &npages, &page_shift, &ncont, &offset);
 919                 if (err)
 920                         goto err_bfreg;
 921         } else {
 922                 ubuffer->umem = NULL;
 923         }
 924
 925         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 926                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 927         *in = kvzalloc(*inlen, GFP_KERNEL);
 928         if (!*in) {
 929                 err = -ENOMEM;
 930                 goto err_umem;
 931         }
 932
 933         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
 934                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 935         MLX5_SET(create_qp_in, *in, uid, uid);
 936         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 937         if (ubuffer->umem)
 938                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 939
 940         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 941
 942         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 943         MLX5_SET(qpc, qpc, page_offset, offset);
 944
 945         MLX5_SET(qpc, qpc, uar_page, uar_index);
 946         if (bfregn != MLX5_IB_INVALID_BFREG)
 947                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 948         else
 949                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 950         qp->bfregn = bfregn;
 951
 952         err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
 953         if (err) {
 954                 mlx5_ib_dbg(dev, "map failed\n");
 955                 goto err_free;
 956         }
 957
 958         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 959         if (err) {
 960                 mlx5_ib_dbg(dev, "copy failed\n");
 961                 goto err_unmap;
 962         }
 963         qp->create_type = MLX5_QP_USER;
 964
 965         return 0;
 966
 967 err_unmap:
 968         mlx5_ib_db_unmap_user(context, &qp->db);
 969
 970 err_free:
 971         kvfree(*in);
 972
 973 err_umem:
 974         if (ubuffer->umem)
 975                 ib_umem_release(ubuffer->umem);
 976
 977 err_bfreg:
 978         if (bfregn != MLX5_IB_INVALID_BFREG)
 979                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 980         return err;
 981 }
 982
 983 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 984                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 985 {
 986         struct mlx5_ib_ucontext *context;
 987
 988         context = to_mucontext(pd->uobject->context);
 989         mlx5_ib_db_unmap_user(context, &qp->db);
 990         if (base->ubuffer.umem)
 991                 ib_umem_release(base->ubuffer.umem);
 992
 993         /*
 994          * Free only the BFREGs which are handled by the kernel.
 995          * BFREGs of UARs allocated dynamically are handled by user.
 996          */
 997         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 998                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 999 }
1000
1001 /* get_sq_edge - Get the next nearby edge.
1002  *
1003  * An 'edge' is defined as the first following address after the end
1004  * of the fragment or the SQ. Accordingly, during the WQE construction
1005  * which repetitively increases the pointer to write the next data, it
1006  * simply should check if it gets to an edge.
1007  *
1008  * @sq - SQ buffer.
1009  * @idx - Stride index in the SQ buffer.
1010  *
1011  * Return:
1012  *      The new edge.
1013  */
1014 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1015 {
1016         void *fragment_end;
1017
1018         fragment_end = mlx5_frag_buf_get_wqe
1019                 (&sq->fbc,
1020                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1021
1022         return fragment_end + MLX5_SEND_WQE_BB;
1023 }
1024
1025 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1026                             struct ib_qp_init_attr *init_attr,
1027                             struct mlx5_ib_qp *qp,
1028                             u32 **in, int *inlen,
1029                             struct mlx5_ib_qp_base *base)
1030 {
1031         int uar_index;
1032         void *qpc;
1033         int err;
1034
1035         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
1036                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
1037                                         IB_QP_CREATE_IPOIB_UD_LSO |
1038                                         IB_QP_CREATE_NETIF_QP |
1039                                         mlx5_ib_create_qp_sqpn_qp1()))
1040                 return -EINVAL;
1041
1042         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1043                 qp->bf.bfreg = &dev->fp_bfreg;
1044         else
1045                 qp->bf.bfreg = &dev->bfreg;
1046
1047         /* We need to divide by two since each register is comprised of
1048          * two buffers of identical size, namely odd and even
1049          */
1050         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1051         uar_index = qp->bf.bfreg->index;
1052
1053         err = calc_sq_size(dev, init_attr, qp);
1054         if (err < 0) {
1055                 mlx5_ib_dbg(dev, "err %d\n", err);
1056                 return err;
1057         }
1058
1059         qp->rq.offset = 0;
1060         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1061         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1062
1063         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1064                                        &qp->buf, dev->mdev->priv.numa_node);
1065         if (err) {
1066                 mlx5_ib_dbg(dev, "err %d\n", err);
1067                 return err;
1068         }
1069
1070         if (qp->rq.wqe_cnt)
1071                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1072                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1073
1074         if (qp->sq.wqe_cnt) {
1075                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1076                                         MLX5_SEND_WQE_BB;
1077                 mlx5_init_fbc_offset(qp->buf.frags +
1078                                      (qp->sq.offset / PAGE_SIZE),
1079                                      ilog2(MLX5_SEND_WQE_BB),
1080                                      ilog2(qp->sq.wqe_cnt),
1081                                      sq_strides_offset, &qp->sq.fbc);
1082
1083                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1084         }
1085
1086         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1087                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1088         *in = kvzalloc(*inlen, GFP_KERNEL);
1089         if (!*in) {
1090                 err = -ENOMEM;
1091                 goto err_buf;
1092         }
1093
1094         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1095         MLX5_SET(qpc, qpc, uar_page, uar_index);
1096         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1097
1098         /* Set "fast registration enabled" for all kernel QPs */
1099         MLX5_SET(qpc, qpc, fre, 1);
1100         MLX5_SET(qpc, qpc, rlky, 1);
1101
1102         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1103                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1104                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1105         }
1106
1107         mlx5_fill_page_frag_array(&qp->buf,
1108                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1109                                                          *in, pas));
1110
1111         err = mlx5_db_alloc(dev->mdev, &qp->db);
1112         if (err) {
1113                 mlx5_ib_dbg(dev, "err %d\n", err);
1114                 goto err_free;
1115         }
1116
1117         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1118                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1119         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1120                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1121         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1122                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1123         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1124                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1125         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1126                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1127
1128         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1129             !qp->sq.w_list || !qp->sq.wqe_head) {
1130                 err = -ENOMEM;
1131                 goto err_wrid;
1132         }
1133         qp->create_type = MLX5_QP_KERNEL;
1134
1135         return 0;
1136
1137 err_wrid:
1138         kvfree(qp->sq.wqe_head);
1139         kvfree(qp->sq.w_list);
1140         kvfree(qp->sq.wrid);
1141         kvfree(qp->sq.wr_data);
1142         kvfree(qp->rq.wrid);
1143         mlx5_db_free(dev->mdev, &qp->db);
1144
1145 err_free:
1146         kvfree(*in);
1147
1148 err_buf:
1149         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1150         return err;
1151 }
1152
1153 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1154 {
1155         kvfree(qp->sq.wqe_head);
1156         kvfree(qp->sq.w_list);
1157         kvfree(qp->sq.wrid);
1158         kvfree(qp->sq.wr_data);
1159         kvfree(qp->rq.wrid);
1160         mlx5_db_free(dev->mdev, &qp->db);
1161         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1162 }
1163
1164 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1165 {
1166         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1167             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1168             (attr->qp_type == IB_QPT_XRC_INI))
1169                 return MLX5_SRQ_RQ;
1170         else if (!qp->has_rq)
1171                 return MLX5_ZERO_LEN_RQ;
1172         else
1173                 return MLX5_NON_ZERO_RQ;
1174 }
1175
1176 static int is_connected(enum ib_qp_type qp_type)
1177 {
1178         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1179             qp_type == MLX5_IB_QPT_DCI)
1180                 return 1;
1181
1182         return 0;
1183 }
1184
1185 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1186                                     struct mlx5_ib_qp *qp,
1187                                     struct mlx5_ib_sq *sq, u32 tdn,
1188                                     struct ib_pd *pd)
1189 {
1190         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1191         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1192
1193         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1194         MLX5_SET(tisc, tisc, transport_domain, tdn);
1195         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1196                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1197
1198         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1199 }
1200
1201 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1202                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1203 {
1204         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1205 }
1206
1207 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1208                                        struct mlx5_ib_sq *sq)
1209 {
1210         if (sq->flow_rule)
1211                 mlx5_del_flow_rules(sq->flow_rule);
1212 }
1213
1214 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1215                                    struct ib_udata *udata,
1216                                    struct mlx5_ib_sq *sq, void *qpin,
1217                                    struct ib_pd *pd)
1218 {
1219         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1220         __be64 *pas;
1221         void *in;
1222         void *sqc;
1223         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1224         void *wq;
1225         int inlen;
1226         int err;
1227         int page_shift = 0;
1228         int npages;
1229         int ncont = 0;
1230         u32 offset = 0;
1231
1232         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1233                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1234                                &offset);
1235         if (err)
1236                 return err;
1237
1238         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1239         in = kvzalloc(inlen, GFP_KERNEL);
1240         if (!in) {
1241                 err = -ENOMEM;
1242                 goto err_umem;
1243         }
1244
1245         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1246         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1247         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1248         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1249                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1250         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1251         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1252         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1253         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1254         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1255         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1256             MLX5_CAP_ETH(dev->mdev, swp))
1257                 MLX5_SET(sqc, sqc, allow_swp, 1);
1258
1259         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1260         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1261         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1262         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1263         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1264         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1265         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1266         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1267         MLX5_SET(wq, wq, page_offset, offset);
1268
1269         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1270         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1271
1272         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1273
1274         kvfree(in);
1275
1276         if (err)
1277                 goto err_umem;
1278
1279         err = create_flow_rule_vport_sq(dev, sq);
1280         if (err)
1281                 goto err_flow;
1282
1283         return 0;
1284
1285 err_flow:
1286         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1287
1288 err_umem:
1289         ib_umem_release(sq->ubuffer.umem);
1290         sq->ubuffer.umem = NULL;
1291
1292         return err;
1293 }
1294
1295 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1296                                      struct mlx5_ib_sq *sq)
1297 {
1298         destroy_flow_rule_vport_sq(dev, sq);
1299         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1300         ib_umem_release(sq->ubuffer.umem);
1301 }
1302
1303 static size_t get_rq_pas_size(void *qpc)
1304 {
1305         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1306         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1307         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1308         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1309         u32 po_quanta     = 1 << (log_page_size - 6);
1310         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1311         u32 page_size     = 1 << log_page_size;
1312         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1313         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1314
1315         return rq_num_pas * sizeof(u64);
1316 }
1317
1318 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1319                                    struct mlx5_ib_rq *rq, void *qpin,
1320                                    size_t qpinlen, struct ib_pd *pd)
1321 {
1322         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1323         __be64 *pas;
1324         __be64 *qp_pas;
1325         void *in;
1326         void *rqc;
1327         void *wq;
1328         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1329         size_t rq_pas_size = get_rq_pas_size(qpc);
1330         size_t inlen;
1331         int err;
1332
1333         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1334                 return -EINVAL;
1335
1336         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1337         in = kvzalloc(inlen, GFP_KERNEL);
1338         if (!in)
1339                 return -ENOMEM;
1340
1341         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1342         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1343         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1344                 MLX5_SET(rqc, rqc, vsd, 1);
1345         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1346         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1347         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1348         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1349         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1350
1351         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1352                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1353
1354         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1355         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1356         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1357                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1358         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1359         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1360         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1361         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1362         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1363         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1364
1365         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1366         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1367         memcpy(pas, qp_pas, rq_pas_size);
1368
1369         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1370
1371         kvfree(in);
1372
1373         return err;
1374 }
1375
1376 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1377                                      struct mlx5_ib_rq *rq)
1378 {
1379         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1380 }
1381
1382 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1383 {
1384         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1385                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1386                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1387 }
1388
1389 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1390                                       struct mlx5_ib_rq *rq,
1391                                       u32 qp_flags_en,
1392                                       struct ib_pd *pd)
1393 {
1394         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1395                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1396                 mlx5_ib_disable_lb(dev, false, true);
1397         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1398 }
1399
1400 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1401                                     struct mlx5_ib_rq *rq, u32 tdn,
1402                                     u32 *qp_flags_en,
1403                                     struct ib_pd *pd)
1404 {
1405         u8 lb_flag = 0;
1406         u32 *in;
1407         void *tirc;
1408         int inlen;
1409         int err;
1410
1411         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1412         in = kvzalloc(inlen, GFP_KERNEL);
1413         if (!in)
1414                 return -ENOMEM;
1415
1416         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1417         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1418         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1419         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1420         MLX5_SET(tirc, tirc, transport_domain, tdn);
1421         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1422                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1423
1424         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1425                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1426
1427         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1428                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1429
1430         if (dev->rep) {
1431                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1432                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1433         }
1434
1435         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1436
1437         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1438
1439         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1440                 err = mlx5_ib_enable_lb(dev, false, true);
1441
1442                 if (err)
1443                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1444         }
1445         kvfree(in);
1446
1447         return err;
1448 }
1449
1450 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1451                                 u32 *in, size_t inlen,
1452                                 struct ib_pd *pd,
1453                                 struct ib_udata *udata,
1454                                 struct mlx5_ib_create_qp_resp *resp)
1455 {
1456         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1457         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1459         struct ib_uobject *uobj = pd->uobject;
1460         struct ib_ucontext *ucontext = uobj->context;
1461         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1462         int err;
1463         u32 tdn = mucontext->tdn;
1464         u16 uid = to_mpd(pd)->uid;
1465
1466         if (qp->sq.wqe_cnt) {
1467                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1468                 if (err)
1469                         return err;
1470
1471                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1472                 if (err)
1473                         goto err_destroy_tis;
1474
1475                 if (uid) {
1476                         resp->tisn = sq->tisn;
1477                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1478                         resp->sqn = sq->base.mqp.qpn;
1479                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1480                 }
1481
1482                 sq->base.container_mibqp = qp;
1483                 sq->base.mqp.event = mlx5_ib_qp_event;
1484         }
1485
1486         if (qp->rq.wqe_cnt) {
1487                 rq->base.container_mibqp = qp;
1488
1489                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1490                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1491                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1492                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1493                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1494                 if (err)
1495                         goto err_destroy_sq;
1496
1497                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1498                 if (err)
1499                         goto err_destroy_rq;
1500
1501                 if (uid) {
1502                         resp->rqn = rq->base.mqp.qpn;
1503                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1504                         resp->tirn = rq->tirn;
1505                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1506                 }
1507         }
1508
1509         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1510                                                      rq->base.mqp.qpn;
1511         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1512         if (err)
1513                 goto err_destroy_tir;
1514
1515         return 0;
1516
1517 err_destroy_tir:
1518         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1519 err_destroy_rq:
1520         destroy_raw_packet_qp_rq(dev, rq);
1521 err_destroy_sq:
1522         if (!qp->sq.wqe_cnt)
1523                 return err;
1524         destroy_raw_packet_qp_sq(dev, sq);
1525 err_destroy_tis:
1526         destroy_raw_packet_qp_tis(dev, sq, pd);
1527
1528         return err;
1529 }
1530
1531 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1532                                   struct mlx5_ib_qp *qp)
1533 {
1534         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1535         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1536         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1537
1538         if (qp->rq.wqe_cnt) {
1539                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1540                 destroy_raw_packet_qp_rq(dev, rq);
1541         }
1542
1543         if (qp->sq.wqe_cnt) {
1544                 destroy_raw_packet_qp_sq(dev, sq);
1545                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1546         }
1547 }
1548
1549 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1550                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1551 {
1552         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1553         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1554
1555         sq->sq = &qp->sq;
1556         rq->rq = &qp->rq;
1557         sq->doorbell = &qp->db;
1558         rq->doorbell = &qp->db;
1559 }
1560
1561 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1562 {
1563         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1564                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1565                 mlx5_ib_disable_lb(dev, false, true);
1566         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1567                              to_mpd(qp->ibqp.pd)->uid);
1568 }
1569
1570 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1571                                  struct ib_pd *pd,
1572                                  struct ib_qp_init_attr *init_attr,
1573                                  struct ib_udata *udata)
1574 {
1575         struct ib_uobject *uobj = pd->uobject;
1576         struct ib_ucontext *ucontext = uobj->context;
1577         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1578         struct mlx5_ib_create_qp_resp resp = {};
1579         int inlen;
1580         int err;
1581         u32 *in;
1582         void *tirc;
1583         void *hfso;
1584         u32 selected_fields = 0;
1585         u32 outer_l4;
1586         size_t min_resp_len;
1587         u32 tdn = mucontext->tdn;
1588         struct mlx5_ib_create_qp_rss ucmd = {};
1589         size_t required_cmd_sz;
1590         u8 lb_flag = 0;
1591
1592         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1593                 return -EOPNOTSUPP;
1594
1595         if (init_attr->create_flags || init_attr->send_cq)
1596                 return -EINVAL;
1597
1598         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1599         if (udata->outlen < min_resp_len)
1600                 return -EINVAL;
1601
1602         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1603         if (udata->inlen < required_cmd_sz) {
1604                 mlx5_ib_dbg(dev, "invalid inlen\n");
1605                 return -EINVAL;
1606         }
1607
1608         if (udata->inlen > sizeof(ucmd) &&
1609             !ib_is_udata_cleared(udata, sizeof(ucmd),
1610                                  udata->inlen - sizeof(ucmd))) {
1611                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1612                 return -EOPNOTSUPP;
1613         }
1614
1615         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1616                 mlx5_ib_dbg(dev, "copy failed\n");
1617                 return -EFAULT;
1618         }
1619
1620         if (ucmd.comp_mask) {
1621                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1622                 return -EOPNOTSUPP;
1623         }
1624
1625         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1626                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1627                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1628                 mlx5_ib_dbg(dev, "invalid flags\n");
1629                 return -EOPNOTSUPP;
1630         }
1631
1632         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1633             !tunnel_offload_supported(dev->mdev)) {
1634                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1635                 return -EOPNOTSUPP;
1636         }
1637
1638         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1639             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1640                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1641                 return -EOPNOTSUPP;
1642         }
1643
1644         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1645                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1646                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1647         }
1648
1649         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1650                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1651                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1652         }
1653
1654         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1655         if (err) {
1656                 mlx5_ib_dbg(dev, "copy failed\n");
1657                 return -EINVAL;
1658         }
1659
1660         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1661         in = kvzalloc(inlen, GFP_KERNEL);
1662         if (!in)
1663                 return -ENOMEM;
1664
1665         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1666         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1667         MLX5_SET(tirc, tirc, disp_type,
1668                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1669         MLX5_SET(tirc, tirc, indirect_table,
1670                  init_attr->rwq_ind_tbl->ind_tbl_num);
1671         MLX5_SET(tirc, tirc, transport_domain, tdn);
1672
1673         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1674
1675         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1676                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1677
1678         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1679
1680         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1681                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1682         else
1683                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1684
1685         switch (ucmd.rx_hash_function) {
1686         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1687         {
1688                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1689                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1690
1691                 if (len != ucmd.rx_key_len) {
1692                         err = -EINVAL;
1693                         goto err;
1694                 }
1695
1696                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1697                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1698                 memcpy(rss_key, ucmd.rx_hash_key, len);
1699                 break;
1700         }
1701         default:
1702                 err = -EOPNOTSUPP;
1703                 goto err;
1704         }
1705
1706         if (!ucmd.rx_hash_fields_mask) {
1707                 /* special case when this TIR serves as steering entry without hashing */
1708                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1709                         goto create_tir;
1710                 err = -EINVAL;
1711                 goto err;
1712         }
1713
1714         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1715              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1716              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1717              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1718                 err = -EINVAL;
1719                 goto err;
1720         }
1721
1722         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1723         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1724             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1725                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1726                          MLX5_L3_PROT_TYPE_IPV4);
1727         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1728                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1729                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1730                          MLX5_L3_PROT_TYPE_IPV6);
1731
1732         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1733                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1734                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1735                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1736                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1737
1738         /* Check that only one l4 protocol is set */
1739         if (outer_l4 & (outer_l4 - 1)) {
1740                 err = -EINVAL;
1741                 goto err;
1742         }
1743
1744         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1745         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1746             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1747                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1748                          MLX5_L4_PROT_TYPE_TCP);
1749         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1750                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1751                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1752                          MLX5_L4_PROT_TYPE_UDP);
1753
1754         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1755             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1756                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1757
1758         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1759             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1760                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1761
1762         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1763             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1764                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1765
1766         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1767             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1768                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1769
1770         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1771                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1772
1773         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1774
1775 create_tir:
1776         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1777
1778         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1779                 err = mlx5_ib_enable_lb(dev, false, true);
1780
1781                 if (err)
1782                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1783                                              to_mpd(pd)->uid);
1784         }
1785
1786         if (err)
1787                 goto err;
1788
1789         if (mucontext->devx_uid) {
1790                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1791                 resp.tirn = qp->rss_qp.tirn;
1792         }
1793
1794         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1795         if (err)
1796                 goto err_copy;
1797
1798         kvfree(in);
1799         /* qpn is reserved for that QP */
1800         qp->trans_qp.base.mqp.qpn = 0;
1801         qp->flags |= MLX5_IB_QP_RSS;
1802         return 0;
1803
1804 err_copy:
1805         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1806 err:
1807         kvfree(in);
1808         return err;
1809 }
1810
1811 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1812                                          void *qpc)
1813 {
1814         int rcqe_sz;
1815
1816         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1817                 return;
1818
1819         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1820
1821         if (rcqe_sz == 128) {
1822                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1823                 return;
1824         }
1825
1826         if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1827                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1828 }
1829
1830 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1831                                          struct ib_qp_init_attr *init_attr,
1832                                          struct mlx5_ib_create_qp *ucmd,
1833                                          void *qpc)
1834 {
1835         enum ib_qp_type qpt = init_attr->qp_type;
1836         int scqe_sz;
1837         bool allow_scat_cqe = 0;
1838
1839         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1840                 return;
1841
1842         if (ucmd)
1843                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1844
1845         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1846                 return;
1847
1848         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1849         if (scqe_sz == 128) {
1850                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1851                 return;
1852         }
1853
1854         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1855             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1856                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1857 }
1858
1859 static int atomic_size_to_mode(int size_mask)
1860 {
1861         /* driver does not support atomic_size > 256B
1862          * and does not know how to translate bigger sizes
1863          */
1864         int supported_size_mask = size_mask & 0x1ff;
1865         int log_max_size;
1866
1867         if (!supported_size_mask)
1868                 return -EOPNOTSUPP;
1869
1870         log_max_size = __fls(supported_size_mask);
1871
1872         if (log_max_size > 3)
1873                 return log_max_size;
1874
1875         return MLX5_ATOMIC_MODE_8B;
1876 }
1877
1878 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1879                            enum ib_qp_type qp_type)
1880 {
1881         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1882         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1883         int atomic_mode = -EOPNOTSUPP;
1884         int atomic_size_mask;
1885
1886         if (!atomic)
1887                 return -EOPNOTSUPP;
1888
1889         if (qp_type == MLX5_IB_QPT_DCT)
1890                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1891         else
1892                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1893
1894         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1895             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1896                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1897
1898         if (atomic_mode <= 0 &&
1899             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1900              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1901                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1902
1903         return atomic_mode;
1904 }
1905
1906 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1907 {
1908         return (input & ~supported) == 0;
1909 }
1910
1911 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1912                             struct ib_qp_init_attr *init_attr,
1913                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1914 {
1915         struct mlx5_ib_resources *devr = &dev->devr;
1916         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1917         struct mlx5_core_dev *mdev = dev->mdev;
1918         struct mlx5_ib_create_qp_resp resp = {};
1919         struct mlx5_ib_cq *send_cq;
1920         struct mlx5_ib_cq *recv_cq;
1921         unsigned long flags;
1922         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1923         struct mlx5_ib_create_qp ucmd;
1924         struct mlx5_ib_qp_base *base;
1925         int mlx5_st;
1926         void *qpc;
1927         u32 *in;
1928         int err;
1929
1930         mutex_init(&qp->mutex);
1931         spin_lock_init(&qp->sq.lock);
1932         spin_lock_init(&qp->rq.lock);
1933
1934         mlx5_st = to_mlx5_st(init_attr->qp_type);
1935         if (mlx5_st < 0)
1936                 return -EINVAL;
1937
1938         if (init_attr->rwq_ind_tbl) {
1939                 if (!udata)
1940                         return -ENOSYS;
1941
1942                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1943                 return err;
1944         }
1945
1946         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1947                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1948                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1949                         return -EINVAL;
1950                 } else {
1951                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1952                 }
1953         }
1954
1955         if (init_attr->create_flags &
1956                         (IB_QP_CREATE_CROSS_CHANNEL |
1957                          IB_QP_CREATE_MANAGED_SEND |
1958                          IB_QP_CREATE_MANAGED_RECV)) {
1959                 if (!MLX5_CAP_GEN(mdev, cd)) {
1960                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1961                         return -EINVAL;
1962                 }
1963                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1964                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1965                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1966                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1967                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1968                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1969         }
1970
1971         if (init_attr->qp_type == IB_QPT_UD &&
1972             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1973                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1974                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1975                         return -EOPNOTSUPP;
1976                 }
1977
1978         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1979                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1980                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1981                         return -EOPNOTSUPP;
1982                 }
1983                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1984                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1985                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1986                         return -EOPNOTSUPP;
1987                 }
1988                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1989         }
1990
1991         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1992                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1993
1994         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1995                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1996                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1997                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1998                         return -EOPNOTSUPP;
1999                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2000         }
2001
2002         if (udata) {
2003                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2004                         mlx5_ib_dbg(dev, "copy failed\n");
2005                         return -EFAULT;
2006                 }
2007
2008                 if (!check_flags_mask(ucmd.flags,
2009                                       MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2010                                       MLX5_QP_FLAG_BFREG_INDEX |
2011                                       MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2012                                       MLX5_QP_FLAG_SCATTER_CQE |
2013                                       MLX5_QP_FLAG_SIGNATURE |
2014                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2015                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2016                                       MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2017                                       MLX5_QP_FLAG_TYPE_DCI |
2018                                       MLX5_QP_FLAG_TYPE_DCT))
2019                         return -EINVAL;
2020
2021                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2022                                         &ucmd, udata->inlen, &uidx);
2023                 if (err)
2024                         return err;
2025
2026                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
2027                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2028                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
2029                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2030                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2031                             !tunnel_offload_supported(mdev)) {
2032                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2033                                 return -EOPNOTSUPP;
2034                         }
2035                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2036                 }
2037
2038                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2039                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2040                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2041                                 return -EOPNOTSUPP;
2042                         }
2043                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2044                 }
2045
2046                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2047                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2048                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2049                                 return -EOPNOTSUPP;
2050                         }
2051                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
2052                 }
2053
2054                 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2055                         if (init_attr->qp_type != IB_QPT_RC ||
2056                                 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2057                                 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2058                                 return -EOPNOTSUPP;
2059                         }
2060                         qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2061                 }
2062
2063                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2064                         if (init_attr->qp_type != IB_QPT_UD ||
2065                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
2066                              MLX5_CAP_PORT_TYPE_IB) ||
2067                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2068                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2069                                 return -EOPNOTSUPP;
2070                         }
2071
2072                         qp->flags |= MLX5_IB_QP_UNDERLAY;
2073                         qp->underlay_qpn = init_attr->source_qpn;
2074                 }
2075         } else {
2076                 qp->wq_sig = !!wq_signature;
2077         }
2078
2079         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2080                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2081                &qp->raw_packet_qp.rq.base :
2082                &qp->trans_qp.base;
2083
2084         qp->has_rq = qp_has_rq(init_attr);
2085         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
2086                           qp, udata ? &ucmd : NULL);
2087         if (err) {
2088                 mlx5_ib_dbg(dev, "err %d\n", err);
2089                 return err;
2090         }
2091
2092         if (pd) {
2093                 if (udata) {
2094                         __u32 max_wqes =
2095                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2096                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2097                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2098                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2099                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2100                                 return -EINVAL;
2101                         }
2102                         if (ucmd.sq_wqe_count > max_wqes) {
2103                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2104                                             ucmd.sq_wqe_count, max_wqes);
2105                                 return -EINVAL;
2106                         }
2107                         if (init_attr->create_flags &
2108                             mlx5_ib_create_qp_sqpn_qp1()) {
2109                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2110                                 return -EINVAL;
2111                         }
2112                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2113                                              &resp, &inlen, base);
2114                         if (err)
2115                                 mlx5_ib_dbg(dev, "err %d\n", err);
2116                 } else {
2117                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2118                                                base);
2119                         if (err)
2120                                 mlx5_ib_dbg(dev, "err %d\n", err);
2121                 }
2122
2123                 if (err)
2124                         return err;
2125         } else {
2126                 in = kvzalloc(inlen, GFP_KERNEL);
2127                 if (!in)
2128                         return -ENOMEM;
2129
2130                 qp->create_type = MLX5_QP_EMPTY;
2131         }
2132
2133         if (is_sqp(init_attr->qp_type))
2134                 qp->port = init_attr->port_num;
2135
2136         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2137
2138         MLX5_SET(qpc, qpc, st, mlx5_st);
2139         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2140
2141         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2142                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2143         else
2144                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2145
2146
2147         if (qp->wq_sig)
2148                 MLX5_SET(qpc, qpc, wq_signature, 1);
2149
2150         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2151                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2152
2153         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2154                 MLX5_SET(qpc, qpc, cd_master, 1);
2155         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2156                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2157         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2158                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2159         if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2160                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2161         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2162                 configure_responder_scat_cqe(init_attr, qpc);
2163                 configure_requester_scat_cqe(dev, init_attr,
2164                                              udata ? &ucmd : NULL,
2165                                              qpc);
2166         }
2167
2168         if (qp->rq.wqe_cnt) {
2169                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2170                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2171         }
2172
2173         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2174
2175         if (qp->sq.wqe_cnt) {
2176                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2177         } else {
2178                 MLX5_SET(qpc, qpc, no_sq, 1);
2179                 if (init_attr->srq &&
2180                     init_attr->srq->srq_type == IB_SRQT_TM)
2181                         MLX5_SET(qpc, qpc, offload_type,
2182                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2183         }
2184
2185         /* Set default resources */
2186         switch (init_attr->qp_type) {
2187         case IB_QPT_XRC_TGT:
2188                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2189                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2190                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2191                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2192                 break;
2193         case IB_QPT_XRC_INI:
2194                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2195                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2196                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2197                 break;
2198         default:
2199                 if (init_attr->srq) {
2200                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2201                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2202                 } else {
2203                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2204                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2205                 }
2206         }
2207
2208         if (init_attr->send_cq)
2209                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2210
2211         if (init_attr->recv_cq)
2212                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2213
2214         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2215
2216         /* 0xffffff means we ask to work with cqe version 0 */
2217         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2218                 MLX5_SET(qpc, qpc, user_index, uidx);
2219
2220         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2221         if (init_attr->qp_type == IB_QPT_UD &&
2222             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2223                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2224                 qp->flags |= MLX5_IB_QP_LSO;
2225         }
2226
2227         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2228                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2229                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2230                         err = -EOPNOTSUPP;
2231                         goto err;
2232                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2233                         MLX5_SET(qpc, qpc, end_padding_mode,
2234                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2235                 } else {
2236                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2237                 }
2238         }
2239
2240         if (inlen < 0) {
2241                 err = -EINVAL;
2242                 goto err;
2243         }
2244
2245         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2246             qp->flags & MLX5_IB_QP_UNDERLAY) {
2247                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2248                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2249                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2250                                            &resp);
2251         } else {
2252                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2253         }
2254
2255         if (err) {
2256                 mlx5_ib_dbg(dev, "create qp failed\n");
2257                 goto err_create;
2258         }
2259
2260         kvfree(in);
2261
2262         base->container_mibqp = qp;
2263         base->mqp.event = mlx5_ib_qp_event;
2264
2265         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2266                 &send_cq, &recv_cq);
2267         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2268         mlx5_ib_lock_cqs(send_cq, recv_cq);
2269         /* Maintain device to QPs access, needed for further handling via reset
2270          * flow
2271          */
2272         list_add_tail(&qp->qps_list, &dev->qp_list);
2273         /* Maintain CQ to QPs access, needed for further handling via reset flow
2274          */
2275         if (send_cq)
2276                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2277         if (recv_cq)
2278                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2279         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2280         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2281
2282         return 0;
2283
2284 err_create:
2285         if (qp->create_type == MLX5_QP_USER)
2286                 destroy_qp_user(dev, pd, qp, base);
2287         else if (qp->create_type == MLX5_QP_KERNEL)
2288                 destroy_qp_kernel(dev, qp);
2289
2290 err:
2291         kvfree(in);
2292         return err;
2293 }
2294
2295 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2296         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2297 {
2298         if (send_cq) {
2299                 if (recv_cq) {
2300                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2301                                 spin_lock(&send_cq->lock);
2302                                 spin_lock_nested(&recv_cq->lock,
2303                                                  SINGLE_DEPTH_NESTING);
2304                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2305                                 spin_lock(&send_cq->lock);
2306                                 __acquire(&recv_cq->lock);
2307                         } else {
2308                                 spin_lock(&recv_cq->lock);
2309                                 spin_lock_nested(&send_cq->lock,
2310                                                  SINGLE_DEPTH_NESTING);
2311                         }
2312                 } else {
2313                         spin_lock(&send_cq->lock);
2314                         __acquire(&recv_cq->lock);
2315                 }
2316         } else if (recv_cq) {
2317                 spin_lock(&recv_cq->lock);
2318                 __acquire(&send_cq->lock);
2319         } else {
2320                 __acquire(&send_cq->lock);
2321                 __acquire(&recv_cq->lock);
2322         }
2323 }
2324
2325 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2326         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2327 {
2328         if (send_cq) {
2329                 if (recv_cq) {
2330                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2331                                 spin_unlock(&recv_cq->lock);
2332                                 spin_unlock(&send_cq->lock);
2333                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2334                                 __release(&recv_cq->lock);
2335                                 spin_unlock(&send_cq->lock);
2336                         } else {
2337                                 spin_unlock(&send_cq->lock);
2338                                 spin_unlock(&recv_cq->lock);
2339                         }
2340                 } else {
2341                         __release(&recv_cq->lock);
2342                         spin_unlock(&send_cq->lock);
2343                 }
2344         } else if (recv_cq) {
2345                 __release(&send_cq->lock);
2346                 spin_unlock(&recv_cq->lock);
2347         } else {
2348                 __release(&recv_cq->lock);
2349                 __release(&send_cq->lock);
2350         }
2351 }
2352
2353 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2354 {
2355         return to_mpd(qp->ibqp.pd);
2356 }
2357
2358 static void get_cqs(enum ib_qp_type qp_type,
2359                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2360                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2361 {
2362         switch (qp_type) {
2363         case IB_QPT_XRC_TGT:
2364                 *send_cq = NULL;
2365                 *recv_cq = NULL;
2366                 break;
2367         case MLX5_IB_QPT_REG_UMR:
2368         case IB_QPT_XRC_INI:
2369                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2370                 *recv_cq = NULL;
2371                 break;
2372
2373         case IB_QPT_SMI:
2374         case MLX5_IB_QPT_HW_GSI:
2375         case IB_QPT_RC:
2376         case IB_QPT_UC:
2377         case IB_QPT_UD:
2378         case IB_QPT_RAW_IPV6:
2379         case IB_QPT_RAW_ETHERTYPE:
2380         case IB_QPT_RAW_PACKET:
2381                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2382                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2383                 break;
2384
2385         case IB_QPT_MAX:
2386         default:
2387                 *send_cq = NULL;
2388                 *recv_cq = NULL;
2389                 break;
2390         }
2391 }
2392
2393 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2394                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2395                                 u8 lag_tx_affinity);
2396
2397 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2398 {
2399         struct mlx5_ib_cq *send_cq, *recv_cq;
2400         struct mlx5_ib_qp_base *base;
2401         unsigned long flags;
2402         int err;
2403
2404         if (qp->ibqp.rwq_ind_tbl) {
2405                 destroy_rss_raw_qp_tir(dev, qp);
2406                 return;
2407         }
2408
2409         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2410                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2411                &qp->raw_packet_qp.rq.base :
2412                &qp->trans_qp.base;
2413
2414         if (qp->state != IB_QPS_RESET) {
2415                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2416                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2417                         err = mlx5_core_qp_modify(dev->mdev,
2418                                                   MLX5_CMD_OP_2RST_QP, 0,
2419                                                   NULL, &base->mqp);
2420                 } else {
2421                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2422                                 .operation = MLX5_CMD_OP_2RST_QP
2423                         };
2424
2425                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2426                 }
2427                 if (err)
2428                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2429                                      base->mqp.qpn);
2430         }
2431
2432         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2433                 &send_cq, &recv_cq);
2434
2435         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2436         mlx5_ib_lock_cqs(send_cq, recv_cq);
2437         /* del from lists under both locks above to protect reset flow paths */
2438         list_del(&qp->qps_list);
2439         if (send_cq)
2440                 list_del(&qp->cq_send_list);
2441
2442         if (recv_cq)
2443                 list_del(&qp->cq_recv_list);
2444
2445         if (qp->create_type == MLX5_QP_KERNEL) {
2446                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2447                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2448                 if (send_cq != recv_cq)
2449                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2450                                            NULL);
2451         }
2452         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2453         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2454
2455         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2456             qp->flags & MLX5_IB_QP_UNDERLAY) {
2457                 destroy_raw_packet_qp(dev, qp);
2458         } else {
2459                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2460                 if (err)
2461                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2462                                      base->mqp.qpn);
2463         }
2464
2465         if (qp->create_type == MLX5_QP_KERNEL)
2466                 destroy_qp_kernel(dev, qp);
2467         else if (qp->create_type == MLX5_QP_USER)
2468                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2469 }
2470
2471 static const char *ib_qp_type_str(enum ib_qp_type type)
2472 {
2473         switch (type) {
2474         case IB_QPT_SMI:
2475                 return "IB_QPT_SMI";
2476         case IB_QPT_GSI:
2477                 return "IB_QPT_GSI";
2478         case IB_QPT_RC:
2479                 return "IB_QPT_RC";
2480         case IB_QPT_UC:
2481                 return "IB_QPT_UC";
2482         case IB_QPT_UD:
2483                 return "IB_QPT_UD";
2484         case IB_QPT_RAW_IPV6:
2485                 return "IB_QPT_RAW_IPV6";
2486         case IB_QPT_RAW_ETHERTYPE:
2487                 return "IB_QPT_RAW_ETHERTYPE";
2488         case IB_QPT_XRC_INI:
2489                 return "IB_QPT_XRC_INI";
2490         case IB_QPT_XRC_TGT:
2491                 return "IB_QPT_XRC_TGT";
2492         case IB_QPT_RAW_PACKET:
2493                 return "IB_QPT_RAW_PACKET";
2494         case MLX5_IB_QPT_REG_UMR:
2495                 return "MLX5_IB_QPT_REG_UMR";
2496         case IB_QPT_DRIVER:
2497                 return "IB_QPT_DRIVER";
2498         case IB_QPT_MAX:
2499         default:
2500                 return "Invalid QP type";
2501         }
2502 }
2503
2504 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2505                                         struct ib_qp_init_attr *attr,
2506                                         struct mlx5_ib_create_qp *ucmd)
2507 {
2508         struct mlx5_ib_qp *qp;
2509         int err = 0;
2510         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2511         void *dctc;
2512
2513         if (!attr->srq || !attr->recv_cq)
2514                 return ERR_PTR(-EINVAL);
2515
2516         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2517                                 ucmd, sizeof(*ucmd), &uidx);
2518         if (err)
2519                 return ERR_PTR(err);
2520
2521         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2522         if (!qp)
2523                 return ERR_PTR(-ENOMEM);
2524
2525         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2526         if (!qp->dct.in) {
2527                 err = -ENOMEM;
2528                 goto err_free;
2529         }
2530
2531         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2532         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2533         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2534         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2535         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2536         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2537         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2538         MLX5_SET(dctc, dctc, user_index, uidx);
2539
2540         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2541                 configure_responder_scat_cqe(attr, dctc);
2542
2543         qp->state = IB_QPS_RESET;
2544
2545         return &qp->ibqp;
2546 err_free:
2547         kfree(qp);
2548         return ERR_PTR(err);
2549 }
2550
2551 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2552                            struct ib_qp_init_attr *init_attr,
2553                            struct mlx5_ib_create_qp *ucmd,
2554                            struct ib_udata *udata)
2555 {
2556         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2557         int err;
2558
2559         if (!udata)
2560                 return -EINVAL;
2561
2562         if (udata->inlen < sizeof(*ucmd)) {
2563                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2564                 return -EINVAL;
2565         }
2566         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2567         if (err)
2568                 return err;
2569
2570         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2571                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2572         } else {
2573                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2574                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2575                 } else {
2576                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2577                         return -EINVAL;
2578                 }
2579         }
2580
2581         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2582                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2583                 return -EOPNOTSUPP;
2584         }
2585
2586         return 0;
2587 }
2588
2589 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2590                                 struct ib_qp_init_attr *verbs_init_attr,
2591                                 struct ib_udata *udata)
2592 {
2593         struct mlx5_ib_dev *dev;
2594         struct mlx5_ib_qp *qp;
2595         u16 xrcdn = 0;
2596         int err;
2597         struct ib_qp_init_attr mlx_init_attr;
2598         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2599
2600         if (pd) {
2601                 dev = to_mdev(pd->device);
2602
2603                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2604                         if (!udata) {
2605                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2606                                 return ERR_PTR(-EINVAL);
2607                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2608                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2609                                 return ERR_PTR(-EINVAL);
2610                         }
2611                 }
2612         } else {
2613                 /* being cautious here */
2614                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2615                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2616                         pr_warn("%s: no PD for transport %s\n", __func__,
2617                                 ib_qp_type_str(init_attr->qp_type));
2618                         return ERR_PTR(-EINVAL);
2619                 }
2620                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2621         }
2622
2623         if (init_attr->qp_type == IB_QPT_DRIVER) {
2624                 struct mlx5_ib_create_qp ucmd;
2625
2626                 init_attr = &mlx_init_attr;
2627                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2628                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2629                 if (err)
2630                         return ERR_PTR(err);
2631
2632                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2633                         if (init_attr->cap.max_recv_wr ||
2634                             init_attr->cap.max_recv_sge) {
2635                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2636                                 return ERR_PTR(-EINVAL);
2637                         }
2638                 } else {
2639                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2640                 }
2641         }
2642
2643         switch (init_attr->qp_type) {
2644         case IB_QPT_XRC_TGT:
2645         case IB_QPT_XRC_INI:
2646                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2647                         mlx5_ib_dbg(dev, "XRC not supported\n");
2648                         return ERR_PTR(-ENOSYS);
2649                 }
2650                 init_attr->recv_cq = NULL;
2651                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2652                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2653                         init_attr->send_cq = NULL;
2654                 }
2655
2656                 /* fall through */
2657         case IB_QPT_RAW_PACKET:
2658         case IB_QPT_RC:
2659         case IB_QPT_UC:
2660         case IB_QPT_UD:
2661         case IB_QPT_SMI:
2662         case MLX5_IB_QPT_HW_GSI:
2663         case MLX5_IB_QPT_REG_UMR:
2664         case MLX5_IB_QPT_DCI:
2665                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2666                 if (!qp)
2667                         return ERR_PTR(-ENOMEM);
2668
2669                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2670                 if (err) {
2671                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2672                         kfree(qp);
2673                         return ERR_PTR(err);
2674                 }
2675
2676                 if (is_qp0(init_attr->qp_type))
2677                         qp->ibqp.qp_num = 0;
2678                 else if (is_qp1(init_attr->qp_type))
2679                         qp->ibqp.qp_num = 1;
2680                 else
2681                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2682
2683                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2684                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2685                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2686                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2687
2688                 qp->trans_qp.xrcdn = xrcdn;
2689
2690                 break;
2691
2692         case IB_QPT_GSI:
2693                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2694
2695         case IB_QPT_RAW_IPV6:
2696         case IB_QPT_RAW_ETHERTYPE:
2697         case IB_QPT_MAX:
2698         default:
2699                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2700                             init_attr->qp_type);
2701                 /* Don't support raw QPs */
2702                 return ERR_PTR(-EINVAL);
2703         }
2704
2705         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2706                 qp->qp_sub_type = init_attr->qp_type;
2707
2708         return &qp->ibqp;
2709 }
2710
2711 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2712 {
2713         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2714
2715         if (mqp->state == IB_QPS_RTR) {
2716                 int err;
2717
2718                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2719                 if (err) {
2720                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2721                         return err;
2722                 }
2723         }
2724
2725         kfree(mqp->dct.in);
2726         kfree(mqp);
2727         return 0;
2728 }
2729
2730 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2731 {
2732         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2733         struct mlx5_ib_qp *mqp = to_mqp(qp);
2734
2735         if (unlikely(qp->qp_type == IB_QPT_GSI))
2736                 return mlx5_ib_gsi_destroy_qp(qp);
2737
2738         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2739                 return mlx5_ib_destroy_dct(mqp);
2740
2741         destroy_qp_common(dev, mqp);
2742
2743         kfree(mqp);
2744
2745         return 0;
2746 }
2747
2748 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2749                                 const struct ib_qp_attr *attr,
2750                                 int attr_mask, __be32 *hw_access_flags_be)
2751 {
2752         u8 dest_rd_atomic;
2753         u32 access_flags, hw_access_flags = 0;
2754
2755         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2756
2757         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2758                 dest_rd_atomic = attr->max_dest_rd_atomic;
2759         else
2760                 dest_rd_atomic = qp->trans_qp.resp_depth;
2761
2762         if (attr_mask & IB_QP_ACCESS_FLAGS)
2763                 access_flags = attr->qp_access_flags;
2764         else
2765                 access_flags = qp->trans_qp.atomic_rd_en;
2766
2767         if (!dest_rd_atomic)
2768                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2769
2770         if (access_flags & IB_ACCESS_REMOTE_READ)
2771                 hw_access_flags |= MLX5_QP_BIT_RRE;
2772         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2773                 int atomic_mode;
2774
2775                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2776                 if (atomic_mode < 0)
2777                         return -EOPNOTSUPP;
2778
2779                 hw_access_flags |= MLX5_QP_BIT_RAE;
2780                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2781         }
2782
2783         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2784                 hw_access_flags |= MLX5_QP_BIT_RWE;
2785
2786         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2787
2788         return 0;
2789 }
2790
2791 enum {
2792         MLX5_PATH_FLAG_FL       = 1 << 0,
2793         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2794         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2795 };
2796
2797 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2798 {
2799         if (rate == IB_RATE_PORT_CURRENT)
2800                 return 0;
2801
2802         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2803                 return -EINVAL;
2804
2805         while (rate != IB_RATE_PORT_CURRENT &&
2806                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2807                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2808                 --rate;
2809
2810         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2811 }
2812
2813 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2814                                       struct mlx5_ib_sq *sq, u8 sl,
2815                                       struct ib_pd *pd)
2816 {
2817         void *in;
2818         void *tisc;
2819         int inlen;
2820         int err;
2821
2822         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2823         in = kvzalloc(inlen, GFP_KERNEL);
2824         if (!in)
2825                 return -ENOMEM;
2826
2827         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2828         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2829
2830         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2831         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2832
2833         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2834
2835         kvfree(in);
2836
2837         return err;
2838 }
2839
2840 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2841                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2842                                          struct ib_pd *pd)
2843 {
2844         void *in;
2845         void *tisc;
2846         int inlen;
2847         int err;
2848
2849         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2850         in = kvzalloc(inlen, GFP_KERNEL);
2851         if (!in)
2852                 return -ENOMEM;
2853
2854         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2855         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2856
2857         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2858         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2859
2860         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2861
2862         kvfree(in);
2863
2864         return err;
2865 }
2866
2867 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2868                          const struct rdma_ah_attr *ah,
2869                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2870                          u32 path_flags, const struct ib_qp_attr *attr,
2871                          bool alt)
2872 {
2873         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2874         int err;
2875         enum ib_gid_type gid_type;
2876         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2877         u8 sl = rdma_ah_get_sl(ah);
2878
2879         if (attr_mask & IB_QP_PKEY_INDEX)
2880                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2881                                                      attr->pkey_index);
2882
2883         if (ah_flags & IB_AH_GRH) {
2884                 if (grh->sgid_index >=
2885                     dev->mdev->port_caps[port - 1].gid_table_len) {
2886                         pr_err("sgid_index (%u) too large. max is %d\n",
2887                                grh->sgid_index,
2888                                dev->mdev->port_caps[port - 1].gid_table_len);
2889                         return -EINVAL;
2890                 }
2891         }
2892
2893         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2894                 if (!(ah_flags & IB_AH_GRH))
2895                         return -EINVAL;
2896
2897                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2898                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2899                     qp->ibqp.qp_type == IB_QPT_UC ||
2900                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2901                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2902                         path->udp_sport =
2903                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2904                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2905                 gid_type = ah->grh.sgid_attr->gid_type;
2906                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2907                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2908         } else {
2909                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2910                 path->fl_free_ar |=
2911                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2912                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2913                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2914                 if (ah_flags & IB_AH_GRH)
2915                         path->grh_mlid  |= 1 << 7;
2916                 path->dci_cfi_prio_sl = sl & 0xf;
2917         }
2918
2919         if (ah_flags & IB_AH_GRH) {
2920                 path->mgid_index = grh->sgid_index;
2921                 path->hop_limit  = grh->hop_limit;
2922                 path->tclass_flowlabel =
2923                         cpu_to_be32((grh->traffic_class << 20) |
2924                                     (grh->flow_label));
2925                 memcpy(path->rgid, grh->dgid.raw, 16);
2926         }
2927
2928         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2929         if (err < 0)
2930                 return err;
2931         path->static_rate = err;
2932         path->port = port;
2933
2934         if (attr_mask & IB_QP_TIMEOUT)
2935                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2936
2937         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2938                 return modify_raw_packet_eth_prio(dev->mdev,
2939                                                   &qp->raw_packet_qp.sq,
2940                                                   sl & 0xf, qp->ibqp.pd);
2941
2942         return 0;
2943 }
2944
2945 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2946         [MLX5_QP_STATE_INIT] = {
2947                 [MLX5_QP_STATE_INIT] = {
2948                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2949                                           MLX5_QP_OPTPAR_RAE            |
2950                                           MLX5_QP_OPTPAR_RWE            |
2951                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2952                                           MLX5_QP_OPTPAR_PRI_PORT,
2953                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2954                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2955                                           MLX5_QP_OPTPAR_PRI_PORT,
2956                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2957                                           MLX5_QP_OPTPAR_Q_KEY          |
2958                                           MLX5_QP_OPTPAR_PRI_PORT,
2959                 },
2960                 [MLX5_QP_STATE_RTR] = {
2961                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2962                                           MLX5_QP_OPTPAR_RRE            |
2963                                           MLX5_QP_OPTPAR_RAE            |
2964                                           MLX5_QP_OPTPAR_RWE            |
2965                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2966                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2967                                           MLX5_QP_OPTPAR_RWE            |
2968                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2969                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2970                                           MLX5_QP_OPTPAR_Q_KEY,
2971                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2972                                            MLX5_QP_OPTPAR_Q_KEY,
2973                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2974                                           MLX5_QP_OPTPAR_RRE            |
2975                                           MLX5_QP_OPTPAR_RAE            |
2976                                           MLX5_QP_OPTPAR_RWE            |
2977                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2978                 },
2979         },
2980         [MLX5_QP_STATE_RTR] = {
2981                 [MLX5_QP_STATE_RTS] = {
2982                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2983                                           MLX5_QP_OPTPAR_RRE            |
2984                                           MLX5_QP_OPTPAR_RAE            |
2985                                           MLX5_QP_OPTPAR_RWE            |
2986                                           MLX5_QP_OPTPAR_PM_STATE       |
2987                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2988                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2989                                           MLX5_QP_OPTPAR_RWE            |
2990                                           MLX5_QP_OPTPAR_PM_STATE,
2991                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2992                 },
2993         },
2994         [MLX5_QP_STATE_RTS] = {
2995                 [MLX5_QP_STATE_RTS] = {
2996                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2997                                           MLX5_QP_OPTPAR_RAE            |
2998                                           MLX5_QP_OPTPAR_RWE            |
2999                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3000                                           MLX5_QP_OPTPAR_PM_STATE       |
3001                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3002                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3003                                           MLX5_QP_OPTPAR_PM_STATE       |
3004                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3005                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3006                                           MLX5_QP_OPTPAR_SRQN           |
3007                                           MLX5_QP_OPTPAR_CQN_RCV,
3008                 },
3009         },
3010         [MLX5_QP_STATE_SQER] = {
3011                 [MLX5_QP_STATE_RTS] = {
3012                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3013                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3014                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3015                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3016                                            MLX5_QP_OPTPAR_RWE           |
3017                                            MLX5_QP_OPTPAR_RAE           |
3018                                            MLX5_QP_OPTPAR_RRE,
3019                 },
3020         },
3021 };
3022
3023 static int ib_nr_to_mlx5_nr(int ib_mask)
3024 {
3025         switch (ib_mask) {
3026         case IB_QP_STATE:
3027                 return 0;
3028         case IB_QP_CUR_STATE:
3029                 return 0;
3030         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3031                 return 0;
3032         case IB_QP_ACCESS_FLAGS:
3033                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3034                         MLX5_QP_OPTPAR_RAE;
3035         case IB_QP_PKEY_INDEX:
3036                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3037         case IB_QP_PORT:
3038                 return MLX5_QP_OPTPAR_PRI_PORT;
3039         case IB_QP_QKEY:
3040                 return MLX5_QP_OPTPAR_Q_KEY;
3041         case IB_QP_AV:
3042                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3043                         MLX5_QP_OPTPAR_PRI_PORT;
3044         case IB_QP_PATH_MTU:
3045                 return 0;
3046         case IB_QP_TIMEOUT:
3047                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3048         case IB_QP_RETRY_CNT:
3049                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3050         case IB_QP_RNR_RETRY:
3051                 return MLX5_QP_OPTPAR_RNR_RETRY;
3052         case IB_QP_RQ_PSN:
3053                 return 0;
3054         case IB_QP_MAX_QP_RD_ATOMIC:
3055                 return MLX5_QP_OPTPAR_SRA_MAX;
3056         case IB_QP_ALT_PATH:
3057                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3058         case IB_QP_MIN_RNR_TIMER:
3059                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3060         case IB_QP_SQ_PSN:
3061                 return 0;
3062         case IB_QP_MAX_DEST_RD_ATOMIC:
3063                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3064                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3065         case IB_QP_PATH_MIG_STATE:
3066                 return MLX5_QP_OPTPAR_PM_STATE;
3067         case IB_QP_CAP:
3068                 return 0;
3069         case IB_QP_DEST_QPN:
3070                 return 0;
3071         }
3072         return 0;
3073 }
3074
3075 static int ib_mask_to_mlx5_opt(int ib_mask)
3076 {
3077         int result = 0;
3078         int i;
3079
3080         for (i = 0; i < 8 * sizeof(int); i++) {
3081                 if ((1 << i) & ib_mask)
3082                         result |= ib_nr_to_mlx5_nr(1 << i);
3083         }
3084
3085         return result;
3086 }
3087
3088 static int modify_raw_packet_qp_rq(
3089         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3090         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3091 {
3092         void *in;
3093         void *rqc;
3094         int inlen;
3095         int err;
3096
3097         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3098         in = kvzalloc(inlen, GFP_KERNEL);
3099         if (!in)
3100                 return -ENOMEM;
3101
3102         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3103         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3104
3105         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3106         MLX5_SET(rqc, rqc, state, new_state);
3107
3108         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3109                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3110                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3111                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3112                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3113                 } else
3114                         dev_info_once(
3115                                 &dev->ib_dev.dev,
3116                                 "RAW PACKET QP counters are not supported on current FW\n");
3117         }
3118
3119         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3120         if (err)
3121                 goto out;
3122
3123         rq->state = new_state;
3124
3125 out:
3126         kvfree(in);
3127         return err;
3128 }
3129
3130 static int modify_raw_packet_qp_sq(
3131         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3132         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3133 {
3134         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3135         struct mlx5_rate_limit old_rl = ibqp->rl;
3136         struct mlx5_rate_limit new_rl = old_rl;
3137         bool new_rate_added = false;
3138         u16 rl_index = 0;
3139         void *in;
3140         void *sqc;
3141         int inlen;
3142         int err;
3143
3144         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3145         in = kvzalloc(inlen, GFP_KERNEL);
3146         if (!in)
3147                 return -ENOMEM;
3148
3149         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3150         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3151
3152         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3153         MLX5_SET(sqc, sqc, state, new_state);
3154
3155         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3156                 if (new_state != MLX5_SQC_STATE_RDY)
3157                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3158                                 __func__);
3159                 else
3160                         new_rl = raw_qp_param->rl;
3161         }
3162
3163         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3164                 if (new_rl.rate) {
3165                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3166                         if (err) {
3167                                 pr_err("Failed configuring rate limit(err %d): \
3168                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3169                                        err, new_rl.rate, new_rl.max_burst_sz,
3170                                        new_rl.typical_pkt_sz);
3171
3172                                 goto out;
3173                         }
3174                         new_rate_added = true;
3175                 }
3176
3177                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3178                 /* index 0 means no limit */
3179                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3180         }
3181
3182         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3183         if (err) {
3184                 /* Remove new rate from table if failed */
3185                 if (new_rate_added)
3186                         mlx5_rl_remove_rate(dev, &new_rl);
3187                 goto out;
3188         }
3189
3190         /* Only remove the old rate after new rate was set */
3191         if ((old_rl.rate &&
3192              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3193             (new_state != MLX5_SQC_STATE_RDY))
3194                 mlx5_rl_remove_rate(dev, &old_rl);
3195
3196         ibqp->rl = new_rl;
3197         sq->state = new_state;
3198
3199 out:
3200         kvfree(in);
3201         return err;
3202 }
3203
3204 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3205                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3206                                 u8 tx_affinity)
3207 {
3208         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3209         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3210         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3211         int modify_rq = !!qp->rq.wqe_cnt;
3212         int modify_sq = !!qp->sq.wqe_cnt;
3213         int rq_state;
3214         int sq_state;
3215         int err;
3216
3217         switch (raw_qp_param->operation) {
3218         case MLX5_CMD_OP_RST2INIT_QP:
3219                 rq_state = MLX5_RQC_STATE_RDY;
3220                 sq_state = MLX5_SQC_STATE_RDY;
3221                 break;
3222         case MLX5_CMD_OP_2ERR_QP:
3223                 rq_state = MLX5_RQC_STATE_ERR;
3224                 sq_state = MLX5_SQC_STATE_ERR;
3225                 break;
3226         case MLX5_CMD_OP_2RST_QP:
3227                 rq_state = MLX5_RQC_STATE_RST;
3228                 sq_state = MLX5_SQC_STATE_RST;
3229                 break;
3230         case MLX5_CMD_OP_RTR2RTS_QP:
3231         case MLX5_CMD_OP_RTS2RTS_QP:
3232                 if (raw_qp_param->set_mask ==
3233                     MLX5_RAW_QP_RATE_LIMIT) {
3234                         modify_rq = 0;
3235                         sq_state = sq->state;
3236                 } else {
3237                         return raw_qp_param->set_mask ? -EINVAL : 0;
3238                 }
3239                 break;
3240         case MLX5_CMD_OP_INIT2INIT_QP:
3241         case MLX5_CMD_OP_INIT2RTR_QP:
3242                 if (raw_qp_param->set_mask)
3243                         return -EINVAL;
3244                 else
3245                         return 0;
3246         default:
3247                 WARN_ON(1);
3248                 return -EINVAL;
3249         }
3250
3251         if (modify_rq) {
3252                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3253                                                qp->ibqp.pd);
3254                 if (err)
3255                         return err;
3256         }
3257
3258         if (modify_sq) {
3259                 if (tx_affinity) {
3260                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3261                                                             tx_affinity,
3262                                                             qp->ibqp.pd);
3263                         if (err)
3264                                 return err;
3265                 }
3266
3267                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3268                                                raw_qp_param, qp->ibqp.pd);
3269         }
3270
3271         return 0;
3272 }
3273
3274 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3275                                     struct mlx5_ib_pd *pd,
3276                                     struct mlx5_ib_qp_base *qp_base,
3277                                     u8 port_num)
3278 {
3279         struct mlx5_ib_ucontext *ucontext = NULL;
3280         unsigned int tx_port_affinity;
3281
3282         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3283                 ucontext = to_mucontext(pd->ibpd.uobject->context);
3284
3285         if (ucontext) {
3286                 tx_port_affinity = (unsigned int)atomic_add_return(
3287                                            1, &ucontext->tx_port_affinity) %
3288                                            MLX5_MAX_PORTS +
3289                                    1;
3290                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3291                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3292         } else {
3293                 tx_port_affinity =
3294                         (unsigned int)atomic_add_return(
3295                                 1, &dev->roce[port_num].tx_port_affinity) %
3296                                 MLX5_MAX_PORTS +
3297                         1;
3298                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3299                                 tx_port_affinity, qp_base->mqp.qpn);
3300         }
3301
3302         return tx_port_affinity;
3303 }
3304
3305 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3306                                const struct ib_qp_attr *attr, int attr_mask,
3307                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
3308                                const struct mlx5_ib_modify_qp *ucmd)
3309 {
3310         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3311                 [MLX5_QP_STATE_RST] = {
3312                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3313                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3314                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3315                 },
3316                 [MLX5_QP_STATE_INIT]  = {
3317                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3318                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3319                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3320                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3321                 },
3322                 [MLX5_QP_STATE_RTR]   = {
3323                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3324                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3325                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3326                 },
3327                 [MLX5_QP_STATE_RTS]   = {
3328                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3329                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3330                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3331                 },
3332                 [MLX5_QP_STATE_SQD] = {
3333                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3334                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3335                 },
3336                 [MLX5_QP_STATE_SQER] = {
3337                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3338                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3339                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3340                 },
3341                 [MLX5_QP_STATE_ERR] = {
3342                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3343                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3344                 }
3345         };
3346
3347         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3348         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3349         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3350         struct mlx5_ib_cq *send_cq, *recv_cq;
3351         struct mlx5_qp_context *context;
3352         struct mlx5_ib_pd *pd;
3353         struct mlx5_ib_port *mibport = NULL;
3354         enum mlx5_qp_state mlx5_cur, mlx5_new;
3355         enum mlx5_qp_optpar optpar;
3356         int mlx5_st;
3357         int err;
3358         u16 op;
3359         u8 tx_affinity = 0;
3360
3361         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3362                              qp->qp_sub_type : ibqp->qp_type);
3363         if (mlx5_st < 0)
3364                 return -EINVAL;
3365
3366         context = kzalloc(sizeof(*context), GFP_KERNEL);
3367         if (!context)
3368                 return -ENOMEM;
3369
3370         pd = get_pd(qp);
3371         context->flags = cpu_to_be32(mlx5_st << 16);
3372
3373         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3374                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3375         } else {
3376                 switch (attr->path_mig_state) {
3377                 case IB_MIG_MIGRATED:
3378                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3379                         break;
3380                 case IB_MIG_REARM:
3381                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3382                         break;
3383                 case IB_MIG_ARMED:
3384                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3385                         break;
3386                 }
3387         }
3388
3389         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3390                 if ((ibqp->qp_type == IB_QPT_RC) ||
3391                     (ibqp->qp_type == IB_QPT_UD &&
3392                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3393                     (ibqp->qp_type == IB_QPT_UC) ||
3394                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3395                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3396                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3397                         if (dev->lag_active) {
3398                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3399                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3400                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3401                         }
3402                 }
3403         }
3404
3405         if (is_sqp(ibqp->qp_type)) {
3406                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3407         } else if ((ibqp->qp_type == IB_QPT_UD &&
3408                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3409                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3410                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3411         } else if (attr_mask & IB_QP_PATH_MTU) {
3412                 if (attr->path_mtu < IB_MTU_256 ||
3413                     attr->path_mtu > IB_MTU_4096) {
3414                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3415                         err = -EINVAL;
3416                         goto out;
3417                 }
3418                 context->mtu_msgmax = (attr->path_mtu << 5) |
3419                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3420         }
3421
3422         if (attr_mask & IB_QP_DEST_QPN)
3423                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3424
3425         if (attr_mask & IB_QP_PKEY_INDEX)
3426                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3427
3428         /* todo implement counter_index functionality */
3429
3430         if (is_sqp(ibqp->qp_type))
3431                 context->pri_path.port = qp->port;
3432
3433         if (attr_mask & IB_QP_PORT)
3434                 context->pri_path.port = attr->port_num;
3435
3436         if (attr_mask & IB_QP_AV) {
3437                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3438                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3439                                     attr_mask, 0, attr, false);
3440                 if (err)
3441                         goto out;
3442         }
3443
3444         if (attr_mask & IB_QP_TIMEOUT)
3445                 context->pri_path.ackto_lt |= attr->timeout << 3;
3446
3447         if (attr_mask & IB_QP_ALT_PATH) {
3448                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3449                                     &context->alt_path,
3450                                     attr->alt_port_num,
3451                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3452                                     0, attr, true);
3453                 if (err)
3454                         goto out;
3455         }
3456
3457         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3458                 &send_cq, &recv_cq);
3459
3460         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3461         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3462         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3463         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3464
3465         if (attr_mask & IB_QP_RNR_RETRY)
3466                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3467
3468         if (attr_mask & IB_QP_RETRY_CNT)
3469                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3470
3471         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3472                 if (attr->max_rd_atomic)
3473                         context->params1 |=
3474                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3475         }
3476
3477         if (attr_mask & IB_QP_SQ_PSN)
3478                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3479
3480         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3481                 if (attr->max_dest_rd_atomic)
3482                         context->params2 |=
3483                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3484         }
3485
3486         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3487                 __be32 access_flags;
3488
3489                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3490                 if (err)
3491                         goto out;
3492
3493                 context->params2 |= access_flags;
3494         }
3495
3496         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3497                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3498
3499         if (attr_mask & IB_QP_RQ_PSN)
3500                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3501
3502         if (attr_mask & IB_QP_QKEY)
3503                 context->qkey = cpu_to_be32(attr->qkey);
3504
3505         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3506                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3507
3508         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3509                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3510                                qp->port) - 1;
3511
3512                 /* Underlay port should be used - index 0 function per port */
3513                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3514                         port_num = 0;
3515
3516                 mibport = &dev->port[port_num];
3517                 context->qp_counter_set_usr_page |=
3518                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3519         }
3520
3521         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3522                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3523
3524         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3525                 context->deth_sqpn = cpu_to_be32(1);
3526
3527         mlx5_cur = to_mlx5_state(cur_state);
3528         mlx5_new = to_mlx5_state(new_state);
3529
3530         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3531             !optab[mlx5_cur][mlx5_new]) {
3532                 err = -EINVAL;
3533                 goto out;
3534         }
3535
3536         op = optab[mlx5_cur][mlx5_new];
3537         optpar = ib_mask_to_mlx5_opt(attr_mask);
3538         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3539
3540         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3541             qp->flags & MLX5_IB_QP_UNDERLAY) {
3542                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3543
3544                 raw_qp_param.operation = op;
3545                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3546                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3547                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3548                 }
3549
3550                 if (attr_mask & IB_QP_RATE_LIMIT) {
3551                         raw_qp_param.rl.rate = attr->rate_limit;
3552
3553                         if (ucmd->burst_info.max_burst_sz) {
3554                                 if (attr->rate_limit &&
3555                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3556                                         raw_qp_param.rl.max_burst_sz =
3557                                                 ucmd->burst_info.max_burst_sz;
3558                                 } else {
3559                                         err = -EINVAL;
3560                                         goto out;
3561                                 }
3562                         }
3563
3564                         if (ucmd->burst_info.typical_pkt_sz) {
3565                                 if (attr->rate_limit &&
3566                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3567                                         raw_qp_param.rl.typical_pkt_sz =
3568                                                 ucmd->burst_info.typical_pkt_sz;
3569                                 } else {
3570                                         err = -EINVAL;
3571                                         goto out;
3572                                 }
3573                         }
3574
3575                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3576                 }
3577
3578                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3579         } else {
3580                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3581                                           &base->mqp);
3582         }
3583
3584         if (err)
3585                 goto out;
3586
3587         qp->state = new_state;
3588
3589         if (attr_mask & IB_QP_ACCESS_FLAGS)
3590                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3591         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3592                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3593         if (attr_mask & IB_QP_PORT)
3594                 qp->port = attr->port_num;
3595         if (attr_mask & IB_QP_ALT_PATH)
3596                 qp->trans_qp.alt_port = attr->alt_port_num;
3597
3598         /*
3599          * If we moved a kernel QP to RESET, clean up all old CQ
3600          * entries and reinitialize the QP.
3601          */
3602         if (new_state == IB_QPS_RESET &&
3603             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3604                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3605                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3606                 if (send_cq != recv_cq)
3607                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3608
3609                 qp->rq.head = 0;
3610                 qp->rq.tail = 0;
3611                 qp->sq.head = 0;
3612                 qp->sq.tail = 0;
3613                 qp->sq.cur_post = 0;
3614                 if (qp->sq.wqe_cnt)
3615                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3616                 qp->db.db[MLX5_RCV_DBR] = 0;
3617                 qp->db.db[MLX5_SND_DBR] = 0;
3618         }
3619
3620 out:
3621         kfree(context);
3622         return err;
3623 }
3624
3625 static inline bool is_valid_mask(int mask, int req, int opt)
3626 {
3627         if ((mask & req) != req)
3628                 return false;
3629
3630         if (mask & ~(req | opt))
3631                 return false;
3632
3633         return true;
3634 }
3635
3636 /* check valid transition for driver QP types
3637  * for now the only QP type that this function supports is DCI
3638  */
3639 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3640                                 enum ib_qp_attr_mask attr_mask)
3641 {
3642         int req = IB_QP_STATE;
3643         int opt = 0;
3644
3645         if (new_state == IB_QPS_RESET) {
3646                 return is_valid_mask(attr_mask, req, opt);
3647         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3648                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3649                 return is_valid_mask(attr_mask, req, opt);
3650         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3651                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3652                 return is_valid_mask(attr_mask, req, opt);
3653         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3654                 req |= IB_QP_PATH_MTU;
3655                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3656                 return is_valid_mask(attr_mask, req, opt);
3657         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3658                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3659                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3660                 opt = IB_QP_MIN_RNR_TIMER;
3661                 return is_valid_mask(attr_mask, req, opt);
3662         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3663                 opt = IB_QP_MIN_RNR_TIMER;
3664                 return is_valid_mask(attr_mask, req, opt);
3665         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3666                 return is_valid_mask(attr_mask, req, opt);
3667         }
3668         return false;
3669 }
3670
3671 /* mlx5_ib_modify_dct: modify a DCT QP
3672  * valid transitions are:
3673  * RESET to INIT: must set access_flags, pkey_index and port
3674  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3675  *                         mtu, gid_index and hop_limit
3676  * Other transitions and attributes are illegal
3677  */
3678 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3679                               int attr_mask, struct ib_udata *udata)
3680 {
3681         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3682         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3683         enum ib_qp_state cur_state, new_state;
3684         int err = 0;
3685         int required = IB_QP_STATE;
3686         void *dctc;
3687
3688         if (!(attr_mask & IB_QP_STATE))
3689                 return -EINVAL;
3690
3691         cur_state = qp->state;
3692         new_state = attr->qp_state;
3693
3694         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3695         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3696                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3697                 if (!is_valid_mask(attr_mask, required, 0))
3698                         return -EINVAL;
3699
3700                 if (attr->port_num == 0 ||
3701                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3702                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3703                                     attr->port_num, dev->num_ports);
3704                         return -EINVAL;
3705                 }
3706                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3707                         MLX5_SET(dctc, dctc, rre, 1);
3708                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3709                         MLX5_SET(dctc, dctc, rwe, 1);
3710                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3711                         int atomic_mode;
3712
3713                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3714                         if (atomic_mode < 0)
3715                                 return -EOPNOTSUPP;
3716
3717                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3718                         MLX5_SET(dctc, dctc, rae, 1);
3719                 }
3720                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3721                 MLX5_SET(dctc, dctc, port, attr->port_num);
3722                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3723
3724         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3725                 struct mlx5_ib_modify_qp_resp resp = {};
3726                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3727                                    sizeof(resp.dctn);
3728
3729                 if (udata->outlen < min_resp_len)
3730                         return -EINVAL;
3731                 resp.response_length = min_resp_len;
3732
3733                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3734                 if (!is_valid_mask(attr_mask, required, 0))
3735                         return -EINVAL;
3736                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3737                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3738                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3739                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3740                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3741                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3742
3743                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3744                                            MLX5_ST_SZ_BYTES(create_dct_in));
3745                 if (err)
3746                         return err;
3747                 resp.dctn = qp->dct.mdct.mqp.qpn;
3748                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3749                 if (err) {
3750                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3751                         return err;
3752                 }
3753         } else {
3754                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3755                 return -EINVAL;
3756         }
3757         if (err)
3758                 qp->state = IB_QPS_ERR;
3759         else
3760                 qp->state = new_state;
3761         return err;
3762 }
3763
3764 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3765                       int attr_mask, struct ib_udata *udata)
3766 {
3767         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3768         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3769         struct mlx5_ib_modify_qp ucmd = {};
3770         enum ib_qp_type qp_type;
3771         enum ib_qp_state cur_state, new_state;
3772         size_t required_cmd_sz;
3773         int err = -EINVAL;
3774         int port;
3775
3776         if (ibqp->rwq_ind_tbl)
3777                 return -ENOSYS;
3778
3779         if (udata && udata->inlen) {
3780                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3781                         sizeof(ucmd.reserved);
3782                 if (udata->inlen < required_cmd_sz)
3783                         return -EINVAL;
3784
3785                 if (udata->inlen > sizeof(ucmd) &&
3786                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3787                                          udata->inlen - sizeof(ucmd)))
3788                         return -EOPNOTSUPP;
3789
3790                 if (ib_copy_from_udata(&ucmd, udata,
3791                                        min(udata->inlen, sizeof(ucmd))))
3792                         return -EFAULT;
3793
3794                 if (ucmd.comp_mask ||
3795                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3796                     memchr_inv(&ucmd.burst_info.reserved, 0,
3797                                sizeof(ucmd.burst_info.reserved)))
3798                         return -EOPNOTSUPP;
3799         }
3800
3801         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3802                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3803
3804         if (ibqp->qp_type == IB_QPT_DRIVER)
3805                 qp_type = qp->qp_sub_type;
3806         else
3807                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3808                         IB_QPT_GSI : ibqp->qp_type;
3809
3810         if (qp_type == MLX5_IB_QPT_DCT)
3811                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3812
3813         mutex_lock(&qp->mutex);
3814
3815         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3816         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3817
3818         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3819                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3820         }
3821
3822         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3823                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3824                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3825                                     attr_mask);
3826                         goto out;
3827                 }
3828         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3829                    qp_type != MLX5_IB_QPT_DCI &&
3830                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3831                                        attr_mask)) {
3832                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3833                             cur_state, new_state, ibqp->qp_type, attr_mask);
3834                 goto out;
3835         } else if (qp_type == MLX5_IB_QPT_DCI &&
3836                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3837                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3838                             cur_state, new_state, qp_type, attr_mask);
3839                 goto out;
3840         }
3841
3842         if ((attr_mask & IB_QP_PORT) &&
3843             (attr->port_num == 0 ||
3844              attr->port_num > dev->num_ports)) {
3845                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3846                             attr->port_num, dev->num_ports);
3847                 goto out;
3848         }
3849
3850         if (attr_mask & IB_QP_PKEY_INDEX) {
3851                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3852                 if (attr->pkey_index >=
3853                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3854                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3855                                     attr->pkey_index);
3856                         goto out;
3857                 }
3858         }
3859
3860         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3861             attr->max_rd_atomic >
3862             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3863                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3864                             attr->max_rd_atomic);
3865                 goto out;
3866         }
3867
3868         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3869             attr->max_dest_rd_atomic >
3870             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3871                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3872                             attr->max_dest_rd_atomic);
3873                 goto out;
3874         }
3875
3876         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3877                 err = 0;
3878                 goto out;
3879         }
3880
3881         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3882                                   new_state, &ucmd);
3883
3884 out:
3885         mutex_unlock(&qp->mutex);
3886         return err;
3887 }
3888
3889 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3890                                    u32 wqe_sz, void **cur_edge)
3891 {
3892         u32 idx;
3893
3894         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3895         *cur_edge = get_sq_edge(sq, idx);
3896
3897         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3898 }
3899
3900 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3901  * next nearby edge and get new address translation for current WQE position.
3902  * @sq - SQ buffer.
3903  * @seg: Current WQE position (16B aligned).
3904  * @wqe_sz: Total current WQE size [16B].
3905  * @cur_edge: Updated current edge.
3906  */
3907 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3908                                          u32 wqe_sz, void **cur_edge)
3909 {
3910         if (likely(*seg != *cur_edge))
3911                 return;
3912
3913         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3914 }
3915
3916 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3917  * pointers. At the end @seg is aligned to 16B regardless the copied size.
3918  * @sq - SQ buffer.
3919  * @cur_edge: Updated current edge.
3920  * @seg: Current WQE position (16B aligned).
3921  * @wqe_sz: Total current WQE size [16B].
3922  * @src: Pointer to copy from.
3923  * @n: Number of bytes to copy.
3924  */
3925 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3926                                    void **seg, u32 *wqe_sz, const void *src,
3927                                    size_t n)
3928 {
3929         while (likely(n)) {
3930                 size_t leftlen = *cur_edge - *seg;
3931                 size_t copysz = min_t(size_t, leftlen, n);
3932                 size_t stride;
3933
3934                 memcpy(*seg, src, copysz);
3935
3936                 n -= copysz;
3937                 src += copysz;
3938                 stride = !n ? ALIGN(copysz, 16) : copysz;
3939                 *seg += stride;
3940                 *wqe_sz += stride >> 4;
3941                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3942         }
3943 }
3944
3945 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3946 {
3947         struct mlx5_ib_cq *cq;
3948         unsigned cur;
3949
3950         cur = wq->head - wq->tail;
3951         if (likely(cur + nreq < wq->max_post))
3952                 return 0;
3953
3954         cq = to_mcq(ib_cq);
3955         spin_lock(&cq->lock);
3956         cur = wq->head - wq->tail;
3957         spin_unlock(&cq->lock);
3958
3959         return cur + nreq >= wq->max_post;
3960 }
3961
3962 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3963                                           u64 remote_addr, u32 rkey)
3964 {
3965         rseg->raddr    = cpu_to_be64(remote_addr);
3966         rseg->rkey     = cpu_to_be32(rkey);
3967         rseg->reserved = 0;
3968 }
3969
3970 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3971                         void **seg, int *size, void **cur_edge)
3972 {
3973         struct mlx5_wqe_eth_seg *eseg = *seg;
3974
3975         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3976
3977         if (wr->send_flags & IB_SEND_IP_CSUM)
3978                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3979                                  MLX5_ETH_WQE_L4_CSUM;
3980
3981         if (wr->opcode == IB_WR_LSO) {
3982                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3983                 size_t left, copysz;
3984                 void *pdata = ud_wr->header;
3985                 size_t stride;
3986
3987                 left = ud_wr->hlen;
3988                 eseg->mss = cpu_to_be16(ud_wr->mss);
3989                 eseg->inline_hdr.sz = cpu_to_be16(left);
3990
3991                 /* memcpy_send_wqe should get a 16B align address. Hence, we
3992                  * first copy up to the current edge and then, if needed,
3993                  * fall-through to memcpy_send_wqe.
3994                  */
3995                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
3996                                left);
3997                 memcpy(eseg->inline_hdr.start, pdata, copysz);
3998                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
3999                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4000                 *size += stride / 16;
4001                 *seg += stride;
4002
4003                 if (copysz < left) {
4004                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4005                         left -= copysz;
4006                         pdata += copysz;
4007                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4008                                         left);
4009                 }
4010
4011                 return;
4012         }
4013
4014         *seg += sizeof(struct mlx5_wqe_eth_seg);
4015         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4016 }
4017
4018 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4019                              const struct ib_send_wr *wr)
4020 {
4021         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4022         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4023         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4024 }
4025
4026 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4027 {
4028         dseg->byte_count = cpu_to_be32(sg->length);
4029         dseg->lkey       = cpu_to_be32(sg->lkey);
4030         dseg->addr       = cpu_to_be64(sg->addr);
4031 }
4032
4033 static u64 get_xlt_octo(u64 bytes)
4034 {
4035         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4036                MLX5_IB_UMR_OCTOWORD;
4037 }
4038
4039 static __be64 frwr_mkey_mask(void)
4040 {
4041         u64 result;
4042
4043         result = MLX5_MKEY_MASK_LEN             |
4044                 MLX5_MKEY_MASK_PAGE_SIZE        |
4045                 MLX5_MKEY_MASK_START_ADDR       |
4046                 MLX5_MKEY_MASK_EN_RINVAL        |
4047                 MLX5_MKEY_MASK_KEY              |
4048                 MLX5_MKEY_MASK_LR               |
4049                 MLX5_MKEY_MASK_LW               |
4050                 MLX5_MKEY_MASK_RR               |
4051                 MLX5_MKEY_MASK_RW               |
4052                 MLX5_MKEY_MASK_A                |
4053                 MLX5_MKEY_MASK_SMALL_FENCE      |
4054                 MLX5_MKEY_MASK_FREE;
4055
4056         return cpu_to_be64(result);
4057 }
4058
4059 static __be64 sig_mkey_mask(void)
4060 {
4061         u64 result;
4062
4063         result = MLX5_MKEY_MASK_LEN             |
4064                 MLX5_MKEY_MASK_PAGE_SIZE        |
4065                 MLX5_MKEY_MASK_START_ADDR       |
4066                 MLX5_MKEY_MASK_EN_SIGERR        |
4067                 MLX5_MKEY_MASK_EN_RINVAL        |
4068                 MLX5_MKEY_MASK_KEY              |
4069                 MLX5_MKEY_MASK_LR               |
4070                 MLX5_MKEY_MASK_LW               |
4071                 MLX5_MKEY_MASK_RR               |
4072                 MLX5_MKEY_MASK_RW               |
4073                 MLX5_MKEY_MASK_SMALL_FENCE      |
4074                 MLX5_MKEY_MASK_FREE             |
4075                 MLX5_MKEY_MASK_BSF_EN;
4076
4077         return cpu_to_be64(result);
4078 }
4079
4080 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4081                             struct mlx5_ib_mr *mr, bool umr_inline)
4082 {
4083         int size = mr->ndescs * mr->desc_size;
4084
4085         memset(umr, 0, sizeof(*umr));
4086
4087         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4088         if (umr_inline)
4089                 umr->flags |= MLX5_UMR_INLINE;
4090         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4091         umr->mkey_mask = frwr_mkey_mask();
4092 }
4093
4094 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4095 {
4096         memset(umr, 0, sizeof(*umr));
4097         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4098         umr->flags = MLX5_UMR_INLINE;
4099 }
4100
4101 static __be64 get_umr_enable_mr_mask(void)
4102 {
4103         u64 result;
4104
4105         result = MLX5_MKEY_MASK_KEY |
4106                  MLX5_MKEY_MASK_FREE;
4107
4108         return cpu_to_be64(result);
4109 }
4110
4111 static __be64 get_umr_disable_mr_mask(void)
4112 {
4113         u64 result;
4114
4115         result = MLX5_MKEY_MASK_FREE;
4116
4117         return cpu_to_be64(result);
4118 }
4119
4120 static __be64 get_umr_update_translation_mask(void)
4121 {
4122         u64 result;
4123
4124         result = MLX5_MKEY_MASK_LEN |
4125                  MLX5_MKEY_MASK_PAGE_SIZE |
4126                  MLX5_MKEY_MASK_START_ADDR;
4127
4128         return cpu_to_be64(result);
4129 }
4130
4131 static __be64 get_umr_update_access_mask(int atomic)
4132 {
4133         u64 result;
4134
4135         result = MLX5_MKEY_MASK_LR |
4136                  MLX5_MKEY_MASK_LW |
4137                  MLX5_MKEY_MASK_RR |
4138                  MLX5_MKEY_MASK_RW;
4139
4140         if (atomic)
4141                 result |= MLX5_MKEY_MASK_A;
4142
4143         return cpu_to_be64(result);
4144 }
4145
4146 static __be64 get_umr_update_pd_mask(void)
4147 {
4148         u64 result;
4149
4150         result = MLX5_MKEY_MASK_PD;
4151
4152         return cpu_to_be64(result);
4153 }
4154
4155 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4156 {
4157         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4158              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4159             (mask & MLX5_MKEY_MASK_A &&
4160              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4161                 return -EPERM;
4162         return 0;
4163 }
4164
4165 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4166                                struct mlx5_wqe_umr_ctrl_seg *umr,
4167                                const struct ib_send_wr *wr, int atomic)
4168 {
4169         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4170
4171         memset(umr, 0, sizeof(*umr));
4172
4173         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4174                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4175         else
4176                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4177
4178         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4179         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4180                 u64 offset = get_xlt_octo(umrwr->offset);
4181
4182                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4183                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4184                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4185         }
4186         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4187                 umr->mkey_mask |= get_umr_update_translation_mask();
4188         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4189                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4190                 umr->mkey_mask |= get_umr_update_pd_mask();
4191         }
4192         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4193                 umr->mkey_mask |= get_umr_enable_mr_mask();
4194         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4195                 umr->mkey_mask |= get_umr_disable_mr_mask();
4196
4197         if (!wr->num_sge)
4198                 umr->flags |= MLX5_UMR_INLINE;
4199
4200         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4201 }
4202
4203 static u8 get_umr_flags(int acc)
4204 {
4205         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4206                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4207                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4208                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4209                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4210 }
4211
4212 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4213                              struct mlx5_ib_mr *mr,
4214                              u32 key, int access)
4215 {
4216         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4217
4218         memset(seg, 0, sizeof(*seg));
4219
4220         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4221                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4222         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4223                 /* KLMs take twice the size of MTTs */
4224                 ndescs *= 2;
4225
4226         seg->flags = get_umr_flags(access) | mr->access_mode;
4227         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4228         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4229         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4230         seg->len = cpu_to_be64(mr->ibmr.length);
4231         seg->xlt_oct_size = cpu_to_be32(ndescs);
4232 }
4233
4234 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4235 {
4236         memset(seg, 0, sizeof(*seg));
4237         seg->status = MLX5_MKEY_STATUS_FREE;
4238 }
4239
4240 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4241                                  const struct ib_send_wr *wr)
4242 {
4243         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4244
4245         memset(seg, 0, sizeof(*seg));
4246         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4247                 seg->status = MLX5_MKEY_STATUS_FREE;
4248
4249         seg->flags = convert_access(umrwr->access_flags);
4250         if (umrwr->pd)
4251                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4252         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4253             !umrwr->length)
4254                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4255
4256         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4257         seg->len = cpu_to_be64(umrwr->length);
4258         seg->log2_page_size = umrwr->page_shift;
4259         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4260                                        mlx5_mkey_variant(umrwr->mkey));
4261 }
4262
4263 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4264                              struct mlx5_ib_mr *mr,
4265                              struct mlx5_ib_pd *pd)
4266 {
4267         int bcount = mr->desc_size * mr->ndescs;
4268
4269         dseg->addr = cpu_to_be64(mr->desc_map);
4270         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4271         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4272 }
4273
4274 static __be32 send_ieth(const struct ib_send_wr *wr)
4275 {
4276         switch (wr->opcode) {
4277         case IB_WR_SEND_WITH_IMM:
4278         case IB_WR_RDMA_WRITE_WITH_IMM:
4279                 return wr->ex.imm_data;
4280
4281         case IB_WR_SEND_WITH_INV:
4282                 return cpu_to_be32(wr->ex.invalidate_rkey);
4283
4284         default:
4285                 return 0;
4286         }
4287 }
4288
4289 static u8 calc_sig(void *wqe, int size)
4290 {
4291         u8 *p = wqe;
4292         u8 res = 0;
4293         int i;
4294
4295         for (i = 0; i < size; i++)
4296                 res ^= p[i];
4297
4298         return ~res;
4299 }
4300
4301 static u8 wq_sig(void *wqe)
4302 {
4303         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4304 }
4305
4306 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4307                             void **wqe, int *wqe_sz, void **cur_edge)
4308 {
4309         struct mlx5_wqe_inline_seg *seg;
4310         size_t offset;
4311         int inl = 0;
4312         int i;
4313
4314         seg = *wqe;
4315         *wqe += sizeof(*seg);
4316         offset = sizeof(*seg);
4317
4318         for (i = 0; i < wr->num_sge; i++) {
4319                 size_t len  = wr->sg_list[i].length;
4320                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4321
4322                 inl += len;
4323
4324                 if (unlikely(inl > qp->max_inline_data))
4325                         return -ENOMEM;
4326
4327                 while (likely(len)) {
4328                         size_t leftlen;
4329                         size_t copysz;
4330
4331                         handle_post_send_edge(&qp->sq, wqe,
4332                                               *wqe_sz + (offset >> 4),
4333                                               cur_edge);
4334
4335                         leftlen = *cur_edge - *wqe;
4336                         copysz = min_t(size_t, leftlen, len);
4337
4338                         memcpy(*wqe, addr, copysz);
4339                         len -= copysz;
4340                         addr += copysz;
4341                         *wqe += copysz;
4342                         offset += copysz;
4343                 }
4344         }
4345
4346         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4347
4348         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4349
4350         return 0;
4351 }
4352
4353 static u16 prot_field_size(enum ib_signature_type type)
4354 {
4355         switch (type) {
4356         case IB_SIG_TYPE_T10_DIF:
4357                 return MLX5_DIF_SIZE;
4358         default:
4359                 return 0;
4360         }
4361 }
4362
4363 static u8 bs_selector(int block_size)
4364 {
4365         switch (block_size) {
4366         case 512:           return 0x1;
4367         case 520:           return 0x2;
4368         case 4096:          return 0x3;
4369         case 4160:          return 0x4;
4370         case 1073741824:    return 0x5;
4371         default:            return 0;
4372         }
4373 }
4374
4375 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4376                               struct mlx5_bsf_inl *inl)
4377 {
4378         /* Valid inline section and allow BSF refresh */
4379         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4380                                        MLX5_BSF_REFRESH_DIF);
4381         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4382         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4383         /* repeating block */
4384         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4385         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4386                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4387
4388         if (domain->sig.dif.ref_remap)
4389                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4390
4391         if (domain->sig.dif.app_escape) {
4392                 if (domain->sig.dif.ref_escape)
4393                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4394                 else
4395                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4396         }
4397
4398         inl->dif_app_bitmask_check =
4399                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4400 }
4401
4402 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4403                         struct ib_sig_attrs *sig_attrs,
4404                         struct mlx5_bsf *bsf, u32 data_size)
4405 {
4406         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4407         struct mlx5_bsf_basic *basic = &bsf->basic;
4408         struct ib_sig_domain *mem = &sig_attrs->mem;
4409         struct ib_sig_domain *wire = &sig_attrs->wire;
4410
4411         memset(bsf, 0, sizeof(*bsf));
4412
4413         /* Basic + Extended + Inline */
4414         basic->bsf_size_sbs = 1 << 7;
4415         /* Input domain check byte mask */
4416         basic->check_byte_mask = sig_attrs->check_mask;
4417         basic->raw_data_size = cpu_to_be32(data_size);
4418
4419         /* Memory domain */
4420         switch (sig_attrs->mem.sig_type) {
4421         case IB_SIG_TYPE_NONE:
4422                 break;
4423         case IB_SIG_TYPE_T10_DIF:
4424                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4425                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4426                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4427                 break;
4428         default:
4429                 return -EINVAL;
4430         }
4431
4432         /* Wire domain */
4433         switch (sig_attrs->wire.sig_type) {
4434         case IB_SIG_TYPE_NONE:
4435                 break;
4436         case IB_SIG_TYPE_T10_DIF:
4437                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4438                     mem->sig_type == wire->sig_type) {
4439                         /* Same block structure */
4440                         basic->bsf_size_sbs |= 1 << 4;
4441                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4442                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4443                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4444                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4445                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4446                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4447                 } else
4448                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4449
4450                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4451                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4452                 break;
4453         default:
4454                 return -EINVAL;
4455         }
4456
4457         return 0;
4458 }
4459
4460 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4461                                 struct mlx5_ib_qp *qp, void **seg,
4462                                 int *size, void **cur_edge)
4463 {
4464         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4465         struct ib_mr *sig_mr = wr->sig_mr;
4466         struct mlx5_bsf *bsf;
4467         u32 data_len = wr->wr.sg_list->length;
4468         u32 data_key = wr->wr.sg_list->lkey;
4469         u64 data_va = wr->wr.sg_list->addr;
4470         int ret;
4471         int wqe_size;
4472
4473         if (!wr->prot ||
4474             (data_key == wr->prot->lkey &&
4475              data_va == wr->prot->addr &&
4476              data_len == wr->prot->length)) {
4477                 /**
4478                  * Source domain doesn't contain signature information
4479                  * or data and protection are interleaved in memory.
4480                  * So need construct:
4481                  *                  ------------------
4482                  *                 |     data_klm     |
4483                  *                  ------------------
4484                  *                 |       BSF        |
4485                  *                  ------------------
4486                  **/
4487                 struct mlx5_klm *data_klm = *seg;
4488
4489                 data_klm->bcount = cpu_to_be32(data_len);
4490                 data_klm->key = cpu_to_be32(data_key);
4491                 data_klm->va = cpu_to_be64(data_va);
4492                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4493         } else {
4494                 /**
4495                  * Source domain contains signature information
4496                  * So need construct a strided block format:
4497                  *               ---------------------------
4498                  *              |     stride_block_ctrl     |
4499                  *               ---------------------------
4500                  *              |          data_klm         |
4501                  *               ---------------------------
4502                  *              |          prot_klm         |
4503                  *               ---------------------------
4504                  *              |             BSF           |
4505                  *               ---------------------------
4506                  **/
4507                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4508                 struct mlx5_stride_block_entry *data_sentry;
4509                 struct mlx5_stride_block_entry *prot_sentry;
4510                 u32 prot_key = wr->prot->lkey;
4511                 u64 prot_va = wr->prot->addr;
4512                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4513                 int prot_size;
4514
4515                 sblock_ctrl = *seg;
4516                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4517                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4518
4519                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4520                 if (!prot_size) {
4521                         pr_err("Bad block size given: %u\n", block_size);
4522                         return -EINVAL;
4523                 }
4524                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4525                                                             prot_size);
4526                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4527                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4528                 sblock_ctrl->num_entries = cpu_to_be16(2);
4529
4530                 data_sentry->bcount = cpu_to_be16(block_size);
4531                 data_sentry->key = cpu_to_be32(data_key);
4532                 data_sentry->va = cpu_to_be64(data_va);
4533                 data_sentry->stride = cpu_to_be16(block_size);
4534
4535                 prot_sentry->bcount = cpu_to_be16(prot_size);
4536                 prot_sentry->key = cpu_to_be32(prot_key);
4537                 prot_sentry->va = cpu_to_be64(prot_va);
4538                 prot_sentry->stride = cpu_to_be16(prot_size);
4539
4540                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4541                                  sizeof(*prot_sentry), 64);
4542         }
4543
4544         *seg += wqe_size;
4545         *size += wqe_size / 16;
4546         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4547
4548         bsf = *seg;
4549         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4550         if (ret)
4551                 return -EINVAL;
4552
4553         *seg += sizeof(*bsf);
4554         *size += sizeof(*bsf) / 16;
4555         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4556
4557         return 0;
4558 }
4559
4560 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4561                                  const struct ib_sig_handover_wr *wr, u32 size,
4562                                  u32 length, u32 pdn)
4563 {
4564         struct ib_mr *sig_mr = wr->sig_mr;
4565         u32 sig_key = sig_mr->rkey;
4566         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4567
4568         memset(seg, 0, sizeof(*seg));
4569
4570         seg->flags = get_umr_flags(wr->access_flags) |
4571                                    MLX5_MKC_ACCESS_MODE_KLMS;
4572         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4573         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4574                                     MLX5_MKEY_BSF_EN | pdn);
4575         seg->len = cpu_to_be64(length);
4576         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4577         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4578 }
4579
4580 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4581                                 u32 size)
4582 {
4583         memset(umr, 0, sizeof(*umr));
4584
4585         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4586         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4587         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4588         umr->mkey_mask = sig_mkey_mask();
4589 }
4590
4591
4592 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4593                           struct mlx5_ib_qp *qp, void **seg, int *size,
4594                           void **cur_edge)
4595 {
4596         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4597         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4598         u32 pdn = get_pd(qp)->pdn;
4599         u32 xlt_size;
4600         int region_len, ret;
4601
4602         if (unlikely(wr->wr.num_sge != 1) ||
4603             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4604             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4605             unlikely(!sig_mr->sig->sig_status_checked))
4606                 return -EINVAL;
4607
4608         /* length of the protected region, data + protection */
4609         region_len = wr->wr.sg_list->length;
4610         if (wr->prot &&
4611             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4612              wr->prot->addr != wr->wr.sg_list->addr  ||
4613              wr->prot->length != wr->wr.sg_list->length))
4614                 region_len += wr->prot->length;
4615
4616         /**
4617          * KLM octoword size - if protection was provided
4618          * then we use strided block format (3 octowords),
4619          * else we use single KLM (1 octoword)
4620          **/
4621         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4622
4623         set_sig_umr_segment(*seg, xlt_size);
4624         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4625         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4626         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4627
4628         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4629         *seg += sizeof(struct mlx5_mkey_seg);
4630         *size += sizeof(struct mlx5_mkey_seg) / 16;
4631         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4632
4633         ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
4634         if (ret)
4635                 return ret;
4636
4637         sig_mr->sig->sig_status_checked = false;
4638         return 0;
4639 }
4640
4641 static int set_psv_wr(struct ib_sig_domain *domain,
4642                       u32 psv_idx, void **seg, int *size)
4643 {
4644         struct mlx5_seg_set_psv *psv_seg = *seg;
4645
4646         memset(psv_seg, 0, sizeof(*psv_seg));
4647         psv_seg->psv_num = cpu_to_be32(psv_idx);
4648         switch (domain->sig_type) {
4649         case IB_SIG_TYPE_NONE:
4650                 break;
4651         case IB_SIG_TYPE_T10_DIF:
4652                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4653                                                      domain->sig.dif.app_tag);
4654                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4655                 break;
4656         default:
4657                 pr_err("Bad signature type (%d) is given.\n",
4658                        domain->sig_type);
4659                 return -EINVAL;
4660         }
4661
4662         *seg += sizeof(*psv_seg);
4663         *size += sizeof(*psv_seg) / 16;
4664
4665         return 0;
4666 }
4667
4668 static int set_reg_wr(struct mlx5_ib_qp *qp,
4669                       const struct ib_reg_wr *wr,
4670                       void **seg, int *size, void **cur_edge)
4671 {
4672         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4673         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4674         size_t mr_list_size = mr->ndescs * mr->desc_size;
4675         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4676
4677         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4678                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4679                              "Invalid IB_SEND_INLINE send flag\n");
4680                 return -EINVAL;
4681         }
4682
4683         set_reg_umr_seg(*seg, mr, umr_inline);
4684         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4685         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4686         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4687
4688         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4689         *seg += sizeof(struct mlx5_mkey_seg);
4690         *size += sizeof(struct mlx5_mkey_seg) / 16;
4691         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4692
4693         if (umr_inline) {
4694                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4695                                 mr_list_size);
4696                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4697         } else {
4698                 set_reg_data_seg(*seg, mr, pd);
4699                 *seg += sizeof(struct mlx5_wqe_data_seg);
4700                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4701         }
4702         return 0;
4703 }
4704
4705 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4706                         void **cur_edge)
4707 {
4708         set_linv_umr_seg(*seg);
4709         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4710         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4711         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4712         set_linv_mkey_seg(*seg);
4713         *seg += sizeof(struct mlx5_mkey_seg);
4714         *size += sizeof(struct mlx5_mkey_seg) / 16;
4715         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4716 }
4717
4718 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4719 {
4720         __be32 *p = NULL;
4721         u32 tidx = idx;
4722         int i, j;
4723
4724         pr_debug("dump WQE index %u:\n", idx);
4725         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4726                 if ((i & 0xf) == 0) {
4727                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4728                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx);
4729                         pr_debug("WQBB at %p:\n", (void *)p);
4730                         j = 0;
4731                 }
4732                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4733                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4734                          be32_to_cpu(p[j + 3]));
4735         }
4736 }
4737
4738 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4739                        struct mlx5_wqe_ctrl_seg **ctrl,
4740                        const struct ib_send_wr *wr, unsigned int *idx,
4741                        int *size, void **cur_edge, int nreq,
4742                        bool send_signaled, bool solicited)
4743 {
4744         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4745                 return -ENOMEM;
4746
4747         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4748         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4749         *ctrl = *seg;
4750         *(uint32_t *)(*seg + 8) = 0;
4751         (*ctrl)->imm = send_ieth(wr);
4752         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4753                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4754                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4755
4756         *seg += sizeof(**ctrl);
4757         *size = sizeof(**ctrl) / 16;
4758         *cur_edge = qp->sq.cur_edge;
4759
4760         return 0;
4761 }
4762
4763 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4764                      struct mlx5_wqe_ctrl_seg **ctrl,
4765                      const struct ib_send_wr *wr, unsigned *idx,
4766                      int *size, void **cur_edge, int nreq)
4767 {
4768         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4769                            wr->send_flags & IB_SEND_SIGNALED,
4770                            wr->send_flags & IB_SEND_SOLICITED);
4771 }
4772
4773 static void finish_wqe(struct mlx5_ib_qp *qp,
4774                        struct mlx5_wqe_ctrl_seg *ctrl,
4775                        void *seg, u8 size, void *cur_edge,
4776                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4777                        u32 mlx5_opcode)
4778 {
4779         u8 opmod = 0;
4780
4781         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4782                                              mlx5_opcode | ((u32)opmod << 24));
4783         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4784         ctrl->fm_ce_se |= fence;
4785         if (unlikely(qp->wq_sig))
4786                 ctrl->signature = wq_sig(ctrl);
4787
4788         qp->sq.wrid[idx] = wr_id;
4789         qp->sq.w_list[idx].opcode = mlx5_opcode;
4790         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4791         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4792         qp->sq.w_list[idx].next = qp->sq.cur_post;
4793
4794         /* We save the edge which was possibly updated during the WQE
4795          * construction, into SQ's cache.
4796          */
4797         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4798         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4799                           get_sq_edge(&qp->sq, qp->sq.cur_post &
4800                                       (qp->sq.wqe_cnt - 1)) :
4801                           cur_edge;
4802 }
4803
4804 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4805                               const struct ib_send_wr **bad_wr, bool drain)
4806 {
4807         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4808         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4809         struct mlx5_core_dev *mdev = dev->mdev;
4810         struct mlx5_ib_qp *qp;
4811         struct mlx5_ib_mr *mr;
4812         struct mlx5_wqe_xrc_seg *xrc;
4813         struct mlx5_bf *bf;
4814         void *cur_edge;
4815         int uninitialized_var(size);
4816         unsigned long flags;
4817         unsigned idx;
4818         int err = 0;
4819         int num_sge;
4820         void *seg;
4821         int nreq;
4822         int i;
4823         u8 next_fence = 0;
4824         u8 fence;
4825
4826         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4827                      !drain)) {
4828                 *bad_wr = wr;
4829                 return -EIO;
4830         }
4831
4832         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4833                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4834
4835         qp = to_mqp(ibqp);
4836         bf = &qp->bf;
4837
4838         spin_lock_irqsave(&qp->sq.lock, flags);
4839
4840         for (nreq = 0; wr; nreq++, wr = wr->next) {
4841                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4842                         mlx5_ib_warn(dev, "\n");
4843                         err = -EINVAL;
4844                         *bad_wr = wr;
4845                         goto out;
4846                 }
4847
4848                 num_sge = wr->num_sge;
4849                 if (unlikely(num_sge > qp->sq.max_gs)) {
4850                         mlx5_ib_warn(dev, "\n");
4851                         err = -EINVAL;
4852                         *bad_wr = wr;
4853                         goto out;
4854                 }
4855
4856                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4857                                 nreq);
4858                 if (err) {
4859                         mlx5_ib_warn(dev, "\n");
4860                         err = -ENOMEM;
4861                         *bad_wr = wr;
4862                         goto out;
4863                 }
4864
4865                 if (wr->opcode == IB_WR_REG_MR) {
4866                         fence = dev->umr_fence;
4867                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4868                 } else  {
4869                         if (wr->send_flags & IB_SEND_FENCE) {
4870                                 if (qp->next_fence)
4871                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4872                                 else
4873                                         fence = MLX5_FENCE_MODE_FENCE;
4874                         } else {
4875                                 fence = qp->next_fence;
4876                         }
4877                 }
4878
4879                 switch (ibqp->qp_type) {
4880                 case IB_QPT_XRC_INI:
4881                         xrc = seg;
4882                         seg += sizeof(*xrc);
4883                         size += sizeof(*xrc) / 16;
4884                         /* fall through */
4885                 case IB_QPT_RC:
4886                         switch (wr->opcode) {
4887                         case IB_WR_RDMA_READ:
4888                         case IB_WR_RDMA_WRITE:
4889                         case IB_WR_RDMA_WRITE_WITH_IMM:
4890                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4891                                               rdma_wr(wr)->rkey);
4892                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4893                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4894                                 break;
4895
4896                         case IB_WR_ATOMIC_CMP_AND_SWP:
4897                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4898                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4899                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4900                                 err = -ENOSYS;
4901                                 *bad_wr = wr;
4902                                 goto out;
4903
4904                         case IB_WR_LOCAL_INV:
4905                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4906                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4907                                 set_linv_wr(qp, &seg, &size, &cur_edge);
4908                                 num_sge = 0;
4909                                 break;
4910
4911                         case IB_WR_REG_MR:
4912                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4913                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4914                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4915                                                  &cur_edge);
4916                                 if (err) {
4917                                         *bad_wr = wr;
4918                                         goto out;
4919                                 }
4920                                 num_sge = 0;
4921                                 break;
4922
4923                         case IB_WR_REG_SIG_MR:
4924                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4925                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4926
4927                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4928                                 err = set_sig_umr_wr(wr, qp, &seg, &size,
4929                                                      &cur_edge);
4930                                 if (err) {
4931                                         mlx5_ib_warn(dev, "\n");
4932                                         *bad_wr = wr;
4933                                         goto out;
4934                                 }
4935
4936                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4937                                            wr->wr_id, nreq, fence,
4938                                            MLX5_OPCODE_UMR);
4939                                 /*
4940                                  * SET_PSV WQEs are not signaled and solicited
4941                                  * on error
4942                                  */
4943                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4944                                                   &size, &cur_edge, nreq, false,
4945                                                   true);
4946                                 if (err) {
4947                                         mlx5_ib_warn(dev, "\n");
4948                                         err = -ENOMEM;
4949                                         *bad_wr = wr;
4950                                         goto out;
4951                                 }
4952
4953                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4954                                                  mr->sig->psv_memory.psv_idx, &seg,
4955                                                  &size);
4956                                 if (err) {
4957                                         mlx5_ib_warn(dev, "\n");
4958                                         *bad_wr = wr;
4959                                         goto out;
4960                                 }
4961
4962                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4963                                            wr->wr_id, nreq, fence,
4964                                            MLX5_OPCODE_SET_PSV);
4965                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4966                                                   &size, &cur_edge, nreq, false,
4967                                                   true);
4968                                 if (err) {
4969                                         mlx5_ib_warn(dev, "\n");
4970                                         err = -ENOMEM;
4971                                         *bad_wr = wr;
4972                                         goto out;
4973                                 }
4974
4975                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4976                                                  mr->sig->psv_wire.psv_idx, &seg,
4977                                                  &size);
4978                                 if (err) {
4979                                         mlx5_ib_warn(dev, "\n");
4980                                         *bad_wr = wr;
4981                                         goto out;
4982                                 }
4983
4984                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4985                                            wr->wr_id, nreq, fence,
4986                                            MLX5_OPCODE_SET_PSV);
4987                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4988                                 num_sge = 0;
4989                                 goto skip_psv;
4990
4991                         default:
4992                                 break;
4993                         }
4994                         break;
4995
4996                 case IB_QPT_UC:
4997                         switch (wr->opcode) {
4998                         case IB_WR_RDMA_WRITE:
4999                         case IB_WR_RDMA_WRITE_WITH_IMM:
5000                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5001                                               rdma_wr(wr)->rkey);
5002                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5003                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5004                                 break;
5005
5006                         default:
5007                                 break;
5008                         }
5009                         break;
5010
5011                 case IB_QPT_SMI:
5012                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5013                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5014                                 err = -EPERM;
5015                                 *bad_wr = wr;
5016                                 goto out;
5017                         }
5018                         /* fall through */
5019                 case MLX5_IB_QPT_HW_GSI:
5020                         set_datagram_seg(seg, wr);
5021                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5022                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5023                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5024
5025                         break;
5026                 case IB_QPT_UD:
5027                         set_datagram_seg(seg, wr);
5028                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5029                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5030                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5031
5032                         /* handle qp that supports ud offload */
5033                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5034                                 struct mlx5_wqe_eth_pad *pad;
5035
5036                                 pad = seg;
5037                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5038                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5039                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5040                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5041                                 handle_post_send_edge(&qp->sq, &seg, size,
5042                                                       &cur_edge);
5043                         }
5044                         break;
5045                 case MLX5_IB_QPT_REG_UMR:
5046                         if (wr->opcode != MLX5_IB_WR_UMR) {
5047                                 err = -EINVAL;
5048                                 mlx5_ib_warn(dev, "bad opcode\n");
5049                                 goto out;
5050                         }
5051                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5052                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5053                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5054                         if (unlikely(err))
5055                                 goto out;
5056                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5057                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5058                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5059                         set_reg_mkey_segment(seg, wr);
5060                         seg += sizeof(struct mlx5_mkey_seg);
5061                         size += sizeof(struct mlx5_mkey_seg) / 16;
5062                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5063                         break;
5064
5065                 default:
5066                         break;
5067                 }
5068
5069                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5070                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5071                         if (unlikely(err)) {
5072                                 mlx5_ib_warn(dev, "\n");
5073                                 *bad_wr = wr;
5074                                 goto out;
5075                         }
5076                 } else {
5077                         for (i = 0; i < num_sge; i++) {
5078                                 handle_post_send_edge(&qp->sq, &seg, size,
5079                                                       &cur_edge);
5080                                 if (likely(wr->sg_list[i].length)) {
5081                                         set_data_ptr_seg
5082                                         ((struct mlx5_wqe_data_seg *)seg,
5083                                          wr->sg_list + i);
5084                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5085                                         seg += sizeof(struct mlx5_wqe_data_seg);
5086                                 }
5087                         }
5088                 }
5089
5090                 qp->next_fence = next_fence;
5091                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5092                            fence, mlx5_ib_opcode[wr->opcode]);
5093 skip_psv:
5094                 if (0)
5095                         dump_wqe(qp, idx, size);
5096         }
5097
5098 out:
5099         if (likely(nreq)) {
5100                 qp->sq.head += nreq;
5101
5102                 /* Make sure that descriptors are written before
5103                  * updating doorbell record and ringing the doorbell
5104                  */
5105                 wmb();
5106
5107                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5108
5109                 /* Make sure doorbell record is visible to the HCA before
5110                  * we hit doorbell */
5111                 wmb();
5112
5113                 /* currently we support only regular doorbells */
5114                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
5115                 /* Make sure doorbells don't leak out of SQ spinlock
5116                  * and reach the HCA out of order.
5117                  */
5118                 mmiowb();
5119                 bf->offset ^= bf->buf_size;
5120         }
5121
5122         spin_unlock_irqrestore(&qp->sq.lock, flags);
5123
5124         return err;
5125 }
5126
5127 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5128                       const struct ib_send_wr **bad_wr)
5129 {
5130         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5131 }
5132
5133 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5134 {
5135         sig->signature = calc_sig(sig, size);
5136 }
5137
5138 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5139                       const struct ib_recv_wr **bad_wr, bool drain)
5140 {
5141         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5142         struct mlx5_wqe_data_seg *scat;
5143         struct mlx5_rwqe_sig *sig;
5144         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5145         struct mlx5_core_dev *mdev = dev->mdev;
5146         unsigned long flags;
5147         int err = 0;
5148         int nreq;
5149         int ind;
5150         int i;
5151
5152         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5153                      !drain)) {
5154                 *bad_wr = wr;
5155                 return -EIO;
5156         }
5157
5158         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5159                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5160
5161         spin_lock_irqsave(&qp->rq.lock, flags);
5162
5163         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5164
5165         for (nreq = 0; wr; nreq++, wr = wr->next) {
5166                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5167                         err = -ENOMEM;
5168                         *bad_wr = wr;
5169                         goto out;
5170                 }
5171
5172                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5173                         err = -EINVAL;
5174                         *bad_wr = wr;
5175                         goto out;
5176                 }
5177
5178                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5179                 if (qp->wq_sig)
5180                         scat++;
5181
5182                 for (i = 0; i < wr->num_sge; i++)
5183                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5184
5185                 if (i < qp->rq.max_gs) {
5186                         scat[i].byte_count = 0;
5187                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5188                         scat[i].addr       = 0;
5189                 }
5190
5191                 if (qp->wq_sig) {
5192                         sig = (struct mlx5_rwqe_sig *)scat;
5193                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5194                 }
5195
5196                 qp->rq.wrid[ind] = wr->wr_id;
5197
5198                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5199         }
5200
5201 out:
5202         if (likely(nreq)) {
5203                 qp->rq.head += nreq;
5204
5205                 /* Make sure that descriptors are written before
5206                  * doorbell record.
5207                  */
5208                 wmb();
5209
5210                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5211         }
5212
5213         spin_unlock_irqrestore(&qp->rq.lock, flags);
5214
5215         return err;
5216 }
5217
5218 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5219                       const struct ib_recv_wr **bad_wr)
5220 {
5221         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5222 }
5223
5224 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5225 {
5226         switch (mlx5_state) {
5227         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5228         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5229         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5230         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5231         case MLX5_QP_STATE_SQ_DRAINING:
5232         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5233         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5234         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5235         default:                     return -1;
5236         }
5237 }
5238
5239 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5240 {
5241         switch (mlx5_mig_state) {
5242         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5243         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5244         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5245         default: return -1;
5246         }
5247 }
5248
5249 static int to_ib_qp_access_flags(int mlx5_flags)
5250 {
5251         int ib_flags = 0;
5252
5253         if (mlx5_flags & MLX5_QP_BIT_RRE)
5254                 ib_flags |= IB_ACCESS_REMOTE_READ;
5255         if (mlx5_flags & MLX5_QP_BIT_RWE)
5256                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5257         if (mlx5_flags & MLX5_QP_BIT_RAE)
5258                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5259
5260         return ib_flags;
5261 }
5262
5263 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5264                             struct rdma_ah_attr *ah_attr,
5265                             struct mlx5_qp_path *path)
5266 {
5267
5268         memset(ah_attr, 0, sizeof(*ah_attr));
5269
5270         if (!path->port || path->port > ibdev->num_ports)
5271                 return;
5272
5273         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5274
5275         rdma_ah_set_port_num(ah_attr, path->port);
5276         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5277
5278         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5279         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5280         rdma_ah_set_static_rate(ah_attr,
5281                                 path->static_rate ? path->static_rate - 5 : 0);
5282         if (path->grh_mlid & (1 << 7)) {
5283                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5284
5285                 rdma_ah_set_grh(ah_attr, NULL,
5286                                 tc_fl & 0xfffff,
5287                                 path->mgid_index,
5288                                 path->hop_limit,
5289                                 (tc_fl >> 20) & 0xff);
5290                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5291         }
5292 }
5293
5294 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5295                                         struct mlx5_ib_sq *sq,
5296                                         u8 *sq_state)
5297 {
5298         int err;
5299
5300         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5301         if (err)
5302                 goto out;
5303         sq->state = *sq_state;
5304
5305 out:
5306         return err;
5307 }
5308
5309 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5310                                         struct mlx5_ib_rq *rq,
5311                                         u8 *rq_state)
5312 {
5313         void *out;
5314         void *rqc;
5315         int inlen;
5316         int err;
5317
5318         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5319         out = kvzalloc(inlen, GFP_KERNEL);
5320         if (!out)
5321                 return -ENOMEM;
5322
5323         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5324         if (err)
5325                 goto out;
5326
5327         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5328         *rq_state = MLX5_GET(rqc, rqc, state);
5329         rq->state = *rq_state;
5330
5331 out:
5332         kvfree(out);
5333         return err;
5334 }
5335
5336 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5337                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5338 {
5339         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5340                 [MLX5_RQC_STATE_RST] = {
5341                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5342                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5343                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5344                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5345                 },
5346                 [MLX5_RQC_STATE_RDY] = {
5347                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5348                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5349                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5350                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5351                 },
5352                 [MLX5_RQC_STATE_ERR] = {
5353                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5354                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5355                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5356                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5357                 },
5358                 [MLX5_RQ_STATE_NA] = {
5359                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5360                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5361                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5362                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5363                 },
5364         };
5365
5366         *qp_state = sqrq_trans[rq_state][sq_state];
5367
5368         if (*qp_state == MLX5_QP_STATE_BAD) {
5369                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5370                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5371                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5372                 return -EINVAL;
5373         }
5374
5375         if (*qp_state == MLX5_QP_STATE)
5376                 *qp_state = qp->state;
5377
5378         return 0;
5379 }
5380
5381 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5382                                      struct mlx5_ib_qp *qp,
5383                                      u8 *raw_packet_qp_state)
5384 {
5385         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5386         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5387         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5388         int err;
5389         u8 sq_state = MLX5_SQ_STATE_NA;
5390         u8 rq_state = MLX5_RQ_STATE_NA;
5391
5392         if (qp->sq.wqe_cnt) {
5393                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5394                 if (err)
5395                         return err;
5396         }
5397
5398         if (qp->rq.wqe_cnt) {
5399                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5400                 if (err)
5401                         return err;
5402         }
5403
5404         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5405                                       raw_packet_qp_state);
5406 }
5407
5408 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5409                          struct ib_qp_attr *qp_attr)
5410 {
5411         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5412         struct mlx5_qp_context *context;
5413         int mlx5_state;
5414         u32 *outb;
5415         int err = 0;
5416
5417         outb = kzalloc(outlen, GFP_KERNEL);
5418         if (!outb)
5419                 return -ENOMEM;
5420
5421         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5422                                  outlen);
5423         if (err)
5424                 goto out;
5425
5426         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5427         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5428
5429         mlx5_state = be32_to_cpu(context->flags) >> 28;
5430
5431         qp->state                    = to_ib_qp_state(mlx5_state);
5432         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5433         qp_attr->path_mig_state      =
5434                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5435         qp_attr->qkey                = be32_to_cpu(context->qkey);
5436         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5437         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5438         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5439         qp_attr->qp_access_flags     =
5440                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5441
5442         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5443                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5444                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5445                 qp_attr->alt_pkey_index =
5446                         be16_to_cpu(context->alt_path.pkey_index);
5447                 qp_attr->alt_port_num   =
5448                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5449         }
5450
5451         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5452         qp_attr->port_num = context->pri_path.port;
5453
5454         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5455         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5456
5457         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5458
5459         qp_attr->max_dest_rd_atomic =
5460                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5461         qp_attr->min_rnr_timer      =
5462                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5463         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5464         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5465         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5466         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5467
5468 out:
5469         kfree(outb);
5470         return err;
5471 }
5472
5473 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5474                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5475                                 struct ib_qp_init_attr *qp_init_attr)
5476 {
5477         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5478         u32 *out;
5479         u32 access_flags = 0;
5480         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5481         void *dctc;
5482         int err;
5483         int supported_mask = IB_QP_STATE |
5484                              IB_QP_ACCESS_FLAGS |
5485                              IB_QP_PORT |
5486                              IB_QP_MIN_RNR_TIMER |
5487                              IB_QP_AV |
5488                              IB_QP_PATH_MTU |
5489                              IB_QP_PKEY_INDEX;
5490
5491         if (qp_attr_mask & ~supported_mask)
5492                 return -EINVAL;
5493         if (mqp->state != IB_QPS_RTR)
5494                 return -EINVAL;
5495
5496         out = kzalloc(outlen, GFP_KERNEL);
5497         if (!out)
5498                 return -ENOMEM;
5499
5500         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5501         if (err)
5502                 goto out;
5503
5504         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5505
5506         if (qp_attr_mask & IB_QP_STATE)
5507                 qp_attr->qp_state = IB_QPS_RTR;
5508
5509         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5510                 if (MLX5_GET(dctc, dctc, rre))
5511                         access_flags |= IB_ACCESS_REMOTE_READ;
5512                 if (MLX5_GET(dctc, dctc, rwe))
5513                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5514                 if (MLX5_GET(dctc, dctc, rae))
5515                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5516                 qp_attr->qp_access_flags = access_flags;
5517         }
5518
5519         if (qp_attr_mask & IB_QP_PORT)
5520                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5521         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5522                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5523         if (qp_attr_mask & IB_QP_AV) {
5524                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5525                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5526                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5527                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5528         }
5529         if (qp_attr_mask & IB_QP_PATH_MTU)
5530                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5531         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5532                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5533 out:
5534         kfree(out);
5535         return err;
5536 }
5537
5538 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5539                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5540 {
5541         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5542         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5543         int err = 0;
5544         u8 raw_packet_qp_state;
5545
5546         if (ibqp->rwq_ind_tbl)
5547                 return -ENOSYS;
5548
5549         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5550                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5551                                             qp_init_attr);
5552
5553         /* Not all of output fields are applicable, make sure to zero them */
5554         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5555         memset(qp_attr, 0, sizeof(*qp_attr));
5556
5557         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5558                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5559                                             qp_attr_mask, qp_init_attr);
5560
5561         mutex_lock(&qp->mutex);
5562
5563         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5564             qp->flags & MLX5_IB_QP_UNDERLAY) {
5565                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5566                 if (err)
5567                         goto out;
5568                 qp->state = raw_packet_qp_state;
5569                 qp_attr->port_num = 1;
5570         } else {
5571                 err = query_qp_attr(dev, qp, qp_attr);
5572                 if (err)
5573                         goto out;
5574         }
5575
5576         qp_attr->qp_state            = qp->state;
5577         qp_attr->cur_qp_state        = qp_attr->qp_state;
5578         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5579         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5580
5581         if (!ibqp->uobject) {
5582                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5583                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5584                 qp_init_attr->qp_context = ibqp->qp_context;
5585         } else {
5586                 qp_attr->cap.max_send_wr  = 0;
5587                 qp_attr->cap.max_send_sge = 0;
5588         }
5589
5590         qp_init_attr->qp_type = ibqp->qp_type;
5591         qp_init_attr->recv_cq = ibqp->recv_cq;
5592         qp_init_attr->send_cq = ibqp->send_cq;
5593         qp_init_attr->srq = ibqp->srq;
5594         qp_attr->cap.max_inline_data = qp->max_inline_data;
5595
5596         qp_init_attr->cap            = qp_attr->cap;
5597
5598         qp_init_attr->create_flags = 0;
5599         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5600                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5601
5602         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5603                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5604         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5605                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5606         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5607                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5608         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5609                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5610
5611         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5612                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5613
5614 out:
5615         mutex_unlock(&qp->mutex);
5616         return err;
5617 }
5618
5619 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5620                                           struct ib_ucontext *context,
5621                                           struct ib_udata *udata)
5622 {
5623         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5624         struct mlx5_ib_xrcd *xrcd;
5625         int err;
5626
5627         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5628                 return ERR_PTR(-ENOSYS);
5629
5630         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5631         if (!xrcd)
5632                 return ERR_PTR(-ENOMEM);
5633
5634         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5635         if (err) {
5636                 kfree(xrcd);
5637                 return ERR_PTR(-ENOMEM);
5638         }
5639
5640         return &xrcd->ibxrcd;
5641 }
5642
5643 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5644 {
5645         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5646         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5647         int err;
5648
5649         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5650         if (err)
5651                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5652
5653         kfree(xrcd);
5654         return 0;
5655 }
5656
5657 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5658 {
5659         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5660         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5661         struct ib_event event;
5662
5663         if (rwq->ibwq.event_handler) {
5664                 event.device     = rwq->ibwq.device;
5665                 event.element.wq = &rwq->ibwq;
5666                 switch (type) {
5667                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5668                         event.event = IB_EVENT_WQ_FATAL;
5669                         break;
5670                 default:
5671                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5672                         return;
5673                 }
5674
5675                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5676         }
5677 }
5678
5679 static int set_delay_drop(struct mlx5_ib_dev *dev)
5680 {
5681         int err = 0;
5682
5683         mutex_lock(&dev->delay_drop.lock);
5684         if (dev->delay_drop.activate)
5685                 goto out;
5686
5687         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5688         if (err)
5689                 goto out;
5690
5691         dev->delay_drop.activate = true;
5692 out:
5693         mutex_unlock(&dev->delay_drop.lock);
5694
5695         if (!err)
5696                 atomic_inc(&dev->delay_drop.rqs_cnt);
5697         return err;
5698 }
5699
5700 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5701                       struct ib_wq_init_attr *init_attr)
5702 {
5703         struct mlx5_ib_dev *dev;
5704         int has_net_offloads;
5705         __be64 *rq_pas0;
5706         void *in;
5707         void *rqc;
5708         void *wq;
5709         int inlen;
5710         int err;
5711
5712         dev = to_mdev(pd->device);
5713
5714         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5715         in = kvzalloc(inlen, GFP_KERNEL);
5716         if (!in)
5717                 return -ENOMEM;
5718
5719         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5720         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5721         MLX5_SET(rqc,  rqc, mem_rq_type,
5722                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5723         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5724         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5725         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5726         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5727         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5728         MLX5_SET(wq, wq, wq_type,
5729                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5730                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5731         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5732                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5733                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5734                         err = -EOPNOTSUPP;
5735                         goto out;
5736                 } else {
5737                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5738                 }
5739         }
5740         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5741         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5742                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5743                 MLX5_SET(wq, wq, log_wqe_stride_size,
5744                          rwq->single_stride_log_num_of_bytes -
5745                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5746                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5747                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5748         }
5749         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5750         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5751         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5752         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5753         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5754         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5755         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5756         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5757                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5758                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5759                         err = -EOPNOTSUPP;
5760                         goto out;
5761                 }
5762         } else {
5763                 MLX5_SET(rqc, rqc, vsd, 1);
5764         }
5765         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5766                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5767                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5768                         err = -EOPNOTSUPP;
5769                         goto out;
5770                 }
5771                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5772         }
5773         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5774                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5775                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5776                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5777                         err = -EOPNOTSUPP;
5778                         goto out;
5779                 }
5780                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5781         }
5782         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5783         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5784         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5785         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5786                 err = set_delay_drop(dev);
5787                 if (err) {
5788                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5789                                      err);
5790                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5791                 } else {
5792                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5793                 }
5794         }
5795 out:
5796         kvfree(in);
5797         return err;
5798 }
5799
5800 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5801                             struct ib_wq_init_attr *wq_init_attr,
5802                             struct mlx5_ib_create_wq *ucmd,
5803                             struct mlx5_ib_rwq *rwq)
5804 {
5805         /* Sanity check RQ size before proceeding */
5806         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5807                 return -EINVAL;
5808
5809         if (!ucmd->rq_wqe_count)
5810                 return -EINVAL;
5811
5812         rwq->wqe_count = ucmd->rq_wqe_count;
5813         rwq->wqe_shift = ucmd->rq_wqe_shift;
5814         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5815                 return -EINVAL;
5816
5817         rwq->log_rq_stride = rwq->wqe_shift;
5818         rwq->log_rq_size = ilog2(rwq->wqe_count);
5819         return 0;
5820 }
5821
5822 static int prepare_user_rq(struct ib_pd *pd,
5823                            struct ib_wq_init_attr *init_attr,
5824                            struct ib_udata *udata,
5825                            struct mlx5_ib_rwq *rwq)
5826 {
5827         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5828         struct mlx5_ib_create_wq ucmd = {};
5829         int err;
5830         size_t required_cmd_sz;
5831
5832         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5833                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5834         if (udata->inlen < required_cmd_sz) {
5835                 mlx5_ib_dbg(dev, "invalid inlen\n");
5836                 return -EINVAL;
5837         }
5838
5839         if (udata->inlen > sizeof(ucmd) &&
5840             !ib_is_udata_cleared(udata, sizeof(ucmd),
5841                                  udata->inlen - sizeof(ucmd))) {
5842                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5843                 return -EOPNOTSUPP;
5844         }
5845
5846         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5847                 mlx5_ib_dbg(dev, "copy failed\n");
5848                 return -EFAULT;
5849         }
5850
5851         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5852                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5853                 return -EOPNOTSUPP;
5854         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5855                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5856                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5857                         return -EOPNOTSUPP;
5858                 }
5859                 if ((ucmd.single_stride_log_num_of_bytes <
5860                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5861                     (ucmd.single_stride_log_num_of_bytes >
5862                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5863                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5864                                     ucmd.single_stride_log_num_of_bytes,
5865                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5866                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5867                         return -EINVAL;
5868                 }
5869                 if ((ucmd.single_wqe_log_num_of_strides >
5870                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5871                      (ucmd.single_wqe_log_num_of_strides <
5872                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5873                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5874                                     ucmd.single_wqe_log_num_of_strides,
5875                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5876                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5877                         return -EINVAL;
5878                 }
5879                 rwq->single_stride_log_num_of_bytes =
5880                         ucmd.single_stride_log_num_of_bytes;
5881                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5882                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5883                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5884         }
5885
5886         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5887         if (err) {
5888                 mlx5_ib_dbg(dev, "err %d\n", err);
5889                 return err;
5890         }
5891
5892         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
5893         if (err) {
5894                 mlx5_ib_dbg(dev, "err %d\n", err);
5895                 return err;
5896         }
5897
5898         rwq->user_index = ucmd.user_index;
5899         return 0;
5900 }
5901
5902 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5903                                 struct ib_wq_init_attr *init_attr,
5904                                 struct ib_udata *udata)
5905 {
5906         struct mlx5_ib_dev *dev;
5907         struct mlx5_ib_rwq *rwq;
5908         struct mlx5_ib_create_wq_resp resp = {};
5909         size_t min_resp_len;
5910         int err;
5911
5912         if (!udata)
5913                 return ERR_PTR(-ENOSYS);
5914
5915         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5916         if (udata->outlen && udata->outlen < min_resp_len)
5917                 return ERR_PTR(-EINVAL);
5918
5919         dev = to_mdev(pd->device);
5920         switch (init_attr->wq_type) {
5921         case IB_WQT_RQ:
5922                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5923                 if (!rwq)
5924                         return ERR_PTR(-ENOMEM);
5925                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5926                 if (err)
5927                         goto err;
5928                 err = create_rq(rwq, pd, init_attr);
5929                 if (err)
5930                         goto err_user_rq;
5931                 break;
5932         default:
5933                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5934                             init_attr->wq_type);
5935                 return ERR_PTR(-EINVAL);
5936         }
5937
5938         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5939         rwq->ibwq.state = IB_WQS_RESET;
5940         if (udata->outlen) {
5941                 resp.response_length = offsetof(typeof(resp), response_length) +
5942                                 sizeof(resp.response_length);
5943                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5944                 if (err)
5945                         goto err_copy;
5946         }
5947
5948         rwq->core_qp.event = mlx5_ib_wq_event;
5949         rwq->ibwq.event_handler = init_attr->event_handler;
5950         return &rwq->ibwq;
5951
5952 err_copy:
5953         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5954 err_user_rq:
5955         destroy_user_rq(dev, pd, rwq);
5956 err:
5957         kfree(rwq);
5958         return ERR_PTR(err);
5959 }
5960
5961 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5962 {
5963         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5964         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5965
5966         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5967         destroy_user_rq(dev, wq->pd, rwq);
5968         kfree(rwq);
5969
5970         return 0;
5971 }
5972
5973 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5974                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5975                                                       struct ib_udata *udata)
5976 {
5977         struct mlx5_ib_dev *dev = to_mdev(device);
5978         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5979         int sz = 1 << init_attr->log_ind_tbl_size;
5980         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5981         size_t min_resp_len;
5982         int inlen;
5983         int err;
5984         int i;
5985         u32 *in;
5986         void *rqtc;
5987
5988         if (udata->inlen > 0 &&
5989             !ib_is_udata_cleared(udata, 0,
5990                                  udata->inlen))
5991                 return ERR_PTR(-EOPNOTSUPP);
5992
5993         if (init_attr->log_ind_tbl_size >
5994             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5995                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5996                             init_attr->log_ind_tbl_size,
5997                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5998                 return ERR_PTR(-EINVAL);
5999         }
6000
6001         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6002         if (udata->outlen && udata->outlen < min_resp_len)
6003                 return ERR_PTR(-EINVAL);
6004
6005         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6006         if (!rwq_ind_tbl)
6007                 return ERR_PTR(-ENOMEM);
6008
6009         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6010         in = kvzalloc(inlen, GFP_KERNEL);
6011         if (!in) {
6012                 err = -ENOMEM;
6013                 goto err;
6014         }
6015
6016         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6017
6018         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6019         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6020
6021         for (i = 0; i < sz; i++)
6022                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6023
6024         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6025         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6026
6027         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6028         kvfree(in);
6029
6030         if (err)
6031                 goto err;
6032
6033         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6034         if (udata->outlen) {
6035                 resp.response_length = offsetof(typeof(resp), response_length) +
6036                                         sizeof(resp.response_length);
6037                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6038                 if (err)
6039                         goto err_copy;
6040         }
6041
6042         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6043
6044 err_copy:
6045         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6046 err:
6047         kfree(rwq_ind_tbl);
6048         return ERR_PTR(err);
6049 }
6050
6051 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6052 {
6053         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6054         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6055
6056         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6057
6058         kfree(rwq_ind_tbl);
6059         return 0;
6060 }
6061
6062 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6063                       u32 wq_attr_mask, struct ib_udata *udata)
6064 {
6065         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6066         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6067         struct mlx5_ib_modify_wq ucmd = {};
6068         size_t required_cmd_sz;
6069         int curr_wq_state;
6070         int wq_state;
6071         int inlen;
6072         int err;
6073         void *rqc;
6074         void *in;
6075
6076         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6077         if (udata->inlen < required_cmd_sz)
6078                 return -EINVAL;
6079
6080         if (udata->inlen > sizeof(ucmd) &&
6081             !ib_is_udata_cleared(udata, sizeof(ucmd),
6082                                  udata->inlen - sizeof(ucmd)))
6083                 return -EOPNOTSUPP;
6084
6085         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6086                 return -EFAULT;
6087
6088         if (ucmd.comp_mask || ucmd.reserved)
6089                 return -EOPNOTSUPP;
6090
6091         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6092         in = kvzalloc(inlen, GFP_KERNEL);
6093         if (!in)
6094                 return -ENOMEM;
6095
6096         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6097
6098         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6099                 wq_attr->curr_wq_state : wq->state;
6100         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6101                 wq_attr->wq_state : curr_wq_state;
6102         if (curr_wq_state == IB_WQS_ERR)
6103                 curr_wq_state = MLX5_RQC_STATE_ERR;
6104         if (wq_state == IB_WQS_ERR)
6105                 wq_state = MLX5_RQC_STATE_ERR;
6106         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6107         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6108         MLX5_SET(rqc, rqc, state, wq_state);
6109
6110         if (wq_attr_mask & IB_WQ_FLAGS) {
6111                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6112                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6113                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6114                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6115                                             "supported\n");
6116                                 err = -EOPNOTSUPP;
6117                                 goto out;
6118                         }
6119                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6120                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6121                         MLX5_SET(rqc, rqc, vsd,
6122                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6123                 }
6124
6125                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6126                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6127                         err = -EOPNOTSUPP;
6128                         goto out;
6129                 }
6130         }
6131
6132         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6133                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6134                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6135                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6136                         MLX5_SET(rqc, rqc, counter_set_id,
6137                                  dev->port->cnts.set_id);
6138                 } else
6139                         dev_info_once(
6140                                 &dev->ib_dev.dev,
6141                                 "Receive WQ counters are not supported on current FW\n");
6142         }
6143
6144         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6145         if (!err)
6146                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6147
6148 out:
6149         kvfree(in);
6150         return err;
6151 }
6152
6153 struct mlx5_ib_drain_cqe {
6154         struct ib_cqe cqe;
6155         struct completion done;
6156 };
6157
6158 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6159 {
6160         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6161                                                      struct mlx5_ib_drain_cqe,
6162                                                      cqe);
6163
6164         complete(&cqe->done);
6165 }
6166
6167 /* This function returns only once the drained WR was completed */
6168 static void handle_drain_completion(struct ib_cq *cq,
6169                                     struct mlx5_ib_drain_cqe *sdrain,
6170                                     struct mlx5_ib_dev *dev)
6171 {
6172         struct mlx5_core_dev *mdev = dev->mdev;
6173
6174         if (cq->poll_ctx == IB_POLL_DIRECT) {
6175                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6176                         ib_process_cq_direct(cq, -1);
6177                 return;
6178         }
6179
6180         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6181                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6182                 bool triggered = false;
6183                 unsigned long flags;
6184
6185                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6186                 /* Make sure that the CQ handler won't run if wasn't run yet */
6187                 if (!mcq->mcq.reset_notify_added)
6188                         mcq->mcq.reset_notify_added = 1;
6189                 else
6190                         triggered = true;
6191                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6192
6193                 if (triggered) {
6194                         /* Wait for any scheduled/running task to be ended */
6195                         switch (cq->poll_ctx) {
6196                         case IB_POLL_SOFTIRQ:
6197                                 irq_poll_disable(&cq->iop);
6198                                 irq_poll_enable(&cq->iop);
6199                                 break;
6200                         case IB_POLL_WORKQUEUE:
6201                                 cancel_work_sync(&cq->work);
6202                                 break;
6203                         default:
6204                                 WARN_ON_ONCE(1);
6205                         }
6206                 }
6207
6208                 /* Run the CQ handler - this makes sure that the drain WR will
6209                  * be processed if wasn't processed yet.
6210                  */
6211                 mcq->mcq.comp(&mcq->mcq);
6212         }
6213
6214         wait_for_completion(&sdrain->done);
6215 }
6216
6217 void mlx5_ib_drain_sq(struct ib_qp *qp)
6218 {
6219         struct ib_cq *cq = qp->send_cq;
6220         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6221         struct mlx5_ib_drain_cqe sdrain;
6222         const struct ib_send_wr *bad_swr;
6223         struct ib_rdma_wr swr = {
6224                 .wr = {
6225                         .next = NULL,
6226                         { .wr_cqe       = &sdrain.cqe, },
6227                         .opcode = IB_WR_RDMA_WRITE,
6228                 },
6229         };
6230         int ret;
6231         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6232         struct mlx5_core_dev *mdev = dev->mdev;
6233
6234         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6235         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6236                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6237                 return;
6238         }
6239
6240         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6241         init_completion(&sdrain.done);
6242
6243         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6244         if (ret) {
6245                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6246                 return;
6247         }
6248
6249         handle_drain_completion(cq, &sdrain, dev);
6250 }
6251
6252 void mlx5_ib_drain_rq(struct ib_qp *qp)
6253 {
6254         struct ib_cq *cq = qp->recv_cq;
6255         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6256         struct mlx5_ib_drain_cqe rdrain;
6257         struct ib_recv_wr rwr = {};
6258         const struct ib_recv_wr *bad_rwr;
6259         int ret;
6260         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6261         struct mlx5_core_dev *mdev = dev->mdev;
6262
6263         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6264         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6265                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6266                 return;
6267         }
6268
6269         rwr.wr_cqe = &rdrain.cqe;
6270         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6271         init_completion(&rdrain.done);
6272
6273         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6274         if (ret) {
6275                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6276                 return;
6277         }
6278
6279         handle_drain_completion(cq, &rdrain, dev);
6280 }