drivers/infiniband/hw/mlx5/odp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <rdma/ib_umem.h>
  34 #include <rdma/ib_umem_odp.h>
  35 #include <linux/kernel.h>
  36 #include <linux/dma-buf.h>
  37 #include <linux/dma-resv.h>
  38
  39 #include "mlx5_ib.h"
  40 #include "cmd.h"
  41 #include "qp.h"
  42
  43 #include <linux/mlx5/eq.h>
  44
  45 /* Contains the details of a pagefault. */
  46 struct mlx5_pagefault {
  47         u32                     bytes_committed;
  48         u32                     token;
  49         u8                      event_subtype;
  50         u8                      type;
  51         union {
  52                 /* Initiator or send message responder pagefault details. */
  53                 struct {
  54                         /* Received packet size, only valid for responders. */
  55                         u32     packet_size;
  56                         /*
  57                          * Number of resource holding WQE, depends on type.
  58                          */
  59                         u32     wq_num;
  60                         /*
  61                          * WQE index. Refers to either the send queue or
  62                          * receive queue, according to event_subtype.
  63                          */
  64                         u16     wqe_index;
  65                 } wqe;
  66                 /* RDMA responder pagefault details */
  67                 struct {
  68                         u32     r_key;
  69                         /*
  70                          * Received packet size, minimal size page fault
  71                          * resolution required for forward progress.
  72                          */
  73                         u32     packet_size;
  74                         u32     rdma_op_len;
  75                         u64     rdma_va;
  76                 } rdma;
  77         };
  78
  79         struct mlx5_ib_pf_eq    *eq;
  80         struct work_struct      work;
  81 };
  82
  83 #define MAX_PREFETCH_LEN (4*1024*1024U)
  84
  85 /* Timeout in ms to wait for an active mmu notifier to complete when handling
  86  * a pagefault. */
  87 #define MMU_NOTIFIER_TIMEOUT 1000
  88
  89 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT)
  90 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT)
  91 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS)
  92 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT)
  93 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1))
  94
  95 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT
  96
  97 static u64 mlx5_imr_ksm_entries;
  98
  99 static void populate_klm(struct mlx5_klm *pklm, size_t idx, size_t nentries,
 100                         struct mlx5_ib_mr *imr, int flags)
 101 {
 102         struct mlx5_klm *end = pklm + nentries;
 103
 104         if (flags & MLX5_IB_UPD_XLT_ZAP) {
 105                 for (; pklm != end; pklm++, idx++) {
 106                         pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 107                         pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey);
 108                         pklm->va = 0;
 109                 }
 110                 return;
 111         }
 112
 113         /*
 114          * The locking here is pretty subtle. Ideally the implicit_children
 115          * xarray would be protected by the umem_mutex, however that is not
 116          * possible. Instead this uses a weaker update-then-lock pattern:
 117          *
 118          *    xa_store()
 119          *    mutex_lock(umem_mutex)
 120          *     mlx5_ib_update_xlt()
 121          *    mutex_unlock(umem_mutex)
 122          *    destroy lkey
 123          *
 124          * ie any change the xarray must be followed by the locked update_xlt
 125          * before destroying.
 126          *
 127          * The umem_mutex provides the acquire/release semantic needed to make
 128          * the xa_store() visible to a racing thread.
 129          */
 130         lockdep_assert_held(&to_ib_umem_odp(imr->umem)->umem_mutex);
 131
 132         for (; pklm != end; pklm++, idx++) {
 133                 struct mlx5_ib_mr *mtt = xa_load(&imr->implicit_children, idx);
 134
 135                 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
 136                 if (mtt) {
 137                         pklm->key = cpu_to_be32(mtt->ibmr.lkey);
 138                         pklm->va = cpu_to_be64(idx * MLX5_IMR_MTT_SIZE);
 139                 } else {
 140                         pklm->key = cpu_to_be32(mr_to_mdev(imr)->null_mkey);
 141                         pklm->va = 0;
 142                 }
 143         }
 144 }
 145
 146 static u64 umem_dma_to_mtt(dma_addr_t umem_dma)
 147 {
 148         u64 mtt_entry = umem_dma & ODP_DMA_ADDR_MASK;
 149
 150         if (umem_dma & ODP_READ_ALLOWED_BIT)
 151                 mtt_entry |= MLX5_IB_MTT_READ;
 152         if (umem_dma & ODP_WRITE_ALLOWED_BIT)
 153                 mtt_entry |= MLX5_IB_MTT_WRITE;
 154
 155         return mtt_entry;
 156 }
 157
 158 static void populate_mtt(__be64 *pas, size_t idx, size_t nentries,
 159                          struct mlx5_ib_mr *mr, int flags)
 160 {
 161         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 162         dma_addr_t pa;
 163         size_t i;
 164
 165         if (flags & MLX5_IB_UPD_XLT_ZAP)
 166                 return;
 167
 168         for (i = 0; i < nentries; i++) {
 169                 pa = odp->dma_list[idx + i];
 170                 pas[i] = cpu_to_be64(umem_dma_to_mtt(pa));
 171         }
 172 }
 173
 174 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
 175                            struct mlx5_ib_mr *mr, int flags)
 176 {
 177         if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
 178                 populate_klm(xlt, idx, nentries, mr, flags);
 179         } else {
 180                 populate_mtt(xlt, idx, nentries, mr, flags);
 181         }
 182 }
 183
 184 static void dma_fence_odp_mr(struct mlx5_ib_mr *mr)
 185 {
 186         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 187
 188         /* Ensure mlx5_ib_invalidate_range() will not touch the MR any more */
 189         mutex_lock(&odp->umem_mutex);
 190         if (odp->npages) {
 191                 mlx5_mr_cache_invalidate(mr);
 192                 ib_umem_odp_unmap_dma_pages(odp, ib_umem_start(odp),
 193                                             ib_umem_end(odp));
 194                 WARN_ON(odp->npages);
 195         }
 196         odp->private = NULL;
 197         mutex_unlock(&odp->umem_mutex);
 198
 199         if (!mr->cache_ent) {
 200                 mlx5_core_destroy_mkey(mr_to_mdev(mr)->mdev, &mr->mmkey);
 201                 WARN_ON(mr->descs);
 202         }
 203 }
 204
 205 /*
 206  * This must be called after the mr has been removed from implicit_children.
 207  * NOTE: The MR does not necessarily have to be
 208  * empty here, parallel page faults could have raced with the free process and
 209  * added pages to it.
 210  */
 211 static void free_implicit_child_mr(struct mlx5_ib_mr *mr, bool need_imr_xlt)
 212 {
 213         struct mlx5_ib_mr *imr = mr->parent;
 214         struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem);
 215         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 216         unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT;
 217
 218         mlx5r_deref_wait_odp_mkey(&mr->mmkey);
 219
 220         if (need_imr_xlt) {
 221                 mutex_lock(&odp_imr->umem_mutex);
 222                 mlx5_ib_update_xlt(mr->parent, idx, 1, 0,
 223                                    MLX5_IB_UPD_XLT_INDIRECT |
 224                                    MLX5_IB_UPD_XLT_ATOMIC);
 225                 mutex_unlock(&odp_imr->umem_mutex);
 226         }
 227
 228         dma_fence_odp_mr(mr);
 229
 230         mlx5_mr_cache_free(mr_to_mdev(mr), mr);
 231         ib_umem_odp_release(odp);
 232 }
 233
 234 static void free_implicit_child_mr_work(struct work_struct *work)
 235 {
 236         struct mlx5_ib_mr *mr =
 237                 container_of(work, struct mlx5_ib_mr, odp_destroy.work);
 238         struct mlx5_ib_mr *imr = mr->parent;
 239
 240         free_implicit_child_mr(mr, true);
 241         mlx5r_deref_odp_mkey(&imr->mmkey);
 242 }
 243
 244 static void destroy_unused_implicit_child_mr(struct mlx5_ib_mr *mr)
 245 {
 246         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 247         unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT;
 248         struct mlx5_ib_mr *imr = mr->parent;
 249
 250         if (!refcount_inc_not_zero(&imr->mmkey.usecount))
 251                 return;
 252
 253         xa_erase(&imr->implicit_children, idx);
 254
 255         /* Freeing a MR is a sleeping operation, so bounce to a work queue */
 256         INIT_WORK(&mr->odp_destroy.work, free_implicit_child_mr_work);
 257         queue_work(system_unbound_wq, &mr->odp_destroy.work);
 258 }
 259
 260 static bool mlx5_ib_invalidate_range(struct mmu_interval_notifier *mni,
 261                                      const struct mmu_notifier_range *range,
 262                                      unsigned long cur_seq)
 263 {
 264         struct ib_umem_odp *umem_odp =
 265                 container_of(mni, struct ib_umem_odp, notifier);
 266         struct mlx5_ib_mr *mr;
 267         const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT /
 268                                     sizeof(struct mlx5_mtt)) - 1;
 269         u64 idx = 0, blk_start_idx = 0;
 270         u64 invalidations = 0;
 271         unsigned long start;
 272         unsigned long end;
 273         int in_block = 0;
 274         u64 addr;
 275
 276         if (!mmu_notifier_range_blockable(range))
 277                 return false;
 278
 279         mutex_lock(&umem_odp->umem_mutex);
 280         mmu_interval_set_seq(mni, cur_seq);
 281         /*
 282          * If npages is zero then umem_odp->private may not be setup yet. This
 283          * does not complete until after the first page is mapped for DMA.
 284          */
 285         if (!umem_odp->npages)
 286                 goto out;
 287         mr = umem_odp->private;
 288
 289         start = max_t(u64, ib_umem_start(umem_odp), range->start);
 290         end = min_t(u64, ib_umem_end(umem_odp), range->end);
 291
 292         /*
 293          * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
 294          * while we are doing the invalidation, no page fault will attempt to
 295          * overwrite the same MTTs.  Concurent invalidations might race us,
 296          * but they will write 0s as well, so no difference in the end result.
 297          */
 298         for (addr = start; addr < end; addr += BIT(umem_odp->page_shift)) {
 299                 idx = (addr - ib_umem_start(umem_odp)) >> umem_odp->page_shift;
 300                 /*
 301                  * Strive to write the MTTs in chunks, but avoid overwriting
 302                  * non-existing MTTs. The huristic here can be improved to
 303                  * estimate the cost of another UMR vs. the cost of bigger
 304                  * UMR.
 305                  */
 306                 if (umem_odp->dma_list[idx] &
 307                     (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
 308                         if (!in_block) {
 309                                 blk_start_idx = idx;
 310                                 in_block = 1;
 311                         }
 312
 313                         /* Count page invalidations */
 314                         invalidations += idx - blk_start_idx + 1;
 315                 } else {
 316                         u64 umr_offset = idx & umr_block_mask;
 317
 318                         if (in_block && umr_offset == 0) {
 319                                 mlx5_ib_update_xlt(mr, blk_start_idx,
 320                                                    idx - blk_start_idx, 0,
 321                                                    MLX5_IB_UPD_XLT_ZAP |
 322                                                    MLX5_IB_UPD_XLT_ATOMIC);
 323                                 in_block = 0;
 324                         }
 325                 }
 326         }
 327         if (in_block)
 328                 mlx5_ib_update_xlt(mr, blk_start_idx,
 329                                    idx - blk_start_idx + 1, 0,
 330                                    MLX5_IB_UPD_XLT_ZAP |
 331                                    MLX5_IB_UPD_XLT_ATOMIC);
 332
 333         mlx5_update_odp_stats(mr, invalidations, invalidations);
 334
 335         /*
 336          * We are now sure that the device will not access the
 337          * memory. We can safely unmap it, and mark it as dirty if
 338          * needed.
 339          */
 340
 341         ib_umem_odp_unmap_dma_pages(umem_odp, start, end);
 342
 343         if (unlikely(!umem_odp->npages && mr->parent))
 344                 destroy_unused_implicit_child_mr(mr);
 345 out:
 346         mutex_unlock(&umem_odp->umem_mutex);
 347         return true;
 348 }
 349
 350 const struct mmu_interval_notifier_ops mlx5_mn_ops = {
 351         .invalidate = mlx5_ib_invalidate_range,
 352 };
 353
 354 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
 355 {
 356         struct ib_odp_caps *caps = &dev->odp_caps;
 357
 358         memset(caps, 0, sizeof(*caps));
 359
 360         if (!MLX5_CAP_GEN(dev->mdev, pg) ||
 361             !mlx5_ib_can_load_pas_with_umr(dev, 0))
 362                 return;
 363
 364         caps->general_caps = IB_ODP_SUPPORT;
 365
 366         if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
 367                 dev->odp_max_size = U64_MAX;
 368         else
 369                 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT);
 370
 371         if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send))
 372                 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND;
 373
 374         if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.srq_receive))
 375                 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 376
 377         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send))
 378                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND;
 379
 380         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive))
 381                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV;
 382
 383         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write))
 384                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE;
 385
 386         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read))
 387                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ;
 388
 389         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic))
 390                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
 391
 392         if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.srq_receive))
 393                 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 394
 395         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.send))
 396                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SEND;
 397
 398         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.receive))
 399                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_RECV;
 400
 401         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.write))
 402                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_WRITE;
 403
 404         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.read))
 405                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_READ;
 406
 407         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.atomic))
 408                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
 409
 410         if (MLX5_CAP_ODP(dev->mdev, xrc_odp_caps.srq_receive))
 411                 caps->per_transport_caps.xrc_odp_caps |= IB_ODP_SUPPORT_SRQ_RECV;
 412
 413         if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) &&
 414             MLX5_CAP_GEN(dev->mdev, null_mkey) &&
 415             MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
 416             !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled))
 417                 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT;
 418 }
 419
 420 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev,
 421                                       struct mlx5_pagefault *pfault,
 422                                       int error)
 423 {
 424         int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ?
 425                      pfault->wqe.wq_num : pfault->token;
 426         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {};
 427         int err;
 428
 429         MLX5_SET(page_fault_resume_in, in, opcode, MLX5_CMD_OP_PAGE_FAULT_RESUME);
 430         MLX5_SET(page_fault_resume_in, in, page_fault_type, pfault->type);
 431         MLX5_SET(page_fault_resume_in, in, token, pfault->token);
 432         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
 433         MLX5_SET(page_fault_resume_in, in, error, !!error);
 434
 435         err = mlx5_cmd_exec_in(dev->mdev, page_fault_resume, in);
 436         if (err)
 437                 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x err %d\n",
 438                             wq_num, err);
 439 }
 440
 441 static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr,
 442                                                 unsigned long idx)
 443 {
 444         struct ib_umem_odp *odp;
 445         struct mlx5_ib_mr *mr;
 446         struct mlx5_ib_mr *ret;
 447         int err;
 448
 449         odp = ib_umem_odp_alloc_child(to_ib_umem_odp(imr->umem),
 450                                       idx * MLX5_IMR_MTT_SIZE,
 451                                       MLX5_IMR_MTT_SIZE, &mlx5_mn_ops);
 452         if (IS_ERR(odp))
 453                 return ERR_CAST(odp);
 454
 455         ret = mr = mlx5_mr_cache_alloc(
 456                 mr_to_mdev(imr), MLX5_IMR_MTT_CACHE_ENTRY, imr->access_flags);
 457         if (IS_ERR(mr))
 458                 goto out_umem;
 459
 460         mr->ibmr.pd = imr->ibmr.pd;
 461         mr->ibmr.device = &mr_to_mdev(imr)->ib_dev;
 462         mr->umem = &odp->umem;
 463         mr->ibmr.lkey = mr->mmkey.key;
 464         mr->ibmr.rkey = mr->mmkey.key;
 465         mr->mmkey.iova = idx * MLX5_IMR_MTT_SIZE;
 466         mr->parent = imr;
 467         odp->private = mr;
 468
 469         /*
 470          * First refcount is owned by the xarray and second refconut
 471          * is returned to the caller.
 472          */
 473         refcount_set(&mr->mmkey.usecount, 2);
 474
 475         err = mlx5_ib_update_xlt(mr, 0,
 476                                  MLX5_IMR_MTT_ENTRIES,
 477                                  PAGE_SHIFT,
 478                                  MLX5_IB_UPD_XLT_ZAP |
 479                                  MLX5_IB_UPD_XLT_ENABLE);
 480         if (err) {
 481                 ret = ERR_PTR(err);
 482                 goto out_mr;
 483         }
 484
 485         xa_lock(&imr->implicit_children);
 486         ret = __xa_cmpxchg(&imr->implicit_children, idx, NULL, mr,
 487                            GFP_KERNEL);
 488         if (unlikely(ret)) {
 489                 if (xa_is_err(ret)) {
 490                         ret = ERR_PTR(xa_err(ret));
 491                         goto out_lock;
 492                 }
 493                 /*
 494                  * Another thread beat us to creating the child mr, use
 495                  * theirs.
 496                  */
 497                 refcount_inc(&ret->mmkey.usecount);
 498                 goto out_lock;
 499         }
 500         xa_unlock(&imr->implicit_children);
 501
 502         mlx5_ib_dbg(mr_to_mdev(imr), "key %x mr %p\n", mr->mmkey.key, mr);
 503         return mr;
 504
 505 out_lock:
 506         xa_unlock(&imr->implicit_children);
 507 out_mr:
 508         mlx5_mr_cache_free(mr_to_mdev(imr), mr);
 509 out_umem:
 510         ib_umem_odp_release(odp);
 511         return ret;
 512 }
 513
 514 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
 515                                              struct ib_udata *udata,
 516                                              int access_flags)
 517 {
 518         struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
 519         struct ib_umem_odp *umem_odp;
 520         struct mlx5_ib_mr *imr;
 521         int err;
 522
 523         if (!mlx5_ib_can_load_pas_with_umr(dev,
 524                                            MLX5_IMR_MTT_ENTRIES * PAGE_SIZE))
 525                 return ERR_PTR(-EOPNOTSUPP);
 526
 527         umem_odp = ib_umem_odp_alloc_implicit(&dev->ib_dev, access_flags);
 528         if (IS_ERR(umem_odp))
 529                 return ERR_CAST(umem_odp);
 530
 531         imr = mlx5_mr_cache_alloc(dev, MLX5_IMR_KSM_CACHE_ENTRY, access_flags);
 532         if (IS_ERR(imr)) {
 533                 err = PTR_ERR(imr);
 534                 goto out_umem;
 535         }
 536
 537         imr->ibmr.pd = &pd->ibpd;
 538         imr->mmkey.iova = 0;
 539         imr->umem = &umem_odp->umem;
 540         imr->ibmr.lkey = imr->mmkey.key;
 541         imr->ibmr.rkey = imr->mmkey.key;
 542         imr->ibmr.device = &dev->ib_dev;
 543         imr->umem = &umem_odp->umem;
 544         imr->is_odp_implicit = true;
 545         xa_init(&imr->implicit_children);
 546
 547         err = mlx5_ib_update_xlt(imr, 0,
 548                                  mlx5_imr_ksm_entries,
 549                                  MLX5_KSM_PAGE_SHIFT,
 550                                  MLX5_IB_UPD_XLT_INDIRECT |
 551                                  MLX5_IB_UPD_XLT_ZAP |
 552                                  MLX5_IB_UPD_XLT_ENABLE);
 553         if (err)
 554                 goto out_mr;
 555
 556         err = mlx5r_store_odp_mkey(dev, &imr->mmkey);
 557         if (err)
 558                 goto out_mr;
 559
 560         mlx5_ib_dbg(dev, "key %x mr %p\n", imr->mmkey.key, imr);
 561         return imr;
 562 out_mr:
 563         mlx5_ib_err(dev, "Failed to register MKEY %d\n", err);
 564         mlx5_mr_cache_free(dev, imr);
 565 out_umem:
 566         ib_umem_odp_release(umem_odp);
 567         return ERR_PTR(err);
 568 }
 569
 570 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *imr)
 571 {
 572         struct ib_umem_odp *odp_imr = to_ib_umem_odp(imr->umem);
 573         struct mlx5_ib_dev *dev = mr_to_mdev(imr);
 574         struct mlx5_ib_mr *mtt;
 575         unsigned long idx;
 576
 577         xa_erase(&dev->odp_mkeys, mlx5_base_mkey(imr->mmkey.key));
 578         /*
 579          * All work on the prefetch list must be completed, xa_erase() prevented
 580          * new work from being created.
 581          */
 582         mlx5r_deref_wait_odp_mkey(&imr->mmkey);
 583         /*
 584          * At this point it is forbidden for any other thread to enter
 585          * pagefault_mr() on this imr. It is already forbidden to call
 586          * pagefault_mr() on an implicit child. Due to this additions to
 587          * implicit_children are prevented.
 588          * In addition, any new call to destroy_unused_implicit_child_mr()
 589          * may return immediately.
 590          */
 591
 592         /*
 593          * Fence the imr before we destroy the children. This allows us to
 594          * skip updating the XLT of the imr during destroy of the child mkey
 595          * the imr points to.
 596          */
 597         mlx5_mr_cache_invalidate(imr);
 598
 599         xa_for_each(&imr->implicit_children, idx, mtt) {
 600                 xa_erase(&imr->implicit_children, idx);
 601                 free_implicit_child_mr(mtt, false);
 602         }
 603
 604         mlx5_mr_cache_free(dev, imr);
 605         ib_umem_odp_release(odp_imr);
 606 }
 607
 608 /**
 609  * mlx5_ib_fence_odp_mr - Stop all access to the ODP MR
 610  * @mr: to fence
 611  *
 612  * On return no parallel threads will be touching this MR and no DMA will be
 613  * active.
 614  */
 615 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr)
 616 {
 617         /* Prevent new page faults and prefetch requests from succeeding */
 618         xa_erase(&mr_to_mdev(mr)->odp_mkeys, mlx5_base_mkey(mr->mmkey.key));
 619
 620         /* Wait for all running page-fault handlers to finish. */
 621         mlx5r_deref_wait_odp_mkey(&mr->mmkey);
 622
 623         dma_fence_odp_mr(mr);
 624 }
 625
 626 /**
 627  * mlx5_ib_fence_dmabuf_mr - Stop all access to the dmabuf MR
 628  * @mr: to fence
 629  *
 630  * On return no parallel threads will be touching this MR and no DMA will be
 631  * active.
 632  */
 633 void mlx5_ib_fence_dmabuf_mr(struct mlx5_ib_mr *mr)
 634 {
 635         struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem);
 636
 637         /* Prevent new page faults and prefetch requests from succeeding */
 638         xa_erase(&mr_to_mdev(mr)->odp_mkeys, mlx5_base_mkey(mr->mmkey.key));
 639
 640         mlx5r_deref_wait_odp_mkey(&mr->mmkey);
 641
 642         dma_resv_lock(umem_dmabuf->attach->dmabuf->resv, NULL);
 643         mlx5_mr_cache_invalidate(mr);
 644         umem_dmabuf->private = NULL;
 645         ib_umem_dmabuf_unmap_pages(umem_dmabuf);
 646         dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv);
 647
 648         if (!mr->cache_ent) {
 649                 mlx5_core_destroy_mkey(mr_to_mdev(mr)->mdev, &mr->mmkey);
 650                 WARN_ON(mr->descs);
 651         }
 652 }
 653
 654 #define MLX5_PF_FLAGS_DOWNGRADE BIT(1)
 655 #define MLX5_PF_FLAGS_SNAPSHOT BIT(2)
 656 #define MLX5_PF_FLAGS_ENABLE BIT(3)
 657 static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp,
 658                              u64 user_va, size_t bcnt, u32 *bytes_mapped,
 659                              u32 flags)
 660 {
 661         int page_shift, ret, np;
 662         bool downgrade = flags & MLX5_PF_FLAGS_DOWNGRADE;
 663         u64 access_mask;
 664         u64 start_idx;
 665         bool fault = !(flags & MLX5_PF_FLAGS_SNAPSHOT);
 666         u32 xlt_flags = MLX5_IB_UPD_XLT_ATOMIC;
 667
 668         if (flags & MLX5_PF_FLAGS_ENABLE)
 669                 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE;
 670
 671         page_shift = odp->page_shift;
 672         start_idx = (user_va - ib_umem_start(odp)) >> page_shift;
 673         access_mask = ODP_READ_ALLOWED_BIT;
 674
 675         if (odp->umem.writable && !downgrade)
 676                 access_mask |= ODP_WRITE_ALLOWED_BIT;
 677
 678         np = ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, fault);
 679         if (np < 0)
 680                 return np;
 681
 682         /*
 683          * No need to check whether the MTTs really belong to this MR, since
 684          * ib_umem_odp_map_dma_and_lock already checks this.
 685          */
 686         ret = mlx5_ib_update_xlt(mr, start_idx, np, page_shift, xlt_flags);
 687         mutex_unlock(&odp->umem_mutex);
 688
 689         if (ret < 0) {
 690                 if (ret != -EAGAIN)
 691                         mlx5_ib_err(mr_to_mdev(mr),
 692                                     "Failed to update mkey page tables\n");
 693                 goto out;
 694         }
 695
 696         if (bytes_mapped) {
 697                 u32 new_mappings = (np << page_shift) -
 698                         (user_va - round_down(user_va, 1 << page_shift));
 699
 700                 *bytes_mapped += min_t(u32, new_mappings, bcnt);
 701         }
 702
 703         return np << (page_shift - PAGE_SHIFT);
 704
 705 out:
 706         return ret;
 707 }
 708
 709 static int pagefault_implicit_mr(struct mlx5_ib_mr *imr,
 710                                  struct ib_umem_odp *odp_imr, u64 user_va,
 711                                  size_t bcnt, u32 *bytes_mapped, u32 flags)
 712 {
 713         unsigned long end_idx = (user_va + bcnt - 1) >> MLX5_IMR_MTT_SHIFT;
 714         unsigned long upd_start_idx = end_idx + 1;
 715         unsigned long upd_len = 0;
 716         unsigned long npages = 0;
 717         int err;
 718         int ret;
 719
 720         if (unlikely(user_va >= mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE ||
 721                      mlx5_imr_ksm_entries * MLX5_IMR_MTT_SIZE - user_va < bcnt))
 722                 return -EFAULT;
 723
 724         /* Fault each child mr that intersects with our interval. */
 725         while (bcnt) {
 726                 unsigned long idx = user_va >> MLX5_IMR_MTT_SHIFT;
 727                 struct ib_umem_odp *umem_odp;
 728                 struct mlx5_ib_mr *mtt;
 729                 u64 len;
 730
 731                 xa_lock(&imr->implicit_children);
 732                 mtt = xa_load(&imr->implicit_children, idx);
 733                 if (unlikely(!mtt)) {
 734                         xa_unlock(&imr->implicit_children);
 735                         mtt = implicit_get_child_mr(imr, idx);
 736                         if (IS_ERR(mtt)) {
 737                                 ret = PTR_ERR(mtt);
 738                                 goto out;
 739                         }
 740                         upd_start_idx = min(upd_start_idx, idx);
 741                         upd_len = idx - upd_start_idx + 1;
 742                 } else {
 743                         refcount_inc(&mtt->mmkey.usecount);
 744                         xa_unlock(&imr->implicit_children);
 745                 }
 746
 747                 umem_odp = to_ib_umem_odp(mtt->umem);
 748                 len = min_t(u64, user_va + bcnt, ib_umem_end(umem_odp)) -
 749                       user_va;
 750
 751                 ret = pagefault_real_mr(mtt, umem_odp, user_va, len,
 752                                         bytes_mapped, flags);
 753
 754                 mlx5r_deref_odp_mkey(&mtt->mmkey);
 755
 756                 if (ret < 0)
 757                         goto out;
 758                 user_va += len;
 759                 bcnt -= len;
 760                 npages += ret;
 761         }
 762
 763         ret = npages;
 764
 765         /*
 766          * Any time the implicit_children are changed we must perform an
 767          * update of the xlt before exiting to ensure the HW and the
 768          * implicit_children remains synchronized.
 769          */
 770 out:
 771         if (likely(!upd_len))
 772                 return ret;
 773
 774         /*
 775          * Notice this is not strictly ordered right, the KSM is updated after
 776          * the implicit_children is updated, so a parallel page fault could
 777          * see a MR that is not yet visible in the KSM.  This is similar to a
 778          * parallel page fault seeing a MR that is being concurrently removed
 779          * from the KSM. Both of these improbable situations are resolved
 780          * safely by resuming the HW and then taking another page fault. The
 781          * next pagefault handler will see the new information.
 782          */
 783         mutex_lock(&odp_imr->umem_mutex);
 784         err = mlx5_ib_update_xlt(imr, upd_start_idx, upd_len, 0,
 785                                  MLX5_IB_UPD_XLT_INDIRECT |
 786                                          MLX5_IB_UPD_XLT_ATOMIC);
 787         mutex_unlock(&odp_imr->umem_mutex);
 788         if (err) {
 789                 mlx5_ib_err(mr_to_mdev(imr), "Failed to update PAS\n");
 790                 return err;
 791         }
 792         return ret;
 793 }
 794
 795 static int pagefault_dmabuf_mr(struct mlx5_ib_mr *mr, size_t bcnt,
 796                                u32 *bytes_mapped, u32 flags)
 797 {
 798         struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem);
 799         u32 xlt_flags = 0;
 800         int err;
 801         unsigned int page_size;
 802
 803         if (flags & MLX5_PF_FLAGS_ENABLE)
 804                 xlt_flags |= MLX5_IB_UPD_XLT_ENABLE;
 805
 806         dma_resv_lock(umem_dmabuf->attach->dmabuf->resv, NULL);
 807         err = ib_umem_dmabuf_map_pages(umem_dmabuf);
 808         if (err) {
 809                 dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv);
 810                 return err;
 811         }
 812
 813         page_size = mlx5_umem_find_best_pgsz(&umem_dmabuf->umem, mkc,
 814                                              log_page_size, 0,
 815                                              umem_dmabuf->umem.iova);
 816         if (unlikely(page_size < PAGE_SIZE)) {
 817                 ib_umem_dmabuf_unmap_pages(umem_dmabuf);
 818                 err = -EINVAL;
 819         } else {
 820                 err = mlx5_ib_update_mr_pas(mr, xlt_flags);
 821         }
 822         dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv);
 823
 824         if (err)
 825                 return err;
 826
 827         if (bytes_mapped)
 828                 *bytes_mapped += bcnt;
 829
 830         return ib_umem_num_pages(mr->umem);
 831 }
 832
 833 /*
 834  * Returns:
 835  *  -EFAULT: The io_virt->bcnt is not within the MR, it covers pages that are
 836  *           not accessible, or the MR is no longer valid.
 837  *  -EAGAIN/-ENOMEM: The operation should be retried
 838  *
 839  *  -EINVAL/others: General internal malfunction
 840  *  >0: Number of pages mapped
 841  */
 842 static int pagefault_mr(struct mlx5_ib_mr *mr, u64 io_virt, size_t bcnt,
 843                         u32 *bytes_mapped, u32 flags)
 844 {
 845         struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
 846
 847         if (unlikely(io_virt < mr->mmkey.iova))
 848                 return -EFAULT;
 849
 850         if (mr->umem->is_dmabuf)
 851                 return pagefault_dmabuf_mr(mr, bcnt, bytes_mapped, flags);
 852
 853         if (!odp->is_implicit_odp) {
 854                 u64 user_va;
 855
 856                 if (check_add_overflow(io_virt - mr->mmkey.iova,
 857                                        (u64)odp->umem.address, &user_va))
 858                         return -EFAULT;
 859                 if (unlikely(user_va >= ib_umem_end(odp) ||
 860                              ib_umem_end(odp) - user_va < bcnt))
 861                         return -EFAULT;
 862                 return pagefault_real_mr(mr, odp, user_va, bcnt, bytes_mapped,
 863                                          flags);
 864         }
 865         return pagefault_implicit_mr(mr, odp, io_virt, bcnt, bytes_mapped,
 866                                      flags);
 867 }
 868
 869 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
 870 {
 871         int ret;
 872
 873         ret = pagefault_real_mr(mr, to_ib_umem_odp(mr->umem), mr->umem->address,
 874                                 mr->umem->length, NULL,
 875                                 MLX5_PF_FLAGS_SNAPSHOT | MLX5_PF_FLAGS_ENABLE);
 876         return ret >= 0 ? 0 : ret;
 877 }
 878
 879 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
 880 {
 881         int ret;
 882
 883         ret = pagefault_dmabuf_mr(mr, mr->umem->length, NULL,
 884                                   MLX5_PF_FLAGS_ENABLE);
 885
 886         return ret >= 0 ? 0 : ret;
 887 }
 888
 889 struct pf_frame {
 890         struct pf_frame *next;
 891         u32 key;
 892         u64 io_virt;
 893         size_t bcnt;
 894         int depth;
 895 };
 896
 897 static bool mkey_is_eq(struct mlx5_core_mkey *mmkey, u32 key)
 898 {
 899         if (!mmkey)
 900                 return false;
 901         if (mmkey->type == MLX5_MKEY_MW)
 902                 return mlx5_base_mkey(mmkey->key) == mlx5_base_mkey(key);
 903         return mmkey->key == key;
 904 }
 905
 906 static int get_indirect_num_descs(struct mlx5_core_mkey *mmkey)
 907 {
 908         struct mlx5_ib_mw *mw;
 909         struct mlx5_ib_devx_mr *devx_mr;
 910
 911         if (mmkey->type == MLX5_MKEY_MW) {
 912                 mw = container_of(mmkey, struct mlx5_ib_mw, mmkey);
 913                 return mw->ndescs;
 914         }
 915
 916         devx_mr = container_of(mmkey, struct mlx5_ib_devx_mr,
 917                                mmkey);
 918         return devx_mr->ndescs;
 919 }
 920
 921 /*
 922  * Handle a single data segment in a page-fault WQE or RDMA region.
 923  *
 924  * Returns number of OS pages retrieved on success. The caller may continue to
 925  * the next data segment.
 926  * Can return the following error codes:
 927  * -EAGAIN to designate a temporary error. The caller will abort handling the
 928  *  page fault and resolve it.
 929  * -EFAULT when there's an error mapping the requested pages. The caller will
 930  *  abort the page fault handling.
 931  */
 932 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev,
 933                                          struct ib_pd *pd, u32 key,
 934                                          u64 io_virt, size_t bcnt,
 935                                          u32 *bytes_committed,
 936                                          u32 *bytes_mapped)
 937 {
 938         int npages = 0, ret, i, outlen, cur_outlen = 0, depth = 0;
 939         struct pf_frame *head = NULL, *frame;
 940         struct mlx5_core_mkey *mmkey;
 941         struct mlx5_ib_mr *mr;
 942         struct mlx5_klm *pklm;
 943         u32 *out = NULL;
 944         size_t offset;
 945         int ndescs;
 946
 947         io_virt += *bytes_committed;
 948         bcnt -= *bytes_committed;
 949
 950 next_mr:
 951         xa_lock(&dev->odp_mkeys);
 952         mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(key));
 953         if (!mmkey) {
 954                 xa_unlock(&dev->odp_mkeys);
 955                 mlx5_ib_dbg(
 956                         dev,
 957                         "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
 958                         key);
 959                 if (bytes_mapped)
 960                         *bytes_mapped += bcnt;
 961                 /*
 962                  * The user could specify a SGL with multiple lkeys and only
 963                  * some of them are ODP. Treat the non-ODP ones as fully
 964                  * faulted.
 965                  */
 966                 ret = 0;
 967                 goto end;
 968         }
 969         refcount_inc(&mmkey->usecount);
 970         xa_unlock(&dev->odp_mkeys);
 971
 972         if (!mkey_is_eq(mmkey, key)) {
 973                 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key);
 974                 ret = -EFAULT;
 975                 goto end;
 976         }
 977
 978         switch (mmkey->type) {
 979         case MLX5_MKEY_MR:
 980                 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
 981
 982                 ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0);
 983                 if (ret < 0)
 984                         goto end;
 985
 986                 mlx5_update_odp_stats(mr, faults, ret);
 987
 988                 npages += ret;
 989                 ret = 0;
 990                 break;
 991
 992         case MLX5_MKEY_MW:
 993         case MLX5_MKEY_INDIRECT_DEVX:
 994                 ndescs = get_indirect_num_descs(mmkey);
 995
 996                 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) {
 997                         mlx5_ib_dbg(dev, "indirection level exceeded\n");
 998                         ret = -EFAULT;
 999                         goto end;
1000                 }
1001
1002                 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) +
1003                         sizeof(*pklm) * (ndescs - 2);
1004
1005                 if (outlen > cur_outlen) {
1006                         kfree(out);
1007                         out = kzalloc(outlen, GFP_KERNEL);
1008                         if (!out) {
1009                                 ret = -ENOMEM;
1010                                 goto end;
1011                         }
1012                         cur_outlen = outlen;
1013                 }
1014
1015                 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out,
1016                                                        bsf0_klm0_pas_mtt0_1);
1017
1018                 ret = mlx5_core_query_mkey(dev->mdev, mmkey, out, outlen);
1019                 if (ret)
1020                         goto end;
1021
1022                 offset = io_virt - MLX5_GET64(query_mkey_out, out,
1023                                               memory_key_mkey_entry.start_addr);
1024
1025                 for (i = 0; bcnt && i < ndescs; i++, pklm++) {
1026                         if (offset >= be32_to_cpu(pklm->bcount)) {
1027                                 offset -= be32_to_cpu(pklm->bcount);
1028                                 continue;
1029                         }
1030
1031                         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1032                         if (!frame) {
1033                                 ret = -ENOMEM;
1034                                 goto end;
1035                         }
1036
1037                         frame->key = be32_to_cpu(pklm->key);
1038                         frame->io_virt = be64_to_cpu(pklm->va) + offset;
1039                         frame->bcnt = min_t(size_t, bcnt,
1040                                             be32_to_cpu(pklm->bcount) - offset);
1041                         frame->depth = depth + 1;
1042                         frame->next = head;
1043                         head = frame;
1044
1045                         bcnt -= frame->bcnt;
1046                         offset = 0;
1047                 }
1048                 break;
1049
1050         default:
1051                 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type);
1052                 ret = -EFAULT;
1053                 goto end;
1054         }
1055
1056         if (head) {
1057                 frame = head;
1058                 head = frame->next;
1059
1060                 key = frame->key;
1061                 io_virt = frame->io_virt;
1062                 bcnt = frame->bcnt;
1063                 depth = frame->depth;
1064                 kfree(frame);
1065
1066                 mlx5r_deref_odp_mkey(mmkey);
1067                 goto next_mr;
1068         }
1069
1070 end:
1071         if (mmkey)
1072                 mlx5r_deref_odp_mkey(mmkey);
1073         while (head) {
1074                 frame = head;
1075                 head = frame->next;
1076                 kfree(frame);
1077         }
1078         kfree(out);
1079
1080         *bytes_committed = 0;
1081         return ret ? ret : npages;
1082 }
1083
1084 /*
1085  * Parse a series of data segments for page fault handling.
1086  *
1087  * @dev:  Pointer to mlx5 IB device
1088  * @pfault: contains page fault information.
1089  * @wqe: points at the first data segment in the WQE.
1090  * @wqe_end: points after the end of the WQE.
1091  * @bytes_mapped: receives the number of bytes that the function was able to
1092  *                map. This allows the caller to decide intelligently whether
1093  *                enough memory was mapped to resolve the page fault
1094  *                successfully (e.g. enough for the next MTU, or the entire
1095  *                WQE).
1096  * @total_wqe_bytes: receives the total data size of this WQE in bytes (minus
1097  *                   the committed bytes).
1098  * @receive_queue: receive WQE end of sg list
1099  *
1100  * Returns the number of pages loaded if positive, zero for an empty WQE, or a
1101  * negative error code.
1102  */
1103 static int pagefault_data_segments(struct mlx5_ib_dev *dev,
1104                                    struct mlx5_pagefault *pfault,
1105                                    void *wqe,
1106                                    void *wqe_end, u32 *bytes_mapped,
1107                                    u32 *total_wqe_bytes, bool receive_queue)
1108 {
1109         int ret = 0, npages = 0;
1110         u64 io_virt;
1111         u32 key;
1112         u32 byte_count;
1113         size_t bcnt;
1114         int inline_segment;
1115
1116         if (bytes_mapped)
1117                 *bytes_mapped = 0;
1118         if (total_wqe_bytes)
1119                 *total_wqe_bytes = 0;
1120
1121         while (wqe < wqe_end) {
1122                 struct mlx5_wqe_data_seg *dseg = wqe;
1123
1124                 io_virt = be64_to_cpu(dseg->addr);
1125                 key = be32_to_cpu(dseg->lkey);
1126                 byte_count = be32_to_cpu(dseg->byte_count);
1127                 inline_segment = !!(byte_count &  MLX5_INLINE_SEG);
1128                 bcnt           = byte_count & ~MLX5_INLINE_SEG;
1129
1130                 if (inline_segment) {
1131                         bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
1132                         wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
1133                                      16);
1134                 } else {
1135                         wqe += sizeof(*dseg);
1136                 }
1137
1138                 /* receive WQE end of sg list. */
1139                 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
1140                     io_virt == 0)
1141                         break;
1142
1143                 if (!inline_segment && total_wqe_bytes) {
1144                         *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
1145                                         pfault->bytes_committed);
1146                 }
1147
1148                 /* A zero length data segment designates a length of 2GB. */
1149                 if (bcnt == 0)
1150                         bcnt = 1U << 31;
1151
1152                 if (inline_segment || bcnt <= pfault->bytes_committed) {
1153                         pfault->bytes_committed -=
1154                                 min_t(size_t, bcnt,
1155                                       pfault->bytes_committed);
1156                         continue;
1157                 }
1158
1159                 ret = pagefault_single_data_segment(dev, NULL, key,
1160                                                     io_virt, bcnt,
1161                                                     &pfault->bytes_committed,
1162                                                     bytes_mapped);
1163                 if (ret < 0)
1164                         break;
1165                 npages += ret;
1166         }
1167
1168         return ret < 0 ? ret : npages;
1169 }
1170
1171 /*
1172  * Parse initiator WQE. Advances the wqe pointer to point at the
1173  * scatter-gather list, and set wqe_end to the end of the WQE.
1174  */
1175 static int mlx5_ib_mr_initiator_pfault_handler(
1176         struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
1177         struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
1178 {
1179         struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
1180         u16 wqe_index = pfault->wqe.wqe_index;
1181         struct mlx5_base_av *av;
1182         unsigned ds, opcode;
1183         u32 qpn = qp->trans_qp.base.mqp.qpn;
1184
1185         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
1186         if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
1187                 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
1188                             ds, wqe_length);
1189                 return -EFAULT;
1190         }
1191
1192         if (ds == 0) {
1193                 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
1194                             wqe_index, qpn);
1195                 return -EFAULT;
1196         }
1197
1198         *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
1199         *wqe += sizeof(*ctrl);
1200
1201         opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
1202                  MLX5_WQE_CTRL_OPCODE_MASK;
1203
1204         if (qp->ibqp.qp_type == IB_QPT_XRC_INI)
1205                 *wqe += sizeof(struct mlx5_wqe_xrc_seg);
1206
1207         if (qp->type == IB_QPT_UD || qp->type == MLX5_IB_QPT_DCI) {
1208                 av = *wqe;
1209                 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV))
1210                         *wqe += sizeof(struct mlx5_av);
1211                 else
1212                         *wqe += sizeof(struct mlx5_base_av);
1213         }
1214
1215         switch (opcode) {
1216         case MLX5_OPCODE_RDMA_WRITE:
1217         case MLX5_OPCODE_RDMA_WRITE_IMM:
1218         case MLX5_OPCODE_RDMA_READ:
1219                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1220                 break;
1221         case MLX5_OPCODE_ATOMIC_CS:
1222         case MLX5_OPCODE_ATOMIC_FA:
1223                 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
1224                 *wqe += sizeof(struct mlx5_wqe_atomic_seg);
1225                 break;
1226         }
1227
1228         return 0;
1229 }
1230
1231 /*
1232  * Parse responder WQE and set wqe_end to the end of the WQE.
1233  */
1234 static int mlx5_ib_mr_responder_pfault_handler_srq(struct mlx5_ib_dev *dev,
1235                                                    struct mlx5_ib_srq *srq,
1236                                                    void **wqe, void **wqe_end,
1237                                                    int wqe_length)
1238 {
1239         int wqe_size = 1 << srq->msrq.wqe_shift;
1240
1241         if (wqe_size > wqe_length) {
1242                 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
1243                 return -EFAULT;
1244         }
1245
1246         *wqe_end = *wqe + wqe_size;
1247         *wqe += sizeof(struct mlx5_wqe_srq_next_seg);
1248
1249         return 0;
1250 }
1251
1252 static int mlx5_ib_mr_responder_pfault_handler_rq(struct mlx5_ib_dev *dev,
1253                                                   struct mlx5_ib_qp *qp,
1254                                                   void *wqe, void **wqe_end,
1255                                                   int wqe_length)
1256 {
1257         struct mlx5_ib_wq *wq = &qp->rq;
1258         int wqe_size = 1 << wq->wqe_shift;
1259
1260         if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) {
1261                 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
1262                 return -EFAULT;
1263         }
1264
1265         if (wqe_size > wqe_length) {
1266                 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
1267                 return -EFAULT;
1268         }
1269
1270         *wqe_end = wqe + wqe_size;
1271
1272         return 0;
1273 }
1274
1275 static inline struct mlx5_core_rsc_common *odp_get_rsc(struct mlx5_ib_dev *dev,
1276                                                        u32 wq_num, int pf_type)
1277 {
1278         struct mlx5_core_rsc_common *common = NULL;
1279         struct mlx5_core_srq *srq;
1280
1281         switch (pf_type) {
1282         case MLX5_WQE_PF_TYPE_RMP:
1283                 srq = mlx5_cmd_get_srq(dev, wq_num);
1284                 if (srq)
1285                         common = &srq->common;
1286                 break;
1287         case MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE:
1288         case MLX5_WQE_PF_TYPE_RESP:
1289         case MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC:
1290                 common = mlx5_core_res_hold(dev, wq_num, MLX5_RES_QP);
1291                 break;
1292         default:
1293                 break;
1294         }
1295
1296         return common;
1297 }
1298
1299 static inline struct mlx5_ib_qp *res_to_qp(struct mlx5_core_rsc_common *res)
1300 {
1301         struct mlx5_core_qp *mqp = (struct mlx5_core_qp *)res;
1302
1303         return to_mibqp(mqp);
1304 }
1305
1306 static inline struct mlx5_ib_srq *res_to_srq(struct mlx5_core_rsc_common *res)
1307 {
1308         struct mlx5_core_srq *msrq =
1309                 container_of(res, struct mlx5_core_srq, common);
1310
1311         return to_mibsrq(msrq);
1312 }
1313
1314 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev,
1315                                           struct mlx5_pagefault *pfault)
1316 {
1317         bool sq = pfault->type & MLX5_PFAULT_REQUESTOR;
1318         u16 wqe_index = pfault->wqe.wqe_index;
1319         void *wqe, *wqe_start = NULL, *wqe_end = NULL;
1320         u32 bytes_mapped, total_wqe_bytes;
1321         struct mlx5_core_rsc_common *res;
1322         int resume_with_error = 1;
1323         struct mlx5_ib_qp *qp;
1324         size_t bytes_copied;
1325         int ret = 0;
1326
1327         res = odp_get_rsc(dev, pfault->wqe.wq_num, pfault->type);
1328         if (!res) {
1329                 mlx5_ib_dbg(dev, "wqe page fault for missing resource %d\n", pfault->wqe.wq_num);
1330                 return;
1331         }
1332
1333         if (res->res != MLX5_RES_QP && res->res != MLX5_RES_SRQ &&
1334             res->res != MLX5_RES_XSRQ) {
1335                 mlx5_ib_err(dev, "wqe page fault for unsupported type %d\n",
1336                             pfault->type);
1337                 goto resolve_page_fault;
1338         }
1339
1340         wqe_start = (void *)__get_free_page(GFP_KERNEL);
1341         if (!wqe_start) {
1342                 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
1343                 goto resolve_page_fault;
1344         }
1345
1346         wqe = wqe_start;
1347         qp = (res->res == MLX5_RES_QP) ? res_to_qp(res) : NULL;
1348         if (qp && sq) {
1349                 ret = mlx5_ib_read_wqe_sq(qp, wqe_index, wqe, PAGE_SIZE,
1350                                           &bytes_copied);
1351                 if (ret)
1352                         goto read_user;
1353                 ret = mlx5_ib_mr_initiator_pfault_handler(
1354                         dev, pfault, qp, &wqe, &wqe_end, bytes_copied);
1355         } else if (qp && !sq) {
1356                 ret = mlx5_ib_read_wqe_rq(qp, wqe_index, wqe, PAGE_SIZE,
1357                                           &bytes_copied);
1358                 if (ret)
1359                         goto read_user;
1360                 ret = mlx5_ib_mr_responder_pfault_handler_rq(
1361                         dev, qp, wqe, &wqe_end, bytes_copied);
1362         } else if (!qp) {
1363                 struct mlx5_ib_srq *srq = res_to_srq(res);
1364
1365                 ret = mlx5_ib_read_wqe_srq(srq, wqe_index, wqe, PAGE_SIZE,
1366                                            &bytes_copied);
1367                 if (ret)
1368                         goto read_user;
1369                 ret = mlx5_ib_mr_responder_pfault_handler_srq(
1370                         dev, srq, &wqe, &wqe_end, bytes_copied);
1371         }
1372
1373         if (ret < 0 || wqe >= wqe_end)
1374                 goto resolve_page_fault;
1375
1376         ret = pagefault_data_segments(dev, pfault, wqe, wqe_end, &bytes_mapped,
1377                                       &total_wqe_bytes, !sq);
1378         if (ret == -EAGAIN)
1379                 goto out;
1380
1381         if (ret < 0 || total_wqe_bytes > bytes_mapped)
1382                 goto resolve_page_fault;
1383
1384 out:
1385         ret = 0;
1386         resume_with_error = 0;
1387
1388 read_user:
1389         if (ret)
1390                 mlx5_ib_err(
1391                         dev,
1392                         "Failed reading a WQE following page fault, error %d, wqe_index %x, qpn %x\n",
1393                         ret, wqe_index, pfault->token);
1394
1395 resolve_page_fault:
1396         mlx5_ib_page_fault_resume(dev, pfault, resume_with_error);
1397         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n",
1398                     pfault->wqe.wq_num, resume_with_error,
1399                     pfault->type);
1400         mlx5_core_res_put(res);
1401         free_page((unsigned long)wqe_start);
1402 }
1403
1404 static int pages_in_range(u64 address, u32 length)
1405 {
1406         return (ALIGN(address + length, PAGE_SIZE) -
1407                 (address & PAGE_MASK)) >> PAGE_SHIFT;
1408 }
1409
1410 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
1411                                            struct mlx5_pagefault *pfault)
1412 {
1413         u64 address;
1414         u32 length;
1415         u32 prefetch_len = pfault->bytes_committed;
1416         int prefetch_activated = 0;
1417         u32 rkey = pfault->rdma.r_key;
1418         int ret;
1419
1420         /* The RDMA responder handler handles the page fault in two parts.
1421          * First it brings the necessary pages for the current packet
1422          * (and uses the pfault context), and then (after resuming the QP)
1423          * prefetches more pages. The second operation cannot use the pfault
1424          * context and therefore uses the dummy_pfault context allocated on
1425          * the stack */
1426         pfault->rdma.rdma_va += pfault->bytes_committed;
1427         pfault->rdma.rdma_op_len -= min(pfault->bytes_committed,
1428                                          pfault->rdma.rdma_op_len);
1429         pfault->bytes_committed = 0;
1430
1431         address = pfault->rdma.rdma_va;
1432         length  = pfault->rdma.rdma_op_len;
1433
1434         /* For some operations, the hardware cannot tell the exact message
1435          * length, and in those cases it reports zero. Use prefetch
1436          * logic. */
1437         if (length == 0) {
1438                 prefetch_activated = 1;
1439                 length = pfault->rdma.packet_size;
1440                 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
1441         }
1442
1443         ret = pagefault_single_data_segment(dev, NULL, rkey, address, length,
1444                                             &pfault->bytes_committed, NULL);
1445         if (ret == -EAGAIN) {
1446                 /* We're racing with an invalidation, don't prefetch */
1447                 prefetch_activated = 0;
1448         } else if (ret < 0 || pages_in_range(address, length) > ret) {
1449                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1450                 if (ret != -ENOENT)
1451                         mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n",
1452                                     ret, pfault->token, pfault->type);
1453                 return;
1454         }
1455
1456         mlx5_ib_page_fault_resume(dev, pfault, 0);
1457         mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n",
1458                     pfault->token, pfault->type,
1459                     prefetch_activated);
1460
1461         /* At this point, there might be a new pagefault already arriving in
1462          * the eq, switch to the dummy pagefault for the rest of the
1463          * processing. We're still OK with the objects being alive as the
1464          * work-queue is being fenced. */
1465
1466         if (prefetch_activated) {
1467                 u32 bytes_committed = 0;
1468
1469                 ret = pagefault_single_data_segment(dev, NULL, rkey, address,
1470                                                     prefetch_len,
1471                                                     &bytes_committed, NULL);
1472                 if (ret < 0 && ret != -EAGAIN) {
1473                         mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n",
1474                                     ret, pfault->token, address, prefetch_len);
1475                 }
1476         }
1477 }
1478
1479 static void mlx5_ib_pfault(struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault)
1480 {
1481         u8 event_subtype = pfault->event_subtype;
1482
1483         switch (event_subtype) {
1484         case MLX5_PFAULT_SUBTYPE_WQE:
1485                 mlx5_ib_mr_wqe_pfault_handler(dev, pfault);
1486                 break;
1487         case MLX5_PFAULT_SUBTYPE_RDMA:
1488                 mlx5_ib_mr_rdma_pfault_handler(dev, pfault);
1489                 break;
1490         default:
1491                 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n",
1492                             event_subtype);
1493                 mlx5_ib_page_fault_resume(dev, pfault, 1);
1494         }
1495 }
1496
1497 static void mlx5_ib_eqe_pf_action(struct work_struct *work)
1498 {
1499         struct mlx5_pagefault *pfault = container_of(work,
1500                                                      struct mlx5_pagefault,
1501                                                      work);
1502         struct mlx5_ib_pf_eq *eq = pfault->eq;
1503
1504         mlx5_ib_pfault(eq->dev, pfault);
1505         mempool_free(pfault, eq->pool);
1506 }
1507
1508 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq)
1509 {
1510         struct mlx5_eqe_page_fault *pf_eqe;
1511         struct mlx5_pagefault *pfault;
1512         struct mlx5_eqe *eqe;
1513         int cc = 0;
1514
1515         while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) {
1516                 pfault = mempool_alloc(eq->pool, GFP_ATOMIC);
1517                 if (!pfault) {
1518                         schedule_work(&eq->work);
1519                         break;
1520                 }
1521
1522                 pf_eqe = &eqe->data.page_fault;
1523                 pfault->event_subtype = eqe->sub_type;
1524                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
1525
1526                 mlx5_ib_dbg(eq->dev,
1527                             "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
1528                             eqe->sub_type, pfault->bytes_committed);
1529
1530                 switch (eqe->sub_type) {
1531                 case MLX5_PFAULT_SUBTYPE_RDMA:
1532                         /* RDMA based event */
1533                         pfault->type =
1534                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
1535                         pfault->token =
1536                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
1537                                 MLX5_24BIT_MASK;
1538                         pfault->rdma.r_key =
1539                                 be32_to_cpu(pf_eqe->rdma.r_key);
1540                         pfault->rdma.packet_size =
1541                                 be16_to_cpu(pf_eqe->rdma.packet_length);
1542                         pfault->rdma.rdma_op_len =
1543                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
1544                         pfault->rdma.rdma_va =
1545                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
1546                         mlx5_ib_dbg(eq->dev,
1547                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
1548                                     pfault->type, pfault->token,
1549                                     pfault->rdma.r_key);
1550                         mlx5_ib_dbg(eq->dev,
1551                                     "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
1552                                     pfault->rdma.rdma_op_len,
1553                                     pfault->rdma.rdma_va);
1554                         break;
1555
1556                 case MLX5_PFAULT_SUBTYPE_WQE:
1557                         /* WQE based event */
1558                         pfault->type =
1559                                 (be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24) & 0x7;
1560                         pfault->token =
1561                                 be32_to_cpu(pf_eqe->wqe.token);
1562                         pfault->wqe.wq_num =
1563                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
1564                                 MLX5_24BIT_MASK;
1565                         pfault->wqe.wqe_index =
1566                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
1567                         pfault->wqe.packet_size =
1568                                 be16_to_cpu(pf_eqe->wqe.packet_length);
1569                         mlx5_ib_dbg(eq->dev,
1570                                     "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
1571                                     pfault->type, pfault->token,
1572                                     pfault->wqe.wq_num,
1573                                     pfault->wqe.wqe_index);
1574                         break;
1575
1576                 default:
1577                         mlx5_ib_warn(eq->dev,
1578                                      "Unsupported page fault event sub-type: 0x%02hhx\n",
1579                                      eqe->sub_type);
1580                         /* Unsupported page faults should still be
1581                          * resolved by the page fault handler
1582                          */
1583                 }
1584
1585                 pfault->eq = eq;
1586                 INIT_WORK(&pfault->work, mlx5_ib_eqe_pf_action);
1587                 queue_work(eq->wq, &pfault->work);
1588
1589                 cc = mlx5_eq_update_cc(eq->core, ++cc);
1590         }
1591
1592         mlx5_eq_update_ci(eq->core, cc, 1);
1593 }
1594
1595 static int mlx5_ib_eq_pf_int(struct notifier_block *nb, unsigned long type,
1596                              void *data)
1597 {
1598         struct mlx5_ib_pf_eq *eq =
1599                 container_of(nb, struct mlx5_ib_pf_eq, irq_nb);
1600         unsigned long flags;
1601
1602         if (spin_trylock_irqsave(&eq->lock, flags)) {
1603                 mlx5_ib_eq_pf_process(eq);
1604                 spin_unlock_irqrestore(&eq->lock, flags);
1605         } else {
1606                 schedule_work(&eq->work);
1607         }
1608
1609         return IRQ_HANDLED;
1610 }
1611
1612 /* mempool_refill() was proposed but unfortunately wasn't accepted
1613  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
1614  * Cheap workaround.
1615  */
1616 static void mempool_refill(mempool_t *pool)
1617 {
1618         while (pool->curr_nr < pool->min_nr)
1619                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
1620 }
1621
1622 static void mlx5_ib_eq_pf_action(struct work_struct *work)
1623 {
1624         struct mlx5_ib_pf_eq *eq =
1625                 container_of(work, struct mlx5_ib_pf_eq, work);
1626
1627         mempool_refill(eq->pool);
1628
1629         spin_lock_irq(&eq->lock);
1630         mlx5_ib_eq_pf_process(eq);
1631         spin_unlock_irq(&eq->lock);
1632 }
1633
1634 enum {
1635         MLX5_IB_NUM_PF_EQE      = 0x1000,
1636         MLX5_IB_NUM_PF_DRAIN    = 64,
1637 };
1638
1639 static int
1640 mlx5_ib_create_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1641 {
1642         struct mlx5_eq_param param = {};
1643         int err;
1644
1645         INIT_WORK(&eq->work, mlx5_ib_eq_pf_action);
1646         spin_lock_init(&eq->lock);
1647         eq->dev = dev;
1648
1649         eq->pool = mempool_create_kmalloc_pool(MLX5_IB_NUM_PF_DRAIN,
1650                                                sizeof(struct mlx5_pagefault));
1651         if (!eq->pool)
1652                 return -ENOMEM;
1653
1654         eq->wq = alloc_workqueue("mlx5_ib_page_fault",
1655                                  WQ_HIGHPRI | WQ_UNBOUND | WQ_MEM_RECLAIM,
1656                                  MLX5_NUM_CMD_EQE);
1657         if (!eq->wq) {
1658                 err = -ENOMEM;
1659                 goto err_mempool;
1660         }
1661
1662         eq->irq_nb.notifier_call = mlx5_ib_eq_pf_int;
1663         param = (struct mlx5_eq_param) {
1664                 .irq_index = 0,
1665                 .nent = MLX5_IB_NUM_PF_EQE,
1666         };
1667         param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_FAULT;
1668         eq->core = mlx5_eq_create_generic(dev->mdev, &param);
1669         if (IS_ERR(eq->core)) {
1670                 err = PTR_ERR(eq->core);
1671                 goto err_wq;
1672         }
1673         err = mlx5_eq_enable(dev->mdev, eq->core, &eq->irq_nb);
1674         if (err) {
1675                 mlx5_ib_err(dev, "failed to enable odp EQ %d\n", err);
1676                 goto err_eq;
1677         }
1678
1679         return 0;
1680 err_eq:
1681         mlx5_eq_destroy_generic(dev->mdev, eq->core);
1682 err_wq:
1683         destroy_workqueue(eq->wq);
1684 err_mempool:
1685         mempool_destroy(eq->pool);
1686         return err;
1687 }
1688
1689 static int
1690 mlx5_ib_destroy_pf_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq)
1691 {
1692         int err;
1693
1694         mlx5_eq_disable(dev->mdev, eq->core, &eq->irq_nb);
1695         err = mlx5_eq_destroy_generic(dev->mdev, eq->core);
1696         cancel_work_sync(&eq->work);
1697         destroy_workqueue(eq->wq);
1698         mempool_destroy(eq->pool);
1699
1700         return err;
1701 }
1702
1703 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent)
1704 {
1705         if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1706                 return;
1707
1708         switch (ent->order - 2) {
1709         case MLX5_IMR_MTT_CACHE_ENTRY:
1710                 ent->page = PAGE_SHIFT;
1711                 ent->xlt = MLX5_IMR_MTT_ENTRIES *
1712                            sizeof(struct mlx5_mtt) /
1713                            MLX5_IB_UMR_OCTOWORD;
1714                 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1715                 ent->limit = 0;
1716                 break;
1717
1718         case MLX5_IMR_KSM_CACHE_ENTRY:
1719                 ent->page = MLX5_KSM_PAGE_SHIFT;
1720                 ent->xlt = mlx5_imr_ksm_entries *
1721                            sizeof(struct mlx5_klm) /
1722                            MLX5_IB_UMR_OCTOWORD;
1723                 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;
1724                 ent->limit = 0;
1725                 break;
1726         }
1727 }
1728
1729 static const struct ib_device_ops mlx5_ib_dev_odp_ops = {
1730         .advise_mr = mlx5_ib_advise_mr,
1731 };
1732
1733 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev)
1734 {
1735         int ret = 0;
1736
1737         if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT))
1738                 return ret;
1739
1740         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_odp_ops);
1741
1742         if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) {
1743                 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey);
1744                 if (ret) {
1745                         mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret);
1746                         return ret;
1747                 }
1748         }
1749
1750         ret = mlx5_ib_create_pf_eq(dev, &dev->odp_pf_eq);
1751
1752         return ret;
1753 }
1754
1755 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *dev)
1756 {
1757         if (!(dev->odp_caps.general_caps & IB_ODP_SUPPORT))
1758                 return;
1759
1760         mlx5_ib_destroy_pf_eq(dev, &dev->odp_pf_eq);
1761 }
1762
1763 int mlx5_ib_odp_init(void)
1764 {
1765         mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) -
1766                                        MLX5_IMR_MTT_BITS);
1767
1768         return 0;
1769 }
1770
1771 struct prefetch_mr_work {
1772         struct work_struct work;
1773         u32 pf_flags;
1774         u32 num_sge;
1775         struct {
1776                 u64 io_virt;
1777                 struct mlx5_ib_mr *mr;
1778                 size_t length;
1779         } frags[];
1780 };
1781
1782 static void destroy_prefetch_work(struct prefetch_mr_work *work)
1783 {
1784         u32 i;
1785
1786         for (i = 0; i < work->num_sge; ++i)
1787                 mlx5r_deref_odp_mkey(&work->frags[i].mr->mmkey);
1788
1789         kvfree(work);
1790 }
1791
1792 static struct mlx5_ib_mr *
1793 get_prefetchable_mr(struct ib_pd *pd, enum ib_uverbs_advise_mr_advice advice,
1794                     u32 lkey)
1795 {
1796         struct mlx5_ib_dev *dev = to_mdev(pd->device);
1797         struct mlx5_core_mkey *mmkey;
1798         struct mlx5_ib_mr *mr = NULL;
1799
1800         xa_lock(&dev->odp_mkeys);
1801         mmkey = xa_load(&dev->odp_mkeys, mlx5_base_mkey(lkey));
1802         if (!mmkey || mmkey->key != lkey || mmkey->type != MLX5_MKEY_MR)
1803                 goto end;
1804
1805         mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
1806
1807         if (mr->ibmr.pd != pd) {
1808                 mr = NULL;
1809                 goto end;
1810         }
1811
1812         /* prefetch with write-access must be supported by the MR */
1813         if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE &&
1814             !mr->umem->writable) {
1815                 mr = NULL;
1816                 goto end;
1817         }
1818
1819         refcount_inc(&mmkey->usecount);
1820 end:
1821         xa_unlock(&dev->odp_mkeys);
1822         return mr;
1823 }
1824
1825 static void mlx5_ib_prefetch_mr_work(struct work_struct *w)
1826 {
1827         struct prefetch_mr_work *work =
1828                 container_of(w, struct prefetch_mr_work, work);
1829         u32 bytes_mapped = 0;
1830         int ret;
1831         u32 i;
1832
1833         /* We rely on IB/core that work is executed if we have num_sge != 0 only. */
1834         WARN_ON(!work->num_sge);
1835         for (i = 0; i < work->num_sge; ++i) {
1836                 ret = pagefault_mr(work->frags[i].mr, work->frags[i].io_virt,
1837                                    work->frags[i].length, &bytes_mapped,
1838                                    work->pf_flags);
1839                 if (ret <= 0)
1840                         continue;
1841                 mlx5_update_odp_stats(work->frags[i].mr, prefetch, ret);
1842         }
1843
1844         destroy_prefetch_work(work);
1845 }
1846
1847 static bool init_prefetch_work(struct ib_pd *pd,
1848                                enum ib_uverbs_advise_mr_advice advice,
1849                                u32 pf_flags, struct prefetch_mr_work *work,
1850                                struct ib_sge *sg_list, u32 num_sge)
1851 {
1852         u32 i;
1853
1854         INIT_WORK(&work->work, mlx5_ib_prefetch_mr_work);
1855         work->pf_flags = pf_flags;
1856
1857         for (i = 0; i < num_sge; ++i) {
1858                 work->frags[i].io_virt = sg_list[i].addr;
1859                 work->frags[i].length = sg_list[i].length;
1860                 work->frags[i].mr =
1861                         get_prefetchable_mr(pd, advice, sg_list[i].lkey);
1862                 if (!work->frags[i].mr) {
1863                         work->num_sge = i;
1864                         return false;
1865                 }
1866         }
1867         work->num_sge = num_sge;
1868         return true;
1869 }
1870
1871 static int mlx5_ib_prefetch_sg_list(struct ib_pd *pd,
1872                                     enum ib_uverbs_advise_mr_advice advice,
1873                                     u32 pf_flags, struct ib_sge *sg_list,
1874                                     u32 num_sge)
1875 {
1876         u32 bytes_mapped = 0;
1877         int ret = 0;
1878         u32 i;
1879
1880         for (i = 0; i < num_sge; ++i) {
1881                 struct mlx5_ib_mr *mr;
1882
1883                 mr = get_prefetchable_mr(pd, advice, sg_list[i].lkey);
1884                 if (!mr)
1885                         return -ENOENT;
1886                 ret = pagefault_mr(mr, sg_list[i].addr, sg_list[i].length,
1887                                    &bytes_mapped, pf_flags);
1888                 if (ret < 0) {
1889                         mlx5r_deref_odp_mkey(&mr->mmkey);
1890                         return ret;
1891                 }
1892                 mlx5_update_odp_stats(mr, prefetch, ret);
1893                 mlx5r_deref_odp_mkey(&mr->mmkey);
1894         }
1895
1896         return 0;
1897 }
1898
1899 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1900                                enum ib_uverbs_advise_mr_advice advice,
1901                                u32 flags, struct ib_sge *sg_list, u32 num_sge)
1902 {
1903         u32 pf_flags = 0;
1904         struct prefetch_mr_work *work;
1905
1906         if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH)
1907                 pf_flags |= MLX5_PF_FLAGS_DOWNGRADE;
1908
1909         if (advice == IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT)
1910                 pf_flags |= MLX5_PF_FLAGS_SNAPSHOT;
1911
1912         if (flags & IB_UVERBS_ADVISE_MR_FLAG_FLUSH)
1913                 return mlx5_ib_prefetch_sg_list(pd, advice, pf_flags, sg_list,
1914                                                 num_sge);
1915
1916         work = kvzalloc(struct_size(work, frags, num_sge), GFP_KERNEL);
1917         if (!work)
1918                 return -ENOMEM;
1919
1920         if (!init_prefetch_work(pd, advice, pf_flags, work, sg_list, num_sge)) {
1921                 destroy_prefetch_work(work);
1922                 return -EINVAL;
1923         }
1924         queue_work(system_unbound_wq, &work->work);
1925         return 0;
1926 }