1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
7 #include <linux/debugfs.h>
8 #include <linux/highmem.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/slab.h>
15 #include <linux/bitmap.h>
16 #include <linux/sched.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/task.h>
19 #include <linux/delay.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/ib_addr.h>
22 #include <rdma/ib_cache.h>
23 #include <linux/mlx5/port.h>
24 #include <linux/mlx5/vport.h>
25 #include <linux/mlx5/fs.h>
26 #include <linux/mlx5/eswitch.h>
27 #include <linux/list.h>
28 #include <rdma/ib_smi.h>
29 #include <rdma/ib_umem.h>
32 #include <linux/etherdevice.h>
44 #include <linux/mlx5/accel.h>
45 #include <rdma/uverbs_std_types.h>
46 #include <rdma/uverbs_ioctl.h>
47 #include <rdma/mlx5_user_ioctl_verbs.h>
48 #include <rdma/mlx5_user_ioctl_cmds.h>
49 #include <rdma/ib_umem_odp.h>
51 #define UVERBS_MODULE_NAME mlx5_ib
52 #include <rdma/uverbs_named_ioctl.h>
54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
56 MODULE_LICENSE("Dual BSD/GPL");
58 struct mlx5_ib_event_work {
59 struct work_struct work;
61 struct mlx5_ib_dev *dev;
62 struct mlx5_ib_multiport_info *mpi;
70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
73 static struct workqueue_struct *mlx5_ib_event_wq;
74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
75 static LIST_HEAD(mlx5_ib_dev_list);
77 * This mutex should be held when accessing either of the above lists
79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
83 struct mlx5_ib_dev *dev;
85 mutex_lock(&mlx5_ib_multiport_mutex);
87 mutex_unlock(&mlx5_ib_multiport_mutex);
91 static enum rdma_link_layer
92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
94 switch (port_type_cap) {
95 case MLX5_CAP_PORT_TYPE_IB:
96 return IB_LINK_LAYER_INFINIBAND;
97 case MLX5_CAP_PORT_TYPE_ETH:
98 return IB_LINK_LAYER_ETHERNET;
100 return IB_LINK_LAYER_UNSPECIFIED;
104 static enum rdma_link_layer
105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
107 struct mlx5_ib_dev *dev = to_mdev(device);
108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
113 static int get_port_state(struct ib_device *ibdev,
115 enum ib_port_state *state)
117 struct ib_port_attr attr;
120 memset(&attr, 0, sizeof(attr));
121 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
128 struct net_device *ndev,
131 struct net_device *rep_ndev;
132 struct mlx5_ib_port *port;
135 for (i = 0; i < dev->num_ports; i++) {
136 port = &dev->port[i];
140 read_lock(&port->roce.netdev_lock);
141 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
143 if (rep_ndev == ndev) {
144 read_unlock(&port->roce.netdev_lock);
148 read_unlock(&port->roce.netdev_lock);
154 static int mlx5_netdev_event(struct notifier_block *this,
155 unsigned long event, void *ptr)
157 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
158 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
159 u32 port_num = roce->native_port_num;
160 struct mlx5_core_dev *mdev;
161 struct mlx5_ib_dev *ibdev;
164 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
169 case NETDEV_REGISTER:
170 /* Should already be registered during the load */
173 write_lock(&roce->netdev_lock);
174 if (ndev->dev.parent == mdev->device)
176 write_unlock(&roce->netdev_lock);
179 case NETDEV_UNREGISTER:
180 /* In case of reps, ib device goes away before the netdevs */
181 write_lock(&roce->netdev_lock);
182 if (roce->netdev == ndev)
184 write_unlock(&roce->netdev_lock);
190 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
191 struct net_device *upper = NULL;
194 upper = netdev_master_upper_dev_get(lag_ndev);
199 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
202 if ((upper == ndev || (!upper && ndev == roce->netdev))
203 && ibdev->ib_active) {
204 struct ib_event ibev = { };
205 enum ib_port_state port_state;
207 if (get_port_state(&ibdev->ib_dev, port_num,
211 if (roce->last_port_state == port_state)
214 roce->last_port_state = port_state;
215 ibev.device = &ibdev->ib_dev;
216 if (port_state == IB_PORT_DOWN)
217 ibev.event = IB_EVENT_PORT_ERR;
218 else if (port_state == IB_PORT_ACTIVE)
219 ibev.event = IB_EVENT_PORT_ACTIVE;
223 ibev.element.port_num = port_num;
224 ib_dispatch_event(&ibev);
233 mlx5_ib_put_native_port_mdev(ibdev, port_num);
237 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
240 struct mlx5_ib_dev *ibdev = to_mdev(device);
241 struct net_device *ndev;
242 struct mlx5_core_dev *mdev;
244 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
248 ndev = mlx5_lag_get_roce_netdev(mdev);
252 /* Ensure ndev does not disappear before we invoke dev_hold()
254 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
255 ndev = ibdev->port[port_num - 1].roce.netdev;
258 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
261 mlx5_ib_put_native_port_mdev(ibdev, port_num);
265 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
267 u32 *native_port_num)
269 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
271 struct mlx5_core_dev *mdev = NULL;
272 struct mlx5_ib_multiport_info *mpi;
273 struct mlx5_ib_port *port;
275 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
276 ll != IB_LINK_LAYER_ETHERNET) {
278 *native_port_num = ib_port_num;
283 *native_port_num = 1;
285 port = &ibdev->port[ib_port_num - 1];
286 spin_lock(&port->mp.mpi_lock);
287 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
288 if (mpi && !mpi->unaffiliate) {
290 /* If it's the master no need to refcount, it'll exist
291 * as long as the ib_dev exists.
296 spin_unlock(&port->mp.mpi_lock);
301 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 struct mlx5_ib_multiport_info *mpi;
306 struct mlx5_ib_port *port;
308 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
311 port = &ibdev->port[port_num - 1];
313 spin_lock(&port->mp.mpi_lock);
314 mpi = ibdev->port[port_num - 1].mp.mpi;
319 if (mpi->unaffiliate)
320 complete(&mpi->unref_comp);
322 spin_unlock(&port->mp.mpi_lock);
325 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
326 u16 *active_speed, u8 *active_width)
328 switch (eth_proto_oper) {
329 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
331 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
332 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
333 *active_width = IB_WIDTH_1X;
334 *active_speed = IB_SPEED_SDR;
336 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
343 *active_width = IB_WIDTH_1X;
344 *active_speed = IB_SPEED_QDR;
346 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
349 *active_width = IB_WIDTH_1X;
350 *active_speed = IB_SPEED_EDR;
352 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
356 *active_width = IB_WIDTH_4X;
357 *active_speed = IB_SPEED_QDR;
359 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
362 *active_width = IB_WIDTH_1X;
363 *active_speed = IB_SPEED_HDR;
365 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
366 *active_width = IB_WIDTH_4X;
367 *active_speed = IB_SPEED_FDR;
369 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
373 *active_width = IB_WIDTH_4X;
374 *active_speed = IB_SPEED_EDR;
383 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
386 switch (eth_proto_oper) {
387 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
388 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
389 *active_width = IB_WIDTH_1X;
390 *active_speed = IB_SPEED_SDR;
392 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
393 *active_width = IB_WIDTH_1X;
394 *active_speed = IB_SPEED_DDR;
396 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_QDR;
400 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_QDR;
404 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
405 *active_width = IB_WIDTH_1X;
406 *active_speed = IB_SPEED_EDR;
408 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
409 *active_width = IB_WIDTH_2X;
410 *active_speed = IB_SPEED_EDR;
412 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
413 *active_width = IB_WIDTH_1X;
414 *active_speed = IB_SPEED_HDR;
416 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
417 *active_width = IB_WIDTH_4X;
418 *active_speed = IB_SPEED_EDR;
420 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
421 *active_width = IB_WIDTH_2X;
422 *active_speed = IB_SPEED_HDR;
424 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
425 *active_width = IB_WIDTH_1X;
426 *active_speed = IB_SPEED_NDR;
428 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
429 *active_width = IB_WIDTH_4X;
430 *active_speed = IB_SPEED_HDR;
432 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
433 *active_width = IB_WIDTH_2X;
434 *active_speed = IB_SPEED_NDR;
436 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
437 *active_width = IB_WIDTH_4X;
438 *active_speed = IB_SPEED_NDR;
447 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
448 u8 *active_width, bool ext)
451 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
453 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
457 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
458 struct ib_port_attr *props)
460 struct mlx5_ib_dev *dev = to_mdev(device);
461 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
462 struct mlx5_core_dev *mdev;
463 struct net_device *ndev, *upper;
464 enum ib_mtu ndev_ib_mtu;
465 bool put_mdev = true;
471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
473 /* This means the port isn't affiliated yet. Get the
474 * info for the master port instead.
482 /* Possible bad flows are checked before filling out props so in case
483 * of an error it will still be zeroed out.
484 * Use native port in case of reps
487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
497 props->active_width = IB_WIDTH_4X;
498 props->active_speed = IB_SPEED_QDR;
500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
501 &props->active_width, ext);
503 if (!dev->is_rep && dev->mdev->roce.roce_en) {
506 props->port_cap_flags |= IB_PORT_CM_SUP;
507 props->ip_gids = true;
508 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
509 roce_address_table_size);
510 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
511 props->qkey_viol_cntr = qkey_viol_cntr;
513 props->max_mtu = IB_MTU_4096;
514 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
515 props->pkey_tbl_len = 1;
516 props->state = IB_PORT_DOWN;
517 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
519 /* If this is a stub query for an unaffiliated port stop here */
523 ndev = mlx5_ib_get_netdev(device, port_num);
527 if (dev->lag_active) {
529 upper = netdev_master_upper_dev_get_rcu(ndev);
538 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
539 props->state = IB_PORT_ACTIVE;
540 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
543 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
547 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
550 mlx5_ib_put_native_port_mdev(dev, port_num);
554 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
555 unsigned int index, const union ib_gid *gid,
556 const struct ib_gid_attr *attr)
558 enum ib_gid_type gid_type;
559 u16 vlan_id = 0xffff;
565 gid_type = attr->gid_type;
567 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
573 case IB_GID_TYPE_ROCE:
574 roce_version = MLX5_ROCE_VERSION_1;
576 case IB_GID_TYPE_ROCE_UDP_ENCAP:
577 roce_version = MLX5_ROCE_VERSION_2;
578 if (gid && ipv6_addr_v4mapped((void *)gid))
579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
581 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
585 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
588 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
589 roce_l3_type, gid->raw, mac,
590 vlan_id < VLAN_CFI_MASK, vlan_id,
594 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
595 __always_unused void **context)
597 return set_roce_addr(to_mdev(attr->device), attr->port_num,
598 attr->index, &attr->gid, attr);
601 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
602 __always_unused void **context)
604 return set_roce_addr(to_mdev(attr->device), attr->port_num,
605 attr->index, NULL, attr);
608 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
609 const struct ib_gid_attr *attr)
611 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
614 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
617 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
619 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
620 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
625 MLX5_VPORT_ACCESS_METHOD_MAD,
626 MLX5_VPORT_ACCESS_METHOD_HCA,
627 MLX5_VPORT_ACCESS_METHOD_NIC,
630 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
632 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
633 return MLX5_VPORT_ACCESS_METHOD_MAD;
635 if (mlx5_ib_port_link_layer(ibdev, 1) ==
636 IB_LINK_LAYER_ETHERNET)
637 return MLX5_VPORT_ACCESS_METHOD_NIC;
639 return MLX5_VPORT_ACCESS_METHOD_HCA;
642 static void get_atomic_caps(struct mlx5_ib_dev *dev,
644 struct ib_device_attr *props)
647 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
648 u8 atomic_req_8B_endianness_mode =
649 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
651 /* Check if HW supports 8 bytes standard atomic operations and capable
652 * of host endianness respond
654 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
655 if (((atomic_operations & tmp) == tmp) &&
656 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
657 (atomic_req_8B_endianness_mode)) {
658 props->atomic_cap = IB_ATOMIC_HCA;
660 props->atomic_cap = IB_ATOMIC_NONE;
664 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
665 struct ib_device_attr *props)
667 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
669 get_atomic_caps(dev, atomic_size_qp, props);
672 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
673 __be64 *sys_image_guid)
675 struct mlx5_ib_dev *dev = to_mdev(ibdev);
676 struct mlx5_core_dev *mdev = dev->mdev;
680 switch (mlx5_get_vport_access_method(ibdev)) {
681 case MLX5_VPORT_ACCESS_METHOD_MAD:
682 return mlx5_query_mad_ifc_system_image_guid(ibdev,
685 case MLX5_VPORT_ACCESS_METHOD_HCA:
686 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
689 case MLX5_VPORT_ACCESS_METHOD_NIC:
690 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
698 *sys_image_guid = cpu_to_be64(tmp);
704 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
707 struct mlx5_ib_dev *dev = to_mdev(ibdev);
708 struct mlx5_core_dev *mdev = dev->mdev;
710 switch (mlx5_get_vport_access_method(ibdev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 case MLX5_VPORT_ACCESS_METHOD_NIC:
716 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
725 static int mlx5_query_vendor_id(struct ib_device *ibdev,
728 struct mlx5_ib_dev *dev = to_mdev(ibdev);
730 switch (mlx5_get_vport_access_method(ibdev)) {
731 case MLX5_VPORT_ACCESS_METHOD_MAD:
732 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
734 case MLX5_VPORT_ACCESS_METHOD_HCA:
735 case MLX5_VPORT_ACCESS_METHOD_NIC:
736 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
743 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
749 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
766 *node_guid = cpu_to_be64(tmp);
771 struct mlx5_reg_node_desc {
772 u8 desc[IB_DEVICE_NODE_DESC_MAX];
775 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
777 struct mlx5_reg_node_desc in;
779 if (mlx5_use_mad_ifc(dev))
780 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
782 memset(&in, 0, sizeof(in));
784 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
785 sizeof(struct mlx5_reg_node_desc),
786 MLX5_REG_NODE_DESC, 0, 0);
789 static int mlx5_ib_query_device(struct ib_device *ibdev,
790 struct ib_device_attr *props,
791 struct ib_udata *uhw)
793 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
794 struct mlx5_ib_dev *dev = to_mdev(ibdev);
795 struct mlx5_core_dev *mdev = dev->mdev;
800 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
801 bool raw_support = !mlx5_core_mp_enabled(mdev);
802 struct mlx5_ib_query_device_resp resp = {};
806 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
807 if (uhw_outlen && uhw_outlen < resp_len)
810 resp.response_length = resp_len;
812 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
815 memset(props, 0, sizeof(*props));
816 err = mlx5_query_system_image_guid(ibdev,
817 &props->sys_image_guid);
821 props->max_pkeys = dev->pkey_table_len;
823 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
827 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
828 (fw_rev_min(dev->mdev) << 16) |
829 fw_rev_sub(dev->mdev);
830 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
831 IB_DEVICE_PORT_ACTIVE_EVENT |
832 IB_DEVICE_SYS_IMAGE_GUID |
833 IB_DEVICE_RC_RNR_NAK_GEN;
835 if (MLX5_CAP_GEN(mdev, pkv))
836 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
837 if (MLX5_CAP_GEN(mdev, qkv))
838 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
839 if (MLX5_CAP_GEN(mdev, apm))
840 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
841 if (MLX5_CAP_GEN(mdev, xrc))
842 props->device_cap_flags |= IB_DEVICE_XRC;
843 if (MLX5_CAP_GEN(mdev, imaicl)) {
844 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
845 IB_DEVICE_MEM_WINDOW_TYPE_2B;
846 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
847 /* We support 'Gappy' memory registration too */
848 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
850 /* IB_WR_REG_MR always requires changing the entity size with UMR */
851 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
852 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
853 if (MLX5_CAP_GEN(mdev, sho)) {
854 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
855 /* At this stage no support for signature handover */
856 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
857 IB_PROT_T10DIF_TYPE_2 |
858 IB_PROT_T10DIF_TYPE_3;
859 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
860 IB_GUARD_T10DIF_CSUM;
862 if (MLX5_CAP_GEN(mdev, block_lb_mc))
863 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
866 if (MLX5_CAP_ETH(mdev, csum_cap)) {
867 /* Legacy bit to support old userspace libraries */
868 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
869 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
872 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
873 props->raw_packet_caps |=
874 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
876 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
877 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
879 resp.tso_caps.max_tso = 1 << max_tso;
880 resp.tso_caps.supported_qpts |=
881 1 << IB_QPT_RAW_PACKET;
882 resp.response_length += sizeof(resp.tso_caps);
886 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
887 resp.rss_caps.rx_hash_function =
888 MLX5_RX_HASH_FUNC_TOEPLITZ;
889 resp.rss_caps.rx_hash_fields_mask =
890 MLX5_RX_HASH_SRC_IPV4 |
891 MLX5_RX_HASH_DST_IPV4 |
892 MLX5_RX_HASH_SRC_IPV6 |
893 MLX5_RX_HASH_DST_IPV6 |
894 MLX5_RX_HASH_SRC_PORT_TCP |
895 MLX5_RX_HASH_DST_PORT_TCP |
896 MLX5_RX_HASH_SRC_PORT_UDP |
897 MLX5_RX_HASH_DST_PORT_UDP |
899 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
900 MLX5_ACCEL_IPSEC_CAP_DEVICE)
901 resp.rss_caps.rx_hash_fields_mask |=
902 MLX5_RX_HASH_IPSEC_SPI;
903 resp.response_length += sizeof(resp.rss_caps);
906 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
907 resp.response_length += sizeof(resp.tso_caps);
908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
909 resp.response_length += sizeof(resp.rss_caps);
912 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
913 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
914 props->device_cap_flags |= IB_DEVICE_UD_TSO;
917 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
918 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
920 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
922 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
923 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
924 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
926 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
927 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
929 /* Legacy bit to support old userspace libraries */
930 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
931 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
934 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
936 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
939 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
940 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
942 if (MLX5_CAP_GEN(mdev, end_pad))
943 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
945 props->vendor_part_id = mdev->pdev->device;
946 props->hw_ver = mdev->pdev->revision;
948 props->max_mr_size = ~0ull;
949 props->page_size_cap = ~(min_page_size - 1);
950 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
951 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
952 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
953 sizeof(struct mlx5_wqe_data_seg);
954 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
955 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
956 sizeof(struct mlx5_wqe_raddr_seg)) /
957 sizeof(struct mlx5_wqe_data_seg);
958 props->max_send_sge = max_sq_sg;
959 props->max_recv_sge = max_rq_sg;
960 props->max_sge_rd = MLX5_MAX_SGE_RD;
961 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
962 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
963 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
964 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
965 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
966 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
967 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
968 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
969 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
970 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
971 props->max_srq_sge = max_rq_sg - 1;
972 props->max_fast_reg_page_list_len =
973 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
974 props->max_pi_fast_reg_page_list_len =
975 props->max_fast_reg_page_list_len / 2;
977 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
978 get_atomic_caps_qp(dev, props);
979 props->masked_atomic_cap = IB_ATOMIC_NONE;
980 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
981 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
982 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
983 props->max_mcast_grp;
984 props->max_ah = INT_MAX;
985 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
986 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
988 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
989 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
990 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
991 props->odp_caps = dev->odp_caps;
993 /* ODP for kernel QPs is not implemented for receive
996 props->odp_caps.per_transport_caps.rc_odp_caps &=
997 ~(IB_ODP_SUPPORT_READ |
998 IB_ODP_SUPPORT_SRQ_RECV);
999 props->odp_caps.per_transport_caps.uc_odp_caps &=
1000 ~(IB_ODP_SUPPORT_READ |
1001 IB_ODP_SUPPORT_SRQ_RECV);
1002 props->odp_caps.per_transport_caps.ud_odp_caps &=
1003 ~(IB_ODP_SUPPORT_READ |
1004 IB_ODP_SUPPORT_SRQ_RECV);
1005 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1006 ~(IB_ODP_SUPPORT_READ |
1007 IB_ODP_SUPPORT_SRQ_RECV);
1011 if (MLX5_CAP_GEN(mdev, cd))
1012 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1014 if (mlx5_core_is_vf(mdev))
1015 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1017 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1018 IB_LINK_LAYER_ETHERNET && raw_support) {
1019 props->rss_caps.max_rwq_indirection_tables =
1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1021 props->rss_caps.max_rwq_indirection_table_size =
1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1023 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1024 props->max_wq_type_rq =
1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1028 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1029 props->tm_caps.max_num_tags =
1030 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1031 props->tm_caps.max_ops =
1032 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1033 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1036 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1037 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1038 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1039 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1042 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1043 props->cq_caps.max_cq_moderation_count =
1045 props->cq_caps.max_cq_moderation_period =
1049 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1050 resp.response_length += sizeof(resp.cqe_comp_caps);
1052 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1053 resp.cqe_comp_caps.max_num =
1054 MLX5_CAP_GEN(dev->mdev,
1055 cqe_compression_max_num);
1057 resp.cqe_comp_caps.supported_format =
1058 MLX5_IB_CQE_RES_FORMAT_HASH |
1059 MLX5_IB_CQE_RES_FORMAT_CSUM;
1061 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1062 resp.cqe_comp_caps.supported_format |=
1063 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1067 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1069 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1070 MLX5_CAP_GEN(mdev, qos)) {
1071 resp.packet_pacing_caps.qp_rate_limit_max =
1072 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1073 resp.packet_pacing_caps.qp_rate_limit_min =
1074 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1075 resp.packet_pacing_caps.supported_qpts |=
1076 1 << IB_QPT_RAW_PACKET;
1077 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1078 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1079 resp.packet_pacing_caps.cap_flags |=
1080 MLX5_IB_PP_SUPPORT_BURST;
1082 resp.response_length += sizeof(resp.packet_pacing_caps);
1085 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1087 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1088 resp.mlx5_ib_support_multi_pkt_send_wqes =
1091 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1092 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1093 MLX5_IB_SUPPORT_EMPW;
1095 resp.response_length +=
1096 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1099 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1100 resp.response_length += sizeof(resp.flags);
1102 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1104 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1106 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1107 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1108 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1110 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1115 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1116 resp.response_length += sizeof(resp.sw_parsing_caps);
1117 if (MLX5_CAP_ETH(mdev, swp)) {
1118 resp.sw_parsing_caps.sw_parsing_offloads |=
1121 if (MLX5_CAP_ETH(mdev, swp_csum))
1122 resp.sw_parsing_caps.sw_parsing_offloads |=
1123 MLX5_IB_SW_PARSING_CSUM;
1125 if (MLX5_CAP_ETH(mdev, swp_lso))
1126 resp.sw_parsing_caps.sw_parsing_offloads |=
1127 MLX5_IB_SW_PARSING_LSO;
1129 if (resp.sw_parsing_caps.sw_parsing_offloads)
1130 resp.sw_parsing_caps.supported_qpts =
1131 BIT(IB_QPT_RAW_PACKET);
1135 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1137 resp.response_length += sizeof(resp.striding_rq_caps);
1138 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1139 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1140 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1141 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1142 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1143 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1144 resp.striding_rq_caps
1145 .min_single_wqe_log_num_of_strides =
1146 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1148 resp.striding_rq_caps
1149 .min_single_wqe_log_num_of_strides =
1150 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1151 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1152 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1153 resp.striding_rq_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1158 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1159 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1161 resp.tunnel_offloads_caps |=
1162 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1164 resp.tunnel_offloads_caps |=
1165 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1167 resp.tunnel_offloads_caps |=
1168 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1170 resp.tunnel_offloads_caps |=
1171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1173 resp.tunnel_offloads_caps |=
1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1178 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1187 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1190 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1192 if (active_width & MLX5_PTYS_WIDTH_1X)
1193 *ib_width = IB_WIDTH_1X;
1194 else if (active_width & MLX5_PTYS_WIDTH_2X)
1195 *ib_width = IB_WIDTH_2X;
1196 else if (active_width & MLX5_PTYS_WIDTH_4X)
1197 *ib_width = IB_WIDTH_4X;
1198 else if (active_width & MLX5_PTYS_WIDTH_8X)
1199 *ib_width = IB_WIDTH_8X;
1200 else if (active_width & MLX5_PTYS_WIDTH_12X)
1201 *ib_width = IB_WIDTH_12X;
1203 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1205 *ib_width = IB_WIDTH_4X;
1211 static int mlx5_mtu_to_ib_mtu(int mtu)
1216 case 1024: return 3;
1217 case 2048: return 4;
1218 case 4096: return 5;
1220 pr_warn("invalid mtu\n");
1225 enum ib_max_vl_num {
1227 __IB_MAX_VL_0_1 = 2,
1228 __IB_MAX_VL_0_3 = 3,
1229 __IB_MAX_VL_0_7 = 4,
1230 __IB_MAX_VL_0_14 = 5,
1233 enum mlx5_vl_hw_cap {
1242 MLX5_VL_HW_0_14 = 15
1245 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1248 switch (vl_hw_cap) {
1250 *max_vl_num = __IB_MAX_VL_0;
1252 case MLX5_VL_HW_0_1:
1253 *max_vl_num = __IB_MAX_VL_0_1;
1255 case MLX5_VL_HW_0_3:
1256 *max_vl_num = __IB_MAX_VL_0_3;
1258 case MLX5_VL_HW_0_7:
1259 *max_vl_num = __IB_MAX_VL_0_7;
1261 case MLX5_VL_HW_0_14:
1262 *max_vl_num = __IB_MAX_VL_0_14;
1272 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1273 struct ib_port_attr *props)
1275 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1276 struct mlx5_core_dev *mdev = dev->mdev;
1277 struct mlx5_hca_vport_context *rep;
1281 u16 ib_link_width_oper;
1284 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1290 /* props being zeroed by the caller, avoid zeroing it here */
1292 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1296 props->lid = rep->lid;
1297 props->lmc = rep->lmc;
1298 props->sm_lid = rep->sm_lid;
1299 props->sm_sl = rep->sm_sl;
1300 props->state = rep->vport_state;
1301 props->phys_state = rep->port_physical_state;
1302 props->port_cap_flags = rep->cap_mask1;
1303 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1304 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1305 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1306 props->bad_pkey_cntr = rep->pkey_violation_counter;
1307 props->qkey_viol_cntr = rep->qkey_violation_counter;
1308 props->subnet_timeout = rep->subnet_timeout;
1309 props->init_type_reply = rep->init_type_reply;
1311 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1312 props->port_cap_flags2 = rep->cap_mask2;
1314 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1315 &props->active_speed, port);
1319 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1321 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1323 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1325 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1327 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1329 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1333 err = translate_max_vl_num(ibdev, vl_hw_cap,
1334 &props->max_vl_num);
1340 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1341 struct ib_port_attr *props)
1346 switch (mlx5_get_vport_access_method(ibdev)) {
1347 case MLX5_VPORT_ACCESS_METHOD_MAD:
1348 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1351 case MLX5_VPORT_ACCESS_METHOD_HCA:
1352 ret = mlx5_query_hca_port(ibdev, port, props);
1355 case MLX5_VPORT_ACCESS_METHOD_NIC:
1356 ret = mlx5_query_port_roce(ibdev, port, props);
1363 if (!ret && props) {
1364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1365 struct mlx5_core_dev *mdev;
1366 bool put_mdev = true;
1368 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1370 /* If the port isn't affiliated yet query the master.
1371 * The master and slave will have the same values.
1377 count = mlx5_core_reserved_gids_count(mdev);
1379 mlx5_ib_put_native_port_mdev(dev, port);
1380 props->gid_tbl_len -= count;
1385 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1386 struct ib_port_attr *props)
1388 return mlx5_query_port_roce(ibdev, port, props);
1391 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1394 /* Default special Pkey for representor device port as per the
1395 * IB specification 1.3 section 10.9.1.2.
1401 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1404 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1405 struct mlx5_core_dev *mdev = dev->mdev;
1407 switch (mlx5_get_vport_access_method(ibdev)) {
1408 case MLX5_VPORT_ACCESS_METHOD_MAD:
1409 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1411 case MLX5_VPORT_ACCESS_METHOD_HCA:
1412 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1420 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1421 u16 index, u16 *pkey)
1423 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1424 struct mlx5_core_dev *mdev;
1425 bool put_mdev = true;
1429 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1431 /* The port isn't affiliated yet, get the PKey from the master
1432 * port. For RoCE the PKey tables will be the same.
1439 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1442 mlx5_ib_put_native_port_mdev(dev, port);
1447 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1450 switch (mlx5_get_vport_access_method(ibdev)) {
1451 case MLX5_VPORT_ACCESS_METHOD_MAD:
1452 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1454 case MLX5_VPORT_ACCESS_METHOD_HCA:
1455 case MLX5_VPORT_ACCESS_METHOD_NIC:
1456 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1462 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1463 struct ib_device_modify *props)
1465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1466 struct mlx5_reg_node_desc in;
1467 struct mlx5_reg_node_desc out;
1470 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1473 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1477 * If possible, pass node desc to FW, so it can generate
1478 * a 144 trap. If cmd fails, just ignore.
1480 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1481 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1482 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1486 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1491 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1494 struct mlx5_hca_vport_context ctx = {};
1495 struct mlx5_core_dev *mdev;
1499 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1503 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1507 if (~ctx.cap_mask1_perm & mask) {
1508 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1509 mask, ctx.cap_mask1_perm);
1514 ctx.cap_mask1 = value;
1515 ctx.cap_mask1_perm = mask;
1516 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1520 mlx5_ib_put_native_port_mdev(dev, port_num);
1525 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1526 struct ib_port_modify *props)
1528 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1529 struct ib_port_attr attr;
1534 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1535 IB_LINK_LAYER_INFINIBAND);
1537 /* CM layer calls ib_modify_port() regardless of the link layer. For
1538 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1543 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1544 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1545 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1546 return set_port_caps_atomic(dev, port, change_mask, value);
1549 mutex_lock(&dev->cap_mask_mutex);
1551 err = ib_query_port(ibdev, port, &attr);
1555 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1556 ~props->clr_port_cap_mask;
1558 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1561 mutex_unlock(&dev->cap_mask_mutex);
1565 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1567 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1568 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1571 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1573 /* Large page with non 4k uar support might limit the dynamic size */
1574 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1575 return MLX5_MIN_DYN_BFREGS;
1577 return MLX5_MAX_DYN_BFREGS;
1580 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1581 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1582 struct mlx5_bfreg_info *bfregi)
1584 int uars_per_sys_page;
1585 int bfregs_per_sys_page;
1586 int ref_bfregs = req->total_num_bfregs;
1588 if (req->total_num_bfregs == 0)
1591 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1592 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1594 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1597 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1598 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1599 /* This holds the required static allocation asked by the user */
1600 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1601 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1604 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1605 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1606 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1607 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1609 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1610 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1611 lib_uar_4k ? "yes" : "no", ref_bfregs,
1612 req->total_num_bfregs, bfregi->total_num_bfregs,
1613 bfregi->num_sys_pages);
1618 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1620 struct mlx5_bfreg_info *bfregi;
1624 bfregi = &context->bfregi;
1625 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1626 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1630 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1633 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1634 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1639 for (--i; i >= 0; i--)
1640 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1641 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1646 static void deallocate_uars(struct mlx5_ib_dev *dev,
1647 struct mlx5_ib_ucontext *context)
1649 struct mlx5_bfreg_info *bfregi;
1652 bfregi = &context->bfregi;
1653 for (i = 0; i < bfregi->num_sys_pages; i++)
1654 if (i < bfregi->num_static_sys_pages ||
1655 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1656 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1659 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1663 mutex_lock(&dev->lb.mutex);
1669 if (dev->lb.user_td == 2 ||
1671 if (!dev->lb.enabled) {
1672 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1673 dev->lb.enabled = true;
1677 mutex_unlock(&dev->lb.mutex);
1682 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1684 mutex_lock(&dev->lb.mutex);
1690 if (dev->lb.user_td == 1 &&
1692 if (dev->lb.enabled) {
1693 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1694 dev->lb.enabled = false;
1698 mutex_unlock(&dev->lb.mutex);
1701 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1706 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1709 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1713 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1714 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1715 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1718 return mlx5_ib_enable_lb(dev, true, false);
1721 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1724 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1727 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1729 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1730 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1731 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1734 mlx5_ib_disable_lb(dev, true, false);
1737 static int set_ucontext_resp(struct ib_ucontext *uctx,
1738 struct mlx5_ib_alloc_ucontext_resp *resp)
1740 struct ib_device *ibdev = uctx->device;
1741 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1742 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1743 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1748 &resp->dump_fill_mkey);
1752 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1755 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1756 if (dev->wc_support)
1757 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1759 resp->cache_line_size = cache_line_size();
1760 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1761 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1762 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1763 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1764 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1765 resp->cqe_version = context->cqe_version;
1766 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1767 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1768 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1769 MLX5_CAP_GEN(dev->mdev,
1770 num_of_uars_per_page) : 1;
1772 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1773 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1774 if (mlx5_get_flow_namespace(dev->mdev,
1775 MLX5_FLOW_NAMESPACE_EGRESS))
1776 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1777 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1778 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1779 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1780 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1781 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1782 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1783 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1784 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1785 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1788 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1789 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1790 resp->num_ports = dev->num_ports;
1791 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1792 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1794 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1795 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1796 resp->eth_min_inline++;
1799 if (dev->mdev->clock_info)
1800 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1803 * We don't want to expose information from the PCI bar that is located
1804 * after 4096 bytes, so if the arch only supports larger pages, let's
1805 * pretend we don't support reading the HCA's core clock. This is also
1806 * forced by mmap function.
1808 if (PAGE_SIZE <= 4096) {
1810 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1811 resp->hca_core_clock_offset =
1812 offsetof(struct mlx5_init_seg,
1813 internal_timer_h) % PAGE_SIZE;
1816 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1817 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1819 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1821 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1822 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1827 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1828 struct ib_udata *udata)
1830 struct ib_device *ibdev = uctx->device;
1831 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1832 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1833 struct mlx5_ib_alloc_ucontext_resp resp = {};
1834 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1835 struct mlx5_bfreg_info *bfregi;
1838 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1843 if (!dev->ib_active)
1846 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1848 else if (udata->inlen >= min_req_v2)
1853 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1857 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1860 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1863 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1864 MLX5_NON_FP_BFREGS_PER_UAR);
1865 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1868 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1869 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1870 bfregi = &context->bfregi;
1873 bfregi->lib_uar_dyn = lib_uar_dyn;
1877 /* updates req->total_num_bfregs */
1878 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1882 mutex_init(&bfregi->lock);
1883 bfregi->lib_uar_4k = lib_uar_4k;
1884 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1886 if (!bfregi->count) {
1891 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1892 sizeof(*bfregi->sys_pages),
1894 if (!bfregi->sys_pages) {
1899 err = allocate_uars(dev, context);
1904 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1905 err = mlx5_ib_devx_create(dev, true);
1908 context->devx_uid = err;
1911 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1916 INIT_LIST_HEAD(&context->db_page_list);
1917 mutex_init(&context->db_page_mutex);
1919 context->cqe_version = min_t(__u8,
1920 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1921 req.max_cqe_version);
1923 err = set_ucontext_resp(uctx, &resp);
1927 resp.response_length = min(udata->outlen, sizeof(resp));
1928 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1933 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1934 context->lib_caps = req.lib_caps;
1935 print_lib_caps(dev, context->lib_caps);
1937 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1938 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1940 atomic_set(&context->tx_port_affinity,
1942 1, &dev->port[port].roce.tx_port_affinity));
1948 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1950 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1951 mlx5_ib_devx_destroy(dev, context->devx_uid);
1954 deallocate_uars(dev, context);
1957 kfree(bfregi->sys_pages);
1960 kfree(bfregi->count);
1966 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1967 struct uverbs_attr_bundle *attrs)
1969 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1972 ret = set_ucontext_resp(ibcontext, &uctx_resp);
1976 uctx_resp.response_length =
1978 uverbs_attr_get_len(attrs,
1979 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1982 ret = uverbs_copy_to_struct_or_zero(attrs,
1983 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1989 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1991 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1992 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1993 struct mlx5_bfreg_info *bfregi;
1995 bfregi = &context->bfregi;
1996 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1998 if (context->devx_uid)
1999 mlx5_ib_devx_destroy(dev, context->devx_uid);
2001 deallocate_uars(dev, context);
2002 kfree(bfregi->sys_pages);
2003 kfree(bfregi->count);
2006 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2009 int fw_uars_per_page;
2011 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2013 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2016 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2019 unsigned int fw_uars_per_page;
2021 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2022 MLX5_UARS_IN_PAGE : 1;
2024 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2027 static int get_command(unsigned long offset)
2029 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2032 static int get_arg(unsigned long offset)
2034 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2037 static int get_index(unsigned long offset)
2039 return get_arg(offset);
2042 /* Index resides in an extra byte to enable larger values than 255 */
2043 static int get_extended_index(unsigned long offset)
2045 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2049 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2053 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2056 case MLX5_IB_MMAP_WC_PAGE:
2058 case MLX5_IB_MMAP_REGULAR_PAGE:
2059 return "best effort WC";
2060 case MLX5_IB_MMAP_NC_PAGE:
2062 case MLX5_IB_MMAP_DEVICE_MEM:
2063 return "Device Memory";
2069 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2070 struct vm_area_struct *vma,
2071 struct mlx5_ib_ucontext *context)
2073 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2074 !(vma->vm_flags & VM_SHARED))
2077 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2080 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2082 vma->vm_flags &= ~VM_MAYWRITE;
2084 if (!dev->mdev->clock_info)
2087 return vm_insert_page(vma, vma->vm_start,
2088 virt_to_page(dev->mdev->clock_info));
2091 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2093 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2094 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2095 struct mlx5_var_table *var_table = &dev->var_table;
2097 switch (mentry->mmap_flag) {
2098 case MLX5_IB_MMAP_TYPE_MEMIC:
2099 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2100 mlx5_ib_dm_mmap_free(dev, mentry);
2102 case MLX5_IB_MMAP_TYPE_VAR:
2103 mutex_lock(&var_table->bitmap_lock);
2104 clear_bit(mentry->page_idx, var_table->bitmap);
2105 mutex_unlock(&var_table->bitmap_lock);
2108 case MLX5_IB_MMAP_TYPE_UAR_WC:
2109 case MLX5_IB_MMAP_TYPE_UAR_NC:
2110 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2118 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2119 struct vm_area_struct *vma,
2120 struct mlx5_ib_ucontext *context)
2122 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2127 u32 bfreg_dyn_idx = 0;
2129 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2130 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2131 bfregi->num_static_sys_pages;
2133 if (bfregi->lib_uar_dyn)
2136 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2140 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2142 idx = get_index(vma->vm_pgoff);
2144 if (idx >= max_valid_idx) {
2145 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2146 idx, max_valid_idx);
2151 case MLX5_IB_MMAP_WC_PAGE:
2152 case MLX5_IB_MMAP_ALLOC_WC:
2153 case MLX5_IB_MMAP_REGULAR_PAGE:
2154 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2155 prot = pgprot_writecombine(vma->vm_page_prot);
2157 case MLX5_IB_MMAP_NC_PAGE:
2158 prot = pgprot_noncached(vma->vm_page_prot);
2167 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2168 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2169 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2170 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2171 bfreg_dyn_idx, bfregi->total_num_bfregs);
2175 mutex_lock(&bfregi->lock);
2176 /* Fail if uar already allocated, first bfreg index of each
2177 * page holds its count.
2179 if (bfregi->count[bfreg_dyn_idx]) {
2180 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2181 mutex_unlock(&bfregi->lock);
2185 bfregi->count[bfreg_dyn_idx]++;
2186 mutex_unlock(&bfregi->lock);
2188 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2190 mlx5_ib_warn(dev, "UAR alloc failed\n");
2194 uar_index = bfregi->sys_pages[idx];
2197 pfn = uar_index2pfn(dev, uar_index);
2198 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2200 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2204 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2205 err, mmap_cmd2str(cmd));
2210 bfregi->sys_pages[idx] = uar_index;
2217 mlx5_cmd_free_uar(dev->mdev, idx);
2220 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2225 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2230 command = get_command(vma->vm_pgoff);
2231 idx = get_extended_index(vma->vm_pgoff);
2233 return (command << 16 | idx);
2236 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2237 struct vm_area_struct *vma,
2238 struct ib_ucontext *ucontext)
2240 struct mlx5_user_mmap_entry *mentry;
2241 struct rdma_user_mmap_entry *entry;
2242 unsigned long pgoff;
2247 pgoff = mlx5_vma_to_pgoff(vma);
2248 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2252 mentry = to_mmmap(entry);
2253 pfn = (mentry->address >> PAGE_SHIFT);
2254 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2255 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2256 prot = pgprot_noncached(vma->vm_page_prot);
2258 prot = pgprot_writecombine(vma->vm_page_prot);
2259 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2260 entry->npages * PAGE_SIZE,
2263 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2267 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2269 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2270 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2272 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2273 (index & 0xFF)) << PAGE_SHIFT;
2276 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2278 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2279 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2280 unsigned long command;
2283 command = get_command(vma->vm_pgoff);
2285 case MLX5_IB_MMAP_WC_PAGE:
2286 case MLX5_IB_MMAP_ALLOC_WC:
2287 if (!dev->wc_support)
2290 case MLX5_IB_MMAP_NC_PAGE:
2291 case MLX5_IB_MMAP_REGULAR_PAGE:
2292 return uar_mmap(dev, command, vma, context);
2294 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2297 case MLX5_IB_MMAP_CORE_CLOCK:
2298 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2301 if (vma->vm_flags & VM_WRITE)
2303 vma->vm_flags &= ~VM_MAYWRITE;
2305 /* Don't expose to user-space information it shouldn't have */
2306 if (PAGE_SIZE > 4096)
2309 pfn = (dev->mdev->iseg_base +
2310 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2312 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2314 pgprot_noncached(vma->vm_page_prot),
2316 case MLX5_IB_MMAP_CLOCK_INFO:
2317 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2320 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2326 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2328 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2329 struct ib_device *ibdev = ibpd->device;
2330 struct mlx5_ib_alloc_pd_resp resp;
2332 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2333 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2335 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2336 udata, struct mlx5_ib_ucontext, ibucontext);
2338 uid = context ? context->devx_uid : 0;
2339 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2340 MLX5_SET(alloc_pd_in, in, uid, uid);
2341 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2345 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2349 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2350 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2358 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2360 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2361 struct mlx5_ib_pd *mpd = to_mpd(pd);
2363 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2366 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2368 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2369 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2374 to_mpd(ibqp->pd)->uid : 0;
2376 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2377 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2381 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2383 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2384 ibqp->qp_num, gid->raw);
2389 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2391 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2396 to_mpd(ibqp->pd)->uid : 0;
2397 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2399 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2400 ibqp->qp_num, gid->raw);
2405 static int init_node_data(struct mlx5_ib_dev *dev)
2409 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2413 dev->mdev->rev_id = dev->mdev->pdev->revision;
2415 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2418 static ssize_t fw_pages_show(struct device *device,
2419 struct device_attribute *attr, char *buf)
2421 struct mlx5_ib_dev *dev =
2422 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2424 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2426 static DEVICE_ATTR_RO(fw_pages);
2428 static ssize_t reg_pages_show(struct device *device,
2429 struct device_attribute *attr, char *buf)
2431 struct mlx5_ib_dev *dev =
2432 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2434 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2436 static DEVICE_ATTR_RO(reg_pages);
2438 static ssize_t hca_type_show(struct device *device,
2439 struct device_attribute *attr, char *buf)
2441 struct mlx5_ib_dev *dev =
2442 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2444 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2446 static DEVICE_ATTR_RO(hca_type);
2448 static ssize_t hw_rev_show(struct device *device,
2449 struct device_attribute *attr, char *buf)
2451 struct mlx5_ib_dev *dev =
2452 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2454 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2456 static DEVICE_ATTR_RO(hw_rev);
2458 static ssize_t board_id_show(struct device *device,
2459 struct device_attribute *attr, char *buf)
2461 struct mlx5_ib_dev *dev =
2462 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2464 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2465 dev->mdev->board_id);
2467 static DEVICE_ATTR_RO(board_id);
2469 static struct attribute *mlx5_class_attributes[] = {
2470 &dev_attr_hw_rev.attr,
2471 &dev_attr_hca_type.attr,
2472 &dev_attr_board_id.attr,
2473 &dev_attr_fw_pages.attr,
2474 &dev_attr_reg_pages.attr,
2478 static const struct attribute_group mlx5_attr_group = {
2479 .attrs = mlx5_class_attributes,
2482 static void pkey_change_handler(struct work_struct *work)
2484 struct mlx5_ib_port_resources *ports =
2485 container_of(work, struct mlx5_ib_port_resources,
2488 mlx5_ib_gsi_pkey_change(ports->gsi);
2491 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2493 struct mlx5_ib_qp *mqp;
2494 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2495 struct mlx5_core_cq *mcq;
2496 struct list_head cq_armed_list;
2497 unsigned long flags_qp;
2498 unsigned long flags_cq;
2499 unsigned long flags;
2501 INIT_LIST_HEAD(&cq_armed_list);
2503 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2504 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2505 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2506 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2507 if (mqp->sq.tail != mqp->sq.head) {
2508 send_mcq = to_mcq(mqp->ibqp.send_cq);
2509 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2510 if (send_mcq->mcq.comp &&
2511 mqp->ibqp.send_cq->comp_handler) {
2512 if (!send_mcq->mcq.reset_notify_added) {
2513 send_mcq->mcq.reset_notify_added = 1;
2514 list_add_tail(&send_mcq->mcq.reset_notify,
2518 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2520 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2521 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2522 /* no handling is needed for SRQ */
2523 if (!mqp->ibqp.srq) {
2524 if (mqp->rq.tail != mqp->rq.head) {
2525 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2526 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2527 if (recv_mcq->mcq.comp &&
2528 mqp->ibqp.recv_cq->comp_handler) {
2529 if (!recv_mcq->mcq.reset_notify_added) {
2530 recv_mcq->mcq.reset_notify_added = 1;
2531 list_add_tail(&recv_mcq->mcq.reset_notify,
2535 spin_unlock_irqrestore(&recv_mcq->lock,
2539 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2541 /*At that point all inflight post send were put to be executed as of we
2542 * lock/unlock above locks Now need to arm all involved CQs.
2544 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2545 mcq->comp(mcq, NULL);
2547 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2550 static void delay_drop_handler(struct work_struct *work)
2553 struct mlx5_ib_delay_drop *delay_drop =
2554 container_of(work, struct mlx5_ib_delay_drop,
2557 atomic_inc(&delay_drop->events_cnt);
2559 mutex_lock(&delay_drop->lock);
2560 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2562 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2563 delay_drop->timeout);
2564 delay_drop->activate = false;
2566 mutex_unlock(&delay_drop->lock);
2569 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2570 struct ib_event *ibev)
2572 u32 port = (eqe->data.port.port >> 4) & 0xf;
2574 switch (eqe->sub_type) {
2575 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2576 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2577 IB_LINK_LAYER_ETHERNET)
2578 schedule_work(&ibdev->delay_drop.delay_drop_work);
2580 default: /* do nothing */
2585 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2586 struct ib_event *ibev)
2588 u32 port = (eqe->data.port.port >> 4) & 0xf;
2590 ibev->element.port_num = port;
2592 switch (eqe->sub_type) {
2593 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2594 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2595 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2596 /* In RoCE, port up/down events are handled in
2597 * mlx5_netdev_event().
2599 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2600 IB_LINK_LAYER_ETHERNET)
2603 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2604 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2607 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2608 ibev->event = IB_EVENT_LID_CHANGE;
2611 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2612 ibev->event = IB_EVENT_PKEY_CHANGE;
2613 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2616 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2617 ibev->event = IB_EVENT_GID_CHANGE;
2620 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2621 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2630 static void mlx5_ib_handle_event(struct work_struct *_work)
2632 struct mlx5_ib_event_work *work =
2633 container_of(_work, struct mlx5_ib_event_work, work);
2634 struct mlx5_ib_dev *ibdev;
2635 struct ib_event ibev;
2638 if (work->is_slave) {
2639 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2646 switch (work->event) {
2647 case MLX5_DEV_EVENT_SYS_ERROR:
2648 ibev.event = IB_EVENT_DEVICE_FATAL;
2649 mlx5_ib_handle_internal_error(ibdev);
2650 ibev.element.port_num = (u8)(unsigned long)work->param;
2653 case MLX5_EVENT_TYPE_PORT_CHANGE:
2654 if (handle_port_change(ibdev, work->param, &ibev))
2657 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2658 handle_general_event(ibdev, work->param, &ibev);
2664 ibev.device = &ibdev->ib_dev;
2666 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2667 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2671 if (ibdev->ib_active)
2672 ib_dispatch_event(&ibev);
2675 ibdev->ib_active = false;
2680 static int mlx5_ib_event(struct notifier_block *nb,
2681 unsigned long event, void *param)
2683 struct mlx5_ib_event_work *work;
2685 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2689 INIT_WORK(&work->work, mlx5_ib_handle_event);
2690 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2691 work->is_slave = false;
2692 work->param = param;
2693 work->event = event;
2695 queue_work(mlx5_ib_event_wq, &work->work);
2700 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2701 unsigned long event, void *param)
2703 struct mlx5_ib_event_work *work;
2705 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2709 INIT_WORK(&work->work, mlx5_ib_handle_event);
2710 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2711 work->is_slave = true;
2712 work->param = param;
2713 work->event = event;
2714 queue_work(mlx5_ib_event_wq, &work->work);
2719 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2721 struct mlx5_hca_vport_context vport_ctx;
2725 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2726 dev->port_caps[port - 1].has_smi = false;
2727 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2728 MLX5_CAP_PORT_TYPE_IB) {
2729 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2730 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2734 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2738 dev->port_caps[port - 1].has_smi =
2741 dev->port_caps[port - 1].has_smi = true;
2748 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2752 rdma_for_each_port (&dev->ib_dev, port)
2753 mlx5_query_ext_port_caps(dev, port);
2756 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2758 switch (umr_fence_cap) {
2759 case MLX5_CAP_UMR_FENCE_NONE:
2760 return MLX5_FENCE_MODE_NONE;
2761 case MLX5_CAP_UMR_FENCE_SMALL:
2762 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2764 return MLX5_FENCE_MODE_STRONG_ORDERING;
2768 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2770 struct mlx5_ib_resources *devr = &dev->devr;
2771 struct ib_srq_init_attr attr;
2772 struct ib_device *ibdev;
2773 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2777 ibdev = &dev->ib_dev;
2779 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2782 mutex_init(&devr->mutex);
2784 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2788 devr->p0->device = ibdev;
2789 devr->p0->uobject = NULL;
2790 atomic_set(&devr->p0->usecnt, 0);
2792 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2796 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2802 devr->c0->device = &dev->ib_dev;
2803 atomic_set(&devr->c0->usecnt, 0);
2805 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2809 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2813 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2817 memset(&attr, 0, sizeof(attr));
2818 attr.attr.max_sge = 1;
2819 attr.attr.max_wr = 1;
2820 attr.srq_type = IB_SRQT_XRC;
2821 attr.ext.cq = devr->c0;
2823 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2829 devr->s0->device = &dev->ib_dev;
2830 devr->s0->pd = devr->p0;
2831 devr->s0->srq_type = IB_SRQT_XRC;
2832 devr->s0->ext.cq = devr->c0;
2833 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
2837 atomic_inc(&devr->s0->ext.cq->usecnt);
2838 atomic_inc(&devr->p0->usecnt);
2839 atomic_set(&devr->s0->usecnt, 0);
2841 memset(&attr, 0, sizeof(attr));
2842 attr.attr.max_sge = 1;
2843 attr.attr.max_wr = 1;
2844 attr.srq_type = IB_SRQT_BASIC;
2845 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2851 devr->s1->device = &dev->ib_dev;
2852 devr->s1->pd = devr->p0;
2853 devr->s1->srq_type = IB_SRQT_BASIC;
2854 devr->s1->ext.cq = devr->c0;
2856 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
2860 atomic_inc(&devr->p0->usecnt);
2861 atomic_set(&devr->s1->usecnt, 0);
2863 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2864 INIT_WORK(&devr->ports[port].pkey_change_work,
2865 pkey_change_handler);
2872 mlx5_ib_destroy_srq(devr->s0, NULL);
2876 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2878 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2880 mlx5_ib_destroy_cq(devr->c0, NULL);
2884 mlx5_ib_dealloc_pd(devr->p0, NULL);
2890 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2892 struct mlx5_ib_resources *devr = &dev->devr;
2895 mlx5_ib_destroy_srq(devr->s1, NULL);
2897 mlx5_ib_destroy_srq(devr->s0, NULL);
2899 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2900 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2901 mlx5_ib_destroy_cq(devr->c0, NULL);
2903 mlx5_ib_dealloc_pd(devr->p0, NULL);
2906 /* Make sure no change P_Key work items are still executing */
2907 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2908 cancel_work_sync(&devr->ports[port].pkey_change_work);
2911 static u32 get_core_cap_flags(struct ib_device *ibdev,
2912 struct mlx5_hca_vport_context *rep)
2914 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2915 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2916 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2917 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2918 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2921 if (rep->grh_required)
2922 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2924 if (ll == IB_LINK_LAYER_INFINIBAND)
2925 return ret | RDMA_CORE_PORT_IBA_IB;
2928 ret |= RDMA_CORE_PORT_RAW_PACKET;
2930 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2933 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2936 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2937 ret |= RDMA_CORE_PORT_IBA_ROCE;
2939 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2940 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2945 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2946 struct ib_port_immutable *immutable)
2948 struct ib_port_attr attr;
2949 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2950 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2951 struct mlx5_hca_vport_context rep = {0};
2954 err = ib_query_port(ibdev, port_num, &attr);
2958 if (ll == IB_LINK_LAYER_INFINIBAND) {
2959 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2965 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2966 immutable->gid_tbl_len = attr.gid_tbl_len;
2967 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2968 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2973 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2974 struct ib_port_immutable *immutable)
2976 struct ib_port_attr attr;
2979 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2981 err = ib_query_port(ibdev, port_num, &attr);
2985 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2986 immutable->gid_tbl_len = attr.gid_tbl_len;
2987 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2992 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
2994 struct mlx5_ib_dev *dev =
2995 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2996 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
2997 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
2998 fw_rev_sub(dev->mdev));
3001 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3003 struct mlx5_core_dev *mdev = dev->mdev;
3004 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3005 MLX5_FLOW_NAMESPACE_LAG);
3006 struct mlx5_flow_table *ft;
3009 if (!ns || !mlx5_lag_is_roce(mdev))
3012 err = mlx5_cmd_create_vport_lag(mdev);
3016 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3019 goto err_destroy_vport_lag;
3022 dev->flow_db->lag_demux_ft = ft;
3023 dev->lag_active = true;
3026 err_destroy_vport_lag:
3027 mlx5_cmd_destroy_vport_lag(mdev);
3031 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3033 struct mlx5_core_dev *mdev = dev->mdev;
3035 if (dev->lag_active) {
3036 dev->lag_active = false;
3038 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3039 dev->flow_db->lag_demux_ft = NULL;
3041 mlx5_cmd_destroy_vport_lag(mdev);
3045 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3049 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3050 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3052 dev->port[port_num].roce.nb.notifier_call = NULL;
3059 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3061 if (dev->port[port_num].roce.nb.notifier_call) {
3062 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3063 dev->port[port_num].roce.nb.notifier_call = NULL;
3067 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3071 err = mlx5_nic_vport_enable_roce(dev->mdev);
3075 err = mlx5_eth_lag_init(dev);
3077 goto err_disable_roce;
3082 mlx5_nic_vport_disable_roce(dev->mdev);
3087 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3089 mlx5_eth_lag_cleanup(dev);
3090 mlx5_nic_vport_disable_roce(dev->mdev);
3093 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3094 enum rdma_netdev_t type,
3095 struct rdma_netdev_alloc_params *params)
3097 if (type != RDMA_NETDEV_IPOIB)
3100 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3103 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3104 size_t count, loff_t *pos)
3106 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3110 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3111 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3114 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3115 size_t count, loff_t *pos)
3117 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3121 if (kstrtouint_from_user(buf, count, 0, &var))
3124 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3127 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3130 delay_drop->timeout = timeout;
3135 static const struct file_operations fops_delay_drop_timeout = {
3136 .owner = THIS_MODULE,
3137 .open = simple_open,
3138 .write = delay_drop_timeout_write,
3139 .read = delay_drop_timeout_read,
3142 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3143 struct mlx5_ib_multiport_info *mpi)
3145 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3146 struct mlx5_ib_port *port = &ibdev->port[port_num];
3151 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3153 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3155 spin_lock(&port->mp.mpi_lock);
3157 spin_unlock(&port->mp.mpi_lock);
3163 spin_unlock(&port->mp.mpi_lock);
3164 if (mpi->mdev_events.notifier_call)
3165 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3166 mpi->mdev_events.notifier_call = NULL;
3167 mlx5_remove_netdev_notifier(ibdev, port_num);
3168 spin_lock(&port->mp.mpi_lock);
3170 comps = mpi->mdev_refcnt;
3172 mpi->unaffiliate = true;
3173 init_completion(&mpi->unref_comp);
3174 spin_unlock(&port->mp.mpi_lock);
3176 for (i = 0; i < comps; i++)
3177 wait_for_completion(&mpi->unref_comp);
3179 spin_lock(&port->mp.mpi_lock);
3180 mpi->unaffiliate = false;
3183 port->mp.mpi = NULL;
3185 spin_unlock(&port->mp.mpi_lock);
3187 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3189 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3190 /* Log an error, still needed to cleanup the pointers and add
3191 * it back to the list.
3194 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3197 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3200 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3201 struct mlx5_ib_multiport_info *mpi)
3203 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3206 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3208 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3209 if (ibdev->port[port_num].mp.mpi) {
3210 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3212 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3216 ibdev->port[port_num].mp.mpi = mpi;
3218 mpi->mdev_events.notifier_call = NULL;
3219 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3221 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3225 err = mlx5_add_netdev_notifier(ibdev, port_num);
3227 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3232 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3233 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3235 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3240 mlx5_ib_unbind_slave_port(ibdev, mpi);
3244 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3246 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3247 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3249 struct mlx5_ib_multiport_info *mpi;
3253 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3256 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3257 &dev->sys_image_guid);
3261 err = mlx5_nic_vport_enable_roce(dev->mdev);
3265 mutex_lock(&mlx5_ib_multiport_mutex);
3266 for (i = 0; i < dev->num_ports; i++) {
3269 /* build a stub multiport info struct for the native port. */
3270 if (i == port_num) {
3271 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3273 mutex_unlock(&mlx5_ib_multiport_mutex);
3274 mlx5_nic_vport_disable_roce(dev->mdev);
3278 mpi->is_master = true;
3279 mpi->mdev = dev->mdev;
3280 mpi->sys_image_guid = dev->sys_image_guid;
3281 dev->port[i].mp.mpi = mpi;
3287 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3289 if (dev->sys_image_guid == mpi->sys_image_guid &&
3290 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3291 bound = mlx5_ib_bind_slave_port(dev, mpi);
3295 dev_dbg(mpi->mdev->device,
3296 "removing port from unaffiliated list.\n");
3297 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3298 list_del(&mpi->list);
3303 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3307 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3308 mutex_unlock(&mlx5_ib_multiport_mutex);
3312 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3314 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3315 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3319 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3322 mutex_lock(&mlx5_ib_multiport_mutex);
3323 for (i = 0; i < dev->num_ports; i++) {
3324 if (dev->port[i].mp.mpi) {
3325 /* Destroy the native port stub */
3326 if (i == port_num) {
3327 kfree(dev->port[i].mp.mpi);
3328 dev->port[i].mp.mpi = NULL;
3330 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3332 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
3333 list_add_tail(&dev->port[i].mp.mpi->list,
3334 &mlx5_ib_unaffiliated_port_list);
3339 mlx5_ib_dbg(dev, "removing from devlist\n");
3340 list_del(&dev->ib_dev_list);
3341 mutex_unlock(&mlx5_ib_multiport_mutex);
3343 mlx5_nic_vport_disable_roce(dev->mdev);
3346 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3347 enum rdma_remove_reason why,
3348 struct uverbs_attr_bundle *attrs)
3350 struct mlx5_user_mmap_entry *obj = uobject->object;
3352 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3356 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3357 struct mlx5_user_mmap_entry *entry,
3360 return rdma_user_mmap_entry_insert_range(
3361 &c->ibucontext, &entry->rdma_entry, length,
3362 (MLX5_IB_MMAP_OFFSET_START << 16),
3363 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3366 static struct mlx5_user_mmap_entry *
3367 alloc_var_entry(struct mlx5_ib_ucontext *c)
3369 struct mlx5_user_mmap_entry *entry;
3370 struct mlx5_var_table *var_table;
3374 var_table = &to_mdev(c->ibucontext.device)->var_table;
3375 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3377 return ERR_PTR(-ENOMEM);
3379 mutex_lock(&var_table->bitmap_lock);
3380 page_idx = find_first_zero_bit(var_table->bitmap,
3381 var_table->num_var_hw_entries);
3382 if (page_idx >= var_table->num_var_hw_entries) {
3384 mutex_unlock(&var_table->bitmap_lock);
3388 set_bit(page_idx, var_table->bitmap);
3389 mutex_unlock(&var_table->bitmap_lock);
3391 entry->address = var_table->hw_start_addr +
3392 (page_idx * var_table->stride_size);
3393 entry->page_idx = page_idx;
3394 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3396 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3397 var_table->stride_size);
3404 mutex_lock(&var_table->bitmap_lock);
3405 clear_bit(page_idx, var_table->bitmap);
3406 mutex_unlock(&var_table->bitmap_lock);
3409 return ERR_PTR(err);
3412 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3413 struct uverbs_attr_bundle *attrs)
3415 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3416 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3417 struct mlx5_ib_ucontext *c;
3418 struct mlx5_user_mmap_entry *entry;
3423 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3427 entry = alloc_var_entry(c);
3429 return PTR_ERR(entry);
3431 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3432 length = entry->rdma_entry.npages * PAGE_SIZE;
3433 uobj->object = entry;
3434 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3436 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3437 &mmap_offset, sizeof(mmap_offset));
3441 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3442 &entry->page_idx, sizeof(entry->page_idx));
3446 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3447 &length, sizeof(length));
3451 DECLARE_UVERBS_NAMED_METHOD(
3452 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3453 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3457 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3458 UVERBS_ATTR_TYPE(u32),
3460 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3461 UVERBS_ATTR_TYPE(u32),
3463 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3464 UVERBS_ATTR_TYPE(u64),
3467 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3468 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3469 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3471 UVERBS_ACCESS_DESTROY,
3474 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3475 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3476 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3477 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3479 static bool var_is_supported(struct ib_device *device)
3481 struct mlx5_ib_dev *dev = to_mdev(device);
3483 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3484 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3487 static struct mlx5_user_mmap_entry *
3488 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3489 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3491 struct mlx5_user_mmap_entry *entry;
3492 struct mlx5_ib_dev *dev;
3496 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3498 return ERR_PTR(-ENOMEM);
3500 dev = to_mdev(c->ibucontext.device);
3501 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3505 entry->page_idx = uar_index;
3506 entry->address = uar_index2paddress(dev, uar_index);
3507 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3508 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3510 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3512 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3519 mlx5_cmd_free_uar(dev->mdev, uar_index);
3522 return ERR_PTR(err);
3525 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3526 struct uverbs_attr_bundle *attrs)
3528 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3529 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3530 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3531 struct mlx5_ib_ucontext *c;
3532 struct mlx5_user_mmap_entry *entry;
3537 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3541 err = uverbs_get_const(&alloc_type, attrs,
3542 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3546 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3547 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3550 if (!to_mdev(c->ibucontext.device)->wc_support &&
3551 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3554 entry = alloc_uar_entry(c, alloc_type);
3556 return PTR_ERR(entry);
3558 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3559 length = entry->rdma_entry.npages * PAGE_SIZE;
3560 uobj->object = entry;
3561 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3563 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3564 &mmap_offset, sizeof(mmap_offset));
3568 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3569 &entry->page_idx, sizeof(entry->page_idx));
3573 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3574 &length, sizeof(length));
3578 DECLARE_UVERBS_NAMED_METHOD(
3579 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3580 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3584 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3585 enum mlx5_ib_uapi_uar_alloc_type,
3587 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3588 UVERBS_ATTR_TYPE(u32),
3590 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3591 UVERBS_ATTR_TYPE(u32),
3593 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3594 UVERBS_ATTR_TYPE(u64),
3597 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3598 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3599 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3601 UVERBS_ACCESS_DESTROY,
3604 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3605 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3606 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3607 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3609 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3610 mlx5_ib_flow_action,
3611 UVERBS_OBJECT_FLOW_ACTION,
3612 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3613 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3614 enum mlx5_ib_uapi_flow_action_flags));
3616 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3617 mlx5_ib_query_context,
3618 UVERBS_OBJECT_DEVICE,
3619 UVERBS_METHOD_QUERY_CONTEXT,
3620 UVERBS_ATTR_PTR_OUT(
3621 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3622 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3626 static const struct uapi_definition mlx5_ib_defs[] = {
3627 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3628 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3629 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3630 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3631 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3633 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3634 &mlx5_ib_flow_action),
3635 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3636 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3637 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3638 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3642 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3644 mlx5_ib_cleanup_multiport_master(dev);
3645 WARN_ON(!xa_empty(&dev->odp_mkeys));
3646 mutex_destroy(&dev->cap_mask_mutex);
3647 WARN_ON(!xa_empty(&dev->sig_mrs));
3648 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3651 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3653 struct mlx5_core_dev *mdev = dev->mdev;
3657 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3658 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3659 dev->ib_dev.phys_port_cnt = dev->num_ports;
3660 dev->ib_dev.dev.parent = mdev->device;
3661 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3663 for (i = 0; i < dev->num_ports; i++) {
3664 spin_lock_init(&dev->port[i].mp.mpi_lock);
3665 rwlock_init(&dev->port[i].roce.netdev_lock);
3666 dev->port[i].roce.dev = dev;
3667 dev->port[i].roce.native_port_num = i + 1;
3668 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3671 err = mlx5_ib_init_multiport_master(dev);
3675 err = set_has_smi_cap(dev);
3679 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3683 if (mlx5_use_mad_ifc(dev))
3684 get_ext_port_caps(dev);
3686 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3688 mutex_init(&dev->cap_mask_mutex);
3689 INIT_LIST_HEAD(&dev->qp_list);
3690 spin_lock_init(&dev->reset_flow_resource_lock);
3691 xa_init(&dev->odp_mkeys);
3692 xa_init(&dev->sig_mrs);
3693 atomic_set(&dev->mkey_var, 0);
3695 spin_lock_init(&dev->dm.lock);
3700 mlx5_ib_cleanup_multiport_master(dev);
3704 static int mlx5_ib_enable_driver(struct ib_device *dev)
3706 struct mlx5_ib_dev *mdev = to_mdev(dev);
3709 ret = mlx5_ib_test_wc(mdev);
3710 mlx5_ib_dbg(mdev, "Write-Combining %s",
3711 mdev->wc_support ? "supported" : "not supported");
3716 static const struct ib_device_ops mlx5_ib_dev_ops = {
3717 .owner = THIS_MODULE,
3718 .driver_id = RDMA_DRIVER_MLX5,
3719 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3721 .add_gid = mlx5_ib_add_gid,
3722 .alloc_mr = mlx5_ib_alloc_mr,
3723 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3724 .alloc_pd = mlx5_ib_alloc_pd,
3725 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3726 .attach_mcast = mlx5_ib_mcg_attach,
3727 .check_mr_status = mlx5_ib_check_mr_status,
3728 .create_ah = mlx5_ib_create_ah,
3729 .create_cq = mlx5_ib_create_cq,
3730 .create_qp = mlx5_ib_create_qp,
3731 .create_srq = mlx5_ib_create_srq,
3732 .create_user_ah = mlx5_ib_create_ah,
3733 .dealloc_pd = mlx5_ib_dealloc_pd,
3734 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3735 .del_gid = mlx5_ib_del_gid,
3736 .dereg_mr = mlx5_ib_dereg_mr,
3737 .destroy_ah = mlx5_ib_destroy_ah,
3738 .destroy_cq = mlx5_ib_destroy_cq,
3739 .destroy_qp = mlx5_ib_destroy_qp,
3740 .destroy_srq = mlx5_ib_destroy_srq,
3741 .detach_mcast = mlx5_ib_mcg_detach,
3742 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3743 .drain_rq = mlx5_ib_drain_rq,
3744 .drain_sq = mlx5_ib_drain_sq,
3745 .device_group = &mlx5_attr_group,
3746 .enable_driver = mlx5_ib_enable_driver,
3747 .get_dev_fw_str = get_dev_fw_str,
3748 .get_dma_mr = mlx5_ib_get_dma_mr,
3749 .get_link_layer = mlx5_ib_port_link_layer,
3750 .map_mr_sg = mlx5_ib_map_mr_sg,
3751 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3752 .mmap = mlx5_ib_mmap,
3753 .mmap_free = mlx5_ib_mmap_free,
3754 .modify_cq = mlx5_ib_modify_cq,
3755 .modify_device = mlx5_ib_modify_device,
3756 .modify_port = mlx5_ib_modify_port,
3757 .modify_qp = mlx5_ib_modify_qp,
3758 .modify_srq = mlx5_ib_modify_srq,
3759 .poll_cq = mlx5_ib_poll_cq,
3760 .post_recv = mlx5_ib_post_recv_nodrain,
3761 .post_send = mlx5_ib_post_send_nodrain,
3762 .post_srq_recv = mlx5_ib_post_srq_recv,
3763 .process_mad = mlx5_ib_process_mad,
3764 .query_ah = mlx5_ib_query_ah,
3765 .query_device = mlx5_ib_query_device,
3766 .query_gid = mlx5_ib_query_gid,
3767 .query_pkey = mlx5_ib_query_pkey,
3768 .query_qp = mlx5_ib_query_qp,
3769 .query_srq = mlx5_ib_query_srq,
3770 .query_ucontext = mlx5_ib_query_ucontext,
3771 .reg_user_mr = mlx5_ib_reg_user_mr,
3772 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3773 .req_notify_cq = mlx5_ib_arm_cq,
3774 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3775 .resize_cq = mlx5_ib_resize_cq,
3777 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3778 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3779 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3780 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3781 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3782 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3785 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3786 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3789 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3790 .get_vf_config = mlx5_ib_get_vf_config,
3791 .get_vf_guid = mlx5_ib_get_vf_guid,
3792 .get_vf_stats = mlx5_ib_get_vf_stats,
3793 .set_vf_guid = mlx5_ib_set_vf_guid,
3794 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3797 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3798 .alloc_mw = mlx5_ib_alloc_mw,
3799 .dealloc_mw = mlx5_ib_dealloc_mw,
3801 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3804 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3805 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3806 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3808 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3811 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3813 struct mlx5_core_dev *mdev = dev->mdev;
3814 struct mlx5_var_table *var_table = &dev->var_table;
3815 u8 log_doorbell_bar_size;
3816 u8 log_doorbell_stride;
3819 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3820 log_doorbell_bar_size);
3821 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3822 log_doorbell_stride);
3823 var_table->hw_start_addr = dev->mdev->bar_addr +
3824 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3825 doorbell_bar_offset);
3826 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3827 var_table->stride_size = 1ULL << log_doorbell_stride;
3828 var_table->num_var_hw_entries = div_u64(bar_size,
3829 var_table->stride_size);
3830 mutex_init(&var_table->bitmap_lock);
3831 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3833 return (var_table->bitmap) ? 0 : -ENOMEM;
3836 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3838 bitmap_free(dev->var_table.bitmap);
3841 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3843 struct mlx5_core_dev *mdev = dev->mdev;
3846 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3847 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3848 ib_set_device_ops(&dev->ib_dev,
3849 &mlx5_ib_dev_ipoib_enhanced_ops);
3851 if (mlx5_core_is_pf(mdev))
3852 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3854 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3856 if (MLX5_CAP_GEN(mdev, imaicl))
3857 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3859 if (MLX5_CAP_GEN(mdev, xrc))
3860 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3862 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3863 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3864 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3865 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3867 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3869 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3870 dev->ib_dev.driver_def = mlx5_ib_defs;
3872 err = init_node_data(dev);
3876 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3877 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3878 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3879 mutex_init(&dev->lb.mutex);
3881 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3882 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3883 err = mlx5_ib_init_var_table(dev);
3888 dev->ib_dev.use_cq_dim = true;
3893 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3894 .get_port_immutable = mlx5_port_immutable,
3895 .query_port = mlx5_ib_query_port,
3898 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3900 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3904 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3905 .get_port_immutable = mlx5_port_rep_immutable,
3906 .query_port = mlx5_ib_rep_query_port,
3907 .query_pkey = mlx5_ib_rep_query_pkey,
3910 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3912 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3916 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3917 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3918 .create_wq = mlx5_ib_create_wq,
3919 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3920 .destroy_wq = mlx5_ib_destroy_wq,
3921 .get_netdev = mlx5_ib_get_netdev,
3922 .modify_wq = mlx5_ib_modify_wq,
3924 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3928 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3930 struct mlx5_core_dev *mdev = dev->mdev;
3931 enum rdma_link_layer ll;
3936 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3937 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3939 if (ll == IB_LINK_LAYER_ETHERNET) {
3940 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3942 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3944 /* Register only for native ports */
3945 err = mlx5_add_netdev_notifier(dev, port_num);
3946 if (err || dev->is_rep || !mlx5_is_roce_init_enabled(mdev))
3948 * We don't enable ETH interface for
3949 * 1. IB representors
3950 * 2. User disabled ROCE through devlink interface
3954 err = mlx5_enable_eth(dev);
3961 mlx5_remove_netdev_notifier(dev, port_num);
3965 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3967 struct mlx5_core_dev *mdev = dev->mdev;
3968 enum rdma_link_layer ll;
3972 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3973 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3975 if (ll == IB_LINK_LAYER_ETHERNET) {
3977 mlx5_disable_eth(dev);
3979 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3980 mlx5_remove_netdev_notifier(dev, port_num);
3984 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
3986 mlx5_ib_init_cong_debugfs(dev,
3987 mlx5_core_native_port_num(dev->mdev) - 1);
3991 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
3993 mlx5_ib_cleanup_cong_debugfs(dev,
3994 mlx5_core_native_port_num(dev->mdev) - 1);
3997 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
3999 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4000 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4003 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4005 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4008 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4012 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4016 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4018 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4023 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4025 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4026 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4029 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4033 if (!mlx5_lag_is_roce(dev->mdev))
4036 name = "mlx5_bond_%d";
4037 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4040 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4044 err = mlx5_mr_cache_cleanup(dev);
4046 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4049 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4051 ib_free_cq(dev->umrc.cq);
4053 ib_dealloc_pd(dev->umrc.pd);
4056 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4058 ib_unregister_device(&dev->ib_dev);
4065 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4067 struct ib_qp_init_attr *init_attr = NULL;
4068 struct ib_qp_attr *attr = NULL;
4074 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4075 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4076 if (!attr || !init_attr) {
4081 pd = ib_alloc_pd(&dev->ib_dev, 0);
4083 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4088 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4090 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4095 init_attr->send_cq = cq;
4096 init_attr->recv_cq = cq;
4097 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4098 init_attr->cap.max_send_wr = MAX_UMR_WR;
4099 init_attr->cap.max_send_sge = 1;
4100 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4101 init_attr->port_num = 1;
4102 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4104 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4108 qp->device = &dev->ib_dev;
4111 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4112 qp->send_cq = init_attr->send_cq;
4113 qp->recv_cq = init_attr->recv_cq;
4115 attr->qp_state = IB_QPS_INIT;
4117 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4120 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4124 memset(attr, 0, sizeof(*attr));
4125 attr->qp_state = IB_QPS_RTR;
4126 attr->path_mtu = IB_MTU_256;
4128 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4130 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4134 memset(attr, 0, sizeof(*attr));
4135 attr->qp_state = IB_QPS_RTS;
4136 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4138 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4146 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4147 ret = mlx5_mr_cache_init(dev);
4149 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4159 mlx5_ib_destroy_qp(qp, NULL);
4160 dev->umrc.qp = NULL;
4164 dev->umrc.cq = NULL;
4168 dev->umrc.pd = NULL;
4176 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4178 struct dentry *root;
4180 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4183 mutex_init(&dev->delay_drop.lock);
4184 dev->delay_drop.dev = dev;
4185 dev->delay_drop.activate = false;
4186 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4187 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4188 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4189 atomic_set(&dev->delay_drop.events_cnt, 0);
4191 if (!mlx5_debugfs_root)
4194 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4195 dev->delay_drop.dir_debugfs = root;
4197 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4198 &dev->delay_drop.events_cnt);
4199 debugfs_create_atomic_t("num_rqs", 0400, root,
4200 &dev->delay_drop.rqs_cnt);
4201 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4202 &fops_delay_drop_timeout);
4206 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4208 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4211 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4212 if (!dev->delay_drop.dir_debugfs)
4215 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4216 dev->delay_drop.dir_debugfs = NULL;
4219 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4221 dev->mdev_events.notifier_call = mlx5_ib_event;
4222 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4226 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4228 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4231 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4232 const struct mlx5_ib_profile *profile,
4235 dev->ib_active = false;
4237 /* Number of stages to cleanup */
4240 if (profile->stage[stage].cleanup)
4241 profile->stage[stage].cleanup(dev);
4245 ib_dealloc_device(&dev->ib_dev);
4248 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4249 const struct mlx5_ib_profile *profile)
4254 dev->profile = profile;
4256 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4257 if (profile->stage[i].init) {
4258 err = profile->stage[i].init(dev);
4264 dev->ib_active = true;
4268 /* Clean up stages which were initialized */
4271 if (profile->stage[i].cleanup)
4272 profile->stage[i].cleanup(dev);
4277 static const struct mlx5_ib_profile pf_profile = {
4278 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4279 mlx5_ib_stage_init_init,
4280 mlx5_ib_stage_init_cleanup),
4281 STAGE_CREATE(MLX5_IB_STAGE_FS,
4283 mlx5_ib_fs_cleanup),
4284 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4285 mlx5_ib_stage_caps_init,
4286 mlx5_ib_stage_caps_cleanup),
4287 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4288 mlx5_ib_stage_non_default_cb,
4290 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4292 mlx5_ib_roce_cleanup),
4293 STAGE_CREATE(MLX5_IB_STAGE_QP,
4295 mlx5_cleanup_qp_table),
4296 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4297 mlx5_init_srq_table,
4298 mlx5_cleanup_srq_table),
4299 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4300 mlx5_ib_dev_res_init,
4301 mlx5_ib_dev_res_cleanup),
4302 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4303 mlx5_ib_stage_dev_notifier_init,
4304 mlx5_ib_stage_dev_notifier_cleanup),
4305 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4306 mlx5_ib_odp_init_one,
4307 mlx5_ib_odp_cleanup_one),
4308 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4309 mlx5_ib_counters_init,
4310 mlx5_ib_counters_cleanup),
4311 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4312 mlx5_ib_stage_cong_debugfs_init,
4313 mlx5_ib_stage_cong_debugfs_cleanup),
4314 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4315 mlx5_ib_stage_uar_init,
4316 mlx5_ib_stage_uar_cleanup),
4317 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4318 mlx5_ib_stage_bfrag_init,
4319 mlx5_ib_stage_bfrag_cleanup),
4320 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4322 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4323 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4325 mlx5_ib_devx_cleanup),
4326 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4327 mlx5_ib_stage_ib_reg_init,
4328 mlx5_ib_stage_ib_reg_cleanup),
4329 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4330 mlx5_ib_stage_post_ib_reg_umr_init,
4332 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4333 mlx5_ib_stage_delay_drop_init,
4334 mlx5_ib_stage_delay_drop_cleanup),
4335 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4336 mlx5_ib_restrack_init,
4340 const struct mlx5_ib_profile raw_eth_profile = {
4341 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4342 mlx5_ib_stage_init_init,
4343 mlx5_ib_stage_init_cleanup),
4344 STAGE_CREATE(MLX5_IB_STAGE_FS,
4346 mlx5_ib_fs_cleanup),
4347 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4348 mlx5_ib_stage_caps_init,
4349 mlx5_ib_stage_caps_cleanup),
4350 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4351 mlx5_ib_stage_raw_eth_non_default_cb,
4353 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4355 mlx5_ib_roce_cleanup),
4356 STAGE_CREATE(MLX5_IB_STAGE_QP,
4358 mlx5_cleanup_qp_table),
4359 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4360 mlx5_init_srq_table,
4361 mlx5_cleanup_srq_table),
4362 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4363 mlx5_ib_dev_res_init,
4364 mlx5_ib_dev_res_cleanup),
4365 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4366 mlx5_ib_stage_dev_notifier_init,
4367 mlx5_ib_stage_dev_notifier_cleanup),
4368 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4369 mlx5_ib_counters_init,
4370 mlx5_ib_counters_cleanup),
4371 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4372 mlx5_ib_stage_cong_debugfs_init,
4373 mlx5_ib_stage_cong_debugfs_cleanup),
4374 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4375 mlx5_ib_stage_uar_init,
4376 mlx5_ib_stage_uar_cleanup),
4377 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4378 mlx5_ib_stage_bfrag_init,
4379 mlx5_ib_stage_bfrag_cleanup),
4380 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4382 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4383 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4385 mlx5_ib_devx_cleanup),
4386 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4387 mlx5_ib_stage_ib_reg_init,
4388 mlx5_ib_stage_ib_reg_cleanup),
4389 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4390 mlx5_ib_stage_post_ib_reg_umr_init,
4392 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4393 mlx5_ib_restrack_init,
4397 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4398 const struct auxiliary_device_id *id)
4400 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4401 struct mlx5_core_dev *mdev = idev->mdev;
4402 struct mlx5_ib_multiport_info *mpi;
4403 struct mlx5_ib_dev *dev;
4407 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4412 err = mlx5_query_nic_vport_system_image_guid(mdev,
4413 &mpi->sys_image_guid);
4419 mutex_lock(&mlx5_ib_multiport_mutex);
4420 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4421 if (dev->sys_image_guid == mpi->sys_image_guid)
4422 bound = mlx5_ib_bind_slave_port(dev, mpi);
4425 rdma_roce_rescan_device(&dev->ib_dev);
4426 mpi->ibdev->ib_active = true;
4432 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4433 dev_dbg(mdev->device,
4434 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4436 mutex_unlock(&mlx5_ib_multiport_mutex);
4438 dev_set_drvdata(&adev->dev, mpi);
4442 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4444 struct mlx5_ib_multiport_info *mpi;
4446 mpi = dev_get_drvdata(&adev->dev);
4447 mutex_lock(&mlx5_ib_multiport_mutex);
4449 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4450 list_del(&mpi->list);
4451 mutex_unlock(&mlx5_ib_multiport_mutex);
4455 static int mlx5r_probe(struct auxiliary_device *adev,
4456 const struct auxiliary_device_id *id)
4458 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4459 struct mlx5_core_dev *mdev = idev->mdev;
4460 const struct mlx5_ib_profile *profile;
4461 int port_type_cap, num_ports, ret;
4462 enum rdma_link_layer ll;
4463 struct mlx5_ib_dev *dev;
4465 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4466 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4468 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4469 MLX5_CAP_GEN(mdev, num_vhca_ports));
4470 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4473 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4476 ib_dealloc_device(&dev->ib_dev);
4481 dev->num_ports = num_ports;
4483 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4484 profile = &raw_eth_profile;
4486 profile = &pf_profile;
4488 ret = __mlx5_ib_add(dev, profile);
4491 ib_dealloc_device(&dev->ib_dev);
4495 dev_set_drvdata(&adev->dev, dev);
4499 static void mlx5r_remove(struct auxiliary_device *adev)
4501 struct mlx5_ib_dev *dev;
4503 dev = dev_get_drvdata(&adev->dev);
4504 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4507 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4508 { .name = MLX5_ADEV_NAME ".multiport", },
4512 static const struct auxiliary_device_id mlx5r_id_table[] = {
4513 { .name = MLX5_ADEV_NAME ".rdma", },
4517 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4518 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4520 static struct auxiliary_driver mlx5r_mp_driver = {
4521 .name = "multiport",
4522 .probe = mlx5r_mp_probe,
4523 .remove = mlx5r_mp_remove,
4524 .id_table = mlx5r_mp_id_table,
4527 static struct auxiliary_driver mlx5r_driver = {
4529 .probe = mlx5r_probe,
4530 .remove = mlx5r_remove,
4531 .id_table = mlx5r_id_table,
4534 static int __init mlx5_ib_init(void)
4538 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4539 if (!xlt_emergency_page)
4542 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4543 if (!mlx5_ib_event_wq) {
4544 free_page((unsigned long)xlt_emergency_page);
4549 ret = mlx5r_rep_init();
4552 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4555 ret = auxiliary_driver_register(&mlx5r_driver);
4561 auxiliary_driver_unregister(&mlx5r_mp_driver);
4563 mlx5r_rep_cleanup();
4565 destroy_workqueue(mlx5_ib_event_wq);
4566 free_page((unsigned long)xlt_emergency_page);
4570 static void __exit mlx5_ib_cleanup(void)
4572 auxiliary_driver_unregister(&mlx5r_driver);
4573 auxiliary_driver_unregister(&mlx5r_mp_driver);
4574 mlx5r_rep_cleanup();
4576 destroy_workqueue(mlx5_ib_event_wq);
4577 free_page((unsigned long)xlt_emergency_page);
4580 module_init(mlx5_ib_init);
4581 module_exit(mlx5_ib_cleanup);