drivers/infiniband/hw/mlx5/main.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /*
   3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4  * Copyright (c) 2020, Intel Corporation. All rights reserved.
   5  */
   6
   7 #include <linux/debugfs.h>
   8 #include <linux/highmem.h>
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/errno.h>
  12 #include <linux/pci.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/slab.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/sched.h>
  17 #include <linux/sched/mm.h>
  18 #include <linux/sched/task.h>
  19 #include <linux/delay.h>
  20 #include <rdma/ib_user_verbs.h>
  21 #include <rdma/ib_addr.h>
  22 #include <rdma/ib_cache.h>
  23 #include <linux/mlx5/port.h>
  24 #include <linux/mlx5/vport.h>
  25 #include <linux/mlx5/fs.h>
  26 #include <linux/mlx5/eswitch.h>
  27 #include <linux/list.h>
  28 #include <rdma/ib_smi.h>
  29 #include <rdma/ib_umem.h>
  30 #include <rdma/lag.h>
  31 #include <linux/in.h>
  32 #include <linux/etherdevice.h>
  33 #include "mlx5_ib.h"
  34 #include "ib_rep.h"
  35 #include "cmd.h"
  36 #include "devx.h"
  37 #include "dm.h"
  38 #include "fs.h"
  39 #include "srq.h"
  40 #include "qp.h"
  41 #include "wr.h"
  42 #include "restrack.h"
  43 #include "counters.h"
  44 #include <linux/mlx5/accel.h>
  45 #include <rdma/uverbs_std_types.h>
  46 #include <rdma/uverbs_ioctl.h>
  47 #include <rdma/mlx5_user_ioctl_verbs.h>
  48 #include <rdma/mlx5_user_ioctl_cmds.h>
  49 #include <rdma/ib_umem_odp.h>
  50
  51 #define UVERBS_MODULE_NAME mlx5_ib
  52 #include <rdma/uverbs_named_ioctl.h>
  53
  54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57
  58 struct mlx5_ib_event_work {
  59         struct work_struct      work;
  60         union {
  61                 struct mlx5_ib_dev            *dev;
  62                 struct mlx5_ib_multiport_info *mpi;
  63         };
  64         bool                    is_slave;
  65         unsigned int            event;
  66         void                    *param;
  67 };
  68
  69 enum {
  70         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  71 };
  72
  73 static struct workqueue_struct *mlx5_ib_event_wq;
  74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  75 static LIST_HEAD(mlx5_ib_dev_list);
  76 /*
  77  * This mutex should be held when accessing either of the above lists
  78  */
  79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  80
  81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  82 {
  83         struct mlx5_ib_dev *dev;
  84
  85         mutex_lock(&mlx5_ib_multiport_mutex);
  86         dev = mpi->ibdev;
  87         mutex_unlock(&mlx5_ib_multiport_mutex);
  88         return dev;
  89 }
  90
  91 static enum rdma_link_layer
  92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  93 {
  94         switch (port_type_cap) {
  95         case MLX5_CAP_PORT_TYPE_IB:
  96                 return IB_LINK_LAYER_INFINIBAND;
  97         case MLX5_CAP_PORT_TYPE_ETH:
  98                 return IB_LINK_LAYER_ETHERNET;
  99         default:
 100                 return IB_LINK_LAYER_UNSPECIFIED;
 101         }
 102 }
 103
 104 static enum rdma_link_layer
 105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
 106 {
 107         struct mlx5_ib_dev *dev = to_mdev(device);
 108         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 109
 110         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 111 }
 112
 113 static int get_port_state(struct ib_device *ibdev,
 114                           u32 port_num,
 115                           enum ib_port_state *state)
 116 {
 117         struct ib_port_attr attr;
 118         int ret;
 119
 120         memset(&attr, 0, sizeof(attr));
 121         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 122         if (!ret)
 123                 *state = attr.state;
 124         return ret;
 125 }
 126
 127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 128                                            struct net_device *ndev,
 129                                            struct net_device *upper,
 130                                            u32 *port_num)
 131 {
 132         struct net_device *rep_ndev;
 133         struct mlx5_ib_port *port;
 134         int i;
 135
 136         for (i = 0; i < dev->num_ports; i++) {
 137                 port  = &dev->port[i];
 138                 if (!port->rep)
 139                         continue;
 140
 141                 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
 142                         *port_num = i + 1;
 143                         return &port->roce;
 144                 }
 145
 146                 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
 147                         continue;
 148
 149                 read_lock(&port->roce.netdev_lock);
 150                 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
 151                                                   port->rep->vport);
 152                 if (rep_ndev == ndev) {
 153                         read_unlock(&port->roce.netdev_lock);
 154                         *port_num = i + 1;
 155                         return &port->roce;
 156                 }
 157                 read_unlock(&port->roce.netdev_lock);
 158         }
 159
 160         return NULL;
 161 }
 162
 163 static int mlx5_netdev_event(struct notifier_block *this,
 164                              unsigned long event, void *ptr)
 165 {
 166         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 167         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 168         u32 port_num = roce->native_port_num;
 169         struct mlx5_core_dev *mdev;
 170         struct mlx5_ib_dev *ibdev;
 171
 172         ibdev = roce->dev;
 173         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 174         if (!mdev)
 175                 return NOTIFY_DONE;
 176
 177         switch (event) {
 178         case NETDEV_REGISTER:
 179                 /* Should already be registered during the load */
 180                 if (ibdev->is_rep)
 181                         break;
 182                 write_lock(&roce->netdev_lock);
 183                 if (ndev->dev.parent == mdev->device)
 184                         roce->netdev = ndev;
 185                 write_unlock(&roce->netdev_lock);
 186                 break;
 187
 188         case NETDEV_UNREGISTER:
 189                 /* In case of reps, ib device goes away before the netdevs */
 190                 write_lock(&roce->netdev_lock);
 191                 if (roce->netdev == ndev)
 192                         roce->netdev = NULL;
 193                 write_unlock(&roce->netdev_lock);
 194                 break;
 195
 196         case NETDEV_CHANGE:
 197         case NETDEV_UP:
 198         case NETDEV_DOWN: {
 199                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 200                 struct net_device *upper = NULL;
 201
 202                 if (lag_ndev) {
 203                         upper = netdev_master_upper_dev_get(lag_ndev);
 204                         dev_put(lag_ndev);
 205                 }
 206
 207                 if (ibdev->is_rep)
 208                         roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
 209                 if (!roce)
 210                         return NOTIFY_DONE;
 211                 if ((upper == ndev ||
 212                      ((!upper || ibdev->is_rep) && ndev == roce->netdev)) &&
 213                     ibdev->ib_active) {
 214                         struct ib_event ibev = { };
 215                         enum ib_port_state port_state;
 216
 217                         if (get_port_state(&ibdev->ib_dev, port_num,
 218                                            &port_state))
 219                                 goto done;
 220
 221                         if (roce->last_port_state == port_state)
 222                                 goto done;
 223
 224                         roce->last_port_state = port_state;
 225                         ibev.device = &ibdev->ib_dev;
 226                         if (port_state == IB_PORT_DOWN)
 227                                 ibev.event = IB_EVENT_PORT_ERR;
 228                         else if (port_state == IB_PORT_ACTIVE)
 229                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 230                         else
 231                                 goto done;
 232
 233                         ibev.element.port_num = port_num;
 234                         ib_dispatch_event(&ibev);
 235                 }
 236                 break;
 237         }
 238
 239         default:
 240                 break;
 241         }
 242 done:
 243         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 244         return NOTIFY_DONE;
 245 }
 246
 247 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 248                                              u32 port_num)
 249 {
 250         struct mlx5_ib_dev *ibdev = to_mdev(device);
 251         struct net_device *ndev;
 252         struct mlx5_core_dev *mdev;
 253
 254         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 255         if (!mdev)
 256                 return NULL;
 257
 258         ndev = mlx5_lag_get_roce_netdev(mdev);
 259         if (ndev)
 260                 goto out;
 261
 262         /* Ensure ndev does not disappear before we invoke dev_hold()
 263          */
 264         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 265         ndev = ibdev->port[port_num - 1].roce.netdev;
 266         if (ndev)
 267                 dev_hold(ndev);
 268         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 269
 270 out:
 271         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 272         return ndev;
 273 }
 274
 275 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 276                                                    u32 ib_port_num,
 277                                                    u32 *native_port_num)
 278 {
 279         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 280                                                           ib_port_num);
 281         struct mlx5_core_dev *mdev = NULL;
 282         struct mlx5_ib_multiport_info *mpi;
 283         struct mlx5_ib_port *port;
 284
 285         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 286             ll != IB_LINK_LAYER_ETHERNET) {
 287                 if (native_port_num)
 288                         *native_port_num = ib_port_num;
 289                 return ibdev->mdev;
 290         }
 291
 292         if (native_port_num)
 293                 *native_port_num = 1;
 294
 295         port = &ibdev->port[ib_port_num - 1];
 296         spin_lock(&port->mp.mpi_lock);
 297         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 298         if (mpi && !mpi->unaffiliate) {
 299                 mdev = mpi->mdev;
 300                 /* If it's the master no need to refcount, it'll exist
 301                  * as long as the ib_dev exists.
 302                  */
 303                 if (!mpi->is_master)
 304                         mpi->mdev_refcnt++;
 305         }
 306         spin_unlock(&port->mp.mpi_lock);
 307
 308         return mdev;
 309 }
 310
 311 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
 312 {
 313         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 314                                                           port_num);
 315         struct mlx5_ib_multiport_info *mpi;
 316         struct mlx5_ib_port *port;
 317
 318         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 319                 return;
 320
 321         port = &ibdev->port[port_num - 1];
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[port_num - 1].mp.mpi;
 325         if (mpi->is_master)
 326                 goto out;
 327
 328         mpi->mdev_refcnt--;
 329         if (mpi->unaffiliate)
 330                 complete(&mpi->unref_comp);
 331 out:
 332         spin_unlock(&port->mp.mpi_lock);
 333 }
 334
 335 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 336                                            u16 *active_speed, u8 *active_width)
 337 {
 338         switch (eth_proto_oper) {
 339         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 340         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 341         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 342         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 343                 *active_width = IB_WIDTH_1X;
 344                 *active_speed = IB_SPEED_SDR;
 345                 break;
 346         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 347         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 348         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 349         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 350         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 351         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 352         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 353                 *active_width = IB_WIDTH_1X;
 354                 *active_speed = IB_SPEED_QDR;
 355                 break;
 356         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 357         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 358         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 359                 *active_width = IB_WIDTH_1X;
 360                 *active_speed = IB_SPEED_EDR;
 361                 break;
 362         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 363         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 364         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 365         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 366                 *active_width = IB_WIDTH_4X;
 367                 *active_speed = IB_SPEED_QDR;
 368                 break;
 369         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 370         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 371         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 372                 *active_width = IB_WIDTH_1X;
 373                 *active_speed = IB_SPEED_HDR;
 374                 break;
 375         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 376                 *active_width = IB_WIDTH_4X;
 377                 *active_speed = IB_SPEED_FDR;
 378                 break;
 379         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 380         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 381         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 382         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 383                 *active_width = IB_WIDTH_4X;
 384                 *active_speed = IB_SPEED_EDR;
 385                 break;
 386         default:
 387                 return -EINVAL;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 394                                         u8 *active_width)
 395 {
 396         switch (eth_proto_oper) {
 397         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 398         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_SDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 403                 *active_width = IB_WIDTH_1X;
 404                 *active_speed = IB_SPEED_DDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 407                 *active_width = IB_WIDTH_1X;
 408                 *active_speed = IB_SPEED_QDR;
 409                 break;
 410         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 411                 *active_width = IB_WIDTH_4X;
 412                 *active_speed = IB_SPEED_QDR;
 413                 break;
 414         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 415                 *active_width = IB_WIDTH_1X;
 416                 *active_speed = IB_SPEED_EDR;
 417                 break;
 418         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 419                 *active_width = IB_WIDTH_2X;
 420                 *active_speed = IB_SPEED_EDR;
 421                 break;
 422         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 423                 *active_width = IB_WIDTH_1X;
 424                 *active_speed = IB_SPEED_HDR;
 425                 break;
 426         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 427                 *active_width = IB_WIDTH_4X;
 428                 *active_speed = IB_SPEED_EDR;
 429                 break;
 430         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 431                 *active_width = IB_WIDTH_2X;
 432                 *active_speed = IB_SPEED_HDR;
 433                 break;
 434         case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
 435                 *active_width = IB_WIDTH_1X;
 436                 *active_speed = IB_SPEED_NDR;
 437                 break;
 438         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 439                 *active_width = IB_WIDTH_4X;
 440                 *active_speed = IB_SPEED_HDR;
 441                 break;
 442         case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
 443                 *active_width = IB_WIDTH_2X;
 444                 *active_speed = IB_SPEED_NDR;
 445                 break;
 446         case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
 447                 *active_width = IB_WIDTH_4X;
 448                 *active_speed = IB_SPEED_NDR;
 449                 break;
 450         default:
 451                 return -EINVAL;
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 458                                     u8 *active_width, bool ext)
 459 {
 460         return ext ?
 461                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 462                                              active_width) :
 463                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 464                                                 active_width);
 465 }
 466
 467 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
 468                                 struct ib_port_attr *props)
 469 {
 470         struct mlx5_ib_dev *dev = to_mdev(device);
 471         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 472         struct mlx5_core_dev *mdev;
 473         struct net_device *ndev, *upper;
 474         enum ib_mtu ndev_ib_mtu;
 475         bool put_mdev = true;
 476         u32 eth_prot_oper;
 477         u32 mdev_port_num;
 478         bool ext;
 479         int err;
 480
 481         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 482         if (!mdev) {
 483                 /* This means the port isn't affiliated yet. Get the
 484                  * info for the master port instead.
 485                  */
 486                 put_mdev = false;
 487                 mdev = dev->mdev;
 488                 mdev_port_num = 1;
 489                 port_num = 1;
 490         }
 491
 492         /* Possible bad flows are checked before filling out props so in case
 493          * of an error it will still be zeroed out.
 494          * Use native port in case of reps
 495          */
 496         if (dev->is_rep)
 497                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 498                                            1);
 499         else
 500                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 501                                            mdev_port_num);
 502         if (err)
 503                 goto out;
 504         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 505         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 506
 507         props->active_width     = IB_WIDTH_4X;
 508         props->active_speed     = IB_SPEED_QDR;
 509
 510         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 511                                  &props->active_width, ext);
 512
 513         if (!dev->is_rep && dev->mdev->roce.roce_en) {
 514                 u16 qkey_viol_cntr;
 515
 516                 props->port_cap_flags |= IB_PORT_CM_SUP;
 517                 props->ip_gids = true;
 518                 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
 519                                                    roce_address_table_size);
 520                 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 521                 props->qkey_viol_cntr = qkey_viol_cntr;
 522         }
 523         props->max_mtu          = IB_MTU_4096;
 524         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 525         props->pkey_tbl_len     = 1;
 526         props->state            = IB_PORT_DOWN;
 527         props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 528
 529         /* If this is a stub query for an unaffiliated port stop here */
 530         if (!put_mdev)
 531                 goto out;
 532
 533         ndev = mlx5_ib_get_netdev(device, port_num);
 534         if (!ndev)
 535                 goto out;
 536
 537         if (dev->lag_active) {
 538                 rcu_read_lock();
 539                 upper = netdev_master_upper_dev_get_rcu(ndev);
 540                 if (upper) {
 541                         dev_put(ndev);
 542                         ndev = upper;
 543                         dev_hold(ndev);
 544                 }
 545                 rcu_read_unlock();
 546         }
 547
 548         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 549                 props->state      = IB_PORT_ACTIVE;
 550                 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 551         }
 552
 553         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 554
 555         dev_put(ndev);
 556
 557         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 558 out:
 559         if (put_mdev)
 560                 mlx5_ib_put_native_port_mdev(dev, port_num);
 561         return err;
 562 }
 563
 564 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
 565                          unsigned int index, const union ib_gid *gid,
 566                          const struct ib_gid_attr *attr)
 567 {
 568         enum ib_gid_type gid_type;
 569         u16 vlan_id = 0xffff;
 570         u8 roce_version = 0;
 571         u8 roce_l3_type = 0;
 572         u8 mac[ETH_ALEN];
 573         int ret;
 574
 575         gid_type = attr->gid_type;
 576         if (gid) {
 577                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 578                 if (ret)
 579                         return ret;
 580         }
 581
 582         switch (gid_type) {
 583         case IB_GID_TYPE_ROCE:
 584                 roce_version = MLX5_ROCE_VERSION_1;
 585                 break;
 586         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 587                 roce_version = MLX5_ROCE_VERSION_2;
 588                 if (gid && ipv6_addr_v4mapped((void *)gid))
 589                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 590                 else
 591                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 592                 break;
 593
 594         default:
 595                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 596         }
 597
 598         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 599                                       roce_l3_type, gid->raw, mac,
 600                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 601                                       port_num);
 602 }
 603
 604 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 605                            __always_unused void **context)
 606 {
 607         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 608                              attr->index, &attr->gid, attr);
 609 }
 610
 611 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 612                            __always_unused void **context)
 613 {
 614         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 615                              attr->index, NULL, attr);
 616 }
 617
 618 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 619                                    const struct ib_gid_attr *attr)
 620 {
 621         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 622                 return 0;
 623
 624         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 625 }
 626
 627 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 628 {
 629         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 630                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 631         return 0;
 632 }
 633
 634 enum {
 635         MLX5_VPORT_ACCESS_METHOD_MAD,
 636         MLX5_VPORT_ACCESS_METHOD_HCA,
 637         MLX5_VPORT_ACCESS_METHOD_NIC,
 638 };
 639
 640 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 641 {
 642         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 643                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 644
 645         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 646             IB_LINK_LAYER_ETHERNET)
 647                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 648
 649         return MLX5_VPORT_ACCESS_METHOD_HCA;
 650 }
 651
 652 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 653                             u8 atomic_size_qp,
 654                             struct ib_device_attr *props)
 655 {
 656         u8 tmp;
 657         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 658         u8 atomic_req_8B_endianness_mode =
 659                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 660
 661         /* Check if HW supports 8 bytes standard atomic operations and capable
 662          * of host endianness respond
 663          */
 664         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 665         if (((atomic_operations & tmp) == tmp) &&
 666             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 667             (atomic_req_8B_endianness_mode)) {
 668                 props->atomic_cap = IB_ATOMIC_HCA;
 669         } else {
 670                 props->atomic_cap = IB_ATOMIC_NONE;
 671         }
 672 }
 673
 674 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 675                                struct ib_device_attr *props)
 676 {
 677         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 678
 679         get_atomic_caps(dev, atomic_size_qp, props);
 680 }
 681
 682 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 683                                         __be64 *sys_image_guid)
 684 {
 685         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 686         struct mlx5_core_dev *mdev = dev->mdev;
 687         u64 tmp;
 688         int err;
 689
 690         switch (mlx5_get_vport_access_method(ibdev)) {
 691         case MLX5_VPORT_ACCESS_METHOD_MAD:
 692                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 693                                                             sys_image_guid);
 694
 695         case MLX5_VPORT_ACCESS_METHOD_HCA:
 696                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 697                 break;
 698
 699         case MLX5_VPORT_ACCESS_METHOD_NIC:
 700                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 701                 break;
 702
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         if (!err)
 708                 *sys_image_guid = cpu_to_be64(tmp);
 709
 710         return err;
 711
 712 }
 713
 714 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 715                                 u16 *max_pkeys)
 716 {
 717         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 718         struct mlx5_core_dev *mdev = dev->mdev;
 719
 720         switch (mlx5_get_vport_access_method(ibdev)) {
 721         case MLX5_VPORT_ACCESS_METHOD_MAD:
 722                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725         case MLX5_VPORT_ACCESS_METHOD_NIC:
 726                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 727                                                 pkey_table_size));
 728                 return 0;
 729
 730         default:
 731                 return -EINVAL;
 732         }
 733 }
 734
 735 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 736                                 u32 *vendor_id)
 737 {
 738         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 739
 740         switch (mlx5_get_vport_access_method(ibdev)) {
 741         case MLX5_VPORT_ACCESS_METHOD_MAD:
 742                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 743
 744         case MLX5_VPORT_ACCESS_METHOD_HCA:
 745         case MLX5_VPORT_ACCESS_METHOD_NIC:
 746                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 747
 748         default:
 749                 return -EINVAL;
 750         }
 751 }
 752
 753 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 754                                 __be64 *node_guid)
 755 {
 756         u64 tmp;
 757         int err;
 758
 759         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 760         case MLX5_VPORT_ACCESS_METHOD_MAD:
 761                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 762
 763         case MLX5_VPORT_ACCESS_METHOD_HCA:
 764                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 765                 break;
 766
 767         case MLX5_VPORT_ACCESS_METHOD_NIC:
 768                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 769                 break;
 770
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         if (!err)
 776                 *node_guid = cpu_to_be64(tmp);
 777
 778         return err;
 779 }
 780
 781 struct mlx5_reg_node_desc {
 782         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 783 };
 784
 785 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 786 {
 787         struct mlx5_reg_node_desc in;
 788
 789         if (mlx5_use_mad_ifc(dev))
 790                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 791
 792         memset(&in, 0, sizeof(in));
 793
 794         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 795                                     sizeof(struct mlx5_reg_node_desc),
 796                                     MLX5_REG_NODE_DESC, 0, 0);
 797 }
 798
 799 static int mlx5_ib_query_device(struct ib_device *ibdev,
 800                                 struct ib_device_attr *props,
 801                                 struct ib_udata *uhw)
 802 {
 803         size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 804         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 805         struct mlx5_core_dev *mdev = dev->mdev;
 806         int err = -ENOMEM;
 807         int max_sq_desc;
 808         int max_rq_sg;
 809         int max_sq_sg;
 810         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 811         bool raw_support = !mlx5_core_mp_enabled(mdev);
 812         struct mlx5_ib_query_device_resp resp = {};
 813         size_t resp_len;
 814         u64 max_tso;
 815
 816         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 817         if (uhw_outlen && uhw_outlen < resp_len)
 818                 return -EINVAL;
 819
 820         resp.response_length = resp_len;
 821
 822         if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 823                 return -EINVAL;
 824
 825         memset(props, 0, sizeof(*props));
 826         err = mlx5_query_system_image_guid(ibdev,
 827                                            &props->sys_image_guid);
 828         if (err)
 829                 return err;
 830
 831         props->max_pkeys = dev->pkey_table_len;
 832
 833         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 834         if (err)
 835                 return err;
 836
 837         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 838                 (fw_rev_min(dev->mdev) << 16) |
 839                 fw_rev_sub(dev->mdev);
 840         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 841                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 842                 IB_DEVICE_SYS_IMAGE_GUID                |
 843                 IB_DEVICE_RC_RNR_NAK_GEN;
 844
 845         if (MLX5_CAP_GEN(mdev, pkv))
 846                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 847         if (MLX5_CAP_GEN(mdev, qkv))
 848                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 849         if (MLX5_CAP_GEN(mdev, apm))
 850                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 851         if (MLX5_CAP_GEN(mdev, xrc))
 852                 props->device_cap_flags |= IB_DEVICE_XRC;
 853         if (MLX5_CAP_GEN(mdev, imaicl)) {
 854                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 855                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 856                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 857                 /* We support 'Gappy' memory registration too */
 858                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 859         }
 860         /* IB_WR_REG_MR always requires changing the entity size with UMR */
 861         if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
 862                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 863         if (MLX5_CAP_GEN(mdev, sho)) {
 864                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 865                 /* At this stage no support for signature handover */
 866                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 867                                       IB_PROT_T10DIF_TYPE_2 |
 868                                       IB_PROT_T10DIF_TYPE_3;
 869                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 870                                        IB_GUARD_T10DIF_CSUM;
 871         }
 872         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 873                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 874
 875         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 876                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 877                         /* Legacy bit to support old userspace libraries */
 878                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 879                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 880                 }
 881
 882                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 883                         props->raw_packet_caps |=
 884                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 885
 886                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
 887                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 888                         if (max_tso) {
 889                                 resp.tso_caps.max_tso = 1 << max_tso;
 890                                 resp.tso_caps.supported_qpts |=
 891                                         1 << IB_QPT_RAW_PACKET;
 892                                 resp.response_length += sizeof(resp.tso_caps);
 893                         }
 894                 }
 895
 896                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
 897                         resp.rss_caps.rx_hash_function =
 898                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 899                         resp.rss_caps.rx_hash_fields_mask =
 900                                                 MLX5_RX_HASH_SRC_IPV4 |
 901                                                 MLX5_RX_HASH_DST_IPV4 |
 902                                                 MLX5_RX_HASH_SRC_IPV6 |
 903                                                 MLX5_RX_HASH_DST_IPV6 |
 904                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 905                                                 MLX5_RX_HASH_DST_PORT_TCP |
 906                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 907                                                 MLX5_RX_HASH_DST_PORT_UDP |
 908                                                 MLX5_RX_HASH_INNER;
 909                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 910                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 911                                 resp.rss_caps.rx_hash_fields_mask |=
 912                                         MLX5_RX_HASH_IPSEC_SPI;
 913                         resp.response_length += sizeof(resp.rss_caps);
 914                 }
 915         } else {
 916                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
 917                         resp.response_length += sizeof(resp.tso_caps);
 918                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
 919                         resp.response_length += sizeof(resp.rss_caps);
 920         }
 921
 922         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 923                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 924                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 925         }
 926
 927         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 928             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 929             raw_support)
 930                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 931
 932         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 933             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 934                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 935
 936         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 937             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 938             raw_support) {
 939                 /* Legacy bit to support old userspace libraries */
 940                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 941                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 942         }
 943
 944         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 945                 props->max_dm_size =
 946                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 947         }
 948
 949         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 950                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 951
 952         if (MLX5_CAP_GEN(mdev, end_pad))
 953                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 954
 955         props->vendor_part_id      = mdev->pdev->device;
 956         props->hw_ver              = mdev->pdev->revision;
 957
 958         props->max_mr_size         = ~0ull;
 959         props->page_size_cap       = ~(min_page_size - 1);
 960         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 961         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 962         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 963                      sizeof(struct mlx5_wqe_data_seg);
 964         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 965         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 966                      sizeof(struct mlx5_wqe_raddr_seg)) /
 967                 sizeof(struct mlx5_wqe_data_seg);
 968         props->max_send_sge = max_sq_sg;
 969         props->max_recv_sge = max_rq_sg;
 970         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 971         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 972         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 973         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 974         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 975         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 976         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 977         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 978         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 979         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 980         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 981         props->max_srq_sge         = max_rq_sg - 1;
 982         props->max_fast_reg_page_list_len =
 983                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 984         props->max_pi_fast_reg_page_list_len =
 985                 props->max_fast_reg_page_list_len / 2;
 986         props->max_sgl_rd =
 987                 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
 988         get_atomic_caps_qp(dev, props);
 989         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 990         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 991         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 992         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 993                                            props->max_mcast_grp;
 994         props->max_ah = INT_MAX;
 995         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 996         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 997
 998         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
 999                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1000                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1001                 props->odp_caps = dev->odp_caps;
1002                 if (!uhw) {
1003                         /* ODP for kernel QPs is not implemented for receive
1004                          * WQEs and SRQ WQEs
1005                          */
1006                         props->odp_caps.per_transport_caps.rc_odp_caps &=
1007                                 ~(IB_ODP_SUPPORT_READ |
1008                                   IB_ODP_SUPPORT_SRQ_RECV);
1009                         props->odp_caps.per_transport_caps.uc_odp_caps &=
1010                                 ~(IB_ODP_SUPPORT_READ |
1011                                   IB_ODP_SUPPORT_SRQ_RECV);
1012                         props->odp_caps.per_transport_caps.ud_odp_caps &=
1013                                 ~(IB_ODP_SUPPORT_READ |
1014                                   IB_ODP_SUPPORT_SRQ_RECV);
1015                         props->odp_caps.per_transport_caps.xrc_odp_caps &=
1016                                 ~(IB_ODP_SUPPORT_READ |
1017                                   IB_ODP_SUPPORT_SRQ_RECV);
1018                 }
1019         }
1020
1021         if (MLX5_CAP_GEN(mdev, cd))
1022                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1023
1024         if (mlx5_core_is_vf(mdev))
1025                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1026
1027         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1028             IB_LINK_LAYER_ETHERNET && raw_support) {
1029                 props->rss_caps.max_rwq_indirection_tables =
1030                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1031                 props->rss_caps.max_rwq_indirection_table_size =
1032                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1033                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1034                 props->max_wq_type_rq =
1035                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1036         }
1037
1038         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1039                 props->tm_caps.max_num_tags =
1040                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1041                 props->tm_caps.max_ops =
1042                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1043                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1044         }
1045
1046         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1047             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1048                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1049                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1050         }
1051
1052         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1053                 props->cq_caps.max_cq_moderation_count =
1054                                                 MLX5_MAX_CQ_COUNT;
1055                 props->cq_caps.max_cq_moderation_period =
1056                                                 MLX5_MAX_CQ_PERIOD;
1057         }
1058
1059         if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1060                 resp.response_length += sizeof(resp.cqe_comp_caps);
1061
1062                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1063                         resp.cqe_comp_caps.max_num =
1064                                 MLX5_CAP_GEN(dev->mdev,
1065                                              cqe_compression_max_num);
1066
1067                         resp.cqe_comp_caps.supported_format =
1068                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1069                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1070
1071                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1072                                 resp.cqe_comp_caps.supported_format |=
1073                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1074                 }
1075         }
1076
1077         if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1078             raw_support) {
1079                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1080                     MLX5_CAP_GEN(mdev, qos)) {
1081                         resp.packet_pacing_caps.qp_rate_limit_max =
1082                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1083                         resp.packet_pacing_caps.qp_rate_limit_min =
1084                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1085                         resp.packet_pacing_caps.supported_qpts |=
1086                                 1 << IB_QPT_RAW_PACKET;
1087                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1088                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1089                                 resp.packet_pacing_caps.cap_flags |=
1090                                         MLX5_IB_PP_SUPPORT_BURST;
1091                 }
1092                 resp.response_length += sizeof(resp.packet_pacing_caps);
1093         }
1094
1095         if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1096             uhw_outlen) {
1097                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1098                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1099                                 MLX5_IB_ALLOW_MPW;
1100
1101                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1102                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1103                                 MLX5_IB_SUPPORT_EMPW;
1104
1105                 resp.response_length +=
1106                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1107         }
1108
1109         if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1110                 resp.response_length += sizeof(resp.flags);
1111
1112                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1113                         resp.flags |=
1114                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1115
1116                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1117                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1118                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1119                         resp.flags |=
1120                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1121
1122                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1123         }
1124
1125         if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1126                 resp.response_length += sizeof(resp.sw_parsing_caps);
1127                 if (MLX5_CAP_ETH(mdev, swp)) {
1128                         resp.sw_parsing_caps.sw_parsing_offloads |=
1129                                 MLX5_IB_SW_PARSING;
1130
1131                         if (MLX5_CAP_ETH(mdev, swp_csum))
1132                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1133                                         MLX5_IB_SW_PARSING_CSUM;
1134
1135                         if (MLX5_CAP_ETH(mdev, swp_lso))
1136                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1137                                         MLX5_IB_SW_PARSING_LSO;
1138
1139                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1140                                 resp.sw_parsing_caps.supported_qpts =
1141                                         BIT(IB_QPT_RAW_PACKET);
1142                 }
1143         }
1144
1145         if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1146             raw_support) {
1147                 resp.response_length += sizeof(resp.striding_rq_caps);
1148                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1149                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1150                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1151                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1152                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1153                         if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1154                                 resp.striding_rq_caps
1155                                         .min_single_wqe_log_num_of_strides =
1156                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1157                         else
1158                                 resp.striding_rq_caps
1159                                         .min_single_wqe_log_num_of_strides =
1160                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1161                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1162                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1163                         resp.striding_rq_caps.supported_qpts =
1164                                 BIT(IB_QPT_RAW_PACKET);
1165                 }
1166         }
1167
1168         if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1169                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1170                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1171                         resp.tunnel_offloads_caps |=
1172                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1173                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1174                         resp.tunnel_offloads_caps |=
1175                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1176                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1177                         resp.tunnel_offloads_caps |=
1178                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1179                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1180                         resp.tunnel_offloads_caps |=
1181                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1182                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1183                         resp.tunnel_offloads_caps |=
1184                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1185         }
1186
1187         if (uhw_outlen) {
1188                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1189
1190                 if (err)
1191                         return err;
1192         }
1193
1194         return 0;
1195 }
1196
1197 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1198                                    u8 *ib_width)
1199 {
1200         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1201
1202         if (active_width & MLX5_PTYS_WIDTH_1X)
1203                 *ib_width = IB_WIDTH_1X;
1204         else if (active_width & MLX5_PTYS_WIDTH_2X)
1205                 *ib_width = IB_WIDTH_2X;
1206         else if (active_width & MLX5_PTYS_WIDTH_4X)
1207                 *ib_width = IB_WIDTH_4X;
1208         else if (active_width & MLX5_PTYS_WIDTH_8X)
1209                 *ib_width = IB_WIDTH_8X;
1210         else if (active_width & MLX5_PTYS_WIDTH_12X)
1211                 *ib_width = IB_WIDTH_12X;
1212         else {
1213                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1214                             active_width);
1215                 *ib_width = IB_WIDTH_4X;
1216         }
1217
1218         return;
1219 }
1220
1221 static int mlx5_mtu_to_ib_mtu(int mtu)
1222 {
1223         switch (mtu) {
1224         case 256: return 1;
1225         case 512: return 2;
1226         case 1024: return 3;
1227         case 2048: return 4;
1228         case 4096: return 5;
1229         default:
1230                 pr_warn("invalid mtu\n");
1231                 return -1;
1232         }
1233 }
1234
1235 enum ib_max_vl_num {
1236         __IB_MAX_VL_0           = 1,
1237         __IB_MAX_VL_0_1         = 2,
1238         __IB_MAX_VL_0_3         = 3,
1239         __IB_MAX_VL_0_7         = 4,
1240         __IB_MAX_VL_0_14        = 5,
1241 };
1242
1243 enum mlx5_vl_hw_cap {
1244         MLX5_VL_HW_0    = 1,
1245         MLX5_VL_HW_0_1  = 2,
1246         MLX5_VL_HW_0_2  = 3,
1247         MLX5_VL_HW_0_3  = 4,
1248         MLX5_VL_HW_0_4  = 5,
1249         MLX5_VL_HW_0_5  = 6,
1250         MLX5_VL_HW_0_6  = 7,
1251         MLX5_VL_HW_0_7  = 8,
1252         MLX5_VL_HW_0_14 = 15
1253 };
1254
1255 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1256                                 u8 *max_vl_num)
1257 {
1258         switch (vl_hw_cap) {
1259         case MLX5_VL_HW_0:
1260                 *max_vl_num = __IB_MAX_VL_0;
1261                 break;
1262         case MLX5_VL_HW_0_1:
1263                 *max_vl_num = __IB_MAX_VL_0_1;
1264                 break;
1265         case MLX5_VL_HW_0_3:
1266                 *max_vl_num = __IB_MAX_VL_0_3;
1267                 break;
1268         case MLX5_VL_HW_0_7:
1269                 *max_vl_num = __IB_MAX_VL_0_7;
1270                 break;
1271         case MLX5_VL_HW_0_14:
1272                 *max_vl_num = __IB_MAX_VL_0_14;
1273                 break;
1274
1275         default:
1276                 return -EINVAL;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1283                                struct ib_port_attr *props)
1284 {
1285         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1286         struct mlx5_core_dev *mdev = dev->mdev;
1287         struct mlx5_hca_vport_context *rep;
1288         u16 max_mtu;
1289         u16 oper_mtu;
1290         int err;
1291         u16 ib_link_width_oper;
1292         u8 vl_hw_cap;
1293
1294         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1295         if (!rep) {
1296                 err = -ENOMEM;
1297                 goto out;
1298         }
1299
1300         /* props being zeroed by the caller, avoid zeroing it here */
1301
1302         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1303         if (err)
1304                 goto out;
1305
1306         props->lid              = rep->lid;
1307         props->lmc              = rep->lmc;
1308         props->sm_lid           = rep->sm_lid;
1309         props->sm_sl            = rep->sm_sl;
1310         props->state            = rep->vport_state;
1311         props->phys_state       = rep->port_physical_state;
1312         props->port_cap_flags   = rep->cap_mask1;
1313         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1314         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1315         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1316         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1317         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1318         props->subnet_timeout   = rep->subnet_timeout;
1319         props->init_type_reply  = rep->init_type_reply;
1320
1321         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1322                 props->port_cap_flags2 = rep->cap_mask2;
1323
1324         err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1325                                       &props->active_speed, port);
1326         if (err)
1327                 goto out;
1328
1329         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1330
1331         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1332
1333         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1334
1335         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1336
1337         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1338
1339         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1340         if (err)
1341                 goto out;
1342
1343         err = translate_max_vl_num(ibdev, vl_hw_cap,
1344                                    &props->max_vl_num);
1345 out:
1346         kfree(rep);
1347         return err;
1348 }
1349
1350 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1351                        struct ib_port_attr *props)
1352 {
1353         unsigned int count;
1354         int ret;
1355
1356         switch (mlx5_get_vport_access_method(ibdev)) {
1357         case MLX5_VPORT_ACCESS_METHOD_MAD:
1358                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1359                 break;
1360
1361         case MLX5_VPORT_ACCESS_METHOD_HCA:
1362                 ret = mlx5_query_hca_port(ibdev, port, props);
1363                 break;
1364
1365         case MLX5_VPORT_ACCESS_METHOD_NIC:
1366                 ret = mlx5_query_port_roce(ibdev, port, props);
1367                 break;
1368
1369         default:
1370                 ret = -EINVAL;
1371         }
1372
1373         if (!ret && props) {
1374                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1375                 struct mlx5_core_dev *mdev;
1376                 bool put_mdev = true;
1377
1378                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1379                 if (!mdev) {
1380                         /* If the port isn't affiliated yet query the master.
1381                          * The master and slave will have the same values.
1382                          */
1383                         mdev = dev->mdev;
1384                         port = 1;
1385                         put_mdev = false;
1386                 }
1387                 count = mlx5_core_reserved_gids_count(mdev);
1388                 if (put_mdev)
1389                         mlx5_ib_put_native_port_mdev(dev, port);
1390                 props->gid_tbl_len -= count;
1391         }
1392         return ret;
1393 }
1394
1395 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1396                                   struct ib_port_attr *props)
1397 {
1398         return mlx5_query_port_roce(ibdev, port, props);
1399 }
1400
1401 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1402                                   u16 *pkey)
1403 {
1404         /* Default special Pkey for representor device port as per the
1405          * IB specification 1.3 section 10.9.1.2.
1406          */
1407         *pkey = 0xffff;
1408         return 0;
1409 }
1410
1411 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1412                              union ib_gid *gid)
1413 {
1414         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1415         struct mlx5_core_dev *mdev = dev->mdev;
1416
1417         switch (mlx5_get_vport_access_method(ibdev)) {
1418         case MLX5_VPORT_ACCESS_METHOD_MAD:
1419                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1420
1421         case MLX5_VPORT_ACCESS_METHOD_HCA:
1422                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1423
1424         default:
1425                 return -EINVAL;
1426         }
1427
1428 }
1429
1430 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1431                                    u16 index, u16 *pkey)
1432 {
1433         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1434         struct mlx5_core_dev *mdev;
1435         bool put_mdev = true;
1436         u32 mdev_port_num;
1437         int err;
1438
1439         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1440         if (!mdev) {
1441                 /* The port isn't affiliated yet, get the PKey from the master
1442                  * port. For RoCE the PKey tables will be the same.
1443                  */
1444                 put_mdev = false;
1445                 mdev = dev->mdev;
1446                 mdev_port_num = 1;
1447         }
1448
1449         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1450                                         index, pkey);
1451         if (put_mdev)
1452                 mlx5_ib_put_native_port_mdev(dev, port);
1453
1454         return err;
1455 }
1456
1457 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1458                               u16 *pkey)
1459 {
1460         switch (mlx5_get_vport_access_method(ibdev)) {
1461         case MLX5_VPORT_ACCESS_METHOD_MAD:
1462                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1463
1464         case MLX5_VPORT_ACCESS_METHOD_HCA:
1465         case MLX5_VPORT_ACCESS_METHOD_NIC:
1466                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1467         default:
1468                 return -EINVAL;
1469         }
1470 }
1471
1472 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1473                                  struct ib_device_modify *props)
1474 {
1475         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1476         struct mlx5_reg_node_desc in;
1477         struct mlx5_reg_node_desc out;
1478         int err;
1479
1480         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1481                 return -EOPNOTSUPP;
1482
1483         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1484                 return 0;
1485
1486         /*
1487          * If possible, pass node desc to FW, so it can generate
1488          * a 144 trap.  If cmd fails, just ignore.
1489          */
1490         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1491         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1492                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1493         if (err)
1494                 return err;
1495
1496         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1497
1498         return err;
1499 }
1500
1501 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1502                                 u32 value)
1503 {
1504         struct mlx5_hca_vport_context ctx = {};
1505         struct mlx5_core_dev *mdev;
1506         u32 mdev_port_num;
1507         int err;
1508
1509         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1510         if (!mdev)
1511                 return -ENODEV;
1512
1513         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1514         if (err)
1515                 goto out;
1516
1517         if (~ctx.cap_mask1_perm & mask) {
1518                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1519                              mask, ctx.cap_mask1_perm);
1520                 err = -EINVAL;
1521                 goto out;
1522         }
1523
1524         ctx.cap_mask1 = value;
1525         ctx.cap_mask1_perm = mask;
1526         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1527                                                  0, &ctx);
1528
1529 out:
1530         mlx5_ib_put_native_port_mdev(dev, port_num);
1531
1532         return err;
1533 }
1534
1535 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1536                                struct ib_port_modify *props)
1537 {
1538         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1539         struct ib_port_attr attr;
1540         u32 tmp;
1541         int err;
1542         u32 change_mask;
1543         u32 value;
1544         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1545                       IB_LINK_LAYER_INFINIBAND);
1546
1547         /* CM layer calls ib_modify_port() regardless of the link layer. For
1548          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1549          */
1550         if (!is_ib)
1551                 return 0;
1552
1553         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1554                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1555                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1556                 return set_port_caps_atomic(dev, port, change_mask, value);
1557         }
1558
1559         mutex_lock(&dev->cap_mask_mutex);
1560
1561         err = ib_query_port(ibdev, port, &attr);
1562         if (err)
1563                 goto out;
1564
1565         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1566                 ~props->clr_port_cap_mask;
1567
1568         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1569
1570 out:
1571         mutex_unlock(&dev->cap_mask_mutex);
1572         return err;
1573 }
1574
1575 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1576 {
1577         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1578                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1579 }
1580
1581 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1582 {
1583         /* Large page with non 4k uar support might limit the dynamic size */
1584         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1585                 return MLX5_MIN_DYN_BFREGS;
1586
1587         return MLX5_MAX_DYN_BFREGS;
1588 }
1589
1590 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1591                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1592                              struct mlx5_bfreg_info *bfregi)
1593 {
1594         int uars_per_sys_page;
1595         int bfregs_per_sys_page;
1596         int ref_bfregs = req->total_num_bfregs;
1597
1598         if (req->total_num_bfregs == 0)
1599                 return -EINVAL;
1600
1601         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1602         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1603
1604         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1605                 return -ENOMEM;
1606
1607         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1608         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1609         /* This holds the required static allocation asked by the user */
1610         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1611         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1612                 return -EINVAL;
1613
1614         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1615         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1616         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1617         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1618
1619         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1620                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1621                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1622                     req->total_num_bfregs, bfregi->total_num_bfregs,
1623                     bfregi->num_sys_pages);
1624
1625         return 0;
1626 }
1627
1628 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1629 {
1630         struct mlx5_bfreg_info *bfregi;
1631         int err;
1632         int i;
1633
1634         bfregi = &context->bfregi;
1635         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1636                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1637                 if (err)
1638                         goto error;
1639
1640                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1641         }
1642
1643         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1644                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1645
1646         return 0;
1647
1648 error:
1649         for (--i; i >= 0; i--)
1650                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1651                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1652
1653         return err;
1654 }
1655
1656 static void deallocate_uars(struct mlx5_ib_dev *dev,
1657                             struct mlx5_ib_ucontext *context)
1658 {
1659         struct mlx5_bfreg_info *bfregi;
1660         int i;
1661
1662         bfregi = &context->bfregi;
1663         for (i = 0; i < bfregi->num_sys_pages; i++)
1664                 if (i < bfregi->num_static_sys_pages ||
1665                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1666                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1667 }
1668
1669 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1670 {
1671         int err = 0;
1672
1673         mutex_lock(&dev->lb.mutex);
1674         if (td)
1675                 dev->lb.user_td++;
1676         if (qp)
1677                 dev->lb.qps++;
1678
1679         if (dev->lb.user_td == 2 ||
1680             dev->lb.qps == 1) {
1681                 if (!dev->lb.enabled) {
1682                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1683                         dev->lb.enabled = true;
1684                 }
1685         }
1686
1687         mutex_unlock(&dev->lb.mutex);
1688
1689         return err;
1690 }
1691
1692 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1693 {
1694         mutex_lock(&dev->lb.mutex);
1695         if (td)
1696                 dev->lb.user_td--;
1697         if (qp)
1698                 dev->lb.qps--;
1699
1700         if (dev->lb.user_td == 1 &&
1701             dev->lb.qps == 0) {
1702                 if (dev->lb.enabled) {
1703                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1704                         dev->lb.enabled = false;
1705                 }
1706         }
1707
1708         mutex_unlock(&dev->lb.mutex);
1709 }
1710
1711 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1712                                           u16 uid)
1713 {
1714         int err;
1715
1716         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1717                 return 0;
1718
1719         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1720         if (err)
1721                 return err;
1722
1723         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1724             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1725              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1726                 return err;
1727
1728         return mlx5_ib_enable_lb(dev, true, false);
1729 }
1730
1731 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1732                                              u16 uid)
1733 {
1734         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1735                 return;
1736
1737         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1738
1739         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1740             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1741              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1742                 return;
1743
1744         mlx5_ib_disable_lb(dev, true, false);
1745 }
1746
1747 static int set_ucontext_resp(struct ib_ucontext *uctx,
1748                              struct mlx5_ib_alloc_ucontext_resp *resp)
1749 {
1750         struct ib_device *ibdev = uctx->device;
1751         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1752         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1753         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1754         int err;
1755
1756         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1757                 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1758                                               &resp->dump_fill_mkey);
1759                 if (err)
1760                         return err;
1761                 resp->comp_mask |=
1762                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1763         }
1764
1765         resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1766         if (dev->wc_support)
1767                 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1768                                                       log_bf_reg_size);
1769         resp->cache_line_size = cache_line_size();
1770         resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1771         resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1772         resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1773         resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1774         resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1775         resp->cqe_version = context->cqe_version;
1776         resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1777                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1778         resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1779                                         MLX5_CAP_GEN(dev->mdev,
1780                                                      num_of_uars_per_page) : 1;
1781
1782         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1783                                 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1784                 if (mlx5_get_flow_namespace(dev->mdev,
1785                                 MLX5_FLOW_NAMESPACE_EGRESS))
1786                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1787                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1788                                 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1789                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1790                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1791                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1792                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1793                                 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1794                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1795                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1796         }
1797
1798         resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1799                         bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1800         resp->num_ports = dev->num_ports;
1801         resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1802                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1803
1804         if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1805                 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1806                 resp->eth_min_inline++;
1807         }
1808
1809         if (dev->mdev->clock_info)
1810                 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1811
1812         /*
1813          * We don't want to expose information from the PCI bar that is located
1814          * after 4096 bytes, so if the arch only supports larger pages, let's
1815          * pretend we don't support reading the HCA's core clock. This is also
1816          * forced by mmap function.
1817          */
1818         if (PAGE_SIZE <= 4096) {
1819                 resp->comp_mask |=
1820                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1821                 resp->hca_core_clock_offset =
1822                         offsetof(struct mlx5_init_seg,
1823                                  internal_timer_h) % PAGE_SIZE;
1824         }
1825
1826         if (MLX5_CAP_GEN(dev->mdev, ece_support))
1827                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1828
1829         if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1830             rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1831             rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1832                 resp->comp_mask |=
1833                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1834
1835         resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1836
1837         if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1838                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1839
1840         return 0;
1841 }
1842
1843 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1844                                   struct ib_udata *udata)
1845 {
1846         struct ib_device *ibdev = uctx->device;
1847         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1848         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1849         struct mlx5_ib_alloc_ucontext_resp resp = {};
1850         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1851         struct mlx5_bfreg_info *bfregi;
1852         int ver;
1853         int err;
1854         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1855                                      max_cqe_version);
1856         bool lib_uar_4k;
1857         bool lib_uar_dyn;
1858
1859         if (!dev->ib_active)
1860                 return -EAGAIN;
1861
1862         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1863                 ver = 0;
1864         else if (udata->inlen >= min_req_v2)
1865                 ver = 2;
1866         else
1867                 return -EINVAL;
1868
1869         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1870         if (err)
1871                 return err;
1872
1873         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1874                 return -EOPNOTSUPP;
1875
1876         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1877                 return -EOPNOTSUPP;
1878
1879         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1880                                     MLX5_NON_FP_BFREGS_PER_UAR);
1881         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1882                 return -EINVAL;
1883
1884         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1885         lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1886         bfregi = &context->bfregi;
1887
1888         if (lib_uar_dyn) {
1889                 bfregi->lib_uar_dyn = lib_uar_dyn;
1890                 goto uar_done;
1891         }
1892
1893         /* updates req->total_num_bfregs */
1894         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1895         if (err)
1896                 goto out_ctx;
1897
1898         mutex_init(&bfregi->lock);
1899         bfregi->lib_uar_4k = lib_uar_4k;
1900         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1901                                 GFP_KERNEL);
1902         if (!bfregi->count) {
1903                 err = -ENOMEM;
1904                 goto out_ctx;
1905         }
1906
1907         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1908                                     sizeof(*bfregi->sys_pages),
1909                                     GFP_KERNEL);
1910         if (!bfregi->sys_pages) {
1911                 err = -ENOMEM;
1912                 goto out_count;
1913         }
1914
1915         err = allocate_uars(dev, context);
1916         if (err)
1917                 goto out_sys_pages;
1918
1919 uar_done:
1920         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1921                 err = mlx5_ib_devx_create(dev, true);
1922                 if (err < 0)
1923                         goto out_uars;
1924                 context->devx_uid = err;
1925         }
1926
1927         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1928                                              context->devx_uid);
1929         if (err)
1930                 goto out_devx;
1931
1932         INIT_LIST_HEAD(&context->db_page_list);
1933         mutex_init(&context->db_page_mutex);
1934
1935         context->cqe_version = min_t(__u8,
1936                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1937                                  req.max_cqe_version);
1938
1939         err = set_ucontext_resp(uctx, &resp);
1940         if (err)
1941                 goto out_mdev;
1942
1943         resp.response_length = min(udata->outlen, sizeof(resp));
1944         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1945         if (err)
1946                 goto out_mdev;
1947
1948         bfregi->ver = ver;
1949         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1950         context->lib_caps = req.lib_caps;
1951         print_lib_caps(dev, context->lib_caps);
1952
1953         if (mlx5_ib_lag_should_assign_affinity(dev)) {
1954                 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1955
1956                 atomic_set(&context->tx_port_affinity,
1957                            atomic_add_return(
1958                                    1, &dev->port[port].roce.tx_port_affinity));
1959         }
1960
1961         return 0;
1962
1963 out_mdev:
1964         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1965 out_devx:
1966         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1967                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1968
1969 out_uars:
1970         deallocate_uars(dev, context);
1971
1972 out_sys_pages:
1973         kfree(bfregi->sys_pages);
1974
1975 out_count:
1976         kfree(bfregi->count);
1977
1978 out_ctx:
1979         return err;
1980 }
1981
1982 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1983                                   struct uverbs_attr_bundle *attrs)
1984 {
1985         struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1986         int ret;
1987
1988         ret = set_ucontext_resp(ibcontext, &uctx_resp);
1989         if (ret)
1990                 return ret;
1991
1992         uctx_resp.response_length =
1993                 min_t(size_t,
1994                       uverbs_attr_get_len(attrs,
1995                                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1996                       sizeof(uctx_resp));
1997
1998         ret = uverbs_copy_to_struct_or_zero(attrs,
1999                                         MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2000                                         &uctx_resp,
2001                                         sizeof(uctx_resp));
2002         return ret;
2003 }
2004
2005 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2006 {
2007         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2008         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2009         struct mlx5_bfreg_info *bfregi;
2010
2011         bfregi = &context->bfregi;
2012         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2013
2014         if (context->devx_uid)
2015                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2016
2017         deallocate_uars(dev, context);
2018         kfree(bfregi->sys_pages);
2019         kfree(bfregi->count);
2020 }
2021
2022 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2023                                  int uar_idx)
2024 {
2025         int fw_uars_per_page;
2026
2027         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2028
2029         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2030 }
2031
2032 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2033                                  int uar_idx)
2034 {
2035         unsigned int fw_uars_per_page;
2036
2037         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2038                                 MLX5_UARS_IN_PAGE : 1;
2039
2040         return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2041 }
2042
2043 static int get_command(unsigned long offset)
2044 {
2045         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2046 }
2047
2048 static int get_arg(unsigned long offset)
2049 {
2050         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2051 }
2052
2053 static int get_index(unsigned long offset)
2054 {
2055         return get_arg(offset);
2056 }
2057
2058 /* Index resides in an extra byte to enable larger values than 255 */
2059 static int get_extended_index(unsigned long offset)
2060 {
2061         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2062 }
2063
2064
2065 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2066 {
2067 }
2068
2069 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2070 {
2071         switch (cmd) {
2072         case MLX5_IB_MMAP_WC_PAGE:
2073                 return "WC";
2074         case MLX5_IB_MMAP_REGULAR_PAGE:
2075                 return "best effort WC";
2076         case MLX5_IB_MMAP_NC_PAGE:
2077                 return "NC";
2078         case MLX5_IB_MMAP_DEVICE_MEM:
2079                 return "Device Memory";
2080         default:
2081                 return NULL;
2082         }
2083 }
2084
2085 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2086                                         struct vm_area_struct *vma,
2087                                         struct mlx5_ib_ucontext *context)
2088 {
2089         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2090             !(vma->vm_flags & VM_SHARED))
2091                 return -EINVAL;
2092
2093         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2094                 return -EOPNOTSUPP;
2095
2096         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2097                 return -EPERM;
2098         vma->vm_flags &= ~VM_MAYWRITE;
2099
2100         if (!dev->mdev->clock_info)
2101                 return -EOPNOTSUPP;
2102
2103         return vm_insert_page(vma, vma->vm_start,
2104                               virt_to_page(dev->mdev->clock_info));
2105 }
2106
2107 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2108 {
2109         struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2110         struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2111         struct mlx5_var_table *var_table = &dev->var_table;
2112
2113         switch (mentry->mmap_flag) {
2114         case MLX5_IB_MMAP_TYPE_MEMIC:
2115         case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2116                 mlx5_ib_dm_mmap_free(dev, mentry);
2117                 break;
2118         case MLX5_IB_MMAP_TYPE_VAR:
2119                 mutex_lock(&var_table->bitmap_lock);
2120                 clear_bit(mentry->page_idx, var_table->bitmap);
2121                 mutex_unlock(&var_table->bitmap_lock);
2122                 kfree(mentry);
2123                 break;
2124         case MLX5_IB_MMAP_TYPE_UAR_WC:
2125         case MLX5_IB_MMAP_TYPE_UAR_NC:
2126                 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2127                 kfree(mentry);
2128                 break;
2129         default:
2130                 WARN_ON(true);
2131         }
2132 }
2133
2134 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2135                     struct vm_area_struct *vma,
2136                     struct mlx5_ib_ucontext *context)
2137 {
2138         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2139         int err;
2140         unsigned long idx;
2141         phys_addr_t pfn;
2142         pgprot_t prot;
2143         u32 bfreg_dyn_idx = 0;
2144         u32 uar_index;
2145         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2146         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2147                                 bfregi->num_static_sys_pages;
2148
2149         if (bfregi->lib_uar_dyn)
2150                 return -EINVAL;
2151
2152         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2153                 return -EINVAL;
2154
2155         if (dyn_uar)
2156                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2157         else
2158                 idx = get_index(vma->vm_pgoff);
2159
2160         if (idx >= max_valid_idx) {
2161                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2162                              idx, max_valid_idx);
2163                 return -EINVAL;
2164         }
2165
2166         switch (cmd) {
2167         case MLX5_IB_MMAP_WC_PAGE:
2168         case MLX5_IB_MMAP_ALLOC_WC:
2169         case MLX5_IB_MMAP_REGULAR_PAGE:
2170                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2171                 prot = pgprot_writecombine(vma->vm_page_prot);
2172                 break;
2173         case MLX5_IB_MMAP_NC_PAGE:
2174                 prot = pgprot_noncached(vma->vm_page_prot);
2175                 break;
2176         default:
2177                 return -EINVAL;
2178         }
2179
2180         if (dyn_uar) {
2181                 int uars_per_page;
2182
2183                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2184                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2185                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2186                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2187                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2188                         return -EINVAL;
2189                 }
2190
2191                 mutex_lock(&bfregi->lock);
2192                 /* Fail if uar already allocated, first bfreg index of each
2193                  * page holds its count.
2194                  */
2195                 if (bfregi->count[bfreg_dyn_idx]) {
2196                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2197                         mutex_unlock(&bfregi->lock);
2198                         return -EINVAL;
2199                 }
2200
2201                 bfregi->count[bfreg_dyn_idx]++;
2202                 mutex_unlock(&bfregi->lock);
2203
2204                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2205                 if (err) {
2206                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2207                         goto free_bfreg;
2208                 }
2209         } else {
2210                 uar_index = bfregi->sys_pages[idx];
2211         }
2212
2213         pfn = uar_index2pfn(dev, uar_index);
2214         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2215
2216         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2217                                 prot, NULL);
2218         if (err) {
2219                 mlx5_ib_err(dev,
2220                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2221                             err, mmap_cmd2str(cmd));
2222                 goto err;
2223         }
2224
2225         if (dyn_uar)
2226                 bfregi->sys_pages[idx] = uar_index;
2227         return 0;
2228
2229 err:
2230         if (!dyn_uar)
2231                 return err;
2232
2233         mlx5_cmd_free_uar(dev->mdev, idx);
2234
2235 free_bfreg:
2236         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2237
2238         return err;
2239 }
2240
2241 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2242 {
2243         unsigned long idx;
2244         u8 command;
2245
2246         command = get_command(vma->vm_pgoff);
2247         idx = get_extended_index(vma->vm_pgoff);
2248
2249         return (command << 16 | idx);
2250 }
2251
2252 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2253                                struct vm_area_struct *vma,
2254                                struct ib_ucontext *ucontext)
2255 {
2256         struct mlx5_user_mmap_entry *mentry;
2257         struct rdma_user_mmap_entry *entry;
2258         unsigned long pgoff;
2259         pgprot_t prot;
2260         phys_addr_t pfn;
2261         int ret;
2262
2263         pgoff = mlx5_vma_to_pgoff(vma);
2264         entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2265         if (!entry)
2266                 return -EINVAL;
2267
2268         mentry = to_mmmap(entry);
2269         pfn = (mentry->address >> PAGE_SHIFT);
2270         if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2271             mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2272                 prot = pgprot_noncached(vma->vm_page_prot);
2273         else
2274                 prot = pgprot_writecombine(vma->vm_page_prot);
2275         ret = rdma_user_mmap_io(ucontext, vma, pfn,
2276                                 entry->npages * PAGE_SIZE,
2277                                 prot,
2278                                 entry);
2279         rdma_user_mmap_entry_put(&mentry->rdma_entry);
2280         return ret;
2281 }
2282
2283 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2284 {
2285         u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2286         u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2287
2288         return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2289                 (index & 0xFF)) << PAGE_SHIFT;
2290 }
2291
2292 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2293 {
2294         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2295         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2296         unsigned long command;
2297         phys_addr_t pfn;
2298
2299         command = get_command(vma->vm_pgoff);
2300         switch (command) {
2301         case MLX5_IB_MMAP_WC_PAGE:
2302         case MLX5_IB_MMAP_ALLOC_WC:
2303                 if (!dev->wc_support)
2304                         return -EPERM;
2305                 fallthrough;
2306         case MLX5_IB_MMAP_NC_PAGE:
2307         case MLX5_IB_MMAP_REGULAR_PAGE:
2308                 return uar_mmap(dev, command, vma, context);
2309
2310         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2311                 return -ENOSYS;
2312
2313         case MLX5_IB_MMAP_CORE_CLOCK:
2314                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2315                         return -EINVAL;
2316
2317                 if (vma->vm_flags & VM_WRITE)
2318                         return -EPERM;
2319                 vma->vm_flags &= ~VM_MAYWRITE;
2320
2321                 /* Don't expose to user-space information it shouldn't have */
2322                 if (PAGE_SIZE > 4096)
2323                         return -EOPNOTSUPP;
2324
2325                 pfn = (dev->mdev->iseg_base +
2326                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2327                         PAGE_SHIFT;
2328                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2329                                          PAGE_SIZE,
2330                                          pgprot_noncached(vma->vm_page_prot),
2331                                          NULL);
2332         case MLX5_IB_MMAP_CLOCK_INFO:
2333                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2334
2335         default:
2336                 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2337         }
2338
2339         return 0;
2340 }
2341
2342 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2343 {
2344         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2345         struct ib_device *ibdev = ibpd->device;
2346         struct mlx5_ib_alloc_pd_resp resp;
2347         int err;
2348         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2349         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2350         u16 uid = 0;
2351         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2352                 udata, struct mlx5_ib_ucontext, ibucontext);
2353
2354         uid = context ? context->devx_uid : 0;
2355         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2356         MLX5_SET(alloc_pd_in, in, uid, uid);
2357         err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2358         if (err)
2359                 return err;
2360
2361         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2362         pd->uid = uid;
2363         if (udata) {
2364                 resp.pdn = pd->pdn;
2365                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2366                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2367                         return -EFAULT;
2368                 }
2369         }
2370
2371         return 0;
2372 }
2373
2374 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2375 {
2376         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2377         struct mlx5_ib_pd *mpd = to_mpd(pd);
2378
2379         return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2380 }
2381
2382 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2383 {
2384         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2385         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2386         int err;
2387         u16 uid;
2388
2389         uid = ibqp->pd ?
2390                 to_mpd(ibqp->pd)->uid : 0;
2391
2392         if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2393                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2394                 return -EOPNOTSUPP;
2395         }
2396
2397         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2398         if (err)
2399                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2400                              ibqp->qp_num, gid->raw);
2401
2402         return err;
2403 }
2404
2405 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2406 {
2407         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2408         int err;
2409         u16 uid;
2410
2411         uid = ibqp->pd ?
2412                 to_mpd(ibqp->pd)->uid : 0;
2413         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2414         if (err)
2415                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2416                              ibqp->qp_num, gid->raw);
2417
2418         return err;
2419 }
2420
2421 static int init_node_data(struct mlx5_ib_dev *dev)
2422 {
2423         int err;
2424
2425         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2426         if (err)
2427                 return err;
2428
2429         dev->mdev->rev_id = dev->mdev->pdev->revision;
2430
2431         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2432 }
2433
2434 static ssize_t fw_pages_show(struct device *device,
2435                              struct device_attribute *attr, char *buf)
2436 {
2437         struct mlx5_ib_dev *dev =
2438                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2439
2440         return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2441 }
2442 static DEVICE_ATTR_RO(fw_pages);
2443
2444 static ssize_t reg_pages_show(struct device *device,
2445                               struct device_attribute *attr, char *buf)
2446 {
2447         struct mlx5_ib_dev *dev =
2448                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2449
2450         return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2451 }
2452 static DEVICE_ATTR_RO(reg_pages);
2453
2454 static ssize_t hca_type_show(struct device *device,
2455                              struct device_attribute *attr, char *buf)
2456 {
2457         struct mlx5_ib_dev *dev =
2458                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2459
2460         return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2461 }
2462 static DEVICE_ATTR_RO(hca_type);
2463
2464 static ssize_t hw_rev_show(struct device *device,
2465                            struct device_attribute *attr, char *buf)
2466 {
2467         struct mlx5_ib_dev *dev =
2468                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2469
2470         return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2471 }
2472 static DEVICE_ATTR_RO(hw_rev);
2473
2474 static ssize_t board_id_show(struct device *device,
2475                              struct device_attribute *attr, char *buf)
2476 {
2477         struct mlx5_ib_dev *dev =
2478                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2479
2480         return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2481                           dev->mdev->board_id);
2482 }
2483 static DEVICE_ATTR_RO(board_id);
2484
2485 static struct attribute *mlx5_class_attributes[] = {
2486         &dev_attr_hw_rev.attr,
2487         &dev_attr_hca_type.attr,
2488         &dev_attr_board_id.attr,
2489         &dev_attr_fw_pages.attr,
2490         &dev_attr_reg_pages.attr,
2491         NULL,
2492 };
2493
2494 static const struct attribute_group mlx5_attr_group = {
2495         .attrs = mlx5_class_attributes,
2496 };
2497
2498 static void pkey_change_handler(struct work_struct *work)
2499 {
2500         struct mlx5_ib_port_resources *ports =
2501                 container_of(work, struct mlx5_ib_port_resources,
2502                              pkey_change_work);
2503
2504         mlx5_ib_gsi_pkey_change(ports->gsi);
2505 }
2506
2507 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2508 {
2509         struct mlx5_ib_qp *mqp;
2510         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2511         struct mlx5_core_cq *mcq;
2512         struct list_head cq_armed_list;
2513         unsigned long flags_qp;
2514         unsigned long flags_cq;
2515         unsigned long flags;
2516
2517         INIT_LIST_HEAD(&cq_armed_list);
2518
2519         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2520         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2521         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2522                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2523                 if (mqp->sq.tail != mqp->sq.head) {
2524                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2525                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2526                         if (send_mcq->mcq.comp &&
2527                             mqp->ibqp.send_cq->comp_handler) {
2528                                 if (!send_mcq->mcq.reset_notify_added) {
2529                                         send_mcq->mcq.reset_notify_added = 1;
2530                                         list_add_tail(&send_mcq->mcq.reset_notify,
2531                                                       &cq_armed_list);
2532                                 }
2533                         }
2534                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2535                 }
2536                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2537                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2538                 /* no handling is needed for SRQ */
2539                 if (!mqp->ibqp.srq) {
2540                         if (mqp->rq.tail != mqp->rq.head) {
2541                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2542                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2543                                 if (recv_mcq->mcq.comp &&
2544                                     mqp->ibqp.recv_cq->comp_handler) {
2545                                         if (!recv_mcq->mcq.reset_notify_added) {
2546                                                 recv_mcq->mcq.reset_notify_added = 1;
2547                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2548                                                               &cq_armed_list);
2549                                         }
2550                                 }
2551                                 spin_unlock_irqrestore(&recv_mcq->lock,
2552                                                        flags_cq);
2553                         }
2554                 }
2555                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2556         }
2557         /*At that point all inflight post send were put to be executed as of we
2558          * lock/unlock above locks Now need to arm all involved CQs.
2559          */
2560         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2561                 mcq->comp(mcq, NULL);
2562         }
2563         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2564 }
2565
2566 static void delay_drop_handler(struct work_struct *work)
2567 {
2568         int err;
2569         struct mlx5_ib_delay_drop *delay_drop =
2570                 container_of(work, struct mlx5_ib_delay_drop,
2571                              delay_drop_work);
2572
2573         atomic_inc(&delay_drop->events_cnt);
2574
2575         mutex_lock(&delay_drop->lock);
2576         err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2577         if (err) {
2578                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2579                              delay_drop->timeout);
2580                 delay_drop->activate = false;
2581         }
2582         mutex_unlock(&delay_drop->lock);
2583 }
2584
2585 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2586                                  struct ib_event *ibev)
2587 {
2588         u32 port = (eqe->data.port.port >> 4) & 0xf;
2589
2590         switch (eqe->sub_type) {
2591         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2592                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2593                                             IB_LINK_LAYER_ETHERNET)
2594                         schedule_work(&ibdev->delay_drop.delay_drop_work);
2595                 break;
2596         default: /* do nothing */
2597                 return;
2598         }
2599 }
2600
2601 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2602                               struct ib_event *ibev)
2603 {
2604         u32 port = (eqe->data.port.port >> 4) & 0xf;
2605
2606         ibev->element.port_num = port;
2607
2608         switch (eqe->sub_type) {
2609         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2610         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2611         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2612                 /* In RoCE, port up/down events are handled in
2613                  * mlx5_netdev_event().
2614                  */
2615                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2616                                             IB_LINK_LAYER_ETHERNET)
2617                         return -EINVAL;
2618
2619                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2620                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2621                 break;
2622
2623         case MLX5_PORT_CHANGE_SUBTYPE_LID:
2624                 ibev->event = IB_EVENT_LID_CHANGE;
2625                 break;
2626
2627         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2628                 ibev->event = IB_EVENT_PKEY_CHANGE;
2629                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2630                 break;
2631
2632         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2633                 ibev->event = IB_EVENT_GID_CHANGE;
2634                 break;
2635
2636         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2637                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2638                 break;
2639         default:
2640                 return -EINVAL;
2641         }
2642
2643         return 0;
2644 }
2645
2646 static void mlx5_ib_handle_event(struct work_struct *_work)
2647 {
2648         struct mlx5_ib_event_work *work =
2649                 container_of(_work, struct mlx5_ib_event_work, work);
2650         struct mlx5_ib_dev *ibdev;
2651         struct ib_event ibev;
2652         bool fatal = false;
2653
2654         if (work->is_slave) {
2655                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2656                 if (!ibdev)
2657                         goto out;
2658         } else {
2659                 ibdev = work->dev;
2660         }
2661
2662         switch (work->event) {
2663         case MLX5_DEV_EVENT_SYS_ERROR:
2664                 ibev.event = IB_EVENT_DEVICE_FATAL;
2665                 mlx5_ib_handle_internal_error(ibdev);
2666                 ibev.element.port_num  = (u8)(unsigned long)work->param;
2667                 fatal = true;
2668                 break;
2669         case MLX5_EVENT_TYPE_PORT_CHANGE:
2670                 if (handle_port_change(ibdev, work->param, &ibev))
2671                         goto out;
2672                 break;
2673         case MLX5_EVENT_TYPE_GENERAL_EVENT:
2674                 handle_general_event(ibdev, work->param, &ibev);
2675                 fallthrough;
2676         default:
2677                 goto out;
2678         }
2679
2680         ibev.device = &ibdev->ib_dev;
2681
2682         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2683                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2684                 goto out;
2685         }
2686
2687         if (ibdev->ib_active)
2688                 ib_dispatch_event(&ibev);
2689
2690         if (fatal)
2691                 ibdev->ib_active = false;
2692 out:
2693         kfree(work);
2694 }
2695
2696 static int mlx5_ib_event(struct notifier_block *nb,
2697                          unsigned long event, void *param)
2698 {
2699         struct mlx5_ib_event_work *work;
2700
2701         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2702         if (!work)
2703                 return NOTIFY_DONE;
2704
2705         INIT_WORK(&work->work, mlx5_ib_handle_event);
2706         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2707         work->is_slave = false;
2708         work->param = param;
2709         work->event = event;
2710
2711         queue_work(mlx5_ib_event_wq, &work->work);
2712
2713         return NOTIFY_OK;
2714 }
2715
2716 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2717                                     unsigned long event, void *param)
2718 {
2719         struct mlx5_ib_event_work *work;
2720
2721         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2722         if (!work)
2723                 return NOTIFY_DONE;
2724
2725         INIT_WORK(&work->work, mlx5_ib_handle_event);
2726         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2727         work->is_slave = true;
2728         work->param = param;
2729         work->event = event;
2730         queue_work(mlx5_ib_event_wq, &work->work);
2731
2732         return NOTIFY_OK;
2733 }
2734
2735 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2736 {
2737         struct mlx5_hca_vport_context vport_ctx;
2738         int err;
2739         int port;
2740
2741         for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2742                 dev->port_caps[port - 1].has_smi = false;
2743                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2744                     MLX5_CAP_PORT_TYPE_IB) {
2745                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2746                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2747                                                                    port, 0,
2748                                                                    &vport_ctx);
2749                                 if (err) {
2750                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2751                                                     port, err);
2752                                         return err;
2753                                 }
2754                                 dev->port_caps[port - 1].has_smi =
2755                                         vport_ctx.has_smi;
2756                         } else {
2757                                 dev->port_caps[port - 1].has_smi = true;
2758                         }
2759                 }
2760         }
2761         return 0;
2762 }
2763
2764 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2765 {
2766         unsigned int port;
2767
2768         rdma_for_each_port (&dev->ib_dev, port)
2769                 mlx5_query_ext_port_caps(dev, port);
2770 }
2771
2772 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2773 {
2774         switch (umr_fence_cap) {
2775         case MLX5_CAP_UMR_FENCE_NONE:
2776                 return MLX5_FENCE_MODE_NONE;
2777         case MLX5_CAP_UMR_FENCE_SMALL:
2778                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2779         default:
2780                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2781         }
2782 }
2783
2784 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2785 {
2786         struct mlx5_ib_resources *devr = &dev->devr;
2787         struct ib_srq_init_attr attr;
2788         struct ib_device *ibdev;
2789         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2790         int port;
2791         int ret = 0;
2792
2793         ibdev = &dev->ib_dev;
2794
2795         if (!MLX5_CAP_GEN(dev->mdev, xrc))
2796                 return -EOPNOTSUPP;
2797
2798         mutex_init(&devr->mutex);
2799
2800         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2801         if (!devr->p0)
2802                 return -ENOMEM;
2803
2804         devr->p0->device  = ibdev;
2805         devr->p0->uobject = NULL;
2806         atomic_set(&devr->p0->usecnt, 0);
2807
2808         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2809         if (ret)
2810                 goto error0;
2811
2812         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2813         if (!devr->c0) {
2814                 ret = -ENOMEM;
2815                 goto error1;
2816         }
2817
2818         devr->c0->device = &dev->ib_dev;
2819         atomic_set(&devr->c0->usecnt, 0);
2820
2821         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2822         if (ret)
2823                 goto err_create_cq;
2824
2825         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2826         if (ret)
2827                 goto error2;
2828
2829         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2830         if (ret)
2831                 goto error3;
2832
2833         memset(&attr, 0, sizeof(attr));
2834         attr.attr.max_sge = 1;
2835         attr.attr.max_wr = 1;
2836         attr.srq_type = IB_SRQT_XRC;
2837         attr.ext.cq = devr->c0;
2838
2839         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2840         if (!devr->s0) {
2841                 ret = -ENOMEM;
2842                 goto error4;
2843         }
2844
2845         devr->s0->device        = &dev->ib_dev;
2846         devr->s0->pd            = devr->p0;
2847         devr->s0->srq_type      = IB_SRQT_XRC;
2848         devr->s0->ext.cq        = devr->c0;
2849         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
2850         if (ret)
2851                 goto err_create;
2852
2853         atomic_inc(&devr->s0->ext.cq->usecnt);
2854         atomic_inc(&devr->p0->usecnt);
2855         atomic_set(&devr->s0->usecnt, 0);
2856
2857         memset(&attr, 0, sizeof(attr));
2858         attr.attr.max_sge = 1;
2859         attr.attr.max_wr = 1;
2860         attr.srq_type = IB_SRQT_BASIC;
2861         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2862         if (!devr->s1) {
2863                 ret = -ENOMEM;
2864                 goto error5;
2865         }
2866
2867         devr->s1->device        = &dev->ib_dev;
2868         devr->s1->pd            = devr->p0;
2869         devr->s1->srq_type      = IB_SRQT_BASIC;
2870         devr->s1->ext.cq        = devr->c0;
2871
2872         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
2873         if (ret)
2874                 goto error6;
2875
2876         atomic_inc(&devr->p0->usecnt);
2877         atomic_set(&devr->s1->usecnt, 0);
2878
2879         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2880                 INIT_WORK(&devr->ports[port].pkey_change_work,
2881                           pkey_change_handler);
2882
2883         return 0;
2884
2885 error6:
2886         kfree(devr->s1);
2887 error5:
2888         mlx5_ib_destroy_srq(devr->s0, NULL);
2889 err_create:
2890         kfree(devr->s0);
2891 error4:
2892         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2893 error3:
2894         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2895 error2:
2896         mlx5_ib_destroy_cq(devr->c0, NULL);
2897 err_create_cq:
2898         kfree(devr->c0);
2899 error1:
2900         mlx5_ib_dealloc_pd(devr->p0, NULL);
2901 error0:
2902         kfree(devr->p0);
2903         return ret;
2904 }
2905
2906 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2907 {
2908         struct mlx5_ib_resources *devr = &dev->devr;
2909         int port;
2910
2911         mlx5_ib_destroy_srq(devr->s1, NULL);
2912         kfree(devr->s1);
2913         mlx5_ib_destroy_srq(devr->s0, NULL);
2914         kfree(devr->s0);
2915         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2916         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2917         mlx5_ib_destroy_cq(devr->c0, NULL);
2918         kfree(devr->c0);
2919         mlx5_ib_dealloc_pd(devr->p0, NULL);
2920         kfree(devr->p0);
2921
2922         /* Make sure no change P_Key work items are still executing */
2923         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2924                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2925 }
2926
2927 static u32 get_core_cap_flags(struct ib_device *ibdev,
2928                               struct mlx5_hca_vport_context *rep)
2929 {
2930         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2931         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2932         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2933         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2934         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2935         u32 ret = 0;
2936
2937         if (rep->grh_required)
2938                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2939
2940         if (ll == IB_LINK_LAYER_INFINIBAND)
2941                 return ret | RDMA_CORE_PORT_IBA_IB;
2942
2943         if (raw_support)
2944                 ret |= RDMA_CORE_PORT_RAW_PACKET;
2945
2946         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2947                 return ret;
2948
2949         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2950                 return ret;
2951
2952         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2953                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2954
2955         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2956                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2957
2958         return ret;
2959 }
2960
2961 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2962                                struct ib_port_immutable *immutable)
2963 {
2964         struct ib_port_attr attr;
2965         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2966         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2967         struct mlx5_hca_vport_context rep = {0};
2968         int err;
2969
2970         err = ib_query_port(ibdev, port_num, &attr);
2971         if (err)
2972                 return err;
2973
2974         if (ll == IB_LINK_LAYER_INFINIBAND) {
2975                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2976                                                    &rep);
2977                 if (err)
2978                         return err;
2979         }
2980
2981         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2982         immutable->gid_tbl_len = attr.gid_tbl_len;
2983         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2984         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2985
2986         return 0;
2987 }
2988
2989 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2990                                    struct ib_port_immutable *immutable)
2991 {
2992         struct ib_port_attr attr;
2993         int err;
2994
2995         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2996
2997         err = ib_query_port(ibdev, port_num, &attr);
2998         if (err)
2999                 return err;
3000
3001         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3002         immutable->gid_tbl_len = attr.gid_tbl_len;
3003         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3004
3005         return 0;
3006 }
3007
3008 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3009 {
3010         struct mlx5_ib_dev *dev =
3011                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3012         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3013                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3014                  fw_rev_sub(dev->mdev));
3015 }
3016
3017 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3018 {
3019         struct mlx5_core_dev *mdev = dev->mdev;
3020         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3021                                                                  MLX5_FLOW_NAMESPACE_LAG);
3022         struct mlx5_flow_table *ft;
3023         int err;
3024
3025         if (!ns || !mlx5_lag_is_active(mdev))
3026                 return 0;
3027
3028         err = mlx5_cmd_create_vport_lag(mdev);
3029         if (err)
3030                 return err;
3031
3032         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3033         if (IS_ERR(ft)) {
3034                 err = PTR_ERR(ft);
3035                 goto err_destroy_vport_lag;
3036         }
3037
3038         dev->flow_db->lag_demux_ft = ft;
3039         dev->lag_active = true;
3040         return 0;
3041
3042 err_destroy_vport_lag:
3043         mlx5_cmd_destroy_vport_lag(mdev);
3044         return err;
3045 }
3046
3047 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3048 {
3049         struct mlx5_core_dev *mdev = dev->mdev;
3050
3051         if (dev->lag_active) {
3052                 dev->lag_active = false;
3053
3054                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3055                 dev->flow_db->lag_demux_ft = NULL;
3056
3057                 mlx5_cmd_destroy_vport_lag(mdev);
3058         }
3059 }
3060
3061 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3062 {
3063         int err;
3064
3065         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3066         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3067         if (err) {
3068                 dev->port[port_num].roce.nb.notifier_call = NULL;
3069                 return err;
3070         }
3071
3072         return 0;
3073 }
3074
3075 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3076 {
3077         if (dev->port[port_num].roce.nb.notifier_call) {
3078                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3079                 dev->port[port_num].roce.nb.notifier_call = NULL;
3080         }
3081 }
3082
3083 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3084 {
3085         int err;
3086
3087         if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3088                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3089                 if (err)
3090                         return err;
3091         }
3092
3093         err = mlx5_eth_lag_init(dev);
3094         if (err)
3095                 goto err_disable_roce;
3096
3097         return 0;
3098
3099 err_disable_roce:
3100         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3101                 mlx5_nic_vport_disable_roce(dev->mdev);
3102
3103         return err;
3104 }
3105
3106 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3107 {
3108         mlx5_eth_lag_cleanup(dev);
3109         if (!dev->is_rep && dev->profile != &raw_eth_profile)
3110                 mlx5_nic_vport_disable_roce(dev->mdev);
3111 }
3112
3113 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3114                                  enum rdma_netdev_t type,
3115                                  struct rdma_netdev_alloc_params *params)
3116 {
3117         if (type != RDMA_NETDEV_IPOIB)
3118                 return -EOPNOTSUPP;
3119
3120         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3121 }
3122
3123 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3124                                        size_t count, loff_t *pos)
3125 {
3126         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3127         char lbuf[20];
3128         int len;
3129
3130         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3131         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3132 }
3133
3134 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3135                                         size_t count, loff_t *pos)
3136 {
3137         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3138         u32 timeout;
3139         u32 var;
3140
3141         if (kstrtouint_from_user(buf, count, 0, &var))
3142                 return -EFAULT;
3143
3144         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3145                         1000);
3146         if (timeout != var)
3147                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3148                             timeout);
3149
3150         delay_drop->timeout = timeout;
3151
3152         return count;
3153 }
3154
3155 static const struct file_operations fops_delay_drop_timeout = {
3156         .owner  = THIS_MODULE,
3157         .open   = simple_open,
3158         .write  = delay_drop_timeout_write,
3159         .read   = delay_drop_timeout_read,
3160 };
3161
3162 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3163                                       struct mlx5_ib_multiport_info *mpi)
3164 {
3165         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3166         struct mlx5_ib_port *port = &ibdev->port[port_num];
3167         int comps;
3168         int err;
3169         int i;
3170
3171         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3172
3173         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3174
3175         spin_lock(&port->mp.mpi_lock);
3176         if (!mpi->ibdev) {
3177                 spin_unlock(&port->mp.mpi_lock);
3178                 return;
3179         }
3180
3181         mpi->ibdev = NULL;
3182
3183         spin_unlock(&port->mp.mpi_lock);
3184         if (mpi->mdev_events.notifier_call)
3185                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3186         mpi->mdev_events.notifier_call = NULL;
3187         mlx5_remove_netdev_notifier(ibdev, port_num);
3188         spin_lock(&port->mp.mpi_lock);
3189
3190         comps = mpi->mdev_refcnt;
3191         if (comps) {
3192                 mpi->unaffiliate = true;
3193                 init_completion(&mpi->unref_comp);
3194                 spin_unlock(&port->mp.mpi_lock);
3195
3196                 for (i = 0; i < comps; i++)
3197                         wait_for_completion(&mpi->unref_comp);
3198
3199                 spin_lock(&port->mp.mpi_lock);
3200                 mpi->unaffiliate = false;
3201         }
3202
3203         port->mp.mpi = NULL;
3204
3205         spin_unlock(&port->mp.mpi_lock);
3206
3207         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3208
3209         mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3210         /* Log an error, still needed to cleanup the pointers and add
3211          * it back to the list.
3212          */
3213         if (err)
3214                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3215                             port_num + 1);
3216
3217         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3218 }
3219
3220 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3221                                     struct mlx5_ib_multiport_info *mpi)
3222 {
3223         u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3224         int err;
3225
3226         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3227
3228         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3229         if (ibdev->port[port_num].mp.mpi) {
3230                 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3231                             port_num + 1);
3232                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3233                 return false;
3234         }
3235
3236         ibdev->port[port_num].mp.mpi = mpi;
3237         mpi->ibdev = ibdev;
3238         mpi->mdev_events.notifier_call = NULL;
3239         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3240
3241         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3242         if (err)
3243                 goto unbind;
3244
3245         err = mlx5_add_netdev_notifier(ibdev, port_num);
3246         if (err) {
3247                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3248                             port_num + 1);
3249                 goto unbind;
3250         }
3251
3252         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3253         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3254
3255         mlx5_ib_init_cong_debugfs(ibdev, port_num);
3256
3257         return true;
3258
3259 unbind:
3260         mlx5_ib_unbind_slave_port(ibdev, mpi);
3261         return false;
3262 }
3263
3264 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3265 {
3266         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3267         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3268                                                           port_num + 1);
3269         struct mlx5_ib_multiport_info *mpi;
3270         int err;
3271         u32 i;
3272
3273         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3274                 return 0;
3275
3276         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3277                                                      &dev->sys_image_guid);
3278         if (err)
3279                 return err;
3280
3281         err = mlx5_nic_vport_enable_roce(dev->mdev);
3282         if (err)
3283                 return err;
3284
3285         mutex_lock(&mlx5_ib_multiport_mutex);
3286         for (i = 0; i < dev->num_ports; i++) {
3287                 bool bound = false;
3288
3289                 /* build a stub multiport info struct for the native port. */
3290                 if (i == port_num) {
3291                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3292                         if (!mpi) {
3293                                 mutex_unlock(&mlx5_ib_multiport_mutex);
3294                                 mlx5_nic_vport_disable_roce(dev->mdev);
3295                                 return -ENOMEM;
3296                         }
3297
3298                         mpi->is_master = true;
3299                         mpi->mdev = dev->mdev;
3300                         mpi->sys_image_guid = dev->sys_image_guid;
3301                         dev->port[i].mp.mpi = mpi;
3302                         mpi->ibdev = dev;
3303                         mpi = NULL;
3304                         continue;
3305                 }
3306
3307                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3308                                     list) {
3309                         if (dev->sys_image_guid == mpi->sys_image_guid &&
3310                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3311                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
3312                         }
3313
3314                         if (bound) {
3315                                 dev_dbg(mpi->mdev->device,
3316                                         "removing port from unaffiliated list.\n");
3317                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3318                                 list_del(&mpi->list);
3319                                 break;
3320                         }
3321                 }
3322                 if (!bound)
3323                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
3324                                     i + 1);
3325         }
3326
3327         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3328         mutex_unlock(&mlx5_ib_multiport_mutex);
3329         return err;
3330 }
3331
3332 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3333 {
3334         u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3335         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3336                                                           port_num + 1);
3337         u32 i;
3338
3339         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3340                 return;
3341
3342         mutex_lock(&mlx5_ib_multiport_mutex);
3343         for (i = 0; i < dev->num_ports; i++) {
3344                 if (dev->port[i].mp.mpi) {
3345                         /* Destroy the native port stub */
3346                         if (i == port_num) {
3347                                 kfree(dev->port[i].mp.mpi);
3348                                 dev->port[i].mp.mpi = NULL;
3349                         } else {
3350                                 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3351                                             i + 1);
3352                                 list_add_tail(&dev->port[i].mp.mpi->list,
3353                                               &mlx5_ib_unaffiliated_port_list);
3354                                 mlx5_ib_unbind_slave_port(dev,
3355                                                           dev->port[i].mp.mpi);
3356                         }
3357                 }
3358         }
3359
3360         mlx5_ib_dbg(dev, "removing from devlist\n");
3361         list_del(&dev->ib_dev_list);
3362         mutex_unlock(&mlx5_ib_multiport_mutex);
3363
3364         mlx5_nic_vport_disable_roce(dev->mdev);
3365 }
3366
3367 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3368                             enum rdma_remove_reason why,
3369                             struct uverbs_attr_bundle *attrs)
3370 {
3371         struct mlx5_user_mmap_entry *obj = uobject->object;
3372
3373         rdma_user_mmap_entry_remove(&obj->rdma_entry);
3374         return 0;
3375 }
3376
3377 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3378                                             struct mlx5_user_mmap_entry *entry,
3379                                             size_t length)
3380 {
3381         return rdma_user_mmap_entry_insert_range(
3382                 &c->ibucontext, &entry->rdma_entry, length,
3383                 (MLX5_IB_MMAP_OFFSET_START << 16),
3384                 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3385 }
3386
3387 static struct mlx5_user_mmap_entry *
3388 alloc_var_entry(struct mlx5_ib_ucontext *c)
3389 {
3390         struct mlx5_user_mmap_entry *entry;
3391         struct mlx5_var_table *var_table;
3392         u32 page_idx;
3393         int err;
3394
3395         var_table = &to_mdev(c->ibucontext.device)->var_table;
3396         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3397         if (!entry)
3398                 return ERR_PTR(-ENOMEM);
3399
3400         mutex_lock(&var_table->bitmap_lock);
3401         page_idx = find_first_zero_bit(var_table->bitmap,
3402                                        var_table->num_var_hw_entries);
3403         if (page_idx >= var_table->num_var_hw_entries) {
3404                 err = -ENOSPC;
3405                 mutex_unlock(&var_table->bitmap_lock);
3406                 goto end;
3407         }
3408
3409         set_bit(page_idx, var_table->bitmap);
3410         mutex_unlock(&var_table->bitmap_lock);
3411
3412         entry->address = var_table->hw_start_addr +
3413                                 (page_idx * var_table->stride_size);
3414         entry->page_idx = page_idx;
3415         entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3416
3417         err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3418                                                var_table->stride_size);
3419         if (err)
3420                 goto err_insert;
3421
3422         return entry;
3423
3424 err_insert:
3425         mutex_lock(&var_table->bitmap_lock);
3426         clear_bit(page_idx, var_table->bitmap);
3427         mutex_unlock(&var_table->bitmap_lock);
3428 end:
3429         kfree(entry);
3430         return ERR_PTR(err);
3431 }
3432
3433 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3434         struct uverbs_attr_bundle *attrs)
3435 {
3436         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3437                 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3438         struct mlx5_ib_ucontext *c;
3439         struct mlx5_user_mmap_entry *entry;
3440         u64 mmap_offset;
3441         u32 length;
3442         int err;
3443
3444         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3445         if (IS_ERR(c))
3446                 return PTR_ERR(c);
3447
3448         entry = alloc_var_entry(c);
3449         if (IS_ERR(entry))
3450                 return PTR_ERR(entry);
3451
3452         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3453         length = entry->rdma_entry.npages * PAGE_SIZE;
3454         uobj->object = entry;
3455         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3456
3457         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3458                              &mmap_offset, sizeof(mmap_offset));
3459         if (err)
3460                 return err;
3461
3462         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3463                              &entry->page_idx, sizeof(entry->page_idx));
3464         if (err)
3465                 return err;
3466
3467         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3468                              &length, sizeof(length));
3469         return err;
3470 }
3471
3472 DECLARE_UVERBS_NAMED_METHOD(
3473         MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3474         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3475                         MLX5_IB_OBJECT_VAR,
3476                         UVERBS_ACCESS_NEW,
3477                         UA_MANDATORY),
3478         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3479                            UVERBS_ATTR_TYPE(u32),
3480                            UA_MANDATORY),
3481         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3482                            UVERBS_ATTR_TYPE(u32),
3483                            UA_MANDATORY),
3484         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3485                             UVERBS_ATTR_TYPE(u64),
3486                             UA_MANDATORY));
3487
3488 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3489         MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3490         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3491                         MLX5_IB_OBJECT_VAR,
3492                         UVERBS_ACCESS_DESTROY,
3493                         UA_MANDATORY));
3494
3495 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3496                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3497                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3498                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3499
3500 static bool var_is_supported(struct ib_device *device)
3501 {
3502         struct mlx5_ib_dev *dev = to_mdev(device);
3503
3504         return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3505                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3506 }
3507
3508 static struct mlx5_user_mmap_entry *
3509 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3510                 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3511 {
3512         struct mlx5_user_mmap_entry *entry;
3513         struct mlx5_ib_dev *dev;
3514         u32 uar_index;
3515         int err;
3516
3517         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3518         if (!entry)
3519                 return ERR_PTR(-ENOMEM);
3520
3521         dev = to_mdev(c->ibucontext.device);
3522         err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3523         if (err)
3524                 goto end;
3525
3526         entry->page_idx = uar_index;
3527         entry->address = uar_index2paddress(dev, uar_index);
3528         if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3529                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3530         else
3531                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3532
3533         err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3534         if (err)
3535                 goto err_insert;
3536
3537         return entry;
3538
3539 err_insert:
3540         mlx5_cmd_free_uar(dev->mdev, uar_index);
3541 end:
3542         kfree(entry);
3543         return ERR_PTR(err);
3544 }
3545
3546 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3547         struct uverbs_attr_bundle *attrs)
3548 {
3549         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3550                 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3551         enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3552         struct mlx5_ib_ucontext *c;
3553         struct mlx5_user_mmap_entry *entry;
3554         u64 mmap_offset;
3555         u32 length;
3556         int err;
3557
3558         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3559         if (IS_ERR(c))
3560                 return PTR_ERR(c);
3561
3562         err = uverbs_get_const(&alloc_type, attrs,
3563                                MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3564         if (err)
3565                 return err;
3566
3567         if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3568             alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3569                 return -EOPNOTSUPP;
3570
3571         if (!to_mdev(c->ibucontext.device)->wc_support &&
3572             alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3573                 return -EOPNOTSUPP;
3574
3575         entry = alloc_uar_entry(c, alloc_type);
3576         if (IS_ERR(entry))
3577                 return PTR_ERR(entry);
3578
3579         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3580         length = entry->rdma_entry.npages * PAGE_SIZE;
3581         uobj->object = entry;
3582         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3583
3584         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3585                              &mmap_offset, sizeof(mmap_offset));
3586         if (err)
3587                 return err;
3588
3589         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3590                              &entry->page_idx, sizeof(entry->page_idx));
3591         if (err)
3592                 return err;
3593
3594         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3595                              &length, sizeof(length));
3596         return err;
3597 }
3598
3599 DECLARE_UVERBS_NAMED_METHOD(
3600         MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3601         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3602                         MLX5_IB_OBJECT_UAR,
3603                         UVERBS_ACCESS_NEW,
3604                         UA_MANDATORY),
3605         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3606                              enum mlx5_ib_uapi_uar_alloc_type,
3607                              UA_MANDATORY),
3608         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3609                            UVERBS_ATTR_TYPE(u32),
3610                            UA_MANDATORY),
3611         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3612                            UVERBS_ATTR_TYPE(u32),
3613                            UA_MANDATORY),
3614         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3615                             UVERBS_ATTR_TYPE(u64),
3616                             UA_MANDATORY));
3617
3618 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3619         MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3620         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3621                         MLX5_IB_OBJECT_UAR,
3622                         UVERBS_ACCESS_DESTROY,
3623                         UA_MANDATORY));
3624
3625 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3626                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3627                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3628                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3629
3630 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3631         mlx5_ib_flow_action,
3632         UVERBS_OBJECT_FLOW_ACTION,
3633         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3634         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3635                              enum mlx5_ib_uapi_flow_action_flags));
3636
3637 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3638         mlx5_ib_query_context,
3639         UVERBS_OBJECT_DEVICE,
3640         UVERBS_METHOD_QUERY_CONTEXT,
3641         UVERBS_ATTR_PTR_OUT(
3642                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3643                 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3644                                    dump_fill_mkey),
3645                 UA_MANDATORY));
3646
3647 static const struct uapi_definition mlx5_ib_defs[] = {
3648         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3649         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3650         UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3651         UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3652         UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3653
3654         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3655                                 &mlx5_ib_flow_action),
3656         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3657         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3658                                 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3659         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3660         {}
3661 };
3662
3663 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3664 {
3665         mlx5_ib_cleanup_multiport_master(dev);
3666         WARN_ON(!xa_empty(&dev->odp_mkeys));
3667         mutex_destroy(&dev->cap_mask_mutex);
3668         WARN_ON(!xa_empty(&dev->sig_mrs));
3669         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3670 }
3671
3672 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3673 {
3674         struct mlx5_core_dev *mdev = dev->mdev;
3675         int err;
3676         int i;
3677
3678         dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3679         dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3680         dev->ib_dev.phys_port_cnt = dev->num_ports;
3681         dev->ib_dev.dev.parent = mdev->device;
3682         dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3683
3684         for (i = 0; i < dev->num_ports; i++) {
3685                 spin_lock_init(&dev->port[i].mp.mpi_lock);
3686                 rwlock_init(&dev->port[i].roce.netdev_lock);
3687                 dev->port[i].roce.dev = dev;
3688                 dev->port[i].roce.native_port_num = i + 1;
3689                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3690         }
3691
3692         err = mlx5_ib_init_multiport_master(dev);
3693         if (err)
3694                 return err;
3695
3696         err = set_has_smi_cap(dev);
3697         if (err)
3698                 goto err_mp;
3699
3700         err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3701         if (err)
3702                 goto err_mp;
3703
3704         if (mlx5_use_mad_ifc(dev))
3705                 get_ext_port_caps(dev);
3706
3707         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
3708
3709         mutex_init(&dev->cap_mask_mutex);
3710         INIT_LIST_HEAD(&dev->qp_list);
3711         spin_lock_init(&dev->reset_flow_resource_lock);
3712         xa_init(&dev->odp_mkeys);
3713         xa_init(&dev->sig_mrs);
3714         atomic_set(&dev->mkey_var, 0);
3715
3716         spin_lock_init(&dev->dm.lock);
3717         dev->dm.dev = mdev;
3718         return 0;
3719
3720 err_mp:
3721         mlx5_ib_cleanup_multiport_master(dev);
3722         return err;
3723 }
3724
3725 static int mlx5_ib_enable_driver(struct ib_device *dev)
3726 {
3727         struct mlx5_ib_dev *mdev = to_mdev(dev);
3728         int ret;
3729
3730         ret = mlx5_ib_test_wc(mdev);
3731         mlx5_ib_dbg(mdev, "Write-Combining %s",
3732                     mdev->wc_support ? "supported" : "not supported");
3733
3734         return ret;
3735 }
3736
3737 static const struct ib_device_ops mlx5_ib_dev_ops = {
3738         .owner = THIS_MODULE,
3739         .driver_id = RDMA_DRIVER_MLX5,
3740         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3741
3742         .add_gid = mlx5_ib_add_gid,
3743         .alloc_mr = mlx5_ib_alloc_mr,
3744         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3745         .alloc_pd = mlx5_ib_alloc_pd,
3746         .alloc_ucontext = mlx5_ib_alloc_ucontext,
3747         .attach_mcast = mlx5_ib_mcg_attach,
3748         .check_mr_status = mlx5_ib_check_mr_status,
3749         .create_ah = mlx5_ib_create_ah,
3750         .create_cq = mlx5_ib_create_cq,
3751         .create_qp = mlx5_ib_create_qp,
3752         .create_srq = mlx5_ib_create_srq,
3753         .create_user_ah = mlx5_ib_create_ah,
3754         .dealloc_pd = mlx5_ib_dealloc_pd,
3755         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3756         .del_gid = mlx5_ib_del_gid,
3757         .dereg_mr = mlx5_ib_dereg_mr,
3758         .destroy_ah = mlx5_ib_destroy_ah,
3759         .destroy_cq = mlx5_ib_destroy_cq,
3760         .destroy_qp = mlx5_ib_destroy_qp,
3761         .destroy_srq = mlx5_ib_destroy_srq,
3762         .detach_mcast = mlx5_ib_mcg_detach,
3763         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3764         .drain_rq = mlx5_ib_drain_rq,
3765         .drain_sq = mlx5_ib_drain_sq,
3766         .device_group = &mlx5_attr_group,
3767         .enable_driver = mlx5_ib_enable_driver,
3768         .get_dev_fw_str = get_dev_fw_str,
3769         .get_dma_mr = mlx5_ib_get_dma_mr,
3770         .get_link_layer = mlx5_ib_port_link_layer,
3771         .map_mr_sg = mlx5_ib_map_mr_sg,
3772         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3773         .mmap = mlx5_ib_mmap,
3774         .mmap_free = mlx5_ib_mmap_free,
3775         .modify_cq = mlx5_ib_modify_cq,
3776         .modify_device = mlx5_ib_modify_device,
3777         .modify_port = mlx5_ib_modify_port,
3778         .modify_qp = mlx5_ib_modify_qp,
3779         .modify_srq = mlx5_ib_modify_srq,
3780         .poll_cq = mlx5_ib_poll_cq,
3781         .post_recv = mlx5_ib_post_recv_nodrain,
3782         .post_send = mlx5_ib_post_send_nodrain,
3783         .post_srq_recv = mlx5_ib_post_srq_recv,
3784         .process_mad = mlx5_ib_process_mad,
3785         .query_ah = mlx5_ib_query_ah,
3786         .query_device = mlx5_ib_query_device,
3787         .query_gid = mlx5_ib_query_gid,
3788         .query_pkey = mlx5_ib_query_pkey,
3789         .query_qp = mlx5_ib_query_qp,
3790         .query_srq = mlx5_ib_query_srq,
3791         .query_ucontext = mlx5_ib_query_ucontext,
3792         .reg_user_mr = mlx5_ib_reg_user_mr,
3793         .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3794         .req_notify_cq = mlx5_ib_arm_cq,
3795         .rereg_user_mr = mlx5_ib_rereg_user_mr,
3796         .resize_cq = mlx5_ib_resize_cq,
3797
3798         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3799         INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3800         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3801         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3802         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3803         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3804 };
3805
3806 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3807         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3808 };
3809
3810 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3811         .get_vf_config = mlx5_ib_get_vf_config,
3812         .get_vf_guid = mlx5_ib_get_vf_guid,
3813         .get_vf_stats = mlx5_ib_get_vf_stats,
3814         .set_vf_guid = mlx5_ib_set_vf_guid,
3815         .set_vf_link_state = mlx5_ib_set_vf_link_state,
3816 };
3817
3818 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3819         .alloc_mw = mlx5_ib_alloc_mw,
3820         .dealloc_mw = mlx5_ib_dealloc_mw,
3821
3822         INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3823 };
3824
3825 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3826         .alloc_xrcd = mlx5_ib_alloc_xrcd,
3827         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3828
3829         INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3830 };
3831
3832 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3833 {
3834         struct mlx5_core_dev *mdev = dev->mdev;
3835         struct mlx5_var_table *var_table = &dev->var_table;
3836         u8 log_doorbell_bar_size;
3837         u8 log_doorbell_stride;
3838         u64 bar_size;
3839
3840         log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3841                                         log_doorbell_bar_size);
3842         log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3843                                         log_doorbell_stride);
3844         var_table->hw_start_addr = dev->mdev->bar_addr +
3845                                 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3846                                         doorbell_bar_offset);
3847         bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3848         var_table->stride_size = 1ULL << log_doorbell_stride;
3849         var_table->num_var_hw_entries = div_u64(bar_size,
3850                                                 var_table->stride_size);
3851         mutex_init(&var_table->bitmap_lock);
3852         var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3853                                           GFP_KERNEL);
3854         return (var_table->bitmap) ? 0 : -ENOMEM;
3855 }
3856
3857 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3858 {
3859         bitmap_free(dev->var_table.bitmap);
3860 }
3861
3862 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3863 {
3864         struct mlx5_core_dev *mdev = dev->mdev;
3865         int err;
3866
3867         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3868             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3869                 ib_set_device_ops(&dev->ib_dev,
3870                                   &mlx5_ib_dev_ipoib_enhanced_ops);
3871
3872         if (mlx5_core_is_pf(mdev))
3873                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3874
3875         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3876
3877         if (MLX5_CAP_GEN(mdev, imaicl))
3878                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3879
3880         if (MLX5_CAP_GEN(mdev, xrc))
3881                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3882
3883         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3884             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3885             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3886                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3887
3888         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3889
3890         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3891                 dev->ib_dev.driver_def = mlx5_ib_defs;
3892
3893         err = init_node_data(dev);
3894         if (err)
3895                 return err;
3896
3897         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3898             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3899              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3900                 mutex_init(&dev->lb.mutex);
3901
3902         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3903                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3904                 err = mlx5_ib_init_var_table(dev);
3905                 if (err)
3906                         return err;
3907         }
3908
3909         dev->ib_dev.use_cq_dim = true;
3910
3911         return 0;
3912 }
3913
3914 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3915         .get_port_immutable = mlx5_port_immutable,
3916         .query_port = mlx5_ib_query_port,
3917 };
3918
3919 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3920 {
3921         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3922         return 0;
3923 }
3924
3925 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3926         .get_port_immutable = mlx5_port_rep_immutable,
3927         .query_port = mlx5_ib_rep_query_port,
3928         .query_pkey = mlx5_ib_rep_query_pkey,
3929 };
3930
3931 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3932 {
3933         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3934         return 0;
3935 }
3936
3937 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3938         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3939         .create_wq = mlx5_ib_create_wq,
3940         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3941         .destroy_wq = mlx5_ib_destroy_wq,
3942         .get_netdev = mlx5_ib_get_netdev,
3943         .modify_wq = mlx5_ib_modify_wq,
3944
3945         INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3946                            ib_rwq_ind_tbl),
3947 };
3948
3949 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3950 {
3951         struct mlx5_core_dev *mdev = dev->mdev;
3952         enum rdma_link_layer ll;
3953         int port_type_cap;
3954         u32 port_num = 0;
3955         int err;
3956
3957         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3958         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3959
3960         if (ll == IB_LINK_LAYER_ETHERNET) {
3961                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3962
3963                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3964
3965                 /* Register only for native ports */
3966                 err = mlx5_add_netdev_notifier(dev, port_num);
3967                 if (err)
3968                         return err;
3969
3970                 err = mlx5_enable_eth(dev);
3971                 if (err)
3972                         goto cleanup;
3973         }
3974
3975         return 0;
3976 cleanup:
3977         mlx5_remove_netdev_notifier(dev, port_num);
3978         return err;
3979 }
3980
3981 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3982 {
3983         struct mlx5_core_dev *mdev = dev->mdev;
3984         enum rdma_link_layer ll;
3985         int port_type_cap;
3986         u32 port_num;
3987
3988         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3989         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3990
3991         if (ll == IB_LINK_LAYER_ETHERNET) {
3992                 mlx5_disable_eth(dev);
3993
3994                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3995                 mlx5_remove_netdev_notifier(dev, port_num);
3996         }
3997 }
3998
3999 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4000 {
4001         mlx5_ib_init_cong_debugfs(dev,
4002                                   mlx5_core_native_port_num(dev->mdev) - 1);
4003         return 0;
4004 }
4005
4006 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4007 {
4008         mlx5_ib_cleanup_cong_debugfs(dev,
4009                                      mlx5_core_native_port_num(dev->mdev) - 1);
4010 }
4011
4012 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4013 {
4014         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4015         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4016 }
4017
4018 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4019 {
4020         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4021 }
4022
4023 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4024 {
4025         int err;
4026
4027         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4028         if (err)
4029                 return err;
4030
4031         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4032         if (err)
4033                 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4034
4035         return err;
4036 }
4037
4038 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4039 {
4040         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4041         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4042 }
4043
4044 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4045 {
4046         const char *name;
4047
4048         if (!mlx5_lag_is_active(dev->mdev))
4049                 name = "mlx5_%d";
4050         else
4051                 name = "mlx5_bond_%d";
4052         return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4053 }
4054
4055 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4056 {
4057         int err;
4058
4059         err = mlx5_mr_cache_cleanup(dev);
4060         if (err)
4061                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4062
4063         if (dev->umrc.qp)
4064                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4065         if (dev->umrc.cq)
4066                 ib_free_cq(dev->umrc.cq);
4067         if (dev->umrc.pd)
4068                 ib_dealloc_pd(dev->umrc.pd);
4069 }
4070
4071 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4072 {
4073         ib_unregister_device(&dev->ib_dev);
4074 }
4075
4076 enum {
4077         MAX_UMR_WR = 128,
4078 };
4079
4080 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4081 {
4082         struct ib_qp_init_attr *init_attr = NULL;
4083         struct ib_qp_attr *attr = NULL;
4084         struct ib_pd *pd;
4085         struct ib_cq *cq;
4086         struct ib_qp *qp;
4087         int ret;
4088
4089         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4090         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4091         if (!attr || !init_attr) {
4092                 ret = -ENOMEM;
4093                 goto error_0;
4094         }
4095
4096         pd = ib_alloc_pd(&dev->ib_dev, 0);
4097         if (IS_ERR(pd)) {
4098                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4099                 ret = PTR_ERR(pd);
4100                 goto error_0;
4101         }
4102
4103         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4104         if (IS_ERR(cq)) {
4105                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4106                 ret = PTR_ERR(cq);
4107                 goto error_2;
4108         }
4109
4110         init_attr->send_cq = cq;
4111         init_attr->recv_cq = cq;
4112         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4113         init_attr->cap.max_send_wr = MAX_UMR_WR;
4114         init_attr->cap.max_send_sge = 1;
4115         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4116         init_attr->port_num = 1;
4117         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4118         if (IS_ERR(qp)) {
4119                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4120                 ret = PTR_ERR(qp);
4121                 goto error_3;
4122         }
4123         qp->device     = &dev->ib_dev;
4124         qp->real_qp    = qp;
4125         qp->uobject    = NULL;
4126         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4127         qp->send_cq    = init_attr->send_cq;
4128         qp->recv_cq    = init_attr->recv_cq;
4129
4130         attr->qp_state = IB_QPS_INIT;
4131         attr->port_num = 1;
4132         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4133                                 IB_QP_PORT, NULL);
4134         if (ret) {
4135                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4136                 goto error_4;
4137         }
4138
4139         memset(attr, 0, sizeof(*attr));
4140         attr->qp_state = IB_QPS_RTR;
4141         attr->path_mtu = IB_MTU_256;
4142
4143         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4144         if (ret) {
4145                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4146                 goto error_4;
4147         }
4148
4149         memset(attr, 0, sizeof(*attr));
4150         attr->qp_state = IB_QPS_RTS;
4151         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4152         if (ret) {
4153                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4154                 goto error_4;
4155         }
4156
4157         dev->umrc.qp = qp;
4158         dev->umrc.cq = cq;
4159         dev->umrc.pd = pd;
4160
4161         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4162         ret = mlx5_mr_cache_init(dev);
4163         if (ret) {
4164                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4165                 goto error_4;
4166         }
4167
4168         kfree(attr);
4169         kfree(init_attr);
4170
4171         return 0;
4172
4173 error_4:
4174         mlx5_ib_destroy_qp(qp, NULL);
4175         dev->umrc.qp = NULL;
4176
4177 error_3:
4178         ib_free_cq(cq);
4179         dev->umrc.cq = NULL;
4180
4181 error_2:
4182         ib_dealloc_pd(pd);
4183         dev->umrc.pd = NULL;
4184
4185 error_0:
4186         kfree(attr);
4187         kfree(init_attr);
4188         return ret;
4189 }
4190
4191 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4192 {
4193         struct dentry *root;
4194
4195         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4196                 return 0;
4197
4198         mutex_init(&dev->delay_drop.lock);
4199         dev->delay_drop.dev = dev;
4200         dev->delay_drop.activate = false;
4201         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4202         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4203         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4204         atomic_set(&dev->delay_drop.events_cnt, 0);
4205
4206         if (!mlx5_debugfs_root)
4207                 return 0;
4208
4209         root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4210         dev->delay_drop.dir_debugfs = root;
4211
4212         debugfs_create_atomic_t("num_timeout_events", 0400, root,
4213                                 &dev->delay_drop.events_cnt);
4214         debugfs_create_atomic_t("num_rqs", 0400, root,
4215                                 &dev->delay_drop.rqs_cnt);
4216         debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4217                             &fops_delay_drop_timeout);
4218         return 0;
4219 }
4220
4221 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4222 {
4223         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4224                 return;
4225
4226         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4227         if (!dev->delay_drop.dir_debugfs)
4228                 return;
4229
4230         debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4231         dev->delay_drop.dir_debugfs = NULL;
4232 }
4233
4234 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4235 {
4236         dev->mdev_events.notifier_call = mlx5_ib_event;
4237         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4238         return 0;
4239 }
4240
4241 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4242 {
4243         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4244 }
4245
4246 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4247                       const struct mlx5_ib_profile *profile,
4248                       int stage)
4249 {
4250         dev->ib_active = false;
4251
4252         /* Number of stages to cleanup */
4253         while (stage) {
4254                 stage--;
4255                 if (profile->stage[stage].cleanup)
4256                         profile->stage[stage].cleanup(dev);
4257         }
4258
4259         kfree(dev->port);
4260         ib_dealloc_device(&dev->ib_dev);
4261 }
4262
4263 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4264                   const struct mlx5_ib_profile *profile)
4265 {
4266         int err;
4267         int i;
4268
4269         dev->profile = profile;
4270
4271         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4272                 if (profile->stage[i].init) {
4273                         err = profile->stage[i].init(dev);
4274                         if (err)
4275                                 goto err_out;
4276                 }
4277         }
4278
4279         dev->ib_active = true;
4280         return 0;
4281
4282 err_out:
4283         /* Clean up stages which were initialized */
4284         while (i) {
4285                 i--;
4286                 if (profile->stage[i].cleanup)
4287                         profile->stage[i].cleanup(dev);
4288         }
4289         return -ENOMEM;
4290 }
4291
4292 static const struct mlx5_ib_profile pf_profile = {
4293         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4294                      mlx5_ib_stage_init_init,
4295                      mlx5_ib_stage_init_cleanup),
4296         STAGE_CREATE(MLX5_IB_STAGE_FS,
4297                      mlx5_ib_fs_init,
4298                      mlx5_ib_fs_cleanup),
4299         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4300                      mlx5_ib_stage_caps_init,
4301                      mlx5_ib_stage_caps_cleanup),
4302         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4303                      mlx5_ib_stage_non_default_cb,
4304                      NULL),
4305         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4306                      mlx5_ib_roce_init,
4307                      mlx5_ib_roce_cleanup),
4308         STAGE_CREATE(MLX5_IB_STAGE_QP,
4309                      mlx5_init_qp_table,
4310                      mlx5_cleanup_qp_table),
4311         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4312                      mlx5_init_srq_table,
4313                      mlx5_cleanup_srq_table),
4314         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4315                      mlx5_ib_dev_res_init,
4316                      mlx5_ib_dev_res_cleanup),
4317         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4318                      mlx5_ib_stage_dev_notifier_init,
4319                      mlx5_ib_stage_dev_notifier_cleanup),
4320         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4321                      mlx5_ib_odp_init_one,
4322                      mlx5_ib_odp_cleanup_one),
4323         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4324                      mlx5_ib_counters_init,
4325                      mlx5_ib_counters_cleanup),
4326         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4327                      mlx5_ib_stage_cong_debugfs_init,
4328                      mlx5_ib_stage_cong_debugfs_cleanup),
4329         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4330                      mlx5_ib_stage_uar_init,
4331                      mlx5_ib_stage_uar_cleanup),
4332         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4333                      mlx5_ib_stage_bfrag_init,
4334                      mlx5_ib_stage_bfrag_cleanup),
4335         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4336                      NULL,
4337                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4338         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4339                      mlx5_ib_devx_init,
4340                      mlx5_ib_devx_cleanup),
4341         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4342                      mlx5_ib_stage_ib_reg_init,
4343                      mlx5_ib_stage_ib_reg_cleanup),
4344         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4345                      mlx5_ib_stage_post_ib_reg_umr_init,
4346                      NULL),
4347         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4348                      mlx5_ib_stage_delay_drop_init,
4349                      mlx5_ib_stage_delay_drop_cleanup),
4350         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4351                      mlx5_ib_restrack_init,
4352                      NULL),
4353 };
4354
4355 const struct mlx5_ib_profile raw_eth_profile = {
4356         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4357                      mlx5_ib_stage_init_init,
4358                      mlx5_ib_stage_init_cleanup),
4359         STAGE_CREATE(MLX5_IB_STAGE_FS,
4360                      mlx5_ib_fs_init,
4361                      mlx5_ib_fs_cleanup),
4362         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4363                      mlx5_ib_stage_caps_init,
4364                      mlx5_ib_stage_caps_cleanup),
4365         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4366                      mlx5_ib_stage_raw_eth_non_default_cb,
4367                      NULL),
4368         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4369                      mlx5_ib_roce_init,
4370                      mlx5_ib_roce_cleanup),
4371         STAGE_CREATE(MLX5_IB_STAGE_QP,
4372                      mlx5_init_qp_table,
4373                      mlx5_cleanup_qp_table),
4374         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4375                      mlx5_init_srq_table,
4376                      mlx5_cleanup_srq_table),
4377         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4378                      mlx5_ib_dev_res_init,
4379                      mlx5_ib_dev_res_cleanup),
4380         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4381                      mlx5_ib_stage_dev_notifier_init,
4382                      mlx5_ib_stage_dev_notifier_cleanup),
4383         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4384                      mlx5_ib_counters_init,
4385                      mlx5_ib_counters_cleanup),
4386         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4387                      mlx5_ib_stage_cong_debugfs_init,
4388                      mlx5_ib_stage_cong_debugfs_cleanup),
4389         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4390                      mlx5_ib_stage_uar_init,
4391                      mlx5_ib_stage_uar_cleanup),
4392         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4393                      mlx5_ib_stage_bfrag_init,
4394                      mlx5_ib_stage_bfrag_cleanup),
4395         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4396                      NULL,
4397                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4398         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4399                      mlx5_ib_devx_init,
4400                      mlx5_ib_devx_cleanup),
4401         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4402                      mlx5_ib_stage_ib_reg_init,
4403                      mlx5_ib_stage_ib_reg_cleanup),
4404         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4405                      mlx5_ib_stage_post_ib_reg_umr_init,
4406                      NULL),
4407         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4408                      mlx5_ib_restrack_init,
4409                      NULL),
4410 };
4411
4412 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4413                           const struct auxiliary_device_id *id)
4414 {
4415         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4416         struct mlx5_core_dev *mdev = idev->mdev;
4417         struct mlx5_ib_multiport_info *mpi;
4418         struct mlx5_ib_dev *dev;
4419         bool bound = false;
4420         int err;
4421
4422         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4423         if (!mpi)
4424                 return -ENOMEM;
4425
4426         mpi->mdev = mdev;
4427         err = mlx5_query_nic_vport_system_image_guid(mdev,
4428                                                      &mpi->sys_image_guid);
4429         if (err) {
4430                 kfree(mpi);
4431                 return err;
4432         }
4433
4434         mutex_lock(&mlx5_ib_multiport_mutex);
4435         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4436                 if (dev->sys_image_guid == mpi->sys_image_guid)
4437                         bound = mlx5_ib_bind_slave_port(dev, mpi);
4438
4439                 if (bound) {
4440                         rdma_roce_rescan_device(&dev->ib_dev);
4441                         mpi->ibdev->ib_active = true;
4442                         break;
4443                 }
4444         }
4445
4446         if (!bound) {
4447                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4448                 dev_dbg(mdev->device,
4449                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
4450         }
4451         mutex_unlock(&mlx5_ib_multiport_mutex);
4452
4453         dev_set_drvdata(&adev->dev, mpi);
4454         return 0;
4455 }
4456
4457 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4458 {
4459         struct mlx5_ib_multiport_info *mpi;
4460
4461         mpi = dev_get_drvdata(&adev->dev);
4462         mutex_lock(&mlx5_ib_multiport_mutex);
4463         if (mpi->ibdev)
4464                 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4465         else
4466                 list_del(&mpi->list);
4467         mutex_unlock(&mlx5_ib_multiport_mutex);
4468         kfree(mpi);
4469 }
4470
4471 static int mlx5r_probe(struct auxiliary_device *adev,
4472                        const struct auxiliary_device_id *id)
4473 {
4474         struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4475         struct mlx5_core_dev *mdev = idev->mdev;
4476         const struct mlx5_ib_profile *profile;
4477         int port_type_cap, num_ports, ret;
4478         enum rdma_link_layer ll;
4479         struct mlx5_ib_dev *dev;
4480
4481         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4482         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4483
4484         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4485                         MLX5_CAP_GEN(mdev, num_vhca_ports));
4486         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4487         if (!dev)
4488                 return -ENOMEM;
4489         dev->port = kcalloc(num_ports, sizeof(*dev->port),
4490                              GFP_KERNEL);
4491         if (!dev->port) {
4492                 ib_dealloc_device(&dev->ib_dev);
4493                 return -ENOMEM;
4494         }
4495
4496         dev->mdev = mdev;
4497         dev->num_ports = num_ports;
4498
4499         if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4500                 profile = &raw_eth_profile;
4501         else
4502                 profile = &pf_profile;
4503
4504         ret = __mlx5_ib_add(dev, profile);
4505         if (ret) {
4506                 kfree(dev->port);
4507                 ib_dealloc_device(&dev->ib_dev);
4508                 return ret;
4509         }
4510
4511         dev_set_drvdata(&adev->dev, dev);
4512         return 0;
4513 }
4514
4515 static void mlx5r_remove(struct auxiliary_device *adev)
4516 {
4517         struct mlx5_ib_dev *dev;
4518
4519         dev = dev_get_drvdata(&adev->dev);
4520         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4521 }
4522
4523 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4524         { .name = MLX5_ADEV_NAME ".multiport", },
4525         {},
4526 };
4527
4528 static const struct auxiliary_device_id mlx5r_id_table[] = {
4529         { .name = MLX5_ADEV_NAME ".rdma", },
4530         {},
4531 };
4532
4533 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4534 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4535
4536 static struct auxiliary_driver mlx5r_mp_driver = {
4537         .name = "multiport",
4538         .probe = mlx5r_mp_probe,
4539         .remove = mlx5r_mp_remove,
4540         .id_table = mlx5r_mp_id_table,
4541 };
4542
4543 static struct auxiliary_driver mlx5r_driver = {
4544         .name = "rdma",
4545         .probe = mlx5r_probe,
4546         .remove = mlx5r_remove,
4547         .id_table = mlx5r_id_table,
4548 };
4549
4550 static int __init mlx5_ib_init(void)
4551 {
4552         int ret;
4553
4554         xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4555         if (!xlt_emergency_page)
4556                 return -ENOMEM;
4557
4558         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4559         if (!mlx5_ib_event_wq) {
4560                 free_page((unsigned long)xlt_emergency_page);
4561                 return -ENOMEM;
4562         }
4563
4564         mlx5_ib_odp_init();
4565         ret = mlx5r_rep_init();
4566         if (ret)
4567                 goto rep_err;
4568         ret = auxiliary_driver_register(&mlx5r_mp_driver);
4569         if (ret)
4570                 goto mp_err;
4571         ret = auxiliary_driver_register(&mlx5r_driver);
4572         if (ret)
4573                 goto drv_err;
4574         return 0;
4575
4576 drv_err:
4577         auxiliary_driver_unregister(&mlx5r_mp_driver);
4578 mp_err:
4579         mlx5r_rep_cleanup();
4580 rep_err:
4581         destroy_workqueue(mlx5_ib_event_wq);
4582         free_page((unsigned long)xlt_emergency_page);
4583         return ret;
4584 }
4585
4586 static void __exit mlx5_ib_cleanup(void)
4587 {
4588         auxiliary_driver_unregister(&mlx5r_driver);
4589         auxiliary_driver_unregister(&mlx5r_mp_driver);
4590         mlx5r_rep_cleanup();
4591
4592         destroy_workqueue(mlx5_ib_event_wq);
4593         free_page((unsigned long)xlt_emergency_page);
4594 }
4595
4596 module_init(mlx5_ib_init);
4597 module_exit(mlx5_ib_cleanup);