drivers/infiniband/hw/mlx5/main.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /*
   3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
   4  */
   5
   6 #include <linux/debugfs.h>
   7 #include <linux/highmem.h>
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/errno.h>
  11 #include <linux/pci.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/slab.h>
  14 #include <linux/bitmap.h>
  15 #include <linux/sched.h>
  16 #include <linux/sched/mm.h>
  17 #include <linux/sched/task.h>
  18 #include <linux/delay.h>
  19 #include <rdma/ib_user_verbs.h>
  20 #include <rdma/ib_addr.h>
  21 #include <rdma/ib_cache.h>
  22 #include <linux/mlx5/port.h>
  23 #include <linux/mlx5/vport.h>
  24 #include <linux/mlx5/fs.h>
  25 #include <linux/mlx5/eswitch.h>
  26 #include <linux/list.h>
  27 #include <rdma/ib_smi.h>
  28 #include <rdma/ib_umem.h>
  29 #include <rdma/lag.h>
  30 #include <linux/in.h>
  31 #include <linux/etherdevice.h>
  32 #include "mlx5_ib.h"
  33 #include "ib_rep.h"
  34 #include "cmd.h"
  35 #include "devx.h"
  36 #include "fs.h"
  37 #include "srq.h"
  38 #include "qp.h"
  39 #include "wr.h"
  40 #include "restrack.h"
  41 #include "counters.h"
  42 #include <linux/mlx5/accel.h>
  43 #include <rdma/uverbs_std_types.h>
  44 #include <rdma/mlx5_user_ioctl_verbs.h>
  45 #include <rdma/mlx5_user_ioctl_cmds.h>
  46 #include <rdma/ib_umem_odp.h>
  47
  48 #define UVERBS_MODULE_NAME mlx5_ib
  49 #include <rdma/uverbs_named_ioctl.h>
  50
  51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  52 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54
  55 struct mlx5_ib_event_work {
  56         struct work_struct      work;
  57         union {
  58                 struct mlx5_ib_dev            *dev;
  59                 struct mlx5_ib_multiport_info *mpi;
  60         };
  61         bool                    is_slave;
  62         unsigned int            event;
  63         void                    *param;
  64 };
  65
  66 enum {
  67         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  68 };
  69
  70 static struct workqueue_struct *mlx5_ib_event_wq;
  71 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  72 static LIST_HEAD(mlx5_ib_dev_list);
  73 /*
  74  * This mutex should be held when accessing either of the above lists
  75  */
  76 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  77
  78 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  79 {
  80         struct mlx5_ib_dev *dev;
  81
  82         mutex_lock(&mlx5_ib_multiport_mutex);
  83         dev = mpi->ibdev;
  84         mutex_unlock(&mlx5_ib_multiport_mutex);
  85         return dev;
  86 }
  87
  88 static enum rdma_link_layer
  89 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  90 {
  91         switch (port_type_cap) {
  92         case MLX5_CAP_PORT_TYPE_IB:
  93                 return IB_LINK_LAYER_INFINIBAND;
  94         case MLX5_CAP_PORT_TYPE_ETH:
  95                 return IB_LINK_LAYER_ETHERNET;
  96         default:
  97                 return IB_LINK_LAYER_UNSPECIFIED;
  98         }
  99 }
 100
 101 static enum rdma_link_layer
 102 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 103 {
 104         struct mlx5_ib_dev *dev = to_mdev(device);
 105         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 106
 107         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 108 }
 109
 110 static int get_port_state(struct ib_device *ibdev,
 111                           u8 port_num,
 112                           enum ib_port_state *state)
 113 {
 114         struct ib_port_attr attr;
 115         int ret;
 116
 117         memset(&attr, 0, sizeof(attr));
 118         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 119         if (!ret)
 120                 *state = attr.state;
 121         return ret;
 122 }
 123
 124 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 125                                            struct net_device *ndev,
 126                                            u8 *port_num)
 127 {
 128         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 129         struct net_device *rep_ndev;
 130         struct mlx5_ib_port *port;
 131         int i;
 132
 133         for (i = 0; i < dev->num_ports; i++) {
 134                 port  = &dev->port[i];
 135                 if (!port->rep)
 136                         continue;
 137
 138                 read_lock(&port->roce.netdev_lock);
 139                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 140                                                   port->rep->vport);
 141                 if (rep_ndev == ndev) {
 142                         read_unlock(&port->roce.netdev_lock);
 143                         *port_num = i + 1;
 144                         return &port->roce;
 145                 }
 146                 read_unlock(&port->roce.netdev_lock);
 147         }
 148
 149         return NULL;
 150 }
 151
 152 static int mlx5_netdev_event(struct notifier_block *this,
 153                              unsigned long event, void *ptr)
 154 {
 155         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 156         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 157         u8 port_num = roce->native_port_num;
 158         struct mlx5_core_dev *mdev;
 159         struct mlx5_ib_dev *ibdev;
 160
 161         ibdev = roce->dev;
 162         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 163         if (!mdev)
 164                 return NOTIFY_DONE;
 165
 166         switch (event) {
 167         case NETDEV_REGISTER:
 168                 /* Should already be registered during the load */
 169                 if (ibdev->is_rep)
 170                         break;
 171                 write_lock(&roce->netdev_lock);
 172                 if (ndev->dev.parent == mdev->device)
 173                         roce->netdev = ndev;
 174                 write_unlock(&roce->netdev_lock);
 175                 break;
 176
 177         case NETDEV_UNREGISTER:
 178                 /* In case of reps, ib device goes away before the netdevs */
 179                 write_lock(&roce->netdev_lock);
 180                 if (roce->netdev == ndev)
 181                         roce->netdev = NULL;
 182                 write_unlock(&roce->netdev_lock);
 183                 break;
 184
 185         case NETDEV_CHANGE:
 186         case NETDEV_UP:
 187         case NETDEV_DOWN: {
 188                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 189                 struct net_device *upper = NULL;
 190
 191                 if (lag_ndev) {
 192                         upper = netdev_master_upper_dev_get(lag_ndev);
 193                         dev_put(lag_ndev);
 194                 }
 195
 196                 if (ibdev->is_rep)
 197                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 198                 if (!roce)
 199                         return NOTIFY_DONE;
 200                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 201                     && ibdev->ib_active) {
 202                         struct ib_event ibev = { };
 203                         enum ib_port_state port_state;
 204
 205                         if (get_port_state(&ibdev->ib_dev, port_num,
 206                                            &port_state))
 207                                 goto done;
 208
 209                         if (roce->last_port_state == port_state)
 210                                 goto done;
 211
 212                         roce->last_port_state = port_state;
 213                         ibev.device = &ibdev->ib_dev;
 214                         if (port_state == IB_PORT_DOWN)
 215                                 ibev.event = IB_EVENT_PORT_ERR;
 216                         else if (port_state == IB_PORT_ACTIVE)
 217                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 218                         else
 219                                 goto done;
 220
 221                         ibev.element.port_num = port_num;
 222                         ib_dispatch_event(&ibev);
 223                 }
 224                 break;
 225         }
 226
 227         default:
 228                 break;
 229         }
 230 done:
 231         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 232         return NOTIFY_DONE;
 233 }
 234
 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 236                                              u8 port_num)
 237 {
 238         struct mlx5_ib_dev *ibdev = to_mdev(device);
 239         struct net_device *ndev;
 240         struct mlx5_core_dev *mdev;
 241
 242         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 243         if (!mdev)
 244                 return NULL;
 245
 246         ndev = mlx5_lag_get_roce_netdev(mdev);
 247         if (ndev)
 248                 goto out;
 249
 250         /* Ensure ndev does not disappear before we invoke dev_hold()
 251          */
 252         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 253         ndev = ibdev->port[port_num - 1].roce.netdev;
 254         if (ndev)
 255                 dev_hold(ndev);
 256         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 257
 258 out:
 259         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 260         return ndev;
 261 }
 262
 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 264                                                    u8 ib_port_num,
 265                                                    u8 *native_port_num)
 266 {
 267         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 268                                                           ib_port_num);
 269         struct mlx5_core_dev *mdev = NULL;
 270         struct mlx5_ib_multiport_info *mpi;
 271         struct mlx5_ib_port *port;
 272
 273         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 274             ll != IB_LINK_LAYER_ETHERNET) {
 275                 if (native_port_num)
 276                         *native_port_num = ib_port_num;
 277                 return ibdev->mdev;
 278         }
 279
 280         if (native_port_num)
 281                 *native_port_num = 1;
 282
 283         port = &ibdev->port[ib_port_num - 1];
 284         spin_lock(&port->mp.mpi_lock);
 285         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 286         if (mpi && !mpi->unaffiliate) {
 287                 mdev = mpi->mdev;
 288                 /* If it's the master no need to refcount, it'll exist
 289                  * as long as the ib_dev exists.
 290                  */
 291                 if (!mpi->is_master)
 292                         mpi->mdev_refcnt++;
 293         }
 294         spin_unlock(&port->mp.mpi_lock);
 295
 296         return mdev;
 297 }
 298
 299 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 300 {
 301         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 302                                                           port_num);
 303         struct mlx5_ib_multiport_info *mpi;
 304         struct mlx5_ib_port *port;
 305
 306         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 307                 return;
 308
 309         port = &ibdev->port[port_num - 1];
 310
 311         spin_lock(&port->mp.mpi_lock);
 312         mpi = ibdev->port[port_num - 1].mp.mpi;
 313         if (mpi->is_master)
 314                 goto out;
 315
 316         mpi->mdev_refcnt--;
 317         if (mpi->unaffiliate)
 318                 complete(&mpi->unref_comp);
 319 out:
 320         spin_unlock(&port->mp.mpi_lock);
 321 }
 322
 323 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
 324                                            u16 *active_speed, u8 *active_width)
 325 {
 326         switch (eth_proto_oper) {
 327         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 328         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 329         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 330         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 331                 *active_width = IB_WIDTH_1X;
 332                 *active_speed = IB_SPEED_SDR;
 333                 break;
 334         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 335         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 336         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 337         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 341                 *active_width = IB_WIDTH_1X;
 342                 *active_speed = IB_SPEED_QDR;
 343                 break;
 344         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 345         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 346         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 347                 *active_width = IB_WIDTH_1X;
 348                 *active_speed = IB_SPEED_EDR;
 349                 break;
 350         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 351         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 352         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 353         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 354                 *active_width = IB_WIDTH_4X;
 355                 *active_speed = IB_SPEED_QDR;
 356                 break;
 357         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 358         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 359         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 360                 *active_width = IB_WIDTH_1X;
 361                 *active_speed = IB_SPEED_HDR;
 362                 break;
 363         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 364                 *active_width = IB_WIDTH_4X;
 365                 *active_speed = IB_SPEED_FDR;
 366                 break;
 367         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 368         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 369         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 370         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 371                 *active_width = IB_WIDTH_4X;
 372                 *active_speed = IB_SPEED_EDR;
 373                 break;
 374         default:
 375                 return -EINVAL;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 382                                         u8 *active_width)
 383 {
 384         switch (eth_proto_oper) {
 385         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 386         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 387                 *active_width = IB_WIDTH_1X;
 388                 *active_speed = IB_SPEED_SDR;
 389                 break;
 390         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 391                 *active_width = IB_WIDTH_1X;
 392                 *active_speed = IB_SPEED_DDR;
 393                 break;
 394         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 395                 *active_width = IB_WIDTH_1X;
 396                 *active_speed = IB_SPEED_QDR;
 397                 break;
 398         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 399                 *active_width = IB_WIDTH_4X;
 400                 *active_speed = IB_SPEED_QDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 403                 *active_width = IB_WIDTH_1X;
 404                 *active_speed = IB_SPEED_EDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 407                 *active_width = IB_WIDTH_2X;
 408                 *active_speed = IB_SPEED_EDR;
 409                 break;
 410         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 411                 *active_width = IB_WIDTH_1X;
 412                 *active_speed = IB_SPEED_HDR;
 413                 break;
 414         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 415                 *active_width = IB_WIDTH_4X;
 416                 *active_speed = IB_SPEED_EDR;
 417                 break;
 418         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 419                 *active_width = IB_WIDTH_2X;
 420                 *active_speed = IB_SPEED_HDR;
 421                 break;
 422         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 423                 *active_width = IB_WIDTH_4X;
 424                 *active_speed = IB_SPEED_HDR;
 425                 break;
 426         default:
 427                 return -EINVAL;
 428         }
 429
 430         return 0;
 431 }
 432
 433 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
 434                                     u8 *active_width, bool ext)
 435 {
 436         return ext ?
 437                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 438                                              active_width) :
 439                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 440                                                 active_width);
 441 }
 442
 443 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 444                                 struct ib_port_attr *props)
 445 {
 446         struct mlx5_ib_dev *dev = to_mdev(device);
 447         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 448         struct mlx5_core_dev *mdev;
 449         struct net_device *ndev, *upper;
 450         enum ib_mtu ndev_ib_mtu;
 451         bool put_mdev = true;
 452         u16 qkey_viol_cntr;
 453         u32 eth_prot_oper;
 454         u8 mdev_port_num;
 455         bool ext;
 456         int err;
 457
 458         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 459         if (!mdev) {
 460                 /* This means the port isn't affiliated yet. Get the
 461                  * info for the master port instead.
 462                  */
 463                 put_mdev = false;
 464                 mdev = dev->mdev;
 465                 mdev_port_num = 1;
 466                 port_num = 1;
 467         }
 468
 469         /* Possible bad flows are checked before filling out props so in case
 470          * of an error it will still be zeroed out.
 471          * Use native port in case of reps
 472          */
 473         if (dev->is_rep)
 474                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 475                                            1);
 476         else
 477                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 478                                            mdev_port_num);
 479         if (err)
 480                 goto out;
 481         ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
 482         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 483
 484         props->active_width     = IB_WIDTH_4X;
 485         props->active_speed     = IB_SPEED_QDR;
 486
 487         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 488                                  &props->active_width, ext);
 489
 490         props->port_cap_flags |= IB_PORT_CM_SUP;
 491         props->ip_gids = true;
 492
 493         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 494                                                 roce_address_table_size);
 495         props->max_mtu          = IB_MTU_4096;
 496         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 497         props->pkey_tbl_len     = 1;
 498         props->state            = IB_PORT_DOWN;
 499         props->phys_state       = IB_PORT_PHYS_STATE_DISABLED;
 500
 501         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 502         props->qkey_viol_cntr = qkey_viol_cntr;
 503
 504         /* If this is a stub query for an unaffiliated port stop here */
 505         if (!put_mdev)
 506                 goto out;
 507
 508         ndev = mlx5_ib_get_netdev(device, port_num);
 509         if (!ndev)
 510                 goto out;
 511
 512         if (dev->lag_active) {
 513                 rcu_read_lock();
 514                 upper = netdev_master_upper_dev_get_rcu(ndev);
 515                 if (upper) {
 516                         dev_put(ndev);
 517                         ndev = upper;
 518                         dev_hold(ndev);
 519                 }
 520                 rcu_read_unlock();
 521         }
 522
 523         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 524                 props->state      = IB_PORT_ACTIVE;
 525                 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 526         }
 527
 528         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 529
 530         dev_put(ndev);
 531
 532         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 533 out:
 534         if (put_mdev)
 535                 mlx5_ib_put_native_port_mdev(dev, port_num);
 536         return err;
 537 }
 538
 539 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 540                          unsigned int index, const union ib_gid *gid,
 541                          const struct ib_gid_attr *attr)
 542 {
 543         enum ib_gid_type gid_type = IB_GID_TYPE_ROCE;
 544         u16 vlan_id = 0xffff;
 545         u8 roce_version = 0;
 546         u8 roce_l3_type = 0;
 547         u8 mac[ETH_ALEN];
 548         int ret;
 549
 550         if (gid) {
 551                 gid_type = attr->gid_type;
 552                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 553                 if (ret)
 554                         return ret;
 555         }
 556
 557         switch (gid_type) {
 558         case IB_GID_TYPE_ROCE:
 559                 roce_version = MLX5_ROCE_VERSION_1;
 560                 break;
 561         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 562                 roce_version = MLX5_ROCE_VERSION_2;
 563                 if (ipv6_addr_v4mapped((void *)gid))
 564                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 565                 else
 566                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 567                 break;
 568
 569         default:
 570                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 571         }
 572
 573         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 574                                       roce_l3_type, gid->raw, mac,
 575                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 576                                       port_num);
 577 }
 578
 579 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 580                            __always_unused void **context)
 581 {
 582         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 583                              attr->index, &attr->gid, attr);
 584 }
 585
 586 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 587                            __always_unused void **context)
 588 {
 589         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 590                              attr->index, NULL, NULL);
 591 }
 592
 593 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
 594                                    const struct ib_gid_attr *attr)
 595 {
 596         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 597                 return 0;
 598
 599         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 600 }
 601
 602 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 603 {
 604         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 605                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 606         return 0;
 607 }
 608
 609 enum {
 610         MLX5_VPORT_ACCESS_METHOD_MAD,
 611         MLX5_VPORT_ACCESS_METHOD_HCA,
 612         MLX5_VPORT_ACCESS_METHOD_NIC,
 613 };
 614
 615 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 616 {
 617         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 618                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 619
 620         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 621             IB_LINK_LAYER_ETHERNET)
 622                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 623
 624         return MLX5_VPORT_ACCESS_METHOD_HCA;
 625 }
 626
 627 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 628                             u8 atomic_size_qp,
 629                             struct ib_device_attr *props)
 630 {
 631         u8 tmp;
 632         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 633         u8 atomic_req_8B_endianness_mode =
 634                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 635
 636         /* Check if HW supports 8 bytes standard atomic operations and capable
 637          * of host endianness respond
 638          */
 639         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 640         if (((atomic_operations & tmp) == tmp) &&
 641             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 642             (atomic_req_8B_endianness_mode)) {
 643                 props->atomic_cap = IB_ATOMIC_HCA;
 644         } else {
 645                 props->atomic_cap = IB_ATOMIC_NONE;
 646         }
 647 }
 648
 649 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 650                                struct ib_device_attr *props)
 651 {
 652         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 653
 654         get_atomic_caps(dev, atomic_size_qp, props);
 655 }
 656
 657 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 658                                         __be64 *sys_image_guid)
 659 {
 660         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 661         struct mlx5_core_dev *mdev = dev->mdev;
 662         u64 tmp;
 663         int err;
 664
 665         switch (mlx5_get_vport_access_method(ibdev)) {
 666         case MLX5_VPORT_ACCESS_METHOD_MAD:
 667                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 668                                                             sys_image_guid);
 669
 670         case MLX5_VPORT_ACCESS_METHOD_HCA:
 671                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 672                 break;
 673
 674         case MLX5_VPORT_ACCESS_METHOD_NIC:
 675                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 676                 break;
 677
 678         default:
 679                 return -EINVAL;
 680         }
 681
 682         if (!err)
 683                 *sys_image_guid = cpu_to_be64(tmp);
 684
 685         return err;
 686
 687 }
 688
 689 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 690                                 u16 *max_pkeys)
 691 {
 692         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 693         struct mlx5_core_dev *mdev = dev->mdev;
 694
 695         switch (mlx5_get_vport_access_method(ibdev)) {
 696         case MLX5_VPORT_ACCESS_METHOD_MAD:
 697                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 698
 699         case MLX5_VPORT_ACCESS_METHOD_HCA:
 700         case MLX5_VPORT_ACCESS_METHOD_NIC:
 701                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 702                                                 pkey_table_size));
 703                 return 0;
 704
 705         default:
 706                 return -EINVAL;
 707         }
 708 }
 709
 710 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 711                                 u32 *vendor_id)
 712 {
 713         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 714
 715         switch (mlx5_get_vport_access_method(ibdev)) {
 716         case MLX5_VPORT_ACCESS_METHOD_MAD:
 717                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 718
 719         case MLX5_VPORT_ACCESS_METHOD_HCA:
 720         case MLX5_VPORT_ACCESS_METHOD_NIC:
 721                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 722
 723         default:
 724                 return -EINVAL;
 725         }
 726 }
 727
 728 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 729                                 __be64 *node_guid)
 730 {
 731         u64 tmp;
 732         int err;
 733
 734         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 735         case MLX5_VPORT_ACCESS_METHOD_MAD:
 736                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 737
 738         case MLX5_VPORT_ACCESS_METHOD_HCA:
 739                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 740                 break;
 741
 742         case MLX5_VPORT_ACCESS_METHOD_NIC:
 743                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 744                 break;
 745
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         if (!err)
 751                 *node_guid = cpu_to_be64(tmp);
 752
 753         return err;
 754 }
 755
 756 struct mlx5_reg_node_desc {
 757         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 758 };
 759
 760 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 761 {
 762         struct mlx5_reg_node_desc in;
 763
 764         if (mlx5_use_mad_ifc(dev))
 765                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 766
 767         memset(&in, 0, sizeof(in));
 768
 769         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 770                                     sizeof(struct mlx5_reg_node_desc),
 771                                     MLX5_REG_NODE_DESC, 0, 0);
 772 }
 773
 774 static int mlx5_ib_query_device(struct ib_device *ibdev,
 775                                 struct ib_device_attr *props,
 776                                 struct ib_udata *uhw)
 777 {
 778         size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
 779         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 780         struct mlx5_core_dev *mdev = dev->mdev;
 781         int err = -ENOMEM;
 782         int max_sq_desc;
 783         int max_rq_sg;
 784         int max_sq_sg;
 785         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 786         bool raw_support = !mlx5_core_mp_enabled(mdev);
 787         struct mlx5_ib_query_device_resp resp = {};
 788         size_t resp_len;
 789         u64 max_tso;
 790
 791         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 792         if (uhw_outlen && uhw_outlen < resp_len)
 793                 return -EINVAL;
 794
 795         resp.response_length = resp_len;
 796
 797         if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 798                 return -EINVAL;
 799
 800         memset(props, 0, sizeof(*props));
 801         err = mlx5_query_system_image_guid(ibdev,
 802                                            &props->sys_image_guid);
 803         if (err)
 804                 return err;
 805
 806         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 807         if (err)
 808                 return err;
 809
 810         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 811         if (err)
 812                 return err;
 813
 814         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 815                 (fw_rev_min(dev->mdev) << 16) |
 816                 fw_rev_sub(dev->mdev);
 817         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 818                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 819                 IB_DEVICE_SYS_IMAGE_GUID                |
 820                 IB_DEVICE_RC_RNR_NAK_GEN;
 821
 822         if (MLX5_CAP_GEN(mdev, pkv))
 823                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 824         if (MLX5_CAP_GEN(mdev, qkv))
 825                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 826         if (MLX5_CAP_GEN(mdev, apm))
 827                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 828         if (MLX5_CAP_GEN(mdev, xrc))
 829                 props->device_cap_flags |= IB_DEVICE_XRC;
 830         if (MLX5_CAP_GEN(mdev, imaicl)) {
 831                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 832                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 833                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 834                 /* We support 'Gappy' memory registration too */
 835                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 836         }
 837         /* IB_WR_REG_MR always requires changing the entity size with UMR */
 838         if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
 839                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 840         if (MLX5_CAP_GEN(mdev, sho)) {
 841                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 842                 /* At this stage no support for signature handover */
 843                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 844                                       IB_PROT_T10DIF_TYPE_2 |
 845                                       IB_PROT_T10DIF_TYPE_3;
 846                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 847                                        IB_GUARD_T10DIF_CSUM;
 848         }
 849         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 850                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 851
 852         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 853                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 854                         /* Legacy bit to support old userspace libraries */
 855                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 856                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 857                 }
 858
 859                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 860                         props->raw_packet_caps |=
 861                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 862
 863                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
 864                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 865                         if (max_tso) {
 866                                 resp.tso_caps.max_tso = 1 << max_tso;
 867                                 resp.tso_caps.supported_qpts |=
 868                                         1 << IB_QPT_RAW_PACKET;
 869                                 resp.response_length += sizeof(resp.tso_caps);
 870                         }
 871                 }
 872
 873                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
 874                         resp.rss_caps.rx_hash_function =
 875                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 876                         resp.rss_caps.rx_hash_fields_mask =
 877                                                 MLX5_RX_HASH_SRC_IPV4 |
 878                                                 MLX5_RX_HASH_DST_IPV4 |
 879                                                 MLX5_RX_HASH_SRC_IPV6 |
 880                                                 MLX5_RX_HASH_DST_IPV6 |
 881                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 882                                                 MLX5_RX_HASH_DST_PORT_TCP |
 883                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 884                                                 MLX5_RX_HASH_DST_PORT_UDP |
 885                                                 MLX5_RX_HASH_INNER;
 886                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 887                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 888                                 resp.rss_caps.rx_hash_fields_mask |=
 889                                         MLX5_RX_HASH_IPSEC_SPI;
 890                         resp.response_length += sizeof(resp.rss_caps);
 891                 }
 892         } else {
 893                 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
 894                         resp.response_length += sizeof(resp.tso_caps);
 895                 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
 896                         resp.response_length += sizeof(resp.rss_caps);
 897         }
 898
 899         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 900                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 901                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 902         }
 903
 904         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 905             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 906             raw_support)
 907                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 908
 909         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 910             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 911                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 912
 913         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 914             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 915             raw_support) {
 916                 /* Legacy bit to support old userspace libraries */
 917                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 918                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 919         }
 920
 921         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 922                 props->max_dm_size =
 923                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 924         }
 925
 926         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 927                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 928
 929         if (MLX5_CAP_GEN(mdev, end_pad))
 930                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 931
 932         props->vendor_part_id      = mdev->pdev->device;
 933         props->hw_ver              = mdev->pdev->revision;
 934
 935         props->max_mr_size         = ~0ull;
 936         props->page_size_cap       = ~(min_page_size - 1);
 937         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 938         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 939         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 940                      sizeof(struct mlx5_wqe_data_seg);
 941         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 942         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 943                      sizeof(struct mlx5_wqe_raddr_seg)) /
 944                 sizeof(struct mlx5_wqe_data_seg);
 945         props->max_send_sge = max_sq_sg;
 946         props->max_recv_sge = max_rq_sg;
 947         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 948         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 949         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 950         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 951         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 952         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 953         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 954         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 955         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 956         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 957         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 958         props->max_srq_sge         = max_rq_sg - 1;
 959         props->max_fast_reg_page_list_len =
 960                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 961         props->max_pi_fast_reg_page_list_len =
 962                 props->max_fast_reg_page_list_len / 2;
 963         props->max_sgl_rd =
 964                 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
 965         get_atomic_caps_qp(dev, props);
 966         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 967         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 968         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 969         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 970                                            props->max_mcast_grp;
 971         props->max_ah = INT_MAX;
 972         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 973         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 974
 975         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
 976                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
 977                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 978                 props->odp_caps = dev->odp_caps;
 979                 if (!uhw) {
 980                         /* ODP for kernel QPs is not implemented for receive
 981                          * WQEs and SRQ WQEs
 982                          */
 983                         props->odp_caps.per_transport_caps.rc_odp_caps &=
 984                                 ~(IB_ODP_SUPPORT_READ |
 985                                   IB_ODP_SUPPORT_SRQ_RECV);
 986                         props->odp_caps.per_transport_caps.uc_odp_caps &=
 987                                 ~(IB_ODP_SUPPORT_READ |
 988                                   IB_ODP_SUPPORT_SRQ_RECV);
 989                         props->odp_caps.per_transport_caps.ud_odp_caps &=
 990                                 ~(IB_ODP_SUPPORT_READ |
 991                                   IB_ODP_SUPPORT_SRQ_RECV);
 992                         props->odp_caps.per_transport_caps.xrc_odp_caps &=
 993                                 ~(IB_ODP_SUPPORT_READ |
 994                                   IB_ODP_SUPPORT_SRQ_RECV);
 995                 }
 996         }
 997
 998         if (MLX5_CAP_GEN(mdev, cd))
 999                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1000
1001         if (mlx5_core_is_vf(mdev))
1002                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1003
1004         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1005             IB_LINK_LAYER_ETHERNET && raw_support) {
1006                 props->rss_caps.max_rwq_indirection_tables =
1007                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1008                 props->rss_caps.max_rwq_indirection_table_size =
1009                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1010                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1011                 props->max_wq_type_rq =
1012                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1013         }
1014
1015         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1016                 props->tm_caps.max_num_tags =
1017                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1018                 props->tm_caps.max_ops =
1019                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1020                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1021         }
1022
1023         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1024             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1025                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1026                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1027         }
1028
1029         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1030                 props->cq_caps.max_cq_moderation_count =
1031                                                 MLX5_MAX_CQ_COUNT;
1032                 props->cq_caps.max_cq_moderation_period =
1033                                                 MLX5_MAX_CQ_PERIOD;
1034         }
1035
1036         if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1037                 resp.response_length += sizeof(resp.cqe_comp_caps);
1038
1039                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1040                         resp.cqe_comp_caps.max_num =
1041                                 MLX5_CAP_GEN(dev->mdev,
1042                                              cqe_compression_max_num);
1043
1044                         resp.cqe_comp_caps.supported_format =
1045                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1046                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1047
1048                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1049                                 resp.cqe_comp_caps.supported_format |=
1050                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1051                 }
1052         }
1053
1054         if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1055             raw_support) {
1056                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1057                     MLX5_CAP_GEN(mdev, qos)) {
1058                         resp.packet_pacing_caps.qp_rate_limit_max =
1059                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1060                         resp.packet_pacing_caps.qp_rate_limit_min =
1061                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1062                         resp.packet_pacing_caps.supported_qpts |=
1063                                 1 << IB_QPT_RAW_PACKET;
1064                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1065                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1066                                 resp.packet_pacing_caps.cap_flags |=
1067                                         MLX5_IB_PP_SUPPORT_BURST;
1068                 }
1069                 resp.response_length += sizeof(resp.packet_pacing_caps);
1070         }
1071
1072         if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1073             uhw_outlen) {
1074                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1075                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1076                                 MLX5_IB_ALLOW_MPW;
1077
1078                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1079                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1080                                 MLX5_IB_SUPPORT_EMPW;
1081
1082                 resp.response_length +=
1083                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1084         }
1085
1086         if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1087                 resp.response_length += sizeof(resp.flags);
1088
1089                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1090                         resp.flags |=
1091                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1092
1093                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1094                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1095                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1096                         resp.flags |=
1097                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1098
1099                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1100         }
1101
1102         if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1103                 resp.response_length += sizeof(resp.sw_parsing_caps);
1104                 if (MLX5_CAP_ETH(mdev, swp)) {
1105                         resp.sw_parsing_caps.sw_parsing_offloads |=
1106                                 MLX5_IB_SW_PARSING;
1107
1108                         if (MLX5_CAP_ETH(mdev, swp_csum))
1109                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1110                                         MLX5_IB_SW_PARSING_CSUM;
1111
1112                         if (MLX5_CAP_ETH(mdev, swp_lso))
1113                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1114                                         MLX5_IB_SW_PARSING_LSO;
1115
1116                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1117                                 resp.sw_parsing_caps.supported_qpts =
1118                                         BIT(IB_QPT_RAW_PACKET);
1119                 }
1120         }
1121
1122         if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1123             raw_support) {
1124                 resp.response_length += sizeof(resp.striding_rq_caps);
1125                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1126                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1127                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1128                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1129                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1130                         if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1131                                 resp.striding_rq_caps
1132                                         .min_single_wqe_log_num_of_strides =
1133                                         MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1134                         else
1135                                 resp.striding_rq_caps
1136                                         .min_single_wqe_log_num_of_strides =
1137                                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1138                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1139                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1140                         resp.striding_rq_caps.supported_qpts =
1141                                 BIT(IB_QPT_RAW_PACKET);
1142                 }
1143         }
1144
1145         if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1146                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1147                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1148                         resp.tunnel_offloads_caps |=
1149                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1150                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1151                         resp.tunnel_offloads_caps |=
1152                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1153                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1154                         resp.tunnel_offloads_caps |=
1155                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1156                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1157                         resp.tunnel_offloads_caps |=
1158                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1159                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1160                         resp.tunnel_offloads_caps |=
1161                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1162         }
1163
1164         if (uhw_outlen) {
1165                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1166
1167                 if (err)
1168                         return err;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1175                                    u8 *ib_width)
1176 {
1177         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1178
1179         if (active_width & MLX5_PTYS_WIDTH_1X)
1180                 *ib_width = IB_WIDTH_1X;
1181         else if (active_width & MLX5_PTYS_WIDTH_2X)
1182                 *ib_width = IB_WIDTH_2X;
1183         else if (active_width & MLX5_PTYS_WIDTH_4X)
1184                 *ib_width = IB_WIDTH_4X;
1185         else if (active_width & MLX5_PTYS_WIDTH_8X)
1186                 *ib_width = IB_WIDTH_8X;
1187         else if (active_width & MLX5_PTYS_WIDTH_12X)
1188                 *ib_width = IB_WIDTH_12X;
1189         else {
1190                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1191                             active_width);
1192                 *ib_width = IB_WIDTH_4X;
1193         }
1194
1195         return;
1196 }
1197
1198 static int mlx5_mtu_to_ib_mtu(int mtu)
1199 {
1200         switch (mtu) {
1201         case 256: return 1;
1202         case 512: return 2;
1203         case 1024: return 3;
1204         case 2048: return 4;
1205         case 4096: return 5;
1206         default:
1207                 pr_warn("invalid mtu\n");
1208                 return -1;
1209         }
1210 }
1211
1212 enum ib_max_vl_num {
1213         __IB_MAX_VL_0           = 1,
1214         __IB_MAX_VL_0_1         = 2,
1215         __IB_MAX_VL_0_3         = 3,
1216         __IB_MAX_VL_0_7         = 4,
1217         __IB_MAX_VL_0_14        = 5,
1218 };
1219
1220 enum mlx5_vl_hw_cap {
1221         MLX5_VL_HW_0    = 1,
1222         MLX5_VL_HW_0_1  = 2,
1223         MLX5_VL_HW_0_2  = 3,
1224         MLX5_VL_HW_0_3  = 4,
1225         MLX5_VL_HW_0_4  = 5,
1226         MLX5_VL_HW_0_5  = 6,
1227         MLX5_VL_HW_0_6  = 7,
1228         MLX5_VL_HW_0_7  = 8,
1229         MLX5_VL_HW_0_14 = 15
1230 };
1231
1232 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1233                                 u8 *max_vl_num)
1234 {
1235         switch (vl_hw_cap) {
1236         case MLX5_VL_HW_0:
1237                 *max_vl_num = __IB_MAX_VL_0;
1238                 break;
1239         case MLX5_VL_HW_0_1:
1240                 *max_vl_num = __IB_MAX_VL_0_1;
1241                 break;
1242         case MLX5_VL_HW_0_3:
1243                 *max_vl_num = __IB_MAX_VL_0_3;
1244                 break;
1245         case MLX5_VL_HW_0_7:
1246                 *max_vl_num = __IB_MAX_VL_0_7;
1247                 break;
1248         case MLX5_VL_HW_0_14:
1249                 *max_vl_num = __IB_MAX_VL_0_14;
1250                 break;
1251
1252         default:
1253                 return -EINVAL;
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1260                                struct ib_port_attr *props)
1261 {
1262         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1263         struct mlx5_core_dev *mdev = dev->mdev;
1264         struct mlx5_hca_vport_context *rep;
1265         u16 max_mtu;
1266         u16 oper_mtu;
1267         int err;
1268         u16 ib_link_width_oper;
1269         u8 vl_hw_cap;
1270
1271         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1272         if (!rep) {
1273                 err = -ENOMEM;
1274                 goto out;
1275         }
1276
1277         /* props being zeroed by the caller, avoid zeroing it here */
1278
1279         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1280         if (err)
1281                 goto out;
1282
1283         props->lid              = rep->lid;
1284         props->lmc              = rep->lmc;
1285         props->sm_lid           = rep->sm_lid;
1286         props->sm_sl            = rep->sm_sl;
1287         props->state            = rep->vport_state;
1288         props->phys_state       = rep->port_physical_state;
1289         props->port_cap_flags   = rep->cap_mask1;
1290         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1291         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1292         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1293         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1294         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1295         props->subnet_timeout   = rep->subnet_timeout;
1296         props->init_type_reply  = rep->init_type_reply;
1297
1298         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1299                 props->port_cap_flags2 = rep->cap_mask2;
1300
1301         err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1302                                       &props->active_speed, port);
1303         if (err)
1304                 goto out;
1305
1306         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1307
1308         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1309
1310         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1311
1312         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1313
1314         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1315
1316         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1317         if (err)
1318                 goto out;
1319
1320         err = translate_max_vl_num(ibdev, vl_hw_cap,
1321                                    &props->max_vl_num);
1322 out:
1323         kfree(rep);
1324         return err;
1325 }
1326
1327 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1328                        struct ib_port_attr *props)
1329 {
1330         unsigned int count;
1331         int ret;
1332
1333         switch (mlx5_get_vport_access_method(ibdev)) {
1334         case MLX5_VPORT_ACCESS_METHOD_MAD:
1335                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1336                 break;
1337
1338         case MLX5_VPORT_ACCESS_METHOD_HCA:
1339                 ret = mlx5_query_hca_port(ibdev, port, props);
1340                 break;
1341
1342         case MLX5_VPORT_ACCESS_METHOD_NIC:
1343                 ret = mlx5_query_port_roce(ibdev, port, props);
1344                 break;
1345
1346         default:
1347                 ret = -EINVAL;
1348         }
1349
1350         if (!ret && props) {
1351                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1352                 struct mlx5_core_dev *mdev;
1353                 bool put_mdev = true;
1354
1355                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1356                 if (!mdev) {
1357                         /* If the port isn't affiliated yet query the master.
1358                          * The master and slave will have the same values.
1359                          */
1360                         mdev = dev->mdev;
1361                         port = 1;
1362                         put_mdev = false;
1363                 }
1364                 count = mlx5_core_reserved_gids_count(mdev);
1365                 if (put_mdev)
1366                         mlx5_ib_put_native_port_mdev(dev, port);
1367                 props->gid_tbl_len -= count;
1368         }
1369         return ret;
1370 }
1371
1372 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1373                                   struct ib_port_attr *props)
1374 {
1375         int ret;
1376
1377         /* Only link layer == ethernet is valid for representors
1378          * and we always use port 1
1379          */
1380         ret = mlx5_query_port_roce(ibdev, port, props);
1381         if (ret || !props)
1382                 return ret;
1383
1384         /* We don't support GIDS */
1385         props->gid_tbl_len = 0;
1386
1387         return ret;
1388 }
1389
1390 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1391                              union ib_gid *gid)
1392 {
1393         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394         struct mlx5_core_dev *mdev = dev->mdev;
1395
1396         switch (mlx5_get_vport_access_method(ibdev)) {
1397         case MLX5_VPORT_ACCESS_METHOD_MAD:
1398                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1399
1400         case MLX5_VPORT_ACCESS_METHOD_HCA:
1401                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1402
1403         default:
1404                 return -EINVAL;
1405         }
1406
1407 }
1408
1409 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1410                                    u16 index, u16 *pkey)
1411 {
1412         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1413         struct mlx5_core_dev *mdev;
1414         bool put_mdev = true;
1415         u8 mdev_port_num;
1416         int err;
1417
1418         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1419         if (!mdev) {
1420                 /* The port isn't affiliated yet, get the PKey from the master
1421                  * port. For RoCE the PKey tables will be the same.
1422                  */
1423                 put_mdev = false;
1424                 mdev = dev->mdev;
1425                 mdev_port_num = 1;
1426         }
1427
1428         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1429                                         index, pkey);
1430         if (put_mdev)
1431                 mlx5_ib_put_native_port_mdev(dev, port);
1432
1433         return err;
1434 }
1435
1436 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1437                               u16 *pkey)
1438 {
1439         switch (mlx5_get_vport_access_method(ibdev)) {
1440         case MLX5_VPORT_ACCESS_METHOD_MAD:
1441                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1442
1443         case MLX5_VPORT_ACCESS_METHOD_HCA:
1444         case MLX5_VPORT_ACCESS_METHOD_NIC:
1445                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1446         default:
1447                 return -EINVAL;
1448         }
1449 }
1450
1451 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1452                                  struct ib_device_modify *props)
1453 {
1454         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455         struct mlx5_reg_node_desc in;
1456         struct mlx5_reg_node_desc out;
1457         int err;
1458
1459         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1460                 return -EOPNOTSUPP;
1461
1462         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1463                 return 0;
1464
1465         /*
1466          * If possible, pass node desc to FW, so it can generate
1467          * a 144 trap.  If cmd fails, just ignore.
1468          */
1469         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1470         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1471                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1472         if (err)
1473                 return err;
1474
1475         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1476
1477         return err;
1478 }
1479
1480 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1481                                 u32 value)
1482 {
1483         struct mlx5_hca_vport_context ctx = {};
1484         struct mlx5_core_dev *mdev;
1485         u8 mdev_port_num;
1486         int err;
1487
1488         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1489         if (!mdev)
1490                 return -ENODEV;
1491
1492         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1493         if (err)
1494                 goto out;
1495
1496         if (~ctx.cap_mask1_perm & mask) {
1497                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1498                              mask, ctx.cap_mask1_perm);
1499                 err = -EINVAL;
1500                 goto out;
1501         }
1502
1503         ctx.cap_mask1 = value;
1504         ctx.cap_mask1_perm = mask;
1505         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1506                                                  0, &ctx);
1507
1508 out:
1509         mlx5_ib_put_native_port_mdev(dev, port_num);
1510
1511         return err;
1512 }
1513
1514 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1515                                struct ib_port_modify *props)
1516 {
1517         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1518         struct ib_port_attr attr;
1519         u32 tmp;
1520         int err;
1521         u32 change_mask;
1522         u32 value;
1523         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1524                       IB_LINK_LAYER_INFINIBAND);
1525
1526         /* CM layer calls ib_modify_port() regardless of the link layer. For
1527          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1528          */
1529         if (!is_ib)
1530                 return 0;
1531
1532         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1533                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1534                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1535                 return set_port_caps_atomic(dev, port, change_mask, value);
1536         }
1537
1538         mutex_lock(&dev->cap_mask_mutex);
1539
1540         err = ib_query_port(ibdev, port, &attr);
1541         if (err)
1542                 goto out;
1543
1544         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1545                 ~props->clr_port_cap_mask;
1546
1547         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1548
1549 out:
1550         mutex_unlock(&dev->cap_mask_mutex);
1551         return err;
1552 }
1553
1554 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1555 {
1556         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1557                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1558 }
1559
1560 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1561 {
1562         /* Large page with non 4k uar support might limit the dynamic size */
1563         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1564                 return MLX5_MIN_DYN_BFREGS;
1565
1566         return MLX5_MAX_DYN_BFREGS;
1567 }
1568
1569 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1570                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1571                              struct mlx5_bfreg_info *bfregi)
1572 {
1573         int uars_per_sys_page;
1574         int bfregs_per_sys_page;
1575         int ref_bfregs = req->total_num_bfregs;
1576
1577         if (req->total_num_bfregs == 0)
1578                 return -EINVAL;
1579
1580         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1581         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1582
1583         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1584                 return -ENOMEM;
1585
1586         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1587         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1588         /* This holds the required static allocation asked by the user */
1589         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1590         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1591                 return -EINVAL;
1592
1593         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1594         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1595         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1596         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1597
1598         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1599                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1600                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1601                     req->total_num_bfregs, bfregi->total_num_bfregs,
1602                     bfregi->num_sys_pages);
1603
1604         return 0;
1605 }
1606
1607 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1608 {
1609         struct mlx5_bfreg_info *bfregi;
1610         int err;
1611         int i;
1612
1613         bfregi = &context->bfregi;
1614         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1615                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1616                 if (err)
1617                         goto error;
1618
1619                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1620         }
1621
1622         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1623                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1624
1625         return 0;
1626
1627 error:
1628         for (--i; i >= 0; i--)
1629                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1630                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1631
1632         return err;
1633 }
1634
1635 static void deallocate_uars(struct mlx5_ib_dev *dev,
1636                             struct mlx5_ib_ucontext *context)
1637 {
1638         struct mlx5_bfreg_info *bfregi;
1639         int i;
1640
1641         bfregi = &context->bfregi;
1642         for (i = 0; i < bfregi->num_sys_pages; i++)
1643                 if (i < bfregi->num_static_sys_pages ||
1644                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1645                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1646 }
1647
1648 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1649 {
1650         int err = 0;
1651
1652         mutex_lock(&dev->lb.mutex);
1653         if (td)
1654                 dev->lb.user_td++;
1655         if (qp)
1656                 dev->lb.qps++;
1657
1658         if (dev->lb.user_td == 2 ||
1659             dev->lb.qps == 1) {
1660                 if (!dev->lb.enabled) {
1661                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1662                         dev->lb.enabled = true;
1663                 }
1664         }
1665
1666         mutex_unlock(&dev->lb.mutex);
1667
1668         return err;
1669 }
1670
1671 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1672 {
1673         mutex_lock(&dev->lb.mutex);
1674         if (td)
1675                 dev->lb.user_td--;
1676         if (qp)
1677                 dev->lb.qps--;
1678
1679         if (dev->lb.user_td == 1 &&
1680             dev->lb.qps == 0) {
1681                 if (dev->lb.enabled) {
1682                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1683                         dev->lb.enabled = false;
1684                 }
1685         }
1686
1687         mutex_unlock(&dev->lb.mutex);
1688 }
1689
1690 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1691                                           u16 uid)
1692 {
1693         int err;
1694
1695         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1696                 return 0;
1697
1698         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1699         if (err)
1700                 return err;
1701
1702         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1703             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1704              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1705                 return err;
1706
1707         return mlx5_ib_enable_lb(dev, true, false);
1708 }
1709
1710 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1711                                              u16 uid)
1712 {
1713         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1714                 return;
1715
1716         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1717
1718         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1719             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1720              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1721                 return;
1722
1723         mlx5_ib_disable_lb(dev, true, false);
1724 }
1725
1726 static int set_ucontext_resp(struct ib_ucontext *uctx,
1727                              struct mlx5_ib_alloc_ucontext_resp *resp)
1728 {
1729         struct ib_device *ibdev = uctx->device;
1730         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1731         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1732         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1733         int err;
1734
1735         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1736                 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1737                                               &resp->dump_fill_mkey);
1738                 if (err)
1739                         return err;
1740                 resp->comp_mask |=
1741                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1742         }
1743
1744         resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1745         if (dev->wc_support)
1746                 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1747                                                       log_bf_reg_size);
1748         resp->cache_line_size = cache_line_size();
1749         resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1750         resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1751         resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1752         resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1753         resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1754         resp->cqe_version = context->cqe_version;
1755         resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1756                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1757         resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1758                                         MLX5_CAP_GEN(dev->mdev,
1759                                                      num_of_uars_per_page) : 1;
1760
1761         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1762                                 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1763                 if (mlx5_get_flow_namespace(dev->mdev,
1764                                 MLX5_FLOW_NAMESPACE_EGRESS))
1765                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1766                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1767                                 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1768                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1769                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1770                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1771                 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1772                                 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1773                         resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1774                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1775         }
1776
1777         resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1778                         bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1779         resp->num_ports = dev->num_ports;
1780         resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1781                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1782
1783         if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1784                 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1785                 resp->eth_min_inline++;
1786         }
1787
1788         if (dev->mdev->clock_info)
1789                 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1790
1791         /*
1792          * We don't want to expose information from the PCI bar that is located
1793          * after 4096 bytes, so if the arch only supports larger pages, let's
1794          * pretend we don't support reading the HCA's core clock. This is also
1795          * forced by mmap function.
1796          */
1797         if (PAGE_SIZE <= 4096) {
1798                 resp->comp_mask |=
1799                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1800                 resp->hca_core_clock_offset =
1801                         offsetof(struct mlx5_init_seg,
1802                                  internal_timer_h) % PAGE_SIZE;
1803         }
1804
1805         if (MLX5_CAP_GEN(dev->mdev, ece_support))
1806                 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1807
1808         resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1809         return 0;
1810 }
1811
1812 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1813                                   struct ib_udata *udata)
1814 {
1815         struct ib_device *ibdev = uctx->device;
1816         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1817         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1818         struct mlx5_ib_alloc_ucontext_resp resp = {};
1819         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1820         struct mlx5_bfreg_info *bfregi;
1821         int ver;
1822         int err;
1823         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1824                                      max_cqe_version);
1825         bool lib_uar_4k;
1826         bool lib_uar_dyn;
1827
1828         if (!dev->ib_active)
1829                 return -EAGAIN;
1830
1831         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1832                 ver = 0;
1833         else if (udata->inlen >= min_req_v2)
1834                 ver = 2;
1835         else
1836                 return -EINVAL;
1837
1838         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1839         if (err)
1840                 return err;
1841
1842         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1843                 return -EOPNOTSUPP;
1844
1845         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1846                 return -EOPNOTSUPP;
1847
1848         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1849                                     MLX5_NON_FP_BFREGS_PER_UAR);
1850         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1851                 return -EINVAL;
1852
1853         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1854         lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1855         bfregi = &context->bfregi;
1856
1857         if (lib_uar_dyn) {
1858                 bfregi->lib_uar_dyn = lib_uar_dyn;
1859                 goto uar_done;
1860         }
1861
1862         /* updates req->total_num_bfregs */
1863         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1864         if (err)
1865                 goto out_ctx;
1866
1867         mutex_init(&bfregi->lock);
1868         bfregi->lib_uar_4k = lib_uar_4k;
1869         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1870                                 GFP_KERNEL);
1871         if (!bfregi->count) {
1872                 err = -ENOMEM;
1873                 goto out_ctx;
1874         }
1875
1876         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1877                                     sizeof(*bfregi->sys_pages),
1878                                     GFP_KERNEL);
1879         if (!bfregi->sys_pages) {
1880                 err = -ENOMEM;
1881                 goto out_count;
1882         }
1883
1884         err = allocate_uars(dev, context);
1885         if (err)
1886                 goto out_sys_pages;
1887
1888 uar_done:
1889         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1890                 err = mlx5_ib_devx_create(dev, true);
1891                 if (err < 0)
1892                         goto out_uars;
1893                 context->devx_uid = err;
1894         }
1895
1896         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1897                                              context->devx_uid);
1898         if (err)
1899                 goto out_devx;
1900
1901         INIT_LIST_HEAD(&context->db_page_list);
1902         mutex_init(&context->db_page_mutex);
1903
1904         context->cqe_version = min_t(__u8,
1905                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1906                                  req.max_cqe_version);
1907
1908         err = set_ucontext_resp(uctx, &resp);
1909         if (err)
1910                 goto out_mdev;
1911
1912         resp.response_length = min(udata->outlen, sizeof(resp));
1913         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1914         if (err)
1915                 goto out_mdev;
1916
1917         bfregi->ver = ver;
1918         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1919         context->lib_caps = req.lib_caps;
1920         print_lib_caps(dev, context->lib_caps);
1921
1922         if (mlx5_ib_lag_should_assign_affinity(dev)) {
1923                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1924
1925                 atomic_set(&context->tx_port_affinity,
1926                            atomic_add_return(
1927                                    1, &dev->port[port].roce.tx_port_affinity));
1928         }
1929
1930         return 0;
1931
1932 out_mdev:
1933         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1934 out_devx:
1935         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1936                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1937
1938 out_uars:
1939         deallocate_uars(dev, context);
1940
1941 out_sys_pages:
1942         kfree(bfregi->sys_pages);
1943
1944 out_count:
1945         kfree(bfregi->count);
1946
1947 out_ctx:
1948         return err;
1949 }
1950
1951 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1952                                   struct uverbs_attr_bundle *attrs)
1953 {
1954         struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1955         int ret;
1956
1957         ret = set_ucontext_resp(ibcontext, &uctx_resp);
1958         if (ret)
1959                 return ret;
1960
1961         uctx_resp.response_length =
1962                 min_t(size_t,
1963                       uverbs_attr_get_len(attrs,
1964                                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1965                       sizeof(uctx_resp));
1966
1967         ret = uverbs_copy_to_struct_or_zero(attrs,
1968                                         MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1969                                         &uctx_resp,
1970                                         sizeof(uctx_resp));
1971         return ret;
1972 }
1973
1974 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1975 {
1976         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1977         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1978         struct mlx5_bfreg_info *bfregi;
1979
1980         bfregi = &context->bfregi;
1981         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1982
1983         if (context->devx_uid)
1984                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1985
1986         deallocate_uars(dev, context);
1987         kfree(bfregi->sys_pages);
1988         kfree(bfregi->count);
1989 }
1990
1991 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1992                                  int uar_idx)
1993 {
1994         int fw_uars_per_page;
1995
1996         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1997
1998         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1999 }
2000
2001 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2002                                  int uar_idx)
2003 {
2004         unsigned int fw_uars_per_page;
2005
2006         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2007                                 MLX5_UARS_IN_PAGE : 1;
2008
2009         return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2010 }
2011
2012 static int get_command(unsigned long offset)
2013 {
2014         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2015 }
2016
2017 static int get_arg(unsigned long offset)
2018 {
2019         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2020 }
2021
2022 static int get_index(unsigned long offset)
2023 {
2024         return get_arg(offset);
2025 }
2026
2027 /* Index resides in an extra byte to enable larger values than 255 */
2028 static int get_extended_index(unsigned long offset)
2029 {
2030         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2031 }
2032
2033
2034 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2035 {
2036 }
2037
2038 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2039 {
2040         switch (cmd) {
2041         case MLX5_IB_MMAP_WC_PAGE:
2042                 return "WC";
2043         case MLX5_IB_MMAP_REGULAR_PAGE:
2044                 return "best effort WC";
2045         case MLX5_IB_MMAP_NC_PAGE:
2046                 return "NC";
2047         case MLX5_IB_MMAP_DEVICE_MEM:
2048                 return "Device Memory";
2049         default:
2050                 return NULL;
2051         }
2052 }
2053
2054 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2055                                         struct vm_area_struct *vma,
2056                                         struct mlx5_ib_ucontext *context)
2057 {
2058         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2059             !(vma->vm_flags & VM_SHARED))
2060                 return -EINVAL;
2061
2062         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2063                 return -EOPNOTSUPP;
2064
2065         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2066                 return -EPERM;
2067         vma->vm_flags &= ~VM_MAYWRITE;
2068
2069         if (!dev->mdev->clock_info)
2070                 return -EOPNOTSUPP;
2071
2072         return vm_insert_page(vma, vma->vm_start,
2073                               virt_to_page(dev->mdev->clock_info));
2074 }
2075
2076 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2077 {
2078         struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2079         struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2080         struct mlx5_var_table *var_table = &dev->var_table;
2081         struct mlx5_ib_dm *mdm;
2082
2083         switch (mentry->mmap_flag) {
2084         case MLX5_IB_MMAP_TYPE_MEMIC:
2085                 mdm = container_of(mentry, struct mlx5_ib_dm, mentry);
2086                 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr,
2087                                        mdm->size);
2088                 kfree(mdm);
2089                 break;
2090         case MLX5_IB_MMAP_TYPE_VAR:
2091                 mutex_lock(&var_table->bitmap_lock);
2092                 clear_bit(mentry->page_idx, var_table->bitmap);
2093                 mutex_unlock(&var_table->bitmap_lock);
2094                 kfree(mentry);
2095                 break;
2096         case MLX5_IB_MMAP_TYPE_UAR_WC:
2097         case MLX5_IB_MMAP_TYPE_UAR_NC:
2098                 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2099                 kfree(mentry);
2100                 break;
2101         default:
2102                 WARN_ON(true);
2103         }
2104 }
2105
2106 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2107                     struct vm_area_struct *vma,
2108                     struct mlx5_ib_ucontext *context)
2109 {
2110         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2111         int err;
2112         unsigned long idx;
2113         phys_addr_t pfn;
2114         pgprot_t prot;
2115         u32 bfreg_dyn_idx = 0;
2116         u32 uar_index;
2117         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2118         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2119                                 bfregi->num_static_sys_pages;
2120
2121         if (bfregi->lib_uar_dyn)
2122                 return -EINVAL;
2123
2124         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2125                 return -EINVAL;
2126
2127         if (dyn_uar)
2128                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2129         else
2130                 idx = get_index(vma->vm_pgoff);
2131
2132         if (idx >= max_valid_idx) {
2133                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2134                              idx, max_valid_idx);
2135                 return -EINVAL;
2136         }
2137
2138         switch (cmd) {
2139         case MLX5_IB_MMAP_WC_PAGE:
2140         case MLX5_IB_MMAP_ALLOC_WC:
2141         case MLX5_IB_MMAP_REGULAR_PAGE:
2142                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2143                 prot = pgprot_writecombine(vma->vm_page_prot);
2144                 break;
2145         case MLX5_IB_MMAP_NC_PAGE:
2146                 prot = pgprot_noncached(vma->vm_page_prot);
2147                 break;
2148         default:
2149                 return -EINVAL;
2150         }
2151
2152         if (dyn_uar) {
2153                 int uars_per_page;
2154
2155                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2156                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2157                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2158                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2159                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2160                         return -EINVAL;
2161                 }
2162
2163                 mutex_lock(&bfregi->lock);
2164                 /* Fail if uar already allocated, first bfreg index of each
2165                  * page holds its count.
2166                  */
2167                 if (bfregi->count[bfreg_dyn_idx]) {
2168                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2169                         mutex_unlock(&bfregi->lock);
2170                         return -EINVAL;
2171                 }
2172
2173                 bfregi->count[bfreg_dyn_idx]++;
2174                 mutex_unlock(&bfregi->lock);
2175
2176                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2177                 if (err) {
2178                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2179                         goto free_bfreg;
2180                 }
2181         } else {
2182                 uar_index = bfregi->sys_pages[idx];
2183         }
2184
2185         pfn = uar_index2pfn(dev, uar_index);
2186         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2187
2188         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2189                                 prot, NULL);
2190         if (err) {
2191                 mlx5_ib_err(dev,
2192                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2193                             err, mmap_cmd2str(cmd));
2194                 goto err;
2195         }
2196
2197         if (dyn_uar)
2198                 bfregi->sys_pages[idx] = uar_index;
2199         return 0;
2200
2201 err:
2202         if (!dyn_uar)
2203                 return err;
2204
2205         mlx5_cmd_free_uar(dev->mdev, idx);
2206
2207 free_bfreg:
2208         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2209
2210         return err;
2211 }
2212
2213 static int add_dm_mmap_entry(struct ib_ucontext *context,
2214                              struct mlx5_ib_dm *mdm,
2215                              u64 address)
2216 {
2217         mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC;
2218         mdm->mentry.address = address;
2219         return rdma_user_mmap_entry_insert_range(
2220                         context, &mdm->mentry.rdma_entry,
2221                         mdm->size,
2222                         MLX5_IB_MMAP_DEVICE_MEM << 16,
2223                         (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1);
2224 }
2225
2226 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2227 {
2228         unsigned long idx;
2229         u8 command;
2230
2231         command = get_command(vma->vm_pgoff);
2232         idx = get_extended_index(vma->vm_pgoff);
2233
2234         return (command << 16 | idx);
2235 }
2236
2237 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2238                                struct vm_area_struct *vma,
2239                                struct ib_ucontext *ucontext)
2240 {
2241         struct mlx5_user_mmap_entry *mentry;
2242         struct rdma_user_mmap_entry *entry;
2243         unsigned long pgoff;
2244         pgprot_t prot;
2245         phys_addr_t pfn;
2246         int ret;
2247
2248         pgoff = mlx5_vma_to_pgoff(vma);
2249         entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2250         if (!entry)
2251                 return -EINVAL;
2252
2253         mentry = to_mmmap(entry);
2254         pfn = (mentry->address >> PAGE_SHIFT);
2255         if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2256             mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2257                 prot = pgprot_noncached(vma->vm_page_prot);
2258         else
2259                 prot = pgprot_writecombine(vma->vm_page_prot);
2260         ret = rdma_user_mmap_io(ucontext, vma, pfn,
2261                                 entry->npages * PAGE_SIZE,
2262                                 prot,
2263                                 entry);
2264         rdma_user_mmap_entry_put(&mentry->rdma_entry);
2265         return ret;
2266 }
2267
2268 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2269 {
2270         u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2271         u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2272
2273         return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2274                 (index & 0xFF)) << PAGE_SHIFT;
2275 }
2276
2277 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2278 {
2279         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2280         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2281         unsigned long command;
2282         phys_addr_t pfn;
2283
2284         command = get_command(vma->vm_pgoff);
2285         switch (command) {
2286         case MLX5_IB_MMAP_WC_PAGE:
2287         case MLX5_IB_MMAP_ALLOC_WC:
2288                 if (!dev->wc_support)
2289                         return -EPERM;
2290                 fallthrough;
2291         case MLX5_IB_MMAP_NC_PAGE:
2292         case MLX5_IB_MMAP_REGULAR_PAGE:
2293                 return uar_mmap(dev, command, vma, context);
2294
2295         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2296                 return -ENOSYS;
2297
2298         case MLX5_IB_MMAP_CORE_CLOCK:
2299                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2300                         return -EINVAL;
2301
2302                 if (vma->vm_flags & VM_WRITE)
2303                         return -EPERM;
2304                 vma->vm_flags &= ~VM_MAYWRITE;
2305
2306                 /* Don't expose to user-space information it shouldn't have */
2307                 if (PAGE_SIZE > 4096)
2308                         return -EOPNOTSUPP;
2309
2310                 pfn = (dev->mdev->iseg_base +
2311                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2312                         PAGE_SHIFT;
2313                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2314                                          PAGE_SIZE,
2315                                          pgprot_noncached(vma->vm_page_prot),
2316                                          NULL);
2317         case MLX5_IB_MMAP_CLOCK_INFO:
2318                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2319
2320         default:
2321                 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2322         }
2323
2324         return 0;
2325 }
2326
2327 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2328                                         u32 type)
2329 {
2330         switch (type) {
2331         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2332                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2333                         return -EOPNOTSUPP;
2334                 break;
2335         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2336         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2337                 if (!capable(CAP_SYS_RAWIO) ||
2338                     !capable(CAP_NET_RAW))
2339                         return -EPERM;
2340
2341                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2342                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) ||
2343                       MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) ||
2344                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2)))
2345                         return -EOPNOTSUPP;
2346                 break;
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2353                                  struct mlx5_ib_dm *dm,
2354                                  struct ib_dm_alloc_attr *attr,
2355                                  struct uverbs_attr_bundle *attrs)
2356 {
2357         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2358         u64 start_offset;
2359         u16 page_idx;
2360         int err;
2361         u64 address;
2362
2363         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2364
2365         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2366                                    dm->size, attr->alignment);
2367         if (err)
2368                 return err;
2369
2370         address = dm->dev_addr & PAGE_MASK;
2371         err = add_dm_mmap_entry(ctx, dm, address);
2372         if (err)
2373                 goto err_dealloc;
2374
2375         page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF;
2376         err = uverbs_copy_to(attrs,
2377                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2378                              &page_idx,
2379                              sizeof(page_idx));
2380         if (err)
2381                 goto err_copy;
2382
2383         start_offset = dm->dev_addr & ~PAGE_MASK;
2384         err = uverbs_copy_to(attrs,
2385                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2386                              &start_offset, sizeof(start_offset));
2387         if (err)
2388                 goto err_copy;
2389
2390         return 0;
2391
2392 err_copy:
2393         rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2394 err_dealloc:
2395         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2396
2397         return err;
2398 }
2399
2400 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2401                                   struct mlx5_ib_dm *dm,
2402                                   struct ib_dm_alloc_attr *attr,
2403                                   struct uverbs_attr_bundle *attrs,
2404                                   int type)
2405 {
2406         struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2407         u64 act_size;
2408         int err;
2409
2410         /* Allocation size must a multiple of the basic block size
2411          * and a power of 2.
2412          */
2413         act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2414         act_size = roundup_pow_of_two(act_size);
2415
2416         dm->size = act_size;
2417         err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment,
2418                                    to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2419                                    &dm->icm_dm.obj_id);
2420         if (err)
2421                 return err;
2422
2423         err = uverbs_copy_to(attrs,
2424                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2425                              &dm->dev_addr, sizeof(dm->dev_addr));
2426         if (err)
2427                 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2428                                        to_mucontext(ctx)->devx_uid, dm->dev_addr,
2429                                        dm->icm_dm.obj_id);
2430
2431         return err;
2432 }
2433
2434 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2435                                struct ib_ucontext *context,
2436                                struct ib_dm_alloc_attr *attr,
2437                                struct uverbs_attr_bundle *attrs)
2438 {
2439         struct mlx5_ib_dm *dm;
2440         enum mlx5_ib_uapi_dm_type type;
2441         int err;
2442
2443         err = uverbs_get_const_default(&type, attrs,
2444                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2445                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2446         if (err)
2447                 return ERR_PTR(err);
2448
2449         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2450                     type, attr->length, attr->alignment);
2451
2452         err = check_dm_type_support(to_mdev(ibdev), type);
2453         if (err)
2454                 return ERR_PTR(err);
2455
2456         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2457         if (!dm)
2458                 return ERR_PTR(-ENOMEM);
2459
2460         dm->type = type;
2461
2462         switch (type) {
2463         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2464                 err = handle_alloc_dm_memic(context, dm,
2465                                             attr,
2466                                             attrs);
2467                 break;
2468         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2469                 err = handle_alloc_dm_sw_icm(context, dm,
2470                                              attr, attrs,
2471                                              MLX5_SW_ICM_TYPE_STEERING);
2472                 break;
2473         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2474                 err = handle_alloc_dm_sw_icm(context, dm,
2475                                              attr, attrs,
2476                                              MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2477                 break;
2478         default:
2479                 err = -EOPNOTSUPP;
2480         }
2481
2482         if (err)
2483                 goto err_free;
2484
2485         return &dm->ibdm;
2486
2487 err_free:
2488         kfree(dm);
2489         return ERR_PTR(err);
2490 }
2491
2492 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2493 {
2494         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2495                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2496         struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2497         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2498         int ret;
2499
2500         switch (dm->type) {
2501         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2502                 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry);
2503                 return 0;
2504         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2505                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2506                                              dm->size, ctx->devx_uid, dm->dev_addr,
2507                                              dm->icm_dm.obj_id);
2508                 if (ret)
2509                         return ret;
2510                 break;
2511         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2512                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2513                                              dm->size, ctx->devx_uid, dm->dev_addr,
2514                                              dm->icm_dm.obj_id);
2515                 if (ret)
2516                         return ret;
2517                 break;
2518         default:
2519                 return -EOPNOTSUPP;
2520         }
2521
2522         kfree(dm);
2523
2524         return 0;
2525 }
2526
2527 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2528 {
2529         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2530         struct ib_device *ibdev = ibpd->device;
2531         struct mlx5_ib_alloc_pd_resp resp;
2532         int err;
2533         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2534         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2535         u16 uid = 0;
2536         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2537                 udata, struct mlx5_ib_ucontext, ibucontext);
2538
2539         uid = context ? context->devx_uid : 0;
2540         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2541         MLX5_SET(alloc_pd_in, in, uid, uid);
2542         err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2543         if (err)
2544                 return err;
2545
2546         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2547         pd->uid = uid;
2548         if (udata) {
2549                 resp.pdn = pd->pdn;
2550                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2551                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2552                         return -EFAULT;
2553                 }
2554         }
2555
2556         return 0;
2557 }
2558
2559 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2560 {
2561         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2562         struct mlx5_ib_pd *mpd = to_mpd(pd);
2563
2564         return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2565 }
2566
2567 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2568 {
2569         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2570         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2571         int err;
2572         u16 uid;
2573
2574         uid = ibqp->pd ?
2575                 to_mpd(ibqp->pd)->uid : 0;
2576
2577         if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2578                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2579                 return -EOPNOTSUPP;
2580         }
2581
2582         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2583         if (err)
2584                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2585                              ibqp->qp_num, gid->raw);
2586
2587         return err;
2588 }
2589
2590 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2591 {
2592         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2593         int err;
2594         u16 uid;
2595
2596         uid = ibqp->pd ?
2597                 to_mpd(ibqp->pd)->uid : 0;
2598         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2599         if (err)
2600                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2601                              ibqp->qp_num, gid->raw);
2602
2603         return err;
2604 }
2605
2606 static int init_node_data(struct mlx5_ib_dev *dev)
2607 {
2608         int err;
2609
2610         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2611         if (err)
2612                 return err;
2613
2614         dev->mdev->rev_id = dev->mdev->pdev->revision;
2615
2616         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2617 }
2618
2619 static ssize_t fw_pages_show(struct device *device,
2620                              struct device_attribute *attr, char *buf)
2621 {
2622         struct mlx5_ib_dev *dev =
2623                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2624
2625         return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2626 }
2627 static DEVICE_ATTR_RO(fw_pages);
2628
2629 static ssize_t reg_pages_show(struct device *device,
2630                               struct device_attribute *attr, char *buf)
2631 {
2632         struct mlx5_ib_dev *dev =
2633                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2634
2635         return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2636 }
2637 static DEVICE_ATTR_RO(reg_pages);
2638
2639 static ssize_t hca_type_show(struct device *device,
2640                              struct device_attribute *attr, char *buf)
2641 {
2642         struct mlx5_ib_dev *dev =
2643                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2644
2645         return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2646 }
2647 static DEVICE_ATTR_RO(hca_type);
2648
2649 static ssize_t hw_rev_show(struct device *device,
2650                            struct device_attribute *attr, char *buf)
2651 {
2652         struct mlx5_ib_dev *dev =
2653                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2654
2655         return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2656 }
2657 static DEVICE_ATTR_RO(hw_rev);
2658
2659 static ssize_t board_id_show(struct device *device,
2660                              struct device_attribute *attr, char *buf)
2661 {
2662         struct mlx5_ib_dev *dev =
2663                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2664
2665         return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2666                           dev->mdev->board_id);
2667 }
2668 static DEVICE_ATTR_RO(board_id);
2669
2670 static struct attribute *mlx5_class_attributes[] = {
2671         &dev_attr_hw_rev.attr,
2672         &dev_attr_hca_type.attr,
2673         &dev_attr_board_id.attr,
2674         &dev_attr_fw_pages.attr,
2675         &dev_attr_reg_pages.attr,
2676         NULL,
2677 };
2678
2679 static const struct attribute_group mlx5_attr_group = {
2680         .attrs = mlx5_class_attributes,
2681 };
2682
2683 static void pkey_change_handler(struct work_struct *work)
2684 {
2685         struct mlx5_ib_port_resources *ports =
2686                 container_of(work, struct mlx5_ib_port_resources,
2687                              pkey_change_work);
2688
2689         mlx5_ib_gsi_pkey_change(ports->gsi);
2690 }
2691
2692 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2693 {
2694         struct mlx5_ib_qp *mqp;
2695         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2696         struct mlx5_core_cq *mcq;
2697         struct list_head cq_armed_list;
2698         unsigned long flags_qp;
2699         unsigned long flags_cq;
2700         unsigned long flags;
2701
2702         INIT_LIST_HEAD(&cq_armed_list);
2703
2704         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2705         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2706         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2707                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2708                 if (mqp->sq.tail != mqp->sq.head) {
2709                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2710                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2711                         if (send_mcq->mcq.comp &&
2712                             mqp->ibqp.send_cq->comp_handler) {
2713                                 if (!send_mcq->mcq.reset_notify_added) {
2714                                         send_mcq->mcq.reset_notify_added = 1;
2715                                         list_add_tail(&send_mcq->mcq.reset_notify,
2716                                                       &cq_armed_list);
2717                                 }
2718                         }
2719                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2720                 }
2721                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2722                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2723                 /* no handling is needed for SRQ */
2724                 if (!mqp->ibqp.srq) {
2725                         if (mqp->rq.tail != mqp->rq.head) {
2726                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2727                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2728                                 if (recv_mcq->mcq.comp &&
2729                                     mqp->ibqp.recv_cq->comp_handler) {
2730                                         if (!recv_mcq->mcq.reset_notify_added) {
2731                                                 recv_mcq->mcq.reset_notify_added = 1;
2732                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2733                                                               &cq_armed_list);
2734                                         }
2735                                 }
2736                                 spin_unlock_irqrestore(&recv_mcq->lock,
2737                                                        flags_cq);
2738                         }
2739                 }
2740                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2741         }
2742         /*At that point all inflight post send were put to be executed as of we
2743          * lock/unlock above locks Now need to arm all involved CQs.
2744          */
2745         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2746                 mcq->comp(mcq, NULL);
2747         }
2748         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2749 }
2750
2751 static void delay_drop_handler(struct work_struct *work)
2752 {
2753         int err;
2754         struct mlx5_ib_delay_drop *delay_drop =
2755                 container_of(work, struct mlx5_ib_delay_drop,
2756                              delay_drop_work);
2757
2758         atomic_inc(&delay_drop->events_cnt);
2759
2760         mutex_lock(&delay_drop->lock);
2761         err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2762         if (err) {
2763                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2764                              delay_drop->timeout);
2765                 delay_drop->activate = false;
2766         }
2767         mutex_unlock(&delay_drop->lock);
2768 }
2769
2770 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2771                                  struct ib_event *ibev)
2772 {
2773         u8 port = (eqe->data.port.port >> 4) & 0xf;
2774
2775         switch (eqe->sub_type) {
2776         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2777                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2778                                             IB_LINK_LAYER_ETHERNET)
2779                         schedule_work(&ibdev->delay_drop.delay_drop_work);
2780                 break;
2781         default: /* do nothing */
2782                 return;
2783         }
2784 }
2785
2786 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2787                               struct ib_event *ibev)
2788 {
2789         u8 port = (eqe->data.port.port >> 4) & 0xf;
2790
2791         ibev->element.port_num = port;
2792
2793         switch (eqe->sub_type) {
2794         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2795         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2796         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2797                 /* In RoCE, port up/down events are handled in
2798                  * mlx5_netdev_event().
2799                  */
2800                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2801                                             IB_LINK_LAYER_ETHERNET)
2802                         return -EINVAL;
2803
2804                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2805                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2806                 break;
2807
2808         case MLX5_PORT_CHANGE_SUBTYPE_LID:
2809                 ibev->event = IB_EVENT_LID_CHANGE;
2810                 break;
2811
2812         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2813                 ibev->event = IB_EVENT_PKEY_CHANGE;
2814                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2815                 break;
2816
2817         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2818                 ibev->event = IB_EVENT_GID_CHANGE;
2819                 break;
2820
2821         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2822                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2823                 break;
2824         default:
2825                 return -EINVAL;
2826         }
2827
2828         return 0;
2829 }
2830
2831 static void mlx5_ib_handle_event(struct work_struct *_work)
2832 {
2833         struct mlx5_ib_event_work *work =
2834                 container_of(_work, struct mlx5_ib_event_work, work);
2835         struct mlx5_ib_dev *ibdev;
2836         struct ib_event ibev;
2837         bool fatal = false;
2838
2839         if (work->is_slave) {
2840                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2841                 if (!ibdev)
2842                         goto out;
2843         } else {
2844                 ibdev = work->dev;
2845         }
2846
2847         switch (work->event) {
2848         case MLX5_DEV_EVENT_SYS_ERROR:
2849                 ibev.event = IB_EVENT_DEVICE_FATAL;
2850                 mlx5_ib_handle_internal_error(ibdev);
2851                 ibev.element.port_num  = (u8)(unsigned long)work->param;
2852                 fatal = true;
2853                 break;
2854         case MLX5_EVENT_TYPE_PORT_CHANGE:
2855                 if (handle_port_change(ibdev, work->param, &ibev))
2856                         goto out;
2857                 break;
2858         case MLX5_EVENT_TYPE_GENERAL_EVENT:
2859                 handle_general_event(ibdev, work->param, &ibev);
2860                 fallthrough;
2861         default:
2862                 goto out;
2863         }
2864
2865         ibev.device = &ibdev->ib_dev;
2866
2867         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2868                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
2869                 goto out;
2870         }
2871
2872         if (ibdev->ib_active)
2873                 ib_dispatch_event(&ibev);
2874
2875         if (fatal)
2876                 ibdev->ib_active = false;
2877 out:
2878         kfree(work);
2879 }
2880
2881 static int mlx5_ib_event(struct notifier_block *nb,
2882                          unsigned long event, void *param)
2883 {
2884         struct mlx5_ib_event_work *work;
2885
2886         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2887         if (!work)
2888                 return NOTIFY_DONE;
2889
2890         INIT_WORK(&work->work, mlx5_ib_handle_event);
2891         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2892         work->is_slave = false;
2893         work->param = param;
2894         work->event = event;
2895
2896         queue_work(mlx5_ib_event_wq, &work->work);
2897
2898         return NOTIFY_OK;
2899 }
2900
2901 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2902                                     unsigned long event, void *param)
2903 {
2904         struct mlx5_ib_event_work *work;
2905
2906         work = kmalloc(sizeof(*work), GFP_ATOMIC);
2907         if (!work)
2908                 return NOTIFY_DONE;
2909
2910         INIT_WORK(&work->work, mlx5_ib_handle_event);
2911         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2912         work->is_slave = true;
2913         work->param = param;
2914         work->event = event;
2915         queue_work(mlx5_ib_event_wq, &work->work);
2916
2917         return NOTIFY_OK;
2918 }
2919
2920 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2921 {
2922         struct mlx5_hca_vport_context vport_ctx;
2923         int err;
2924         int port;
2925
2926         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
2927                 dev->mdev->port_caps[port - 1].has_smi = false;
2928                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2929                     MLX5_CAP_PORT_TYPE_IB) {
2930                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2931                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2932                                                                    port, 0,
2933                                                                    &vport_ctx);
2934                                 if (err) {
2935                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2936                                                     port, err);
2937                                         return err;
2938                                 }
2939                                 dev->mdev->port_caps[port - 1].has_smi =
2940                                         vport_ctx.has_smi;
2941                         } else {
2942                                 dev->mdev->port_caps[port - 1].has_smi = true;
2943                         }
2944                 }
2945         }
2946         return 0;
2947 }
2948
2949 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2950 {
2951         int port;
2952
2953         for (port = 1; port <= dev->num_ports; port++)
2954                 mlx5_query_ext_port_caps(dev, port);
2955 }
2956
2957 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
2958 {
2959         struct ib_device_attr *dprops = NULL;
2960         struct ib_port_attr *pprops = NULL;
2961         int err = -ENOMEM;
2962
2963         pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
2964         if (!pprops)
2965                 goto out;
2966
2967         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2968         if (!dprops)
2969                 goto out;
2970
2971         err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
2972         if (err) {
2973                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2974                 goto out;
2975         }
2976
2977         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2978         if (err) {
2979                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2980                              port, err);
2981                 goto out;
2982         }
2983
2984         dev->mdev->port_caps[port - 1].pkey_table_len =
2985                                         dprops->max_pkeys;
2986         dev->mdev->port_caps[port - 1].gid_table_len =
2987                                         pprops->gid_tbl_len;
2988         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
2989                     port, dprops->max_pkeys, pprops->gid_tbl_len);
2990
2991 out:
2992         kfree(pprops);
2993         kfree(dprops);
2994
2995         return err;
2996 }
2997
2998 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
2999 {
3000         /* For representors use port 1, is this is the only native
3001          * port
3002          */
3003         if (dev->is_rep)
3004                 return __get_port_caps(dev, 1);
3005         return __get_port_caps(dev, port);
3006 }
3007
3008 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3009 {
3010         switch (umr_fence_cap) {
3011         case MLX5_CAP_UMR_FENCE_NONE:
3012                 return MLX5_FENCE_MODE_NONE;
3013         case MLX5_CAP_UMR_FENCE_SMALL:
3014                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3015         default:
3016                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3017         }
3018 }
3019
3020 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
3021 {
3022         struct mlx5_ib_resources *devr = &dev->devr;
3023         struct ib_srq_init_attr attr;
3024         struct ib_device *ibdev;
3025         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3026         int port;
3027         int ret = 0;
3028
3029         ibdev = &dev->ib_dev;
3030
3031         if (!MLX5_CAP_GEN(dev->mdev, xrc))
3032                 return -EOPNOTSUPP;
3033
3034         mutex_init(&devr->mutex);
3035
3036         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
3037         if (!devr->p0)
3038                 return -ENOMEM;
3039
3040         devr->p0->device  = ibdev;
3041         devr->p0->uobject = NULL;
3042         atomic_set(&devr->p0->usecnt, 0);
3043
3044         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
3045         if (ret)
3046                 goto error0;
3047
3048         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
3049         if (!devr->c0) {
3050                 ret = -ENOMEM;
3051                 goto error1;
3052         }
3053
3054         devr->c0->device = &dev->ib_dev;
3055         atomic_set(&devr->c0->usecnt, 0);
3056
3057         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
3058         if (ret)
3059                 goto err_create_cq;
3060
3061         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
3062         if (ret)
3063                 goto error2;
3064
3065         ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
3066         if (ret)
3067                 goto error3;
3068
3069         memset(&attr, 0, sizeof(attr));
3070         attr.attr.max_sge = 1;
3071         attr.attr.max_wr = 1;
3072         attr.srq_type = IB_SRQT_XRC;
3073         attr.ext.cq = devr->c0;
3074
3075         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3076         if (!devr->s0) {
3077                 ret = -ENOMEM;
3078                 goto error4;
3079         }
3080
3081         devr->s0->device        = &dev->ib_dev;
3082         devr->s0->pd            = devr->p0;
3083         devr->s0->srq_type      = IB_SRQT_XRC;
3084         devr->s0->ext.cq        = devr->c0;
3085         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
3086         if (ret)
3087                 goto err_create;
3088
3089         atomic_inc(&devr->s0->ext.cq->usecnt);
3090         atomic_inc(&devr->p0->usecnt);
3091         atomic_set(&devr->s0->usecnt, 0);
3092
3093         memset(&attr, 0, sizeof(attr));
3094         attr.attr.max_sge = 1;
3095         attr.attr.max_wr = 1;
3096         attr.srq_type = IB_SRQT_BASIC;
3097         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
3098         if (!devr->s1) {
3099                 ret = -ENOMEM;
3100                 goto error5;
3101         }
3102
3103         devr->s1->device        = &dev->ib_dev;
3104         devr->s1->pd            = devr->p0;
3105         devr->s1->srq_type      = IB_SRQT_BASIC;
3106         devr->s1->ext.cq        = devr->c0;
3107
3108         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
3109         if (ret)
3110                 goto error6;
3111
3112         atomic_inc(&devr->p0->usecnt);
3113         atomic_set(&devr->s1->usecnt, 0);
3114
3115         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3116                 INIT_WORK(&devr->ports[port].pkey_change_work,
3117                           pkey_change_handler);
3118
3119         return 0;
3120
3121 error6:
3122         kfree(devr->s1);
3123 error5:
3124         mlx5_ib_destroy_srq(devr->s0, NULL);
3125 err_create:
3126         kfree(devr->s0);
3127 error4:
3128         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3129 error3:
3130         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3131 error2:
3132         mlx5_ib_destroy_cq(devr->c0, NULL);
3133 err_create_cq:
3134         kfree(devr->c0);
3135 error1:
3136         mlx5_ib_dealloc_pd(devr->p0, NULL);
3137 error0:
3138         kfree(devr->p0);
3139         return ret;
3140 }
3141
3142 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
3143 {
3144         struct mlx5_ib_resources *devr = &dev->devr;
3145         int port;
3146
3147         mlx5_ib_destroy_srq(devr->s1, NULL);
3148         kfree(devr->s1);
3149         mlx5_ib_destroy_srq(devr->s0, NULL);
3150         kfree(devr->s0);
3151         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
3152         mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
3153         mlx5_ib_destroy_cq(devr->c0, NULL);
3154         kfree(devr->c0);
3155         mlx5_ib_dealloc_pd(devr->p0, NULL);
3156         kfree(devr->p0);
3157
3158         /* Make sure no change P_Key work items are still executing */
3159         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
3160                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3161 }
3162
3163 static u32 get_core_cap_flags(struct ib_device *ibdev,
3164                               struct mlx5_hca_vport_context *rep)
3165 {
3166         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3167         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3168         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3169         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3170         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3171         u32 ret = 0;
3172
3173         if (rep->grh_required)
3174                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
3175
3176         if (ll == IB_LINK_LAYER_INFINIBAND)
3177                 return ret | RDMA_CORE_PORT_IBA_IB;
3178
3179         if (raw_support)
3180                 ret |= RDMA_CORE_PORT_RAW_PACKET;
3181
3182         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3183                 return ret;
3184
3185         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3186                 return ret;
3187
3188         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3189                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3190
3191         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3192                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3193
3194         return ret;
3195 }
3196
3197 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3198                                struct ib_port_immutable *immutable)
3199 {
3200         struct ib_port_attr attr;
3201         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3202         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3203         struct mlx5_hca_vport_context rep = {0};
3204         int err;
3205
3206         err = ib_query_port(ibdev, port_num, &attr);
3207         if (err)
3208                 return err;
3209
3210         if (ll == IB_LINK_LAYER_INFINIBAND) {
3211                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3212                                                    &rep);
3213                 if (err)
3214                         return err;
3215         }
3216
3217         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3218         immutable->gid_tbl_len = attr.gid_tbl_len;
3219         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
3220         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3221
3222         return 0;
3223 }
3224
3225 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
3226                                    struct ib_port_immutable *immutable)
3227 {
3228         struct ib_port_attr attr;
3229         int err;
3230
3231         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3232
3233         err = ib_query_port(ibdev, port_num, &attr);
3234         if (err)
3235                 return err;
3236
3237         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3238         immutable->gid_tbl_len = attr.gid_tbl_len;
3239         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3240
3241         return 0;
3242 }
3243
3244 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3245 {
3246         struct mlx5_ib_dev *dev =
3247                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3248         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3249                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3250                  fw_rev_sub(dev->mdev));
3251 }
3252
3253 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3254 {
3255         struct mlx5_core_dev *mdev = dev->mdev;
3256         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3257                                                                  MLX5_FLOW_NAMESPACE_LAG);
3258         struct mlx5_flow_table *ft;
3259         int err;
3260
3261         if (!ns || !mlx5_lag_is_roce(mdev))
3262                 return 0;
3263
3264         err = mlx5_cmd_create_vport_lag(mdev);
3265         if (err)
3266                 return err;
3267
3268         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3269         if (IS_ERR(ft)) {
3270                 err = PTR_ERR(ft);
3271                 goto err_destroy_vport_lag;
3272         }
3273
3274         dev->flow_db->lag_demux_ft = ft;
3275         dev->lag_active = true;
3276         return 0;
3277
3278 err_destroy_vport_lag:
3279         mlx5_cmd_destroy_vport_lag(mdev);
3280         return err;
3281 }
3282
3283 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3284 {
3285         struct mlx5_core_dev *mdev = dev->mdev;
3286
3287         if (dev->lag_active) {
3288                 dev->lag_active = false;
3289
3290                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3291                 dev->flow_db->lag_demux_ft = NULL;
3292
3293                 mlx5_cmd_destroy_vport_lag(mdev);
3294         }
3295 }
3296
3297 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3298 {
3299         int err;
3300
3301         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3302         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3303         if (err) {
3304                 dev->port[port_num].roce.nb.notifier_call = NULL;
3305                 return err;
3306         }
3307
3308         return 0;
3309 }
3310
3311 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3312 {
3313         if (dev->port[port_num].roce.nb.notifier_call) {
3314                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3315                 dev->port[port_num].roce.nb.notifier_call = NULL;
3316         }
3317 }
3318
3319 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3320 {
3321         int err;
3322
3323         err = mlx5_nic_vport_enable_roce(dev->mdev);
3324         if (err)
3325                 return err;
3326
3327         err = mlx5_eth_lag_init(dev);
3328         if (err)
3329                 goto err_disable_roce;
3330
3331         return 0;
3332
3333 err_disable_roce:
3334         mlx5_nic_vport_disable_roce(dev->mdev);
3335
3336         return err;
3337 }
3338
3339 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3340 {
3341         mlx5_eth_lag_cleanup(dev);
3342         mlx5_nic_vport_disable_roce(dev->mdev);
3343 }
3344
3345 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
3346                                  enum rdma_netdev_t type,
3347                                  struct rdma_netdev_alloc_params *params)
3348 {
3349         if (type != RDMA_NETDEV_IPOIB)
3350                 return -EOPNOTSUPP;
3351
3352         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3353 }
3354
3355 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3356                                        size_t count, loff_t *pos)
3357 {
3358         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3359         char lbuf[20];
3360         int len;
3361
3362         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3363         return simple_read_from_buffer(buf, count, pos, lbuf, len);
3364 }
3365
3366 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3367                                         size_t count, loff_t *pos)
3368 {
3369         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3370         u32 timeout;
3371         u32 var;
3372
3373         if (kstrtouint_from_user(buf, count, 0, &var))
3374                 return -EFAULT;
3375
3376         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3377                         1000);
3378         if (timeout != var)
3379                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3380                             timeout);
3381
3382         delay_drop->timeout = timeout;
3383
3384         return count;
3385 }
3386
3387 static const struct file_operations fops_delay_drop_timeout = {
3388         .owner  = THIS_MODULE,
3389         .open   = simple_open,
3390         .write  = delay_drop_timeout_write,
3391         .read   = delay_drop_timeout_read,
3392 };
3393
3394 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3395                                       struct mlx5_ib_multiport_info *mpi)
3396 {
3397         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3398         struct mlx5_ib_port *port = &ibdev->port[port_num];
3399         int comps;
3400         int err;
3401         int i;
3402
3403         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3404
3405         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3406
3407         spin_lock(&port->mp.mpi_lock);
3408         if (!mpi->ibdev) {
3409                 spin_unlock(&port->mp.mpi_lock);
3410                 return;
3411         }
3412
3413         mpi->ibdev = NULL;
3414
3415         spin_unlock(&port->mp.mpi_lock);
3416         if (mpi->mdev_events.notifier_call)
3417                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3418         mpi->mdev_events.notifier_call = NULL;
3419         mlx5_remove_netdev_notifier(ibdev, port_num);
3420         spin_lock(&port->mp.mpi_lock);
3421
3422         comps = mpi->mdev_refcnt;
3423         if (comps) {
3424                 mpi->unaffiliate = true;
3425                 init_completion(&mpi->unref_comp);
3426                 spin_unlock(&port->mp.mpi_lock);
3427
3428                 for (i = 0; i < comps; i++)
3429                         wait_for_completion(&mpi->unref_comp);
3430
3431                 spin_lock(&port->mp.mpi_lock);
3432                 mpi->unaffiliate = false;
3433         }
3434
3435         port->mp.mpi = NULL;
3436
3437         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
3438
3439         spin_unlock(&port->mp.mpi_lock);
3440
3441         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3442
3443         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
3444         /* Log an error, still needed to cleanup the pointers and add
3445          * it back to the list.
3446          */
3447         if (err)
3448                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3449                             port_num + 1);
3450
3451         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3452 }
3453
3454 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3455                                     struct mlx5_ib_multiport_info *mpi)
3456 {
3457         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3458         int err;
3459
3460         lockdep_assert_held(&mlx5_ib_multiport_mutex);
3461
3462         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3463         if (ibdev->port[port_num].mp.mpi) {
3464                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
3465                             port_num + 1);
3466                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3467                 return false;
3468         }
3469
3470         ibdev->port[port_num].mp.mpi = mpi;
3471         mpi->ibdev = ibdev;
3472         mpi->mdev_events.notifier_call = NULL;
3473         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3474
3475         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3476         if (err)
3477                 goto unbind;
3478
3479         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
3480         if (err)
3481                 goto unbind;
3482
3483         err = mlx5_add_netdev_notifier(ibdev, port_num);
3484         if (err) {
3485                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3486                             port_num + 1);
3487                 goto unbind;
3488         }
3489
3490         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3491         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3492
3493         mlx5_ib_init_cong_debugfs(ibdev, port_num);
3494
3495         return true;
3496
3497 unbind:
3498         mlx5_ib_unbind_slave_port(ibdev, mpi);
3499         return false;
3500 }
3501
3502 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3503 {
3504         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3505         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3506                                                           port_num + 1);
3507         struct mlx5_ib_multiport_info *mpi;
3508         int err;
3509         int i;
3510
3511         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3512                 return 0;
3513
3514         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3515                                                      &dev->sys_image_guid);
3516         if (err)
3517                 return err;
3518
3519         err = mlx5_nic_vport_enable_roce(dev->mdev);
3520         if (err)
3521                 return err;
3522
3523         mutex_lock(&mlx5_ib_multiport_mutex);
3524         for (i = 0; i < dev->num_ports; i++) {
3525                 bool bound = false;
3526
3527                 /* build a stub multiport info struct for the native port. */
3528                 if (i == port_num) {
3529                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3530                         if (!mpi) {
3531                                 mutex_unlock(&mlx5_ib_multiport_mutex);
3532                                 mlx5_nic_vport_disable_roce(dev->mdev);
3533                                 return -ENOMEM;
3534                         }
3535
3536                         mpi->is_master = true;
3537                         mpi->mdev = dev->mdev;
3538                         mpi->sys_image_guid = dev->sys_image_guid;
3539                         dev->port[i].mp.mpi = mpi;
3540                         mpi->ibdev = dev;
3541                         mpi = NULL;
3542                         continue;
3543                 }
3544
3545                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3546                                     list) {
3547                         if (dev->sys_image_guid == mpi->sys_image_guid &&
3548                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3549                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
3550                         }
3551
3552                         if (bound) {
3553                                 dev_dbg(mpi->mdev->device,
3554                                         "removing port from unaffiliated list.\n");
3555                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3556                                 list_del(&mpi->list);
3557                                 break;
3558                         }
3559                 }
3560                 if (!bound) {
3561                         get_port_caps(dev, i + 1);
3562                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
3563                                     i + 1);
3564                 }
3565         }
3566
3567         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3568         mutex_unlock(&mlx5_ib_multiport_mutex);
3569         return err;
3570 }
3571
3572 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3573 {
3574         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3575         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3576                                                           port_num + 1);
3577         int i;
3578
3579         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3580                 return;
3581
3582         mutex_lock(&mlx5_ib_multiport_mutex);
3583         for (i = 0; i < dev->num_ports; i++) {
3584                 if (dev->port[i].mp.mpi) {
3585                         /* Destroy the native port stub */
3586                         if (i == port_num) {
3587                                 kfree(dev->port[i].mp.mpi);
3588                                 dev->port[i].mp.mpi = NULL;
3589                         } else {
3590                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
3591                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
3592                         }
3593                 }
3594         }
3595
3596         mlx5_ib_dbg(dev, "removing from devlist\n");
3597         list_del(&dev->ib_dev_list);
3598         mutex_unlock(&mlx5_ib_multiport_mutex);
3599
3600         mlx5_nic_vport_disable_roce(dev->mdev);
3601 }
3602
3603 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3604                             enum rdma_remove_reason why,
3605                             struct uverbs_attr_bundle *attrs)
3606 {
3607         struct mlx5_user_mmap_entry *obj = uobject->object;
3608
3609         rdma_user_mmap_entry_remove(&obj->rdma_entry);
3610         return 0;
3611 }
3612
3613 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3614                                             struct mlx5_user_mmap_entry *entry,
3615                                             size_t length)
3616 {
3617         return rdma_user_mmap_entry_insert_range(
3618                 &c->ibucontext, &entry->rdma_entry, length,
3619                 (MLX5_IB_MMAP_OFFSET_START << 16),
3620                 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3621 }
3622
3623 static struct mlx5_user_mmap_entry *
3624 alloc_var_entry(struct mlx5_ib_ucontext *c)
3625 {
3626         struct mlx5_user_mmap_entry *entry;
3627         struct mlx5_var_table *var_table;
3628         u32 page_idx;
3629         int err;
3630
3631         var_table = &to_mdev(c->ibucontext.device)->var_table;
3632         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3633         if (!entry)
3634                 return ERR_PTR(-ENOMEM);
3635
3636         mutex_lock(&var_table->bitmap_lock);
3637         page_idx = find_first_zero_bit(var_table->bitmap,
3638                                        var_table->num_var_hw_entries);
3639         if (page_idx >= var_table->num_var_hw_entries) {
3640                 err = -ENOSPC;
3641                 mutex_unlock(&var_table->bitmap_lock);
3642                 goto end;
3643         }
3644
3645         set_bit(page_idx, var_table->bitmap);
3646         mutex_unlock(&var_table->bitmap_lock);
3647
3648         entry->address = var_table->hw_start_addr +
3649                                 (page_idx * var_table->stride_size);
3650         entry->page_idx = page_idx;
3651         entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3652
3653         err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3654                                                var_table->stride_size);
3655         if (err)
3656                 goto err_insert;
3657
3658         return entry;
3659
3660 err_insert:
3661         mutex_lock(&var_table->bitmap_lock);
3662         clear_bit(page_idx, var_table->bitmap);
3663         mutex_unlock(&var_table->bitmap_lock);
3664 end:
3665         kfree(entry);
3666         return ERR_PTR(err);
3667 }
3668
3669 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3670         struct uverbs_attr_bundle *attrs)
3671 {
3672         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3673                 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3674         struct mlx5_ib_ucontext *c;
3675         struct mlx5_user_mmap_entry *entry;
3676         u64 mmap_offset;
3677         u32 length;
3678         int err;
3679
3680         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3681         if (IS_ERR(c))
3682                 return PTR_ERR(c);
3683
3684         entry = alloc_var_entry(c);
3685         if (IS_ERR(entry))
3686                 return PTR_ERR(entry);
3687
3688         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3689         length = entry->rdma_entry.npages * PAGE_SIZE;
3690         uobj->object = entry;
3691         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3692
3693         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3694                              &mmap_offset, sizeof(mmap_offset));
3695         if (err)
3696                 return err;
3697
3698         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3699                              &entry->page_idx, sizeof(entry->page_idx));
3700         if (err)
3701                 return err;
3702
3703         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3704                              &length, sizeof(length));
3705         return err;
3706 }
3707
3708 DECLARE_UVERBS_NAMED_METHOD(
3709         MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3710         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3711                         MLX5_IB_OBJECT_VAR,
3712                         UVERBS_ACCESS_NEW,
3713                         UA_MANDATORY),
3714         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3715                            UVERBS_ATTR_TYPE(u32),
3716                            UA_MANDATORY),
3717         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3718                            UVERBS_ATTR_TYPE(u32),
3719                            UA_MANDATORY),
3720         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3721                             UVERBS_ATTR_TYPE(u64),
3722                             UA_MANDATORY));
3723
3724 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3725         MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3726         UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3727                         MLX5_IB_OBJECT_VAR,
3728                         UVERBS_ACCESS_DESTROY,
3729                         UA_MANDATORY));
3730
3731 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3732                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3733                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3734                             &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3735
3736 static bool var_is_supported(struct ib_device *device)
3737 {
3738         struct mlx5_ib_dev *dev = to_mdev(device);
3739
3740         return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3741                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3742 }
3743
3744 static struct mlx5_user_mmap_entry *
3745 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3746                 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3747 {
3748         struct mlx5_user_mmap_entry *entry;
3749         struct mlx5_ib_dev *dev;
3750         u32 uar_index;
3751         int err;
3752
3753         entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3754         if (!entry)
3755                 return ERR_PTR(-ENOMEM);
3756
3757         dev = to_mdev(c->ibucontext.device);
3758         err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3759         if (err)
3760                 goto end;
3761
3762         entry->page_idx = uar_index;
3763         entry->address = uar_index2paddress(dev, uar_index);
3764         if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3765                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3766         else
3767                 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3768
3769         err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3770         if (err)
3771                 goto err_insert;
3772
3773         return entry;
3774
3775 err_insert:
3776         mlx5_cmd_free_uar(dev->mdev, uar_index);
3777 end:
3778         kfree(entry);
3779         return ERR_PTR(err);
3780 }
3781
3782 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3783         struct uverbs_attr_bundle *attrs)
3784 {
3785         struct ib_uobject *uobj = uverbs_attr_get_uobject(
3786                 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3787         enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3788         struct mlx5_ib_ucontext *c;
3789         struct mlx5_user_mmap_entry *entry;
3790         u64 mmap_offset;
3791         u32 length;
3792         int err;
3793
3794         c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3795         if (IS_ERR(c))
3796                 return PTR_ERR(c);
3797
3798         err = uverbs_get_const(&alloc_type, attrs,
3799                                MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3800         if (err)
3801                 return err;
3802
3803         if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3804             alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3805                 return -EOPNOTSUPP;
3806
3807         if (!to_mdev(c->ibucontext.device)->wc_support &&
3808             alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3809                 return -EOPNOTSUPP;
3810
3811         entry = alloc_uar_entry(c, alloc_type);
3812         if (IS_ERR(entry))
3813                 return PTR_ERR(entry);
3814
3815         mmap_offset = mlx5_entry_to_mmap_offset(entry);
3816         length = entry->rdma_entry.npages * PAGE_SIZE;
3817         uobj->object = entry;
3818         uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3819
3820         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3821                              &mmap_offset, sizeof(mmap_offset));
3822         if (err)
3823                 return err;
3824
3825         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3826                              &entry->page_idx, sizeof(entry->page_idx));
3827         if (err)
3828                 return err;
3829
3830         err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3831                              &length, sizeof(length));
3832         return err;
3833 }
3834
3835 DECLARE_UVERBS_NAMED_METHOD(
3836         MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3837         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3838                         MLX5_IB_OBJECT_UAR,
3839                         UVERBS_ACCESS_NEW,
3840                         UA_MANDATORY),
3841         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3842                              enum mlx5_ib_uapi_uar_alloc_type,
3843                              UA_MANDATORY),
3844         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3845                            UVERBS_ATTR_TYPE(u32),
3846                            UA_MANDATORY),
3847         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3848                            UVERBS_ATTR_TYPE(u32),
3849                            UA_MANDATORY),
3850         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3851                             UVERBS_ATTR_TYPE(u64),
3852                             UA_MANDATORY));
3853
3854 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3855         MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3856         UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3857                         MLX5_IB_OBJECT_UAR,
3858                         UVERBS_ACCESS_DESTROY,
3859                         UA_MANDATORY));
3860
3861 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3862                             UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3863                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3864                             &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3865
3866 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3867         mlx5_ib_dm,
3868         UVERBS_OBJECT_DM,
3869         UVERBS_METHOD_DM_ALLOC,
3870         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
3871                             UVERBS_ATTR_TYPE(u64),
3872                             UA_MANDATORY),
3873         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
3874                             UVERBS_ATTR_TYPE(u16),
3875                             UA_OPTIONAL),
3876         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
3877                              enum mlx5_ib_uapi_dm_type,
3878                              UA_OPTIONAL));
3879
3880 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3881         mlx5_ib_flow_action,
3882         UVERBS_OBJECT_FLOW_ACTION,
3883         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3884         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3885                              enum mlx5_ib_uapi_flow_action_flags));
3886
3887 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3888         mlx5_ib_query_context,
3889         UVERBS_OBJECT_DEVICE,
3890         UVERBS_METHOD_QUERY_CONTEXT,
3891         UVERBS_ATTR_PTR_OUT(
3892                 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3893                 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3894                                    dump_fill_mkey),
3895                 UA_MANDATORY));
3896
3897 static const struct uapi_definition mlx5_ib_defs[] = {
3898         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3899         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3900         UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3901         UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3902
3903         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3904                                 &mlx5_ib_flow_action),
3905         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
3906         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3907         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3908                                 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3909         UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3910         {}
3911 };
3912
3913 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3914 {
3915         mlx5_ib_cleanup_multiport_master(dev);
3916         WARN_ON(!xa_empty(&dev->odp_mkeys));
3917         cleanup_srcu_struct(&dev->odp_srcu);
3918
3919         WARN_ON(!xa_empty(&dev->sig_mrs));
3920         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3921 }
3922
3923 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3924 {
3925         struct mlx5_core_dev *mdev = dev->mdev;
3926         int err;
3927         int i;
3928
3929         for (i = 0; i < dev->num_ports; i++) {
3930                 spin_lock_init(&dev->port[i].mp.mpi_lock);
3931                 rwlock_init(&dev->port[i].roce.netdev_lock);
3932                 dev->port[i].roce.dev = dev;
3933                 dev->port[i].roce.native_port_num = i + 1;
3934                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3935         }
3936
3937         mlx5_ib_internal_fill_odp_caps(dev);
3938
3939         err = mlx5_ib_init_multiport_master(dev);
3940         if (err)
3941                 return err;
3942
3943         err = set_has_smi_cap(dev);
3944         if (err)
3945                 return err;
3946
3947         if (!mlx5_core_mp_enabled(mdev)) {
3948                 for (i = 1; i <= dev->num_ports; i++) {
3949                         err = get_port_caps(dev, i);
3950                         if (err)
3951                                 break;
3952                 }
3953         } else {
3954                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
3955         }
3956         if (err)
3957                 goto err_mp;
3958
3959         if (mlx5_use_mad_ifc(dev))
3960                 get_ext_port_caps(dev);
3961
3962         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3963         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3964         dev->ib_dev.phys_port_cnt       = dev->num_ports;
3965         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
3966         dev->ib_dev.dev.parent          = mdev->device;
3967         dev->ib_dev.lag_flags           = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3968
3969         mutex_init(&dev->cap_mask_mutex);
3970         INIT_LIST_HEAD(&dev->qp_list);
3971         spin_lock_init(&dev->reset_flow_resource_lock);
3972         xa_init(&dev->odp_mkeys);
3973         xa_init(&dev->sig_mrs);
3974         atomic_set(&dev->mkey_var, 0);
3975
3976         spin_lock_init(&dev->dm.lock);
3977         dev->dm.dev = mdev;
3978
3979         err = init_srcu_struct(&dev->odp_srcu);
3980         if (err)
3981                 goto err_mp;
3982
3983         return 0;
3984
3985 err_mp:
3986         mlx5_ib_cleanup_multiport_master(dev);
3987
3988         return -ENOMEM;
3989 }
3990
3991 static int mlx5_ib_enable_driver(struct ib_device *dev)
3992 {
3993         struct mlx5_ib_dev *mdev = to_mdev(dev);
3994         int ret;
3995
3996         ret = mlx5_ib_test_wc(mdev);
3997         mlx5_ib_dbg(mdev, "Write-Combining %s",
3998                     mdev->wc_support ? "supported" : "not supported");
3999
4000         return ret;
4001 }
4002
4003 static const struct ib_device_ops mlx5_ib_dev_ops = {
4004         .owner = THIS_MODULE,
4005         .driver_id = RDMA_DRIVER_MLX5,
4006         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
4007
4008         .add_gid = mlx5_ib_add_gid,
4009         .alloc_mr = mlx5_ib_alloc_mr,
4010         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
4011         .alloc_pd = mlx5_ib_alloc_pd,
4012         .alloc_ucontext = mlx5_ib_alloc_ucontext,
4013         .attach_mcast = mlx5_ib_mcg_attach,
4014         .check_mr_status = mlx5_ib_check_mr_status,
4015         .create_ah = mlx5_ib_create_ah,
4016         .create_cq = mlx5_ib_create_cq,
4017         .create_qp = mlx5_ib_create_qp,
4018         .create_srq = mlx5_ib_create_srq,
4019         .create_user_ah = mlx5_ib_create_ah,
4020         .dealloc_pd = mlx5_ib_dealloc_pd,
4021         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
4022         .del_gid = mlx5_ib_del_gid,
4023         .dereg_mr = mlx5_ib_dereg_mr,
4024         .destroy_ah = mlx5_ib_destroy_ah,
4025         .destroy_cq = mlx5_ib_destroy_cq,
4026         .destroy_qp = mlx5_ib_destroy_qp,
4027         .destroy_srq = mlx5_ib_destroy_srq,
4028         .detach_mcast = mlx5_ib_mcg_detach,
4029         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
4030         .drain_rq = mlx5_ib_drain_rq,
4031         .drain_sq = mlx5_ib_drain_sq,
4032         .enable_driver = mlx5_ib_enable_driver,
4033         .get_dev_fw_str = get_dev_fw_str,
4034         .get_dma_mr = mlx5_ib_get_dma_mr,
4035         .get_link_layer = mlx5_ib_port_link_layer,
4036         .map_mr_sg = mlx5_ib_map_mr_sg,
4037         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
4038         .mmap = mlx5_ib_mmap,
4039         .mmap_free = mlx5_ib_mmap_free,
4040         .modify_cq = mlx5_ib_modify_cq,
4041         .modify_device = mlx5_ib_modify_device,
4042         .modify_port = mlx5_ib_modify_port,
4043         .modify_qp = mlx5_ib_modify_qp,
4044         .modify_srq = mlx5_ib_modify_srq,
4045         .poll_cq = mlx5_ib_poll_cq,
4046         .post_recv = mlx5_ib_post_recv_nodrain,
4047         .post_send = mlx5_ib_post_send_nodrain,
4048         .post_srq_recv = mlx5_ib_post_srq_recv,
4049         .process_mad = mlx5_ib_process_mad,
4050         .query_ah = mlx5_ib_query_ah,
4051         .query_device = mlx5_ib_query_device,
4052         .query_gid = mlx5_ib_query_gid,
4053         .query_pkey = mlx5_ib_query_pkey,
4054         .query_qp = mlx5_ib_query_qp,
4055         .query_srq = mlx5_ib_query_srq,
4056         .query_ucontext = mlx5_ib_query_ucontext,
4057         .reg_user_mr = mlx5_ib_reg_user_mr,
4058         .req_notify_cq = mlx5_ib_arm_cq,
4059         .rereg_user_mr = mlx5_ib_rereg_user_mr,
4060         .resize_cq = mlx5_ib_resize_cq,
4061
4062         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
4063         INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
4064         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
4065         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
4066         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
4067         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
4068 };
4069
4070 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
4071         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
4072 };
4073
4074 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
4075         .get_vf_config = mlx5_ib_get_vf_config,
4076         .get_vf_guid = mlx5_ib_get_vf_guid,
4077         .get_vf_stats = mlx5_ib_get_vf_stats,
4078         .set_vf_guid = mlx5_ib_set_vf_guid,
4079         .set_vf_link_state = mlx5_ib_set_vf_link_state,
4080 };
4081
4082 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
4083         .alloc_mw = mlx5_ib_alloc_mw,
4084         .dealloc_mw = mlx5_ib_dealloc_mw,
4085
4086         INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
4087 };
4088
4089 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
4090         .alloc_xrcd = mlx5_ib_alloc_xrcd,
4091         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
4092
4093         INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
4094 };
4095
4096 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
4097         .alloc_dm = mlx5_ib_alloc_dm,
4098         .dealloc_dm = mlx5_ib_dealloc_dm,
4099         .reg_dm_mr = mlx5_ib_reg_dm_mr,
4100 };
4101
4102 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
4103 {
4104         struct mlx5_core_dev *mdev = dev->mdev;
4105         struct mlx5_var_table *var_table = &dev->var_table;
4106         u8 log_doorbell_bar_size;
4107         u8 log_doorbell_stride;
4108         u64 bar_size;
4109
4110         log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4111                                         log_doorbell_bar_size);
4112         log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
4113                                         log_doorbell_stride);
4114         var_table->hw_start_addr = dev->mdev->bar_addr +
4115                                 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
4116                                         doorbell_bar_offset);
4117         bar_size = (1ULL << log_doorbell_bar_size) * 4096;
4118         var_table->stride_size = 1ULL << log_doorbell_stride;
4119         var_table->num_var_hw_entries = div_u64(bar_size,
4120                                                 var_table->stride_size);
4121         mutex_init(&var_table->bitmap_lock);
4122         var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
4123                                           GFP_KERNEL);
4124         return (var_table->bitmap) ? 0 : -ENOMEM;
4125 }
4126
4127 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
4128 {
4129         bitmap_free(dev->var_table.bitmap);
4130 }
4131
4132 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4133 {
4134         struct mlx5_core_dev *mdev = dev->mdev;
4135         int err;
4136
4137         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
4138             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
4139                 ib_set_device_ops(&dev->ib_dev,
4140                                   &mlx5_ib_dev_ipoib_enhanced_ops);
4141
4142         if (mlx5_core_is_pf(mdev))
4143                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
4144
4145         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4146
4147         if (MLX5_CAP_GEN(mdev, imaicl))
4148                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
4149
4150         if (MLX5_CAP_GEN(mdev, xrc))
4151                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
4152
4153         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
4154             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4155             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
4156                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
4157
4158         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
4159
4160         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
4161                 dev->ib_dev.driver_def = mlx5_ib_defs;
4162
4163         err = init_node_data(dev);
4164         if (err)
4165                 return err;
4166
4167         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4168             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4169              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4170                 mutex_init(&dev->lb.mutex);
4171
4172         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4173                         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4174                 err = mlx5_ib_init_var_table(dev);
4175                 if (err)
4176                         return err;
4177         }
4178
4179         dev->ib_dev.use_cq_dim = true;
4180
4181         return 0;
4182 }
4183
4184 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4185         .get_port_immutable = mlx5_port_immutable,
4186         .query_port = mlx5_ib_query_port,
4187 };
4188
4189 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4190 {
4191         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
4192         return 0;
4193 }
4194
4195 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4196         .get_port_immutable = mlx5_port_rep_immutable,
4197         .query_port = mlx5_ib_rep_query_port,
4198 };
4199
4200 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
4201 {
4202         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
4203         return 0;
4204 }
4205
4206 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4207         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4208         .create_wq = mlx5_ib_create_wq,
4209         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4210         .destroy_wq = mlx5_ib_destroy_wq,
4211         .get_netdev = mlx5_ib_get_netdev,
4212         .modify_wq = mlx5_ib_modify_wq,
4213
4214         INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4215                            ib_rwq_ind_tbl),
4216 };
4217
4218 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
4219 {
4220         struct mlx5_core_dev *mdev = dev->mdev;
4221         enum rdma_link_layer ll;
4222         int port_type_cap;
4223         u8 port_num = 0;
4224         int err;
4225
4226         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4227         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4228
4229         if (ll == IB_LINK_LAYER_ETHERNET) {
4230                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4231
4232                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4233
4234                 /* Register only for native ports */
4235                 err = mlx5_add_netdev_notifier(dev, port_num);
4236                 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev))
4237                         /*
4238                          * We don't enable ETH interface for
4239                          * 1. IB representors
4240                          * 2. User disabled ROCE through devlink interface
4241                          */
4242                         return err;
4243
4244                 err = mlx5_enable_eth(dev);
4245                 if (err)
4246                         goto cleanup;
4247         }
4248
4249         return 0;
4250 cleanup:
4251         mlx5_remove_netdev_notifier(dev, port_num);
4252         return err;
4253 }
4254
4255 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
4256 {
4257         struct mlx5_core_dev *mdev = dev->mdev;
4258         enum rdma_link_layer ll;
4259         int port_type_cap;
4260         u8 port_num;
4261
4262         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4263         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4264
4265         if (ll == IB_LINK_LAYER_ETHERNET) {
4266                 if (!dev->is_rep)
4267                         mlx5_disable_eth(dev);
4268
4269                 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4270                 mlx5_remove_netdev_notifier(dev, port_num);
4271         }
4272 }
4273
4274 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4275 {
4276         mlx5_ib_init_cong_debugfs(dev,
4277                                   mlx5_core_native_port_num(dev->mdev) - 1);
4278         return 0;
4279 }
4280
4281 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4282 {
4283         mlx5_ib_cleanup_cong_debugfs(dev,
4284                                      mlx5_core_native_port_num(dev->mdev) - 1);
4285 }
4286
4287 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4288 {
4289         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4290         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4291 }
4292
4293 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4294 {
4295         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4296 }
4297
4298 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4299 {
4300         int err;
4301
4302         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4303         if (err)
4304                 return err;
4305
4306         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4307         if (err)
4308                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4309
4310         return err;
4311 }
4312
4313 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4314 {
4315         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4316         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4317 }
4318
4319 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4320 {
4321         const char *name;
4322
4323         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
4324         if (!mlx5_lag_is_roce(dev->mdev))
4325                 name = "mlx5_%d";
4326         else
4327                 name = "mlx5_bond_%d";
4328         return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4329 }
4330
4331 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4332 {
4333         int err;
4334
4335         err = mlx5_mr_cache_cleanup(dev);
4336         if (err)
4337                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4338
4339         if (dev->umrc.qp)
4340                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4341         if (dev->umrc.cq)
4342                 ib_free_cq(dev->umrc.cq);
4343         if (dev->umrc.pd)
4344                 ib_dealloc_pd(dev->umrc.pd);
4345 }
4346
4347 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4348 {
4349         ib_unregister_device(&dev->ib_dev);
4350 }
4351
4352 enum {
4353         MAX_UMR_WR = 128,
4354 };
4355
4356 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4357 {
4358         struct ib_qp_init_attr *init_attr = NULL;
4359         struct ib_qp_attr *attr = NULL;
4360         struct ib_pd *pd;
4361         struct ib_cq *cq;
4362         struct ib_qp *qp;
4363         int ret;
4364
4365         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4366         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4367         if (!attr || !init_attr) {
4368                 ret = -ENOMEM;
4369                 goto error_0;
4370         }
4371
4372         pd = ib_alloc_pd(&dev->ib_dev, 0);
4373         if (IS_ERR(pd)) {
4374                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4375                 ret = PTR_ERR(pd);
4376                 goto error_0;
4377         }
4378
4379         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4380         if (IS_ERR(cq)) {
4381                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4382                 ret = PTR_ERR(cq);
4383                 goto error_2;
4384         }
4385
4386         init_attr->send_cq = cq;
4387         init_attr->recv_cq = cq;
4388         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4389         init_attr->cap.max_send_wr = MAX_UMR_WR;
4390         init_attr->cap.max_send_sge = 1;
4391         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4392         init_attr->port_num = 1;
4393         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4394         if (IS_ERR(qp)) {
4395                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4396                 ret = PTR_ERR(qp);
4397                 goto error_3;
4398         }
4399         qp->device     = &dev->ib_dev;
4400         qp->real_qp    = qp;
4401         qp->uobject    = NULL;
4402         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4403         qp->send_cq    = init_attr->send_cq;
4404         qp->recv_cq    = init_attr->recv_cq;
4405
4406         attr->qp_state = IB_QPS_INIT;
4407         attr->port_num = 1;
4408         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4409                                 IB_QP_PORT, NULL);
4410         if (ret) {
4411                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4412                 goto error_4;
4413         }
4414
4415         memset(attr, 0, sizeof(*attr));
4416         attr->qp_state = IB_QPS_RTR;
4417         attr->path_mtu = IB_MTU_256;
4418
4419         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4420         if (ret) {
4421                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4422                 goto error_4;
4423         }
4424
4425         memset(attr, 0, sizeof(*attr));
4426         attr->qp_state = IB_QPS_RTS;
4427         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4428         if (ret) {
4429                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4430                 goto error_4;
4431         }
4432
4433         dev->umrc.qp = qp;
4434         dev->umrc.cq = cq;
4435         dev->umrc.pd = pd;
4436
4437         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4438         ret = mlx5_mr_cache_init(dev);
4439         if (ret) {
4440                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4441                 goto error_4;
4442         }
4443
4444         kfree(attr);
4445         kfree(init_attr);
4446
4447         return 0;
4448
4449 error_4:
4450         mlx5_ib_destroy_qp(qp, NULL);
4451         dev->umrc.qp = NULL;
4452
4453 error_3:
4454         ib_free_cq(cq);
4455         dev->umrc.cq = NULL;
4456
4457 error_2:
4458         ib_dealloc_pd(pd);
4459         dev->umrc.pd = NULL;
4460
4461 error_0:
4462         kfree(attr);
4463         kfree(init_attr);
4464         return ret;
4465 }
4466
4467 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4468 {
4469         struct dentry *root;
4470
4471         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4472                 return 0;
4473
4474         mutex_init(&dev->delay_drop.lock);
4475         dev->delay_drop.dev = dev;
4476         dev->delay_drop.activate = false;
4477         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4478         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4479         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4480         atomic_set(&dev->delay_drop.events_cnt, 0);
4481
4482         if (!mlx5_debugfs_root)
4483                 return 0;
4484
4485         root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4486         dev->delay_drop.dir_debugfs = root;
4487
4488         debugfs_create_atomic_t("num_timeout_events", 0400, root,
4489                                 &dev->delay_drop.events_cnt);
4490         debugfs_create_atomic_t("num_rqs", 0400, root,
4491                                 &dev->delay_drop.rqs_cnt);
4492         debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4493                             &fops_delay_drop_timeout);
4494         return 0;
4495 }
4496
4497 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4498 {
4499         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4500                 return;
4501
4502         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4503         if (!dev->delay_drop.dir_debugfs)
4504                 return;
4505
4506         debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4507         dev->delay_drop.dir_debugfs = NULL;
4508 }
4509
4510 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4511 {
4512         dev->mdev_events.notifier_call = mlx5_ib_event;
4513         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4514         return 0;
4515 }
4516
4517 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4518 {
4519         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4520 }
4521
4522 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4523                       const struct mlx5_ib_profile *profile,
4524                       int stage)
4525 {
4526         dev->ib_active = false;
4527
4528         /* Number of stages to cleanup */
4529         while (stage) {
4530                 stage--;
4531                 if (profile->stage[stage].cleanup)
4532                         profile->stage[stage].cleanup(dev);
4533         }
4534
4535         kfree(dev->port);
4536         ib_dealloc_device(&dev->ib_dev);
4537 }
4538
4539 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
4540                     const struct mlx5_ib_profile *profile)
4541 {
4542         int err;
4543         int i;
4544
4545         dev->profile = profile;
4546
4547         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4548                 if (profile->stage[i].init) {
4549                         err = profile->stage[i].init(dev);
4550                         if (err)
4551                                 goto err_out;
4552                 }
4553         }
4554
4555         dev->ib_active = true;
4556
4557         return dev;
4558
4559 err_out:
4560         __mlx5_ib_remove(dev, profile, i);
4561
4562         return NULL;
4563 }
4564
4565 static const struct mlx5_ib_profile pf_profile = {
4566         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4567                      mlx5_ib_stage_init_init,
4568                      mlx5_ib_stage_init_cleanup),
4569         STAGE_CREATE(MLX5_IB_STAGE_FS,
4570                      mlx5_ib_fs_init,
4571                      mlx5_ib_fs_cleanup),
4572         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4573                      mlx5_ib_stage_caps_init,
4574                      mlx5_ib_stage_caps_cleanup),
4575         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4576                      mlx5_ib_stage_non_default_cb,
4577                      NULL),
4578         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4579                      mlx5_ib_roce_init,
4580                      mlx5_ib_roce_cleanup),
4581         STAGE_CREATE(MLX5_IB_STAGE_QP,
4582                      mlx5_init_qp_table,
4583                      mlx5_cleanup_qp_table),
4584         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4585                      mlx5_init_srq_table,
4586                      mlx5_cleanup_srq_table),
4587         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4588                      mlx5_ib_dev_res_init,
4589                      mlx5_ib_dev_res_cleanup),
4590         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4591                      mlx5_ib_stage_dev_notifier_init,
4592                      mlx5_ib_stage_dev_notifier_cleanup),
4593         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4594                      mlx5_ib_odp_init_one,
4595                      mlx5_ib_odp_cleanup_one),
4596         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4597                      mlx5_ib_counters_init,
4598                      mlx5_ib_counters_cleanup),
4599         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4600                      mlx5_ib_stage_cong_debugfs_init,
4601                      mlx5_ib_stage_cong_debugfs_cleanup),
4602         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4603                      mlx5_ib_stage_uar_init,
4604                      mlx5_ib_stage_uar_cleanup),
4605         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4606                      mlx5_ib_stage_bfrag_init,
4607                      mlx5_ib_stage_bfrag_cleanup),
4608         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4609                      NULL,
4610                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4611         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4612                      mlx5_ib_devx_init,
4613                      mlx5_ib_devx_cleanup),
4614         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4615                      mlx5_ib_stage_ib_reg_init,
4616                      mlx5_ib_stage_ib_reg_cleanup),
4617         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4618                      mlx5_ib_stage_post_ib_reg_umr_init,
4619                      NULL),
4620         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4621                      mlx5_ib_stage_delay_drop_init,
4622                      mlx5_ib_stage_delay_drop_cleanup),
4623         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4624                      mlx5_ib_restrack_init,
4625                      NULL),
4626 };
4627
4628 const struct mlx5_ib_profile raw_eth_profile = {
4629         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4630                      mlx5_ib_stage_init_init,
4631                      mlx5_ib_stage_init_cleanup),
4632         STAGE_CREATE(MLX5_IB_STAGE_FS,
4633                      mlx5_ib_fs_init,
4634                      mlx5_ib_fs_cleanup),
4635         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4636                      mlx5_ib_stage_caps_init,
4637                      mlx5_ib_stage_caps_cleanup),
4638         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4639                      mlx5_ib_stage_raw_eth_non_default_cb,
4640                      NULL),
4641         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4642                      mlx5_ib_roce_init,
4643                      mlx5_ib_roce_cleanup),
4644         STAGE_CREATE(MLX5_IB_STAGE_QP,
4645                      mlx5_init_qp_table,
4646                      mlx5_cleanup_qp_table),
4647         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4648                      mlx5_init_srq_table,
4649                      mlx5_cleanup_srq_table),
4650         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4651                      mlx5_ib_dev_res_init,
4652                      mlx5_ib_dev_res_cleanup),
4653         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4654                      mlx5_ib_stage_dev_notifier_init,
4655                      mlx5_ib_stage_dev_notifier_cleanup),
4656         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4657                      mlx5_ib_counters_init,
4658                      mlx5_ib_counters_cleanup),
4659         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4660                      mlx5_ib_stage_cong_debugfs_init,
4661                      mlx5_ib_stage_cong_debugfs_cleanup),
4662         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4663                      mlx5_ib_stage_uar_init,
4664                      mlx5_ib_stage_uar_cleanup),
4665         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4666                      mlx5_ib_stage_bfrag_init,
4667                      mlx5_ib_stage_bfrag_cleanup),
4668         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4669                      NULL,
4670                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4671         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4672                      mlx5_ib_devx_init,
4673                      mlx5_ib_devx_cleanup),
4674         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4675                      mlx5_ib_stage_ib_reg_init,
4676                      mlx5_ib_stage_ib_reg_cleanup),
4677         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4678                      mlx5_ib_stage_post_ib_reg_umr_init,
4679                      NULL),
4680         STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4681                      mlx5_ib_restrack_init,
4682                      NULL),
4683 };
4684
4685 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
4686 {
4687         struct mlx5_ib_multiport_info *mpi;
4688         struct mlx5_ib_dev *dev;
4689         bool bound = false;
4690         int err;
4691
4692         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4693         if (!mpi)
4694                 return NULL;
4695
4696         mpi->mdev = mdev;
4697
4698         err = mlx5_query_nic_vport_system_image_guid(mdev,
4699                                                      &mpi->sys_image_guid);
4700         if (err) {
4701                 kfree(mpi);
4702                 return NULL;
4703         }
4704
4705         mutex_lock(&mlx5_ib_multiport_mutex);
4706         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4707                 if (dev->sys_image_guid == mpi->sys_image_guid)
4708                         bound = mlx5_ib_bind_slave_port(dev, mpi);
4709
4710                 if (bound) {
4711                         rdma_roce_rescan_device(&dev->ib_dev);
4712                         break;
4713                 }
4714         }
4715
4716         if (!bound) {
4717                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4718                 dev_dbg(mdev->device,
4719                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
4720         }
4721         mutex_unlock(&mlx5_ib_multiport_mutex);
4722
4723         return mpi;
4724 }
4725
4726 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
4727 {
4728         const struct mlx5_ib_profile *profile;
4729         enum rdma_link_layer ll;
4730         struct mlx5_ib_dev *dev;
4731         int port_type_cap;
4732         int num_ports;
4733
4734         if (MLX5_ESWITCH_MANAGER(mdev) &&
4735             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
4736                 if (!mlx5_core_mp_enabled(mdev))
4737                         mlx5_ib_register_vport_reps(mdev);
4738                 return mdev;
4739         }
4740
4741         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4742         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4743
4744         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
4745                 return mlx5_ib_add_slave_port(mdev);
4746
4747         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4748                         MLX5_CAP_GEN(mdev, num_vhca_ports));
4749         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4750         if (!dev)
4751                 return NULL;
4752         dev->port = kcalloc(num_ports, sizeof(*dev->port),
4753                              GFP_KERNEL);
4754         if (!dev->port) {
4755                 ib_dealloc_device(&dev->ib_dev);
4756                 return NULL;
4757         }
4758
4759         dev->mdev = mdev;
4760         dev->num_ports = num_ports;
4761
4762         if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
4763                 profile = &raw_eth_profile;
4764         else
4765                 profile = &pf_profile;
4766
4767         return __mlx5_ib_add(dev, profile);
4768 }
4769
4770 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
4771 {
4772         struct mlx5_ib_multiport_info *mpi;
4773         struct mlx5_ib_dev *dev;
4774
4775         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
4776                 mlx5_ib_unregister_vport_reps(mdev);
4777                 return;
4778         }
4779
4780         if (mlx5_core_is_mp_slave(mdev)) {
4781                 mpi = context;
4782                 mutex_lock(&mlx5_ib_multiport_mutex);
4783                 if (mpi->ibdev)
4784                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4785                 list_del(&mpi->list);
4786                 mutex_unlock(&mlx5_ib_multiport_mutex);
4787                 kfree(mpi);
4788                 return;
4789         }
4790
4791         dev = context;
4792         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4793 }
4794
4795 static struct mlx5_interface mlx5_ib_interface = {
4796         .add            = mlx5_ib_add,
4797         .remove         = mlx5_ib_remove,
4798         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
4799 };
4800
4801 static int __init mlx5_ib_init(void)
4802 {
4803         int err;
4804
4805         xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4806         if (!xlt_emergency_page)
4807                 return -ENOMEM;
4808
4809         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4810         if (!mlx5_ib_event_wq) {
4811                 free_page((unsigned long)xlt_emergency_page);
4812                 return -ENOMEM;
4813         }
4814
4815         mlx5_ib_odp_init();
4816
4817         err = mlx5_register_interface(&mlx5_ib_interface);
4818
4819         return err;
4820 }
4821
4822 static void __exit mlx5_ib_cleanup(void)
4823 {
4824         mlx5_unregister_interface(&mlx5_ib_interface);
4825         destroy_workqueue(mlx5_ib_event_wq);
4826         free_page((unsigned long)xlt_emergency_page);
4827 }
4828
4829 module_init(mlx5_ib_init);
4830 module_exit(mlx5_ib_cleanup);