drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 /**
  47  * hns_get_gid_index - Get gid index.
  48  * @hr_dev: pointer to structure hns_roce_dev.
  49  * @port:  port, value range: 0 ~ MAX
  50  * @gid_index:  gid_index, value range: 0 ~ MAX
  51  * Description:
  52  *    N ports shared gids, allocation method as follow:
  53  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  54  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  55  *              And so on
  56  */
  57 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  58 {
  59         return gid_index * hr_dev->caps.num_ports + port;
  60 }
  61
  62 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  63 {
  64         dseg->lkey = cpu_to_le32(sg->lkey);
  65         dseg->addr = cpu_to_le64(sg->addr);
  66         dseg->len  = cpu_to_le32(sg->length);
  67 }
  68
  69 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  70                           u32 rkey)
  71 {
  72         rseg->raddr = cpu_to_le64(remote_addr);
  73         rseg->rkey  = cpu_to_le32(rkey);
  74         rseg->len   = 0;
  75 }
  76
  77 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  78                                  const struct ib_send_wr *wr,
  79                                  const struct ib_send_wr **bad_wr)
  80 {
  81         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  82         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  83         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  84         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  85         struct hns_roce_wqe_data_seg *dseg = NULL;
  86         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  87         struct device *dev = &hr_dev->pdev->dev;
  88         struct hns_roce_sq_db sq_db = {};
  89         int ps_opcode, i;
  90         unsigned long flags = 0;
  91         void *wqe = NULL;
  92         __le32 doorbell[2];
  93         int ret = 0;
  94         int loopback;
  95         u32 wqe_idx;
  96         int nreq;
  97         u8 *smac;
  98
  99         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
 100                 ibqp->qp_type != IB_QPT_RC)) {
 101                 dev_err(dev, "un-supported QP type\n");
 102                 *bad_wr = NULL;
 103                 return -EOPNOTSUPP;
 104         }
 105
 106         spin_lock_irqsave(&qp->sq.lock, flags);
 107
 108         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 109                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 110                         ret = -ENOMEM;
 111                         *bad_wr = wr;
 112                         goto out;
 113                 }
 114
 115                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 116
 117                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 118                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 119                                 wr->num_sge, qp->sq.max_gs);
 120                         ret = -EINVAL;
 121                         *bad_wr = wr;
 122                         goto out;
 123                 }
 124
 125                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 126                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 127
 128                 /* Corresponding to the RC and RD type wqe process separately */
 129                 if (ibqp->qp_type == IB_QPT_GSI) {
 130                         ud_sq_wqe = wqe;
 131                         roce_set_field(ud_sq_wqe->dmac_h,
 132                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 133                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 134                                        ah->av.mac[0]);
 135                         roce_set_field(ud_sq_wqe->dmac_h,
 136                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 137                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 138                                        ah->av.mac[1]);
 139                         roce_set_field(ud_sq_wqe->dmac_h,
 140                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 141                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 142                                        ah->av.mac[2]);
 143                         roce_set_field(ud_sq_wqe->dmac_h,
 144                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 145                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 146                                        ah->av.mac[3]);
 147
 148                         roce_set_field(ud_sq_wqe->u32_8,
 149                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 150                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 151                                        ah->av.mac[4]);
 152                         roce_set_field(ud_sq_wqe->u32_8,
 153                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 154                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 155                                        ah->av.mac[5]);
 156
 157                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 158                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 159                                                               smac) ? 1 : 0;
 160                         roce_set_bit(ud_sq_wqe->u32_8,
 161                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 162                                      loopback);
 163
 164                         roce_set_field(ud_sq_wqe->u32_8,
 165                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 166                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 167                                        HNS_ROCE_WQE_OPCODE_SEND);
 168                         roce_set_field(ud_sq_wqe->u32_8,
 169                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 170                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 171                                        2);
 172                         roce_set_bit(ud_sq_wqe->u32_8,
 173                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 174                                 1);
 175
 176                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 177                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 178                                 (wr->send_flags & IB_SEND_SOLICITED ?
 179                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 180                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 181                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 182
 183                         roce_set_field(ud_sq_wqe->u32_16,
 184                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 185                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 186                                        ud_wr(wr)->remote_qpn);
 187                         roce_set_field(ud_sq_wqe->u32_16,
 188                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 189                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 190                                        ah->av.stat_rate);
 191
 192                         roce_set_field(ud_sq_wqe->u32_36,
 193                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 194                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 195                                        ah->av.flowlabel);
 196                         roce_set_field(ud_sq_wqe->u32_36,
 197                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 198                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 199                                       ah->av.sl);
 200                         roce_set_field(ud_sq_wqe->u32_36,
 201                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 202                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 203                                        hns_get_gid_index(hr_dev, qp->phy_port,
 204                                                          ah->av.gid_index));
 205
 206                         roce_set_field(ud_sq_wqe->u32_40,
 207                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 208                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 209                                        ah->av.hop_limit);
 210                         roce_set_field(ud_sq_wqe->u32_40,
 211                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 212                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 213                                        ah->av.tclass);
 214
 215                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 216
 217                         ud_sq_wqe->va0_l =
 218                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 219                         ud_sq_wqe->va0_h =
 220                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 221                         ud_sq_wqe->l_key0 =
 222                                        cpu_to_le32(wr->sg_list[0].lkey);
 223
 224                         ud_sq_wqe->va1_l =
 225                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 226                         ud_sq_wqe->va1_h =
 227                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 228                         ud_sq_wqe->l_key1 =
 229                                        cpu_to_le32(wr->sg_list[1].lkey);
 230                 } else if (ibqp->qp_type == IB_QPT_RC) {
 231                         u32 tmp_len = 0;
 232
 233                         ctrl = wqe;
 234                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 235                         for (i = 0; i < wr->num_sge; i++)
 236                                 tmp_len += wr->sg_list[i].length;
 237
 238                         ctrl->msg_length =
 239                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 240
 241                         ctrl->sgl_pa_h = 0;
 242                         ctrl->flag = 0;
 243
 244                         switch (wr->opcode) {
 245                         case IB_WR_SEND_WITH_IMM:
 246                         case IB_WR_RDMA_WRITE_WITH_IMM:
 247                                 ctrl->imm_data = wr->ex.imm_data;
 248                                 break;
 249                         case IB_WR_SEND_WITH_INV:
 250                                 ctrl->inv_key =
 251                                         cpu_to_le32(wr->ex.invalidate_rkey);
 252                                 break;
 253                         default:
 254                                 ctrl->imm_data = 0;
 255                                 break;
 256                         }
 257
 258                         /* Ctrl field, ctrl set type: sig, solic, imm, fence */
 259                         /* SO wait for conforming application scenarios */
 260                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 261                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 262                                       (wr->send_flags & IB_SEND_SOLICITED ?
 263                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 264                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 265                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 266                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 267                                       (wr->send_flags & IB_SEND_FENCE ?
 268                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 269
 270                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 271
 272                         switch (wr->opcode) {
 273                         case IB_WR_RDMA_READ:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 275                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 276                                                rdma_wr(wr)->rkey);
 277                                 break;
 278                         case IB_WR_RDMA_WRITE:
 279                         case IB_WR_RDMA_WRITE_WITH_IMM:
 280                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 281                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 282                                               rdma_wr(wr)->rkey);
 283                                 break;
 284                         case IB_WR_SEND:
 285                         case IB_WR_SEND_WITH_INV:
 286                         case IB_WR_SEND_WITH_IMM:
 287                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 288                                 break;
 289                         case IB_WR_LOCAL_INV:
 290                         case IB_WR_ATOMIC_CMP_AND_SWP:
 291                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 292                         case IB_WR_LSO:
 293                         default:
 294                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 295                                 break;
 296                         }
 297                         ctrl->flag |= cpu_to_le32(ps_opcode);
 298                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 299
 300                         dseg = wqe;
 301                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 302                                 if (le32_to_cpu(ctrl->msg_length) >
 303                                     hr_dev->caps.max_sq_inline) {
 304                                         ret = -EINVAL;
 305                                         *bad_wr = wr;
 306                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 307                                                 le32_to_cpu(ctrl->msg_length),
 308                                                 hr_dev->caps.max_sq_inline);
 309                                         goto out;
 310                                 }
 311                                 for (i = 0; i < wr->num_sge; i++) {
 312                                         memcpy(wqe, ((void *) (uintptr_t)
 313                                                wr->sg_list[i].addr),
 314                                                wr->sg_list[i].length);
 315                                         wqe += wr->sg_list[i].length;
 316                                 }
 317                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 318                         } else {
 319                                 /* sqe num is two */
 320                                 for (i = 0; i < wr->num_sge; i++)
 321                                         set_data_seg(dseg + i, wr->sg_list + i);
 322
 323                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 324                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 325                         }
 326                 }
 327         }
 328
 329 out:
 330         /* Set DB return */
 331         if (likely(nreq)) {
 332                 qp->sq.head += nreq;
 333
 334                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 335                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 336                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 337                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 338                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 339                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 340                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 341                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 342                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 343                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 344
 345                 doorbell[0] = sq_db.u32_4;
 346                 doorbell[1] = sq_db.u32_8;
 347
 348                 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
 349         }
 350
 351         spin_unlock_irqrestore(&qp->sq.lock, flags);
 352
 353         return ret;
 354 }
 355
 356 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 357                                  const struct ib_recv_wr *wr,
 358                                  const struct ib_recv_wr **bad_wr)
 359 {
 360         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 361         struct hns_roce_wqe_data_seg *scat = NULL;
 362         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 363         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 364         struct device *dev = &hr_dev->pdev->dev;
 365         struct hns_roce_rq_db rq_db = {};
 366         __le32 doorbell[2] = {0};
 367         unsigned long flags = 0;
 368         unsigned int wqe_idx;
 369         int ret = 0;
 370         int nreq;
 371         int i;
 372         u32 reg_val;
 373
 374         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 375
 376         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 377                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 378                         hr_qp->ibqp.recv_cq)) {
 379                         ret = -ENOMEM;
 380                         *bad_wr = wr;
 381                         goto out;
 382                 }
 383
 384                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 385
 386                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 387                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 388                                 wr->num_sge, hr_qp->rq.max_gs);
 389                         ret = -EINVAL;
 390                         *bad_wr = wr;
 391                         goto out;
 392                 }
 393
 394                 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 395
 396                 roce_set_field(ctrl->rwqe_byte_12,
 397                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 398                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 399                                wr->num_sge);
 400
 401                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 402
 403                 for (i = 0; i < wr->num_sge; i++)
 404                         set_data_seg(scat + i, wr->sg_list + i);
 405
 406                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 407         }
 408
 409 out:
 410         if (likely(nreq)) {
 411                 hr_qp->rq.head += nreq;
 412
 413                 if (ibqp->qp_type == IB_QPT_GSI) {
 414                         __le32 tmp;
 415
 416                         /* SW update GSI rq header */
 417                         reg_val = roce_read(to_hr_dev(ibqp->device),
 418                                             ROCEE_QP1C_CFG3_0_REG +
 419                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 420                         tmp = cpu_to_le32(reg_val);
 421                         roce_set_field(tmp,
 422                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 423                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 424                                        hr_qp->rq.head);
 425                         reg_val = le32_to_cpu(tmp);
 426                         roce_write(to_hr_dev(ibqp->device),
 427                                    ROCEE_QP1C_CFG3_0_REG +
 428                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 429                 } else {
 430                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 431                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 432                                        hr_qp->rq.head);
 433                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 434                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 435                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 436                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 437                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 438                                      1);
 439
 440                         doorbell[0] = rq_db.u32_4;
 441                         doorbell[1] = rq_db.u32_8;
 442
 443                         hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
 444                 }
 445         }
 446         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 447
 448         return ret;
 449 }
 450
 451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 452                                        int sdb_mode, int odb_mode)
 453 {
 454         __le32 tmp;
 455         u32 val;
 456
 457         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 458         tmp = cpu_to_le32(val);
 459         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 461         val = le32_to_cpu(tmp);
 462         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 463 }
 464
 465 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 466                                      u32 odb_mode)
 467 {
 468         __le32 tmp;
 469         u32 val;
 470
 471         /* Configure SDB/ODB extend mode */
 472         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 473         tmp = cpu_to_le32(val);
 474         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 475         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 476         val = le32_to_cpu(tmp);
 477         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 478 }
 479
 480 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 481                              u32 sdb_alful)
 482 {
 483         __le32 tmp;
 484         u32 val;
 485
 486         /* Configure SDB */
 487         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 488         tmp = cpu_to_le32(val);
 489         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 490                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 491         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 492                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 493         val = le32_to_cpu(tmp);
 494         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 495 }
 496
 497 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 498                              u32 odb_alful)
 499 {
 500         __le32 tmp;
 501         u32 val;
 502
 503         /* Configure ODB */
 504         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 505         tmp = cpu_to_le32(val);
 506         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 507                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 508         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 509                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 510         val = le32_to_cpu(tmp);
 511         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 512 }
 513
 514 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 515                                  u32 ext_sdb_alful)
 516 {
 517         struct hns_roce_v1_priv *priv = hr_dev->priv;
 518         struct hns_roce_db_table *db = &priv->db_table;
 519         struct device *dev = &hr_dev->pdev->dev;
 520         dma_addr_t sdb_dma_addr;
 521         __le32 tmp;
 522         u32 val;
 523
 524         /* Configure extend SDB threshold */
 525         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 526         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 527
 528         /* Configure extend SDB base addr */
 529         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 530         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 531
 532         /* Configure extend SDB depth */
 533         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 534         tmp = cpu_to_le32(val);
 535         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 536                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 537                        db->ext_db->esdb_dep);
 538         /*
 539          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 540          * using 4K page, and shift more 32 because of
 541          * caculating the high 32 bit value evaluated to hardware.
 542          */
 543         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 544                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 545         val = le32_to_cpu(tmp);
 546         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 547
 548         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 549         dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
 550                 ext_sdb_alept, ext_sdb_alful);
 551 }
 552
 553 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 554                                  u32 ext_odb_alful)
 555 {
 556         struct hns_roce_v1_priv *priv = hr_dev->priv;
 557         struct hns_roce_db_table *db = &priv->db_table;
 558         struct device *dev = &hr_dev->pdev->dev;
 559         dma_addr_t odb_dma_addr;
 560         __le32 tmp;
 561         u32 val;
 562
 563         /* Configure extend ODB threshold */
 564         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 565         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 566
 567         /* Configure extend ODB base addr */
 568         odb_dma_addr = db->ext_db->odb_buf_list->map;
 569         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 570
 571         /* Configure extend ODB depth */
 572         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 573         tmp = cpu_to_le32(val);
 574         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 575                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 576                        db->ext_db->eodb_dep);
 577         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 578                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 579                        db->ext_db->eodb_dep);
 580         val = le32_to_cpu(tmp);
 581         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 582
 583         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 584         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 585                 ext_odb_alept, ext_odb_alful);
 586 }
 587
 588 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 589                                 u32 odb_ext_mod)
 590 {
 591         struct hns_roce_v1_priv *priv = hr_dev->priv;
 592         struct hns_roce_db_table *db = &priv->db_table;
 593         struct device *dev = &hr_dev->pdev->dev;
 594         dma_addr_t sdb_dma_addr;
 595         dma_addr_t odb_dma_addr;
 596         int ret = 0;
 597
 598         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 599         if (!db->ext_db)
 600                 return -ENOMEM;
 601
 602         if (sdb_ext_mod) {
 603                 db->ext_db->sdb_buf_list = kmalloc(
 604                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 605                 if (!db->ext_db->sdb_buf_list) {
 606                         ret = -ENOMEM;
 607                         goto ext_sdb_buf_fail_out;
 608                 }
 609
 610                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 611                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 612                                                      &sdb_dma_addr, GFP_KERNEL);
 613                 if (!db->ext_db->sdb_buf_list->buf) {
 614                         ret = -ENOMEM;
 615                         goto alloc_sq_db_buf_fail;
 616                 }
 617                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 618
 619                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 620                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 621                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 622         } else
 623                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 624                                  HNS_ROCE_V1_SDB_ALFUL);
 625
 626         if (odb_ext_mod) {
 627                 db->ext_db->odb_buf_list = kmalloc(
 628                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 629                 if (!db->ext_db->odb_buf_list) {
 630                         ret = -ENOMEM;
 631                         goto ext_odb_buf_fail_out;
 632                 }
 633
 634                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 635                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 636                                                      &odb_dma_addr, GFP_KERNEL);
 637                 if (!db->ext_db->odb_buf_list->buf) {
 638                         ret = -ENOMEM;
 639                         goto alloc_otr_db_buf_fail;
 640                 }
 641                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 642
 643                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 644                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 645                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 646         } else
 647                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 648                                  HNS_ROCE_V1_ODB_ALFUL);
 649
 650         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 651
 652         return 0;
 653
 654 alloc_otr_db_buf_fail:
 655         kfree(db->ext_db->odb_buf_list);
 656
 657 ext_odb_buf_fail_out:
 658         if (sdb_ext_mod) {
 659                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 660                                   db->ext_db->sdb_buf_list->buf,
 661                                   db->ext_db->sdb_buf_list->map);
 662         }
 663
 664 alloc_sq_db_buf_fail:
 665         if (sdb_ext_mod)
 666                 kfree(db->ext_db->sdb_buf_list);
 667
 668 ext_sdb_buf_fail_out:
 669         kfree(db->ext_db);
 670         return ret;
 671 }
 672
 673 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 674                                                     struct ib_pd *pd)
 675 {
 676         struct device *dev = &hr_dev->pdev->dev;
 677         struct ib_qp_init_attr init_attr;
 678         struct ib_qp *qp;
 679
 680         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 681         init_attr.qp_type               = IB_QPT_RC;
 682         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 683         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 684         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 685
 686         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 687         if (IS_ERR(qp)) {
 688                 dev_err(dev, "Create loop qp for mr free failed!");
 689                 return NULL;
 690         }
 691
 692         return to_hr_qp(qp);
 693 }
 694
 695 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 696 {
 697         struct hns_roce_v1_priv *priv = hr_dev->priv;
 698         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 699         struct hns_roce_caps *caps = &hr_dev->caps;
 700         struct ib_device *ibdev = &hr_dev->ib_dev;
 701         struct device *dev = &hr_dev->pdev->dev;
 702         struct ib_cq_init_attr cq_init_attr;
 703         struct ib_qp_attr attr = { 0 };
 704         struct hns_roce_qp *hr_qp;
 705         struct ib_cq *cq;
 706         struct ib_pd *pd;
 707         union ib_gid dgid;
 708         __be64 subnet_prefix;
 709         int attr_mask = 0;
 710         int ret;
 711         int i, j;
 712         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 713         u8 phy_port;
 714         u8 port = 0;
 715         u8 sl;
 716
 717         /* Reserved cq for loop qp */
 718         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 719         cq_init_attr.comp_vector        = 0;
 720
 721         cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
 722         if (!cq)
 723                 return -ENOMEM;
 724
 725         ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
 726         if (ret) {
 727                 dev_err(dev, "Create cq for reserved loop qp failed!");
 728                 goto alloc_cq_failed;
 729         }
 730         free_mr->mr_free_cq = to_hr_cq(cq);
 731         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 732         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 733         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 734         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 735         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 736         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 737
 738         pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
 739         if (!pd) {
 740                 ret = -ENOMEM;
 741                 goto alloc_mem_failed;
 742         }
 743
 744         pd->device  = ibdev;
 745         ret = hns_roce_alloc_pd(pd, NULL);
 746         if (ret)
 747                 goto alloc_pd_failed;
 748
 749         free_mr->mr_free_pd = to_hr_pd(pd);
 750         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 751         free_mr->mr_free_pd->ibpd.uobject = NULL;
 752         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 753         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 754
 755         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 756         attr.pkey_index         = 0;
 757         attr.min_rnr_timer      = 0;
 758         /* Disable read ability */
 759         attr.max_dest_rd_atomic = 0;
 760         attr.max_rd_atomic      = 0;
 761         /* Use arbitrary values as rq_psn and sq_psn */
 762         attr.rq_psn             = 0x0808;
 763         attr.sq_psn             = 0x0808;
 764         attr.retry_cnt          = 7;
 765         attr.rnr_retry          = 7;
 766         attr.timeout            = 0x12;
 767         attr.path_mtu           = IB_MTU_256;
 768         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 769         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 770         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 771
 772         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 773         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 774                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 775                                 (i % HNS_ROCE_MAX_PORTS);
 776                 sl = i / HNS_ROCE_MAX_PORTS;
 777
 778                 for (j = 0; j < caps->num_ports; j++) {
 779                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 780                                 queue_en[i] = 1;
 781                                 port = j;
 782                                 break;
 783                         }
 784                 }
 785
 786                 if (!queue_en[i])
 787                         continue;
 788
 789                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 790                 if (!free_mr->mr_free_qp[i]) {
 791                         dev_err(dev, "Create loop qp failed!\n");
 792                         ret = -ENOMEM;
 793                         goto create_lp_qp_failed;
 794                 }
 795                 hr_qp = free_mr->mr_free_qp[i];
 796
 797                 hr_qp->port             = port;
 798                 hr_qp->phy_port         = phy_port;
 799                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 800                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 801                 hr_qp->ibqp.uobject     = NULL;
 802                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 803                 hr_qp->ibqp.pd          = pd;
 804                 hr_qp->ibqp.recv_cq     = cq;
 805                 hr_qp->ibqp.send_cq     = cq;
 806
 807                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 808                 rdma_ah_set_sl(&attr.ah_attr, sl);
 809                 attr.port_num           = port + 1;
 810
 811                 attr.dest_qp_num        = hr_qp->qpn;
 812                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 813                        hr_dev->dev_addr[port],
 814                        ETH_ALEN);
 815
 816                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 817                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 818                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 819                 dgid.raw[11] = 0xff;
 820                 dgid.raw[12] = 0xfe;
 821                 dgid.raw[8] ^= 2;
 822                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 823
 824                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 825                                             IB_QPS_RESET, IB_QPS_INIT);
 826                 if (ret) {
 827                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 828                         goto create_lp_qp_failed;
 829                 }
 830
 831                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 832                                             IB_QPS_INIT, IB_QPS_RTR);
 833                 if (ret) {
 834                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 835                         goto create_lp_qp_failed;
 836                 }
 837
 838                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 839                                             IB_QPS_RTR, IB_QPS_RTS);
 840                 if (ret) {
 841                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 842                         goto create_lp_qp_failed;
 843                 }
 844         }
 845
 846         return 0;
 847
 848 create_lp_qp_failed:
 849         for (i -= 1; i >= 0; i--) {
 850                 hr_qp = free_mr->mr_free_qp[i];
 851                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
 852                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 853         }
 854
 855         hns_roce_dealloc_pd(pd, NULL);
 856
 857 alloc_pd_failed:
 858         kfree(pd);
 859
 860 alloc_mem_failed:
 861         hns_roce_destroy_cq(cq, NULL);
 862 alloc_cq_failed:
 863         kfree(cq);
 864         return ret;
 865 }
 866
 867 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 868 {
 869         struct hns_roce_v1_priv *priv = hr_dev->priv;
 870         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 871         struct device *dev = &hr_dev->pdev->dev;
 872         struct hns_roce_qp *hr_qp;
 873         int ret;
 874         int i;
 875
 876         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 877                 hr_qp = free_mr->mr_free_qp[i];
 878                 if (!hr_qp)
 879                         continue;
 880
 881                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
 882                 if (ret)
 883                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 884                                 i, ret);
 885         }
 886
 887         hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
 888         kfree(&free_mr->mr_free_cq->ib_cq);
 889         hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
 890         kfree(&free_mr->mr_free_pd->ibpd);
 891 }
 892
 893 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 894 {
 895         struct hns_roce_v1_priv *priv = hr_dev->priv;
 896         struct hns_roce_db_table *db = &priv->db_table;
 897         struct device *dev = &hr_dev->pdev->dev;
 898         u32 sdb_ext_mod;
 899         u32 odb_ext_mod;
 900         u32 sdb_evt_mod;
 901         u32 odb_evt_mod;
 902         int ret;
 903
 904         memset(db, 0, sizeof(*db));
 905
 906         /* Default DB mode */
 907         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 908         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 909         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 910         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 911
 912         db->sdb_ext_mod = sdb_ext_mod;
 913         db->odb_ext_mod = odb_ext_mod;
 914
 915         /* Init extend DB */
 916         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 917         if (ret) {
 918                 dev_err(dev, "Failed in extend DB configuration.\n");
 919                 return ret;
 920         }
 921
 922         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 923
 924         return 0;
 925 }
 926
 927 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 928 {
 929         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 930         struct hns_roce_dev *hr_dev;
 931
 932         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 933                                   work);
 934         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 935
 936         hns_roce_v1_release_lp_qp(hr_dev);
 937
 938         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 939                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 940
 941         if (lp_qp_work->comp_flag)
 942                 complete(lp_qp_work->comp);
 943
 944         kfree(lp_qp_work);
 945 }
 946
 947 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 948 {
 949         long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
 950         struct hns_roce_v1_priv *priv = hr_dev->priv;
 951         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 952         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 953         struct device *dev = &hr_dev->pdev->dev;
 954         struct completion comp;
 955
 956         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 957                              GFP_KERNEL);
 958         if (!lp_qp_work)
 959                 return -ENOMEM;
 960
 961         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 962
 963         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 964         lp_qp_work->comp = &comp;
 965         lp_qp_work->comp_flag = 1;
 966
 967         init_completion(lp_qp_work->comp);
 968
 969         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 970
 971         while (end > 0) {
 972                 if (try_wait_for_completion(&comp))
 973                         return 0;
 974                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 975                 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
 976         }
 977
 978         lp_qp_work->comp_flag = 0;
 979         if (try_wait_for_completion(&comp))
 980                 return 0;
 981
 982         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
 983         return -ETIMEDOUT;
 984 }
 985
 986 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
 987 {
 988         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
 989         struct device *dev = &hr_dev->pdev->dev;
 990         struct ib_send_wr send_wr;
 991         const struct ib_send_wr *bad_wr;
 992         int ret;
 993
 994         memset(&send_wr, 0, sizeof(send_wr));
 995         send_wr.next    = NULL;
 996         send_wr.num_sge = 0;
 997         send_wr.send_flags = 0;
 998         send_wr.sg_list = NULL;
 999         send_wr.wr_id   = (unsigned long long)&send_wr;
1000         send_wr.opcode  = IB_WR_RDMA_WRITE;
1001
1002         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1003         if (ret) {
1004                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1005                 return ret;
1006         }
1007
1008         return 0;
1009 }
1010
1011 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1012 {
1013         unsigned long end =
1014                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1015         struct hns_roce_mr_free_work *mr_work =
1016                 container_of(work, struct hns_roce_mr_free_work, work);
1017         struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1018         struct hns_roce_v1_priv *priv = hr_dev->priv;
1019         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1020         struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1021         struct hns_roce_mr *hr_mr = mr_work->mr;
1022         struct device *dev = &hr_dev->pdev->dev;
1023         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1024         struct hns_roce_qp *hr_qp;
1025         int ne = 0;
1026         int ret;
1027         int i;
1028
1029         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1030                 hr_qp = free_mr->mr_free_qp[i];
1031                 if (!hr_qp)
1032                         continue;
1033                 ne++;
1034
1035                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1036                 if (ret) {
1037                         dev_err(dev,
1038                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1039                              hr_qp->qpn, ret);
1040                         goto free_work;
1041                 }
1042         }
1043
1044         if (!ne) {
1045                 dev_err(dev, "Reserved loop qp is absent!\n");
1046                 goto free_work;
1047         }
1048
1049         do {
1050                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1051                 if (ret < 0 && hr_qp) {
1052                         dev_err(dev,
1053                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1054                            hr_qp->qpn, ret, hr_mr->key, ne);
1055                         goto free_work;
1056                 }
1057                 ne -= ret;
1058                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1059                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1060         } while (ne && time_before_eq(jiffies, end));
1061
1062         if (ne != 0)
1063                 dev_err(dev,
1064                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1065                         hr_mr->key, ne);
1066
1067 free_work:
1068         if (mr_work->comp_flag)
1069                 complete(mr_work->comp);
1070         kfree(mr_work);
1071 }
1072
1073 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1074                                 struct hns_roce_mr *mr, struct ib_udata *udata)
1075 {
1076         struct hns_roce_v1_priv *priv = hr_dev->priv;
1077         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1078         long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1079         struct device *dev = &hr_dev->pdev->dev;
1080         struct hns_roce_mr_free_work *mr_work;
1081         unsigned long start = jiffies;
1082         struct completion comp;
1083         int ret = 0;
1084
1085         if (mr->enabled) {
1086                 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1087                                             key_to_hw_index(mr->key) &
1088                                             (hr_dev->caps.num_mtpts - 1)))
1089                         dev_warn(dev, "DESTROY_MPT failed!\n");
1090         }
1091
1092         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1093         if (!mr_work) {
1094                 ret = -ENOMEM;
1095                 goto free_mr;
1096         }
1097
1098         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1099
1100         mr_work->ib_dev = &(hr_dev->ib_dev);
1101         mr_work->comp = &comp;
1102         mr_work->comp_flag = 1;
1103         mr_work->mr = (void *)mr;
1104         init_completion(mr_work->comp);
1105
1106         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1107
1108         while (end > 0) {
1109                 if (try_wait_for_completion(&comp))
1110                         goto free_mr;
1111                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1112                 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1113         }
1114
1115         mr_work->comp_flag = 0;
1116         if (try_wait_for_completion(&comp))
1117                 goto free_mr;
1118
1119         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1120         ret = -ETIMEDOUT;
1121
1122 free_mr:
1123         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1124                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1125
1126         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1127                              key_to_hw_index(mr->key), 0);
1128         hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1129         kfree(mr);
1130
1131         return ret;
1132 }
1133
1134 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1135 {
1136         struct hns_roce_v1_priv *priv = hr_dev->priv;
1137         struct hns_roce_db_table *db = &priv->db_table;
1138         struct device *dev = &hr_dev->pdev->dev;
1139
1140         if (db->sdb_ext_mod) {
1141                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1142                                   db->ext_db->sdb_buf_list->buf,
1143                                   db->ext_db->sdb_buf_list->map);
1144                 kfree(db->ext_db->sdb_buf_list);
1145         }
1146
1147         if (db->odb_ext_mod) {
1148                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1149                                   db->ext_db->odb_buf_list->buf,
1150                                   db->ext_db->odb_buf_list->map);
1151                 kfree(db->ext_db->odb_buf_list);
1152         }
1153
1154         kfree(db->ext_db);
1155 }
1156
1157 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1158 {
1159         struct hns_roce_v1_priv *priv = hr_dev->priv;
1160         struct hns_roce_raq_table *raq = &priv->raq_table;
1161         struct device *dev = &hr_dev->pdev->dev;
1162         dma_addr_t addr;
1163         int raq_shift;
1164         __le32 tmp;
1165         u32 val;
1166         int ret;
1167
1168         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1169         if (!raq->e_raq_buf)
1170                 return -ENOMEM;
1171
1172         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1173                                                  &addr, GFP_KERNEL);
1174         if (!raq->e_raq_buf->buf) {
1175                 ret = -ENOMEM;
1176                 goto err_dma_alloc_raq;
1177         }
1178         raq->e_raq_buf->map = addr;
1179
1180         /* Configure raq extended address. 48bit 4K align */
1181         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1182
1183         /* Configure raq_shift */
1184         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1185         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1186         tmp = cpu_to_le32(val);
1187         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1188                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1189         /*
1190          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1191          * using 4K page, and shift more 32 because of
1192          * caculating the high 32 bit value evaluated to hardware.
1193          */
1194         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1195                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1196                        raq->e_raq_buf->map >> 44);
1197         val = le32_to_cpu(tmp);
1198         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1199         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1200
1201         /* Configure raq threshold */
1202         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1203         tmp = cpu_to_le32(val);
1204         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1205                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1206                        HNS_ROCE_V1_EXT_RAQ_WF);
1207         val = le32_to_cpu(tmp);
1208         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1209         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1210
1211         /* Enable extend raq */
1212         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1213         tmp = cpu_to_le32(val);
1214         roce_set_field(tmp,
1215                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1216                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1217                        POL_TIME_INTERVAL_VAL);
1218         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1219         roce_set_field(tmp,
1220                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1221                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1222                        2);
1223         roce_set_bit(tmp,
1224                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1225         val = le32_to_cpu(tmp);
1226         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1227         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1228
1229         /* Enable raq drop */
1230         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1231         tmp = cpu_to_le32(val);
1232         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1233         val = le32_to_cpu(tmp);
1234         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1235         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1236
1237         return 0;
1238
1239 err_dma_alloc_raq:
1240         kfree(raq->e_raq_buf);
1241         return ret;
1242 }
1243
1244 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1245 {
1246         struct hns_roce_v1_priv *priv = hr_dev->priv;
1247         struct hns_roce_raq_table *raq = &priv->raq_table;
1248         struct device *dev = &hr_dev->pdev->dev;
1249
1250         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1251                           raq->e_raq_buf->map);
1252         kfree(raq->e_raq_buf);
1253 }
1254
1255 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1256 {
1257         __le32 tmp;
1258         u32 val;
1259
1260         if (enable_flag) {
1261                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1262                  /* Open all ports */
1263                 tmp = cpu_to_le32(val);
1264                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1265                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1266                                ALL_PORT_VAL_OPEN);
1267                 val = le32_to_cpu(tmp);
1268                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1269         } else {
1270                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1271                 /* Close all ports */
1272                 tmp = cpu_to_le32(val);
1273                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1274                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1275                 val = le32_to_cpu(tmp);
1276                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1277         }
1278 }
1279
1280 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1281 {
1282         struct hns_roce_v1_priv *priv = hr_dev->priv;
1283         struct device *dev = &hr_dev->pdev->dev;
1284         int ret;
1285
1286         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1287                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1288                 GFP_KERNEL);
1289         if (!priv->bt_table.qpc_buf.buf)
1290                 return -ENOMEM;
1291
1292         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1293                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1294                 GFP_KERNEL);
1295         if (!priv->bt_table.mtpt_buf.buf) {
1296                 ret = -ENOMEM;
1297                 goto err_failed_alloc_mtpt_buf;
1298         }
1299
1300         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1301                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1302                 GFP_KERNEL);
1303         if (!priv->bt_table.cqc_buf.buf) {
1304                 ret = -ENOMEM;
1305                 goto err_failed_alloc_cqc_buf;
1306         }
1307
1308         return 0;
1309
1310 err_failed_alloc_cqc_buf:
1311         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1312                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1313
1314 err_failed_alloc_mtpt_buf:
1315         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1316                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1317
1318         return ret;
1319 }
1320
1321 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1322 {
1323         struct hns_roce_v1_priv *priv = hr_dev->priv;
1324         struct device *dev = &hr_dev->pdev->dev;
1325
1326         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1327                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1328
1329         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1330                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1331
1332         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1333                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1334 }
1335
1336 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1337 {
1338         struct hns_roce_v1_priv *priv = hr_dev->priv;
1339         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1340         struct device *dev = &hr_dev->pdev->dev;
1341
1342         /*
1343          * This buffer will be used for CQ's tptr(tail pointer), also
1344          * named ci(customer index). Every CQ will use 2 bytes to save
1345          * cqe ci in hip06. Hardware will read this area to get new ci
1346          * when the queue is almost full.
1347          */
1348         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1349                                            &tptr_buf->map, GFP_KERNEL);
1350         if (!tptr_buf->buf)
1351                 return -ENOMEM;
1352
1353         hr_dev->tptr_dma_addr = tptr_buf->map;
1354         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1355
1356         return 0;
1357 }
1358
1359 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1360 {
1361         struct hns_roce_v1_priv *priv = hr_dev->priv;
1362         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1363         struct device *dev = &hr_dev->pdev->dev;
1364
1365         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1366                           tptr_buf->buf, tptr_buf->map);
1367 }
1368
1369 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1370 {
1371         struct hns_roce_v1_priv *priv = hr_dev->priv;
1372         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1373         struct device *dev = &hr_dev->pdev->dev;
1374         int ret;
1375
1376         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1377         if (!free_mr->free_mr_wq) {
1378                 dev_err(dev, "Create free mr workqueue failed!\n");
1379                 return -ENOMEM;
1380         }
1381
1382         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1383         if (ret) {
1384                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1385                 flush_workqueue(free_mr->free_mr_wq);
1386                 destroy_workqueue(free_mr->free_mr_wq);
1387         }
1388
1389         return ret;
1390 }
1391
1392 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1393 {
1394         struct hns_roce_v1_priv *priv = hr_dev->priv;
1395         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1396
1397         flush_workqueue(free_mr->free_mr_wq);
1398         destroy_workqueue(free_mr->free_mr_wq);
1399
1400         hns_roce_v1_release_lp_qp(hr_dev);
1401 }
1402
1403 /**
1404  * hns_roce_v1_reset - reset RoCE
1405  * @hr_dev: RoCE device struct pointer
1406  * @dereset: true -- drop reset, false -- reset
1407  * return 0 - success , negative --fail
1408  */
1409 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1410 {
1411         struct device_node *dsaf_node;
1412         struct device *dev = &hr_dev->pdev->dev;
1413         struct device_node *np = dev->of_node;
1414         struct fwnode_handle *fwnode;
1415         int ret;
1416
1417         /* check if this is DT/ACPI case */
1418         if (dev_of_node(dev)) {
1419                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1420                 if (!dsaf_node) {
1421                         dev_err(dev, "could not find dsaf-handle\n");
1422                         return -EINVAL;
1423                 }
1424                 fwnode = &dsaf_node->fwnode;
1425         } else if (is_acpi_device_node(dev->fwnode)) {
1426                 struct fwnode_reference_args args;
1427
1428                 ret = acpi_node_get_property_reference(dev->fwnode,
1429                                                        "dsaf-handle", 0, &args);
1430                 if (ret) {
1431                         dev_err(dev, "could not find dsaf-handle\n");
1432                         return ret;
1433                 }
1434                 fwnode = args.fwnode;
1435         } else {
1436                 dev_err(dev, "cannot read data from DT or ACPI\n");
1437                 return -ENXIO;
1438         }
1439
1440         ret = hns_dsaf_roce_reset(fwnode, false);
1441         if (ret)
1442                 return ret;
1443
1444         if (dereset) {
1445                 msleep(SLEEP_TIME_INTERVAL);
1446                 ret = hns_dsaf_roce_reset(fwnode, true);
1447         }
1448
1449         return ret;
1450 }
1451
1452 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1453 {
1454         struct hns_roce_caps *caps = &hr_dev->caps;
1455         int i;
1456
1457         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1458         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1459         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1460                                 ((u64)roce_read(hr_dev,
1461                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1462         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1463
1464         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1465         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1466         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1467         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1468         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1469         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1470         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1471         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1472         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1473         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1474         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1475         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1476         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1477         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1478         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1479         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1480         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1481         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1482         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1483         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1484         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1485         caps->qpc_sz            = HNS_ROCE_V1_QPC_SIZE;
1486         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1487         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1488         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1489         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1490         caps->cqe_sz            = HNS_ROCE_V1_CQE_SIZE;
1491         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1492         caps->reserved_lkey     = 0;
1493         caps->reserved_pds      = 0;
1494         caps->reserved_mrws     = 1;
1495         caps->reserved_uars     = 0;
1496         caps->reserved_cqs      = 0;
1497         caps->reserved_qps      = 12; /* 2 SQP per port, six ports total 12 */
1498         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1499
1500         for (i = 0; i < caps->num_ports; i++)
1501                 caps->pkey_table_len[i] = 1;
1502
1503         for (i = 0; i < caps->num_ports; i++) {
1504                 /* Six ports shared 16 GID in v1 engine */
1505                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1506                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1507                                                  caps->num_ports;
1508                 else
1509                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1510                                                  caps->num_ports + 1;
1511         }
1512
1513         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1514         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1515         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1516         caps->max_mtu = IB_MTU_2048;
1517
1518         return 0;
1519 }
1520
1521 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1522 {
1523         int ret;
1524         u32 val;
1525         __le32 tmp;
1526         struct device *dev = &hr_dev->pdev->dev;
1527
1528         /* DMAE user config */
1529         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1530         tmp = cpu_to_le32(val);
1531         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1532                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1533         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1534                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1535                        1 << PAGES_SHIFT_16);
1536         val = le32_to_cpu(tmp);
1537         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1538
1539         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1540         tmp = cpu_to_le32(val);
1541         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1542                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1543         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1544                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1545                        1 << PAGES_SHIFT_16);
1546
1547         ret = hns_roce_db_init(hr_dev);
1548         if (ret) {
1549                 dev_err(dev, "doorbell init failed!\n");
1550                 return ret;
1551         }
1552
1553         ret = hns_roce_raq_init(hr_dev);
1554         if (ret) {
1555                 dev_err(dev, "raq init failed!\n");
1556                 goto error_failed_raq_init;
1557         }
1558
1559         ret = hns_roce_bt_init(hr_dev);
1560         if (ret) {
1561                 dev_err(dev, "bt init failed!\n");
1562                 goto error_failed_bt_init;
1563         }
1564
1565         ret = hns_roce_tptr_init(hr_dev);
1566         if (ret) {
1567                 dev_err(dev, "tptr init failed!\n");
1568                 goto error_failed_tptr_init;
1569         }
1570
1571         ret = hns_roce_free_mr_init(hr_dev);
1572         if (ret) {
1573                 dev_err(dev, "free mr init failed!\n");
1574                 goto error_failed_free_mr_init;
1575         }
1576
1577         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1578
1579         return 0;
1580
1581 error_failed_free_mr_init:
1582         hns_roce_tptr_free(hr_dev);
1583
1584 error_failed_tptr_init:
1585         hns_roce_bt_free(hr_dev);
1586
1587 error_failed_bt_init:
1588         hns_roce_raq_free(hr_dev);
1589
1590 error_failed_raq_init:
1591         hns_roce_db_free(hr_dev);
1592         return ret;
1593 }
1594
1595 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1596 {
1597         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1598         hns_roce_free_mr_free(hr_dev);
1599         hns_roce_tptr_free(hr_dev);
1600         hns_roce_bt_free(hr_dev);
1601         hns_roce_raq_free(hr_dev);
1602         hns_roce_db_free(hr_dev);
1603 }
1604
1605 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1606 {
1607         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1608
1609         return (!!(status & (1 << HCR_GO_BIT)));
1610 }
1611
1612 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1613                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1614                                  u16 op, u16 token, int event)
1615 {
1616         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1617         unsigned long end;
1618         u32 val = 0;
1619         __le32 tmp;
1620
1621         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1622         while (hns_roce_v1_cmd_pending(hr_dev)) {
1623                 if (time_after(jiffies, end)) {
1624                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1625                                 (int)jiffies, (int)end);
1626                         return -EAGAIN;
1627                 }
1628                 cond_resched();
1629         }
1630
1631         tmp = cpu_to_le32(val);
1632         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1633                        op);
1634         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1635                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1636         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1637         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1638         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1639                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1640
1641         val = le32_to_cpu(tmp);
1642         writeq(in_param, hcr + 0);
1643         writeq(out_param, hcr + 2);
1644         writel(in_modifier, hcr + 4);
1645         /* Memory barrier */
1646         wmb();
1647
1648         writel(val, hcr + 5);
1649
1650         return 0;
1651 }
1652
1653 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1654                                 unsigned int timeout)
1655 {
1656         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1657         unsigned long end;
1658         u32 status = 0;
1659
1660         end = msecs_to_jiffies(timeout) + jiffies;
1661         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1662                 cond_resched();
1663
1664         if (hns_roce_v1_cmd_pending(hr_dev)) {
1665                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1666                 return -ETIMEDOUT;
1667         }
1668
1669         status = le32_to_cpu((__force __le32)
1670                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1671         if ((status & STATUS_MASK) != 0x1) {
1672                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1673                 return -EBUSY;
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1680                                int gid_index, const union ib_gid *gid,
1681                                const struct ib_gid_attr *attr)
1682 {
1683         unsigned long flags;
1684         u32 *p = NULL;
1685         u8 gid_idx;
1686
1687         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1688
1689         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1690
1691         p = (u32 *)&gid->raw[0];
1692         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1693                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1694
1695         p = (u32 *)&gid->raw[4];
1696         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1697                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1698
1699         p = (u32 *)&gid->raw[8];
1700         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1701                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1702
1703         p = (u32 *)&gid->raw[0xc];
1704         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1705                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1706
1707         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1708
1709         return 0;
1710 }
1711
1712 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1713                                u8 *addr)
1714 {
1715         u32 reg_smac_l;
1716         u16 reg_smac_h;
1717         __le32 tmp;
1718         u16 *p_h;
1719         u32 *p;
1720         u32 val;
1721
1722         /*
1723          * When mac changed, loopback may fail
1724          * because of smac not equal to dmac.
1725          * We Need to release and create reserved qp again.
1726          */
1727         if (hr_dev->hw->dereg_mr) {
1728                 int ret;
1729
1730                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1731                 if (ret && ret != -ETIMEDOUT)
1732                         return ret;
1733         }
1734
1735         p = (u32 *)(&addr[0]);
1736         reg_smac_l = *p;
1737         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1738                        PHY_PORT_OFFSET * phy_port);
1739
1740         val = roce_read(hr_dev,
1741                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1742         tmp = cpu_to_le32(val);
1743         p_h = (u16 *)(&addr[4]);
1744         reg_smac_h  = *p_h;
1745         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1746                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1747         val = le32_to_cpu(tmp);
1748         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1749                    val);
1750
1751         return 0;
1752 }
1753
1754 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1755                                 enum ib_mtu mtu)
1756 {
1757         __le32 tmp;
1758         u32 val;
1759
1760         val = roce_read(hr_dev,
1761                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1762         tmp = cpu_to_le32(val);
1763         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1764                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1765         val = le32_to_cpu(tmp);
1766         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1767                    val);
1768 }
1769
1770 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1771                                   struct hns_roce_mr *mr,
1772                                   unsigned long mtpt_idx)
1773 {
1774         u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1775         struct ib_device *ibdev = &hr_dev->ib_dev;
1776         struct hns_roce_v1_mpt_entry *mpt_entry;
1777         dma_addr_t pbl_ba;
1778         int count;
1779         int i;
1780
1781         /* MPT filled into mailbox buf */
1782         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1783         memset(mpt_entry, 0, sizeof(*mpt_entry));
1784
1785         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1786                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1787         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1788                        MPT_BYTE_4_KEY_S, mr->key);
1789         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1790                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1791         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1792         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1793                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1794         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1795         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1796                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1797         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1798         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1799                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1800         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1801                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1802         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1803                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1804         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1805                      0);
1806         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1807
1808         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1809                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1810         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1811                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1812
1813         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1814         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1815         mpt_entry->length = cpu_to_le32((u32)mr->size);
1816
1817         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1818                        MPT_BYTE_28_PD_S, mr->pd);
1819         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1820                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1821         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1822                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1823
1824         /* DMA memory register */
1825         if (mr->type == MR_TYPE_DMA)
1826                 return 0;
1827
1828         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1829                                   ARRAY_SIZE(pages), &pbl_ba);
1830         if (count < 1) {
1831                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1832                 return -ENOBUFS;
1833         }
1834
1835         /* Register user mr */
1836         for (i = 0; i < count; i++) {
1837                 switch (i) {
1838                 case 0:
1839                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1840                         roce_set_field(mpt_entry->mpt_byte_36,
1841                                 MPT_BYTE_36_PA0_H_M,
1842                                 MPT_BYTE_36_PA0_H_S,
1843                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1844                         break;
1845                 case 1:
1846                         roce_set_field(mpt_entry->mpt_byte_36,
1847                                        MPT_BYTE_36_PA1_L_M,
1848                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1849                         roce_set_field(mpt_entry->mpt_byte_40,
1850                                 MPT_BYTE_40_PA1_H_M,
1851                                 MPT_BYTE_40_PA1_H_S,
1852                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1853                         break;
1854                 case 2:
1855                         roce_set_field(mpt_entry->mpt_byte_40,
1856                                        MPT_BYTE_40_PA2_L_M,
1857                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1858                         roce_set_field(mpt_entry->mpt_byte_44,
1859                                 MPT_BYTE_44_PA2_H_M,
1860                                 MPT_BYTE_44_PA2_H_S,
1861                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1862                         break;
1863                 case 3:
1864                         roce_set_field(mpt_entry->mpt_byte_44,
1865                                        MPT_BYTE_44_PA3_L_M,
1866                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1867                         roce_set_field(mpt_entry->mpt_byte_48,
1868                                 MPT_BYTE_48_PA3_H_M,
1869                                 MPT_BYTE_48_PA3_H_S,
1870                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1871                         break;
1872                 case 4:
1873                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1874                         roce_set_field(mpt_entry->mpt_byte_56,
1875                                 MPT_BYTE_56_PA4_H_M,
1876                                 MPT_BYTE_56_PA4_H_S,
1877                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1878                         break;
1879                 case 5:
1880                         roce_set_field(mpt_entry->mpt_byte_56,
1881                                        MPT_BYTE_56_PA5_L_M,
1882                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1883                         roce_set_field(mpt_entry->mpt_byte_60,
1884                                 MPT_BYTE_60_PA5_H_M,
1885                                 MPT_BYTE_60_PA5_H_S,
1886                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1887                         break;
1888                 case 6:
1889                         roce_set_field(mpt_entry->mpt_byte_60,
1890                                        MPT_BYTE_60_PA6_L_M,
1891                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1892                         roce_set_field(mpt_entry->mpt_byte_64,
1893                                 MPT_BYTE_64_PA6_H_M,
1894                                 MPT_BYTE_64_PA6_H_S,
1895                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1896                         break;
1897                 default:
1898                         break;
1899                 }
1900         }
1901
1902         mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1903         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1904                        MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1905
1906         return 0;
1907 }
1908
1909 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1910 {
1911         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1912 }
1913
1914 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1915 {
1916         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1917
1918         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1919         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1920                 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1921 }
1922
1923 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1924 {
1925         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1926 }
1927
1928 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1929 {
1930         __le32 doorbell[2];
1931
1932         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
1933         doorbell[1] = 0;
1934         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1935         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1936                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1937         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1938                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1939         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1940                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1941
1942         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1943 }
1944
1945 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1946                                    struct hns_roce_srq *srq)
1947 {
1948         struct hns_roce_cqe *cqe, *dest;
1949         u32 prod_index;
1950         int nfreed = 0;
1951         u8 owner_bit;
1952
1953         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1954              ++prod_index) {
1955                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1956                         break;
1957         }
1958
1959         /*
1960          * Now backwards through the CQ, removing CQ entries
1961          * that match our QP by overwriting them with next entries.
1962          */
1963         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1964                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1965                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1966                                      CQE_BYTE_16_LOCAL_QPN_S) &
1967                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
1968                         /* In v1 engine, not support SRQ */
1969                         ++nfreed;
1970                 } else if (nfreed) {
1971                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
1972                                        hr_cq->ib_cq.cqe);
1973                         owner_bit = roce_get_bit(dest->cqe_byte_4,
1974                                                  CQE_BYTE_4_OWNER_S);
1975                         memcpy(dest, cqe, sizeof(*cqe));
1976                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1977                                      owner_bit);
1978                 }
1979         }
1980
1981         if (nfreed) {
1982                 hr_cq->cons_index += nfreed;
1983                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1984         }
1985 }
1986
1987 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1988                                  struct hns_roce_srq *srq)
1989 {
1990         spin_lock_irq(&hr_cq->lock);
1991         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1992         spin_unlock_irq(&hr_cq->lock);
1993 }
1994
1995 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1996                                   struct hns_roce_cq *hr_cq, void *mb_buf,
1997                                   u64 *mtts, dma_addr_t dma_handle)
1998 {
1999         struct hns_roce_v1_priv *priv = hr_dev->priv;
2000         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
2001         struct hns_roce_cq_context *cq_context = mb_buf;
2002         dma_addr_t tptr_dma_addr;
2003         int offset;
2004
2005         memset(cq_context, 0, sizeof(*cq_context));
2006
2007         /* Get the tptr for this CQ. */
2008         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2009         tptr_dma_addr = tptr_buf->map + offset;
2010         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2011
2012         /* Register cq_context members */
2013         roce_set_field(cq_context->cqc_byte_4,
2014                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2015                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2016         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2017                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2018
2019         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2020
2021         roce_set_field(cq_context->cqc_byte_12,
2022                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2023                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2024                        ((u64)dma_handle >> 32));
2025         roce_set_field(cq_context->cqc_byte_12,
2026                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2027                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2028                        ilog2(hr_cq->cq_depth));
2029         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2030                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2031
2032         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2033
2034         roce_set_field(cq_context->cqc_byte_20,
2035                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2036                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2037         /* Dedicated hardware, directly set 0 */
2038         roce_set_field(cq_context->cqc_byte_20,
2039                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2040                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2041         /**
2042          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2043          * using 4K page, and shift more 32 because of
2044          * caculating the high 32 bit value evaluated to hardware.
2045          */
2046         roce_set_field(cq_context->cqc_byte_20,
2047                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2048                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2049                        tptr_dma_addr >> 44);
2050
2051         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2052
2053         roce_set_field(cq_context->cqc_byte_32,
2054                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2055                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2056         roce_set_bit(cq_context->cqc_byte_32,
2057                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2058         roce_set_bit(cq_context->cqc_byte_32,
2059                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2060         roce_set_bit(cq_context->cqc_byte_32,
2061                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2062         roce_set_bit(cq_context->cqc_byte_32,
2063                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2064                      0);
2065         /* The initial value of cq's ci is 0 */
2066         roce_set_field(cq_context->cqc_byte_32,
2067                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2068                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2069 }
2070
2071 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2072                                      enum ib_cq_notify_flags flags)
2073 {
2074         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2075         u32 notification_flag;
2076         __le32 doorbell[2] = {};
2077
2078         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2079                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2080         /*
2081          * flags = 0; Notification Flag = 1, next
2082          * flags = 1; Notification Flag = 0, solocited
2083          */
2084         doorbell[0] =
2085                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2086         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2087         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2088                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2089         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2090                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2091         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2092                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2093                        hr_cq->cqn | notification_flag);
2094
2095         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2096
2097         return 0;
2098 }
2099
2100 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2101                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2102 {
2103         int qpn;
2104         int is_send;
2105         u16 wqe_ctr;
2106         u32 status;
2107         u32 opcode;
2108         struct hns_roce_cqe *cqe;
2109         struct hns_roce_qp *hr_qp;
2110         struct hns_roce_wq *wq;
2111         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2112         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2113         struct device *dev = &hr_dev->pdev->dev;
2114
2115         /* Find cqe according consumer index */
2116         cqe = next_cqe_sw(hr_cq);
2117         if (!cqe)
2118                 return -EAGAIN;
2119
2120         ++hr_cq->cons_index;
2121         /* Memory barrier */
2122         rmb();
2123         /* 0->SQ, 1->RQ */
2124         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2125
2126         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2127         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2128                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2129                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2130                                      CQE_BYTE_20_PORT_NUM_S) +
2131                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2132                                      CQE_BYTE_16_LOCAL_QPN_S) *
2133                                      HNS_ROCE_MAX_PORTS;
2134         } else {
2135                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2136                                      CQE_BYTE_16_LOCAL_QPN_S);
2137         }
2138
2139         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2140                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2141                 if (unlikely(!hr_qp)) {
2142                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2143                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2144                         return -EINVAL;
2145                 }
2146
2147                 *cur_qp = hr_qp;
2148         }
2149
2150         wc->qp = &(*cur_qp)->ibqp;
2151         wc->vendor_err = 0;
2152
2153         status = roce_get_field(cqe->cqe_byte_4,
2154                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2155                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2156                                 HNS_ROCE_CQE_STATUS_MASK;
2157         switch (status) {
2158         case HNS_ROCE_CQE_SUCCESS:
2159                 wc->status = IB_WC_SUCCESS;
2160                 break;
2161         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2162                 wc->status = IB_WC_LOC_LEN_ERR;
2163                 break;
2164         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2165                 wc->status = IB_WC_LOC_QP_OP_ERR;
2166                 break;
2167         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2168                 wc->status = IB_WC_LOC_PROT_ERR;
2169                 break;
2170         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2171                 wc->status = IB_WC_WR_FLUSH_ERR;
2172                 break;
2173         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2174                 wc->status = IB_WC_MW_BIND_ERR;
2175                 break;
2176         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2177                 wc->status = IB_WC_BAD_RESP_ERR;
2178                 break;
2179         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2180                 wc->status = IB_WC_LOC_ACCESS_ERR;
2181                 break;
2182         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2183                 wc->status = IB_WC_REM_INV_REQ_ERR;
2184                 break;
2185         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2186                 wc->status = IB_WC_REM_ACCESS_ERR;
2187                 break;
2188         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2189                 wc->status = IB_WC_REM_OP_ERR;
2190                 break;
2191         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2192                 wc->status = IB_WC_RETRY_EXC_ERR;
2193                 break;
2194         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2195                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2196                 break;
2197         default:
2198                 wc->status = IB_WC_GENERAL_ERR;
2199                 break;
2200         }
2201
2202         /* CQE status error, directly return */
2203         if (wc->status != IB_WC_SUCCESS)
2204                 return 0;
2205
2206         if (is_send) {
2207                 /* SQ conrespond to CQE */
2208                 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2209                                                 roce_get_field(cqe->cqe_byte_4,
2210                                                 CQE_BYTE_4_WQE_INDEX_M,
2211                                                 CQE_BYTE_4_WQE_INDEX_S) &
2212                                                 ((*cur_qp)->sq.wqe_cnt-1));
2213                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2214                 case HNS_ROCE_WQE_OPCODE_SEND:
2215                         wc->opcode = IB_WC_SEND;
2216                         break;
2217                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2218                         wc->opcode = IB_WC_RDMA_READ;
2219                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2220                         break;
2221                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2222                         wc->opcode = IB_WC_RDMA_WRITE;
2223                         break;
2224                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2225                         wc->opcode = IB_WC_LOCAL_INV;
2226                         break;
2227                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2228                         wc->opcode = IB_WC_SEND;
2229                         break;
2230                 default:
2231                         wc->status = IB_WC_GENERAL_ERR;
2232                         break;
2233                 }
2234                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2235                                 IB_WC_WITH_IMM : 0);
2236
2237                 wq = &(*cur_qp)->sq;
2238                 if ((*cur_qp)->sq_signal_bits) {
2239                         /*
2240                          * If sg_signal_bit is 1,
2241                          * firstly tail pointer updated to wqe
2242                          * which current cqe correspond to
2243                          */
2244                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2245                                                       CQE_BYTE_4_WQE_INDEX_M,
2246                                                       CQE_BYTE_4_WQE_INDEX_S);
2247                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2248                                     (wq->wqe_cnt - 1);
2249                 }
2250                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2251                 ++wq->tail;
2252         } else {
2253                 /* RQ conrespond to CQE */
2254                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2255                 opcode = roce_get_field(cqe->cqe_byte_4,
2256                                         CQE_BYTE_4_OPERATION_TYPE_M,
2257                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2258                                         HNS_ROCE_CQE_OPCODE_MASK;
2259                 switch (opcode) {
2260                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2261                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2262                         wc->wc_flags = IB_WC_WITH_IMM;
2263                         wc->ex.imm_data =
2264                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2265                         break;
2266                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2267                         if (roce_get_bit(cqe->cqe_byte_4,
2268                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2269                                 wc->opcode = IB_WC_RECV;
2270                                 wc->wc_flags = IB_WC_WITH_IMM;
2271                                 wc->ex.imm_data = cpu_to_be32(
2272                                         le32_to_cpu(cqe->immediate_data));
2273                         } else {
2274                                 wc->opcode = IB_WC_RECV;
2275                                 wc->wc_flags = 0;
2276                         }
2277                         break;
2278                 default:
2279                         wc->status = IB_WC_GENERAL_ERR;
2280                         break;
2281                 }
2282
2283                 /* Update tail pointer, record wr_id */
2284                 wq = &(*cur_qp)->rq;
2285                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2286                 ++wq->tail;
2287                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2288                                             CQE_BYTE_20_SL_S);
2289                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2290                                                 CQE_BYTE_20_REMOTE_QPN_M,
2291                                                 CQE_BYTE_20_REMOTE_QPN_S);
2292                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2293                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2294                                               IB_WC_GRH : 0);
2295                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2296                                                      CQE_BYTE_28_P_KEY_IDX_M,
2297                                                      CQE_BYTE_28_P_KEY_IDX_S);
2298         }
2299
2300         return 0;
2301 }
2302
2303 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2304 {
2305         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2306         struct hns_roce_qp *cur_qp = NULL;
2307         unsigned long flags;
2308         int npolled;
2309         int ret;
2310
2311         spin_lock_irqsave(&hr_cq->lock, flags);
2312
2313         for (npolled = 0; npolled < num_entries; ++npolled) {
2314                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2315                 if (ret)
2316                         break;
2317         }
2318
2319         if (npolled) {
2320                 *hr_cq->tptr_addr = hr_cq->cons_index &
2321                         ((hr_cq->cq_depth << 1) - 1);
2322
2323                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2324         }
2325
2326         spin_unlock_irqrestore(&hr_cq->lock, flags);
2327
2328         if (ret == 0 || ret == -EAGAIN)
2329                 return npolled;
2330         else
2331                 return ret;
2332 }
2333
2334 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2335                                  struct hns_roce_hem_table *table, int obj,
2336                                  int step_idx)
2337 {
2338         struct hns_roce_v1_priv *priv = hr_dev->priv;
2339         struct device *dev = &hr_dev->pdev->dev;
2340         long end = HW_SYNC_TIMEOUT_MSECS;
2341         __le32 bt_cmd_val[2] = {0};
2342         unsigned long flags = 0;
2343         void __iomem *bt_cmd;
2344         u64 bt_ba = 0;
2345
2346         switch (table->type) {
2347         case HEM_TYPE_QPC:
2348                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2349                 break;
2350         case HEM_TYPE_MTPT:
2351                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2352                 break;
2353         case HEM_TYPE_CQC:
2354                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2355                 break;
2356         case HEM_TYPE_SRQC:
2357                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2358                 return -EINVAL;
2359         default:
2360                 return 0;
2361         }
2362         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2363                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2364         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2365                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2366         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2367         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2368
2369         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2370
2371         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2372
2373         while (1) {
2374                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2375                         if (!end) {
2376                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2377                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2378                                         flags);
2379                                 return -EBUSY;
2380                         }
2381                 } else {
2382                         break;
2383                 }
2384                 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2385                 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2386         }
2387
2388         bt_cmd_val[0] = cpu_to_le32(bt_ba);
2389         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2390                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2391         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2392
2393         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2394
2395         return 0;
2396 }
2397
2398 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2399                                  enum hns_roce_qp_state cur_state,
2400                                  enum hns_roce_qp_state new_state,
2401                                  struct hns_roce_qp_context *context,
2402                                  struct hns_roce_qp *hr_qp)
2403 {
2404         static const u16
2405         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2406                 [HNS_ROCE_QP_STATE_RST] = {
2407                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2408                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2409                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2410                 },
2411                 [HNS_ROCE_QP_STATE_INIT] = {
2412                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2413                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2414                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2415                  * We use RST2INIT cmd instead of INIT2INIT.
2416                  */
2417                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2418                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2419                 },
2420                 [HNS_ROCE_QP_STATE_RTR] = {
2421                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2422                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2423                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2424                 },
2425                 [HNS_ROCE_QP_STATE_RTS] = {
2426                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2427                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2428                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2429                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2430                 },
2431                 [HNS_ROCE_QP_STATE_SQD] = {
2432                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2433                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2434                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2435                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2436                 },
2437                 [HNS_ROCE_QP_STATE_ERR] = {
2438                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2439                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2440                 }
2441         };
2442
2443         struct hns_roce_cmd_mailbox *mailbox;
2444         struct device *dev = &hr_dev->pdev->dev;
2445         int ret;
2446
2447         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2448             new_state >= HNS_ROCE_QP_NUM_STATE ||
2449             !op[cur_state][new_state]) {
2450                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2451                         cur_state, new_state);
2452                 return -EINVAL;
2453         }
2454
2455         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2456                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2457                                          HNS_ROCE_CMD_2RST_QP,
2458                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2459
2460         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2461                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2462                                          HNS_ROCE_CMD_2ERR_QP,
2463                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2464
2465         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2466         if (IS_ERR(mailbox))
2467                 return PTR_ERR(mailbox);
2468
2469         memcpy(mailbox->buf, context, sizeof(*context));
2470
2471         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2472                                 op[cur_state][new_state],
2473                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2474
2475         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2476         return ret;
2477 }
2478
2479 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2480                         u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2481 {
2482         struct ib_device *ibdev = &hr_dev->ib_dev;
2483         int count;
2484
2485         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2486         if (count < 1) {
2487                 ibdev_err(ibdev, "Failed to find SQ ba\n");
2488                 return -ENOBUFS;
2489         }
2490
2491         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2492                                   1, NULL);
2493         if (!count) {
2494                 ibdev_err(ibdev, "Failed to find RQ ba\n");
2495                 return -ENOBUFS;
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2502                              int attr_mask, enum ib_qp_state cur_state,
2503                              enum ib_qp_state new_state)
2504 {
2505         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2506         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2507         struct hns_roce_sqp_context *context;
2508         dma_addr_t dma_handle = 0;
2509         u32 __iomem *addr;
2510         u64 sq_ba = 0;
2511         u64 rq_ba = 0;
2512         __le32 tmp;
2513         u32 reg_val;
2514
2515         context = kzalloc(sizeof(*context), GFP_KERNEL);
2516         if (!context)
2517                 return -ENOMEM;
2518
2519         /* Search QP buf's MTTs */
2520         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2521                 goto out;
2522
2523         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2524                 roce_set_field(context->qp1c_bytes_4,
2525                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2526                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2527                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2528                 roce_set_field(context->qp1c_bytes_4,
2529                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2530                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2531                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2532                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2533                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2534
2535                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2536                 roce_set_field(context->qp1c_bytes_12,
2537                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2538                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2539                                upper_32_bits(dma_handle));
2540
2541                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2542                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2543                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2544                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2545                 roce_set_bit(context->qp1c_bytes_16,
2546                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2547                              hr_qp->sq_signal_bits);
2548                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2549                              1);
2550                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2551                              1);
2552                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2553                              0);
2554
2555                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2556                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2557                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2558                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2559
2560                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2561
2562                 roce_set_field(context->qp1c_bytes_28,
2563                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2564                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2565                                upper_32_bits(rq_ba));
2566                 roce_set_field(context->qp1c_bytes_28,
2567                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2568                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2569
2570                 roce_set_field(context->qp1c_bytes_32,
2571                                QP1C_BYTES_32_RX_CQ_NUM_M,
2572                                QP1C_BYTES_32_RX_CQ_NUM_S,
2573                                to_hr_cq(ibqp->recv_cq)->cqn);
2574                 roce_set_field(context->qp1c_bytes_32,
2575                                QP1C_BYTES_32_TX_CQ_NUM_M,
2576                                QP1C_BYTES_32_TX_CQ_NUM_S,
2577                                to_hr_cq(ibqp->send_cq)->cqn);
2578
2579                 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2580
2581                 roce_set_field(context->qp1c_bytes_40,
2582                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2583                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2584                                upper_32_bits(sq_ba));
2585                 roce_set_field(context->qp1c_bytes_40,
2586                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2587                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2588
2589                 /* Copy context to QP1C register */
2590                 addr = (u32 __iomem *)(hr_dev->reg_base +
2591                                        ROCEE_QP1C_CFG0_0_REG +
2592                                        hr_qp->phy_port * sizeof(*context));
2593
2594                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2595                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2596                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2597                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2598                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2599                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2600                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2601                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2602                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2603                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2604         }
2605
2606         /* Modify QP1C status */
2607         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2608                             hr_qp->phy_port * sizeof(*context));
2609         tmp = cpu_to_le32(reg_val);
2610         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2611                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2612         reg_val = le32_to_cpu(tmp);
2613         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2614                     hr_qp->phy_port * sizeof(*context), reg_val);
2615
2616         hr_qp->state = new_state;
2617         if (new_state == IB_QPS_RESET) {
2618                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2619                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2620                 if (ibqp->send_cq != ibqp->recv_cq)
2621                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2622                                              hr_qp->qpn, NULL);
2623
2624                 hr_qp->rq.head = 0;
2625                 hr_qp->rq.tail = 0;
2626                 hr_qp->sq.head = 0;
2627                 hr_qp->sq.tail = 0;
2628         }
2629
2630         kfree(context);
2631         return 0;
2632
2633 out:
2634         kfree(context);
2635         return -EINVAL;
2636 }
2637
2638 static bool check_qp_state(enum ib_qp_state cur_state,
2639                            enum ib_qp_state new_state)
2640 {
2641         static const bool sm[][IB_QPS_ERR + 1] = {
2642                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2643                                    [IB_QPS_INIT] = true },
2644                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2645                                   [IB_QPS_INIT] = true,
2646                                   [IB_QPS_RTR] = true,
2647                                   [IB_QPS_ERR] = true },
2648                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2649                                  [IB_QPS_RTS] = true,
2650                                  [IB_QPS_ERR] = true },
2651                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2652                 [IB_QPS_SQD] = {},
2653                 [IB_QPS_SQE] = {},
2654                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2655         };
2656
2657         return sm[cur_state][new_state];
2658 }
2659
2660 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2661                             int attr_mask, enum ib_qp_state cur_state,
2662                             enum ib_qp_state new_state)
2663 {
2664         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2665         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2666         struct device *dev = &hr_dev->pdev->dev;
2667         struct hns_roce_qp_context *context;
2668         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2669         dma_addr_t dma_handle_2 = 0;
2670         dma_addr_t dma_handle = 0;
2671         __le32 doorbell[2] = {0};
2672         u64 *mtts_2 = NULL;
2673         int ret = -EINVAL;
2674         u64 sq_ba = 0;
2675         u64 rq_ba = 0;
2676         int port;
2677         u8 port_num;
2678         u8 *dmac;
2679         u8 *smac;
2680
2681         if (!check_qp_state(cur_state, new_state)) {
2682                 ibdev_err(ibqp->device,
2683                           "not support QP(%u) status from %d to %d\n",
2684                           ibqp->qp_num, cur_state, new_state);
2685                 return -EINVAL;
2686         }
2687
2688         context = kzalloc(sizeof(*context), GFP_KERNEL);
2689         if (!context)
2690                 return -ENOMEM;
2691
2692         /* Search qp buf's mtts */
2693         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2694                 goto out;
2695
2696         /* Search IRRL's mtts */
2697         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2698                                      hr_qp->qpn, &dma_handle_2);
2699         if (mtts_2 == NULL) {
2700                 dev_err(dev, "qp irrl_table find failed\n");
2701                 goto out;
2702         }
2703
2704         /*
2705          * Reset to init
2706          *      Mandatory param:
2707          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2708          *      Optional param: NA
2709          */
2710         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2711                 roce_set_field(context->qpc_bytes_4,
2712                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2713                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2714                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2715
2716                 roce_set_bit(context->qpc_bytes_4,
2717                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2718                 roce_set_bit(context->qpc_bytes_4,
2719                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2720                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2721                 roce_set_bit(context->qpc_bytes_4,
2722                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2723                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2724                              );
2725                 roce_set_bit(context->qpc_bytes_4,
2726                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2727                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2728                              );
2729                 roce_set_bit(context->qpc_bytes_4,
2730                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2731                 roce_set_field(context->qpc_bytes_4,
2732                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2733                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2734                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2735                 roce_set_field(context->qpc_bytes_4,
2736                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2737                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2738                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2739                 roce_set_field(context->qpc_bytes_4,
2740                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2741                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2742                                to_hr_pd(ibqp->pd)->pdn);
2743                 hr_qp->access_flags = attr->qp_access_flags;
2744                 roce_set_field(context->qpc_bytes_8,
2745                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2746                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2747                                to_hr_cq(ibqp->send_cq)->cqn);
2748                 roce_set_field(context->qpc_bytes_8,
2749                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2750                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2751                                to_hr_cq(ibqp->recv_cq)->cqn);
2752
2753                 if (ibqp->srq)
2754                         roce_set_field(context->qpc_bytes_12,
2755                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2756                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2757                                        to_hr_srq(ibqp->srq)->srqn);
2758
2759                 roce_set_field(context->qpc_bytes_12,
2760                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2761                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2762                                attr->pkey_index);
2763                 hr_qp->pkey_index = attr->pkey_index;
2764                 roce_set_field(context->qpc_bytes_16,
2765                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2766                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2767         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2768                 roce_set_field(context->qpc_bytes_4,
2769                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2770                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2771                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2772                 roce_set_bit(context->qpc_bytes_4,
2773                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2774                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2775                         roce_set_bit(context->qpc_bytes_4,
2776                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2777                                      !!(attr->qp_access_flags &
2778                                      IB_ACCESS_REMOTE_READ));
2779                         roce_set_bit(context->qpc_bytes_4,
2780                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2781                                      !!(attr->qp_access_flags &
2782                                      IB_ACCESS_REMOTE_WRITE));
2783                 } else {
2784                         roce_set_bit(context->qpc_bytes_4,
2785                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2786                                      !!(hr_qp->access_flags &
2787                                      IB_ACCESS_REMOTE_READ));
2788                         roce_set_bit(context->qpc_bytes_4,
2789                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2790                                      !!(hr_qp->access_flags &
2791                                      IB_ACCESS_REMOTE_WRITE));
2792                 }
2793
2794                 roce_set_bit(context->qpc_bytes_4,
2795                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2796                 roce_set_field(context->qpc_bytes_4,
2797                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2798                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2799                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2800                 roce_set_field(context->qpc_bytes_4,
2801                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2802                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2803                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2804                 roce_set_field(context->qpc_bytes_4,
2805                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2806                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2807                                to_hr_pd(ibqp->pd)->pdn);
2808
2809                 roce_set_field(context->qpc_bytes_8,
2810                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2811                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2812                                to_hr_cq(ibqp->send_cq)->cqn);
2813                 roce_set_field(context->qpc_bytes_8,
2814                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2815                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2816                                to_hr_cq(ibqp->recv_cq)->cqn);
2817
2818                 if (ibqp->srq)
2819                         roce_set_field(context->qpc_bytes_12,
2820                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2821                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2822                                        to_hr_srq(ibqp->srq)->srqn);
2823                 if (attr_mask & IB_QP_PKEY_INDEX)
2824                         roce_set_field(context->qpc_bytes_12,
2825                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2826                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2827                                        attr->pkey_index);
2828                 else
2829                         roce_set_field(context->qpc_bytes_12,
2830                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2831                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2832                                        hr_qp->pkey_index);
2833
2834                 roce_set_field(context->qpc_bytes_16,
2835                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2836                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2837         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2838                 if ((attr_mask & IB_QP_ALT_PATH) ||
2839                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2840                     (attr_mask & IB_QP_PKEY_INDEX) ||
2841                     (attr_mask & IB_QP_QKEY)) {
2842                         dev_err(dev, "INIT2RTR attr_mask error\n");
2843                         goto out;
2844                 }
2845
2846                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2847
2848                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2849                 roce_set_field(context->qpc_bytes_24,
2850                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2851                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2852                                upper_32_bits(dma_handle));
2853                 roce_set_bit(context->qpc_bytes_24,
2854                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2855                              1);
2856                 roce_set_field(context->qpc_bytes_24,
2857                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2858                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2859                                attr->min_rnr_timer);
2860                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2861                 roce_set_field(context->qpc_bytes_32,
2862                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2863                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2864                                ((u32)(dma_handle_2 >> 32)) &
2865                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2866                 roce_set_field(context->qpc_bytes_32,
2867                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2868                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2869                 roce_set_bit(context->qpc_bytes_32,
2870                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2871                              1);
2872                 roce_set_bit(context->qpc_bytes_32,
2873                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2874                              hr_qp->sq_signal_bits);
2875
2876                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2877                         hr_qp->port;
2878                 smac = (u8 *)hr_dev->dev_addr[port];
2879                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2880                 if (ether_addr_equal_unaligned(dmac, smac) ||
2881                     hr_dev->loop_idc == 0x1)
2882                         roce_set_bit(context->qpc_bytes_32,
2883                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2884
2885                 roce_set_bit(context->qpc_bytes_32,
2886                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2887                              rdma_ah_get_ah_flags(&attr->ah_attr));
2888                 roce_set_field(context->qpc_bytes_32,
2889                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2890                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2891                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2892
2893                 if (attr_mask & IB_QP_DEST_QPN)
2894                         roce_set_field(context->qpc_bytes_36,
2895                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2896                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2897                                        attr->dest_qp_num);
2898
2899                 /* Configure GID index */
2900                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2901                 roce_set_field(context->qpc_bytes_36,
2902                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2903                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2904                                 hns_get_gid_index(hr_dev,
2905                                                   port_num - 1,
2906                                                   grh->sgid_index));
2907
2908                 memcpy(&(context->dmac_l), dmac, 4);
2909
2910                 roce_set_field(context->qpc_bytes_44,
2911                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2912                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2913                                *((u16 *)(&dmac[4])));
2914                 roce_set_field(context->qpc_bytes_44,
2915                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2916                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2917                                rdma_ah_get_static_rate(&attr->ah_attr));
2918                 roce_set_field(context->qpc_bytes_44,
2919                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2920                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2921                                grh->hop_limit);
2922
2923                 roce_set_field(context->qpc_bytes_48,
2924                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2925                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2926                                grh->flow_label);
2927                 roce_set_field(context->qpc_bytes_48,
2928                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2929                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2930                                grh->traffic_class);
2931                 roce_set_field(context->qpc_bytes_48,
2932                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
2933                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2934
2935                 memcpy(context->dgid, grh->dgid.raw,
2936                        sizeof(grh->dgid.raw));
2937
2938                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2939                         roce_get_field(context->qpc_bytes_44,
2940                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2941                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2942
2943                 roce_set_field(context->qpc_bytes_68,
2944                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2945                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2946                                hr_qp->rq.head);
2947                 roce_set_field(context->qpc_bytes_68,
2948                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2949                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2950
2951                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2952
2953                 roce_set_field(context->qpc_bytes_76,
2954                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2955                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2956                         upper_32_bits(rq_ba));
2957                 roce_set_field(context->qpc_bytes_76,
2958                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2959                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2960
2961                 context->rx_rnr_time = 0;
2962
2963                 roce_set_field(context->qpc_bytes_84,
2964                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2965                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2966                                attr->rq_psn - 1);
2967                 roce_set_field(context->qpc_bytes_84,
2968                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2969                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2970
2971                 roce_set_field(context->qpc_bytes_88,
2972                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2973                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2974                                attr->rq_psn);
2975                 roce_set_bit(context->qpc_bytes_88,
2976                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2977                 roce_set_bit(context->qpc_bytes_88,
2978                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2979                 roce_set_field(context->qpc_bytes_88,
2980                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2981                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2982                         0);
2983                 roce_set_field(context->qpc_bytes_88,
2984                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2985                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2986                                0);
2987
2988                 context->dma_length = 0;
2989                 context->r_key = 0;
2990                 context->va_l = 0;
2991                 context->va_h = 0;
2992
2993                 roce_set_field(context->qpc_bytes_108,
2994                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2995                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2996                 roce_set_bit(context->qpc_bytes_108,
2997                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2998                 roce_set_bit(context->qpc_bytes_108,
2999                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3000
3001                 roce_set_field(context->qpc_bytes_112,
3002                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3003                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3004                 roce_set_field(context->qpc_bytes_112,
3005                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3006                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3007
3008                 /* For chip resp ack */
3009                 roce_set_field(context->qpc_bytes_156,
3010                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3011                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3012                                hr_qp->phy_port);
3013                 roce_set_field(context->qpc_bytes_156,
3014                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3015                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3016                                rdma_ah_get_sl(&attr->ah_attr));
3017                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3018         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3019                 /* If exist optional param, return error */
3020                 if ((attr_mask & IB_QP_ALT_PATH) ||
3021                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3022                     (attr_mask & IB_QP_QKEY) ||
3023                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3024                     (attr_mask & IB_QP_CUR_STATE) ||
3025                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3026                         dev_err(dev, "RTR2RTS attr_mask error\n");
3027                         goto out;
3028                 }
3029
3030                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3031
3032                 roce_set_field(context->qpc_bytes_120,
3033                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3034                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3035                                upper_32_bits(sq_ba));
3036
3037                 roce_set_field(context->qpc_bytes_124,
3038                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3039                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3040                 roce_set_field(context->qpc_bytes_124,
3041                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3042                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3043
3044                 roce_set_field(context->qpc_bytes_128,
3045                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3046                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3047                                attr->sq_psn);
3048                 roce_set_bit(context->qpc_bytes_128,
3049                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3050                 roce_set_field(context->qpc_bytes_128,
3051                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3052                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3053                              0);
3054                 roce_set_bit(context->qpc_bytes_128,
3055                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3056
3057                 roce_set_field(context->qpc_bytes_132,
3058                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3059                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3060                 roce_set_field(context->qpc_bytes_132,
3061                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3062                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3063
3064                 roce_set_field(context->qpc_bytes_136,
3065                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3066                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3067                                attr->sq_psn);
3068                 roce_set_field(context->qpc_bytes_136,
3069                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3070                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3071                                attr->sq_psn);
3072
3073                 roce_set_field(context->qpc_bytes_140,
3074                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3075                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3076                                (attr->sq_psn >> SQ_PSN_SHIFT));
3077                 roce_set_field(context->qpc_bytes_140,
3078                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3079                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3080                 roce_set_bit(context->qpc_bytes_140,
3081                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3082
3083                 roce_set_field(context->qpc_bytes_148,
3084                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3085                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3086                 roce_set_field(context->qpc_bytes_148,
3087                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3088                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3089                                attr->retry_cnt);
3090                 roce_set_field(context->qpc_bytes_148,
3091                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3092                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3093                                attr->rnr_retry);
3094                 roce_set_field(context->qpc_bytes_148,
3095                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3096                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3097
3098                 context->rnr_retry = 0;
3099
3100                 roce_set_field(context->qpc_bytes_156,
3101                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3102                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3103                                attr->retry_cnt);
3104                 if (attr->timeout < 0x12) {
3105                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3106                                  attr->timeout);
3107                         roce_set_field(context->qpc_bytes_156,
3108                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3109                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3110                                        0x12);
3111                 } else {
3112                         roce_set_field(context->qpc_bytes_156,
3113                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3114                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3115                                        attr->timeout);
3116                 }
3117                 roce_set_field(context->qpc_bytes_156,
3118                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3119                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3120                                attr->rnr_retry);
3121                 roce_set_field(context->qpc_bytes_156,
3122                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3123                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3124                                hr_qp->phy_port);
3125                 roce_set_field(context->qpc_bytes_156,
3126                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3127                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3128                                rdma_ah_get_sl(&attr->ah_attr));
3129                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3130                 roce_set_field(context->qpc_bytes_156,
3131                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3132                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3133                                ilog2((unsigned int)attr->max_rd_atomic));
3134                 roce_set_field(context->qpc_bytes_156,
3135                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3136                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3137                 context->pkt_use_len = 0;
3138
3139                 roce_set_field(context->qpc_bytes_164,
3140                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3141                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3142                 roce_set_field(context->qpc_bytes_164,
3143                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3144                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3145
3146                 roce_set_field(context->qpc_bytes_168,
3147                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3148                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3149                                attr->sq_psn);
3150                 roce_set_field(context->qpc_bytes_168,
3151                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3152                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3153                 roce_set_field(context->qpc_bytes_168,
3154                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3155                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3156                 roce_set_bit(context->qpc_bytes_168,
3157                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3158                 roce_set_bit(context->qpc_bytes_168,
3159                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3160                 roce_set_bit(context->qpc_bytes_168,
3161                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3162                 context->sge_use_len = 0;
3163
3164                 roce_set_field(context->qpc_bytes_176,
3165                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3166                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3167                 roce_set_field(context->qpc_bytes_176,
3168                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3169                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3170                                0);
3171                 roce_set_field(context->qpc_bytes_180,
3172                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3173                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3174                 roce_set_field(context->qpc_bytes_180,
3175                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3176                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3177
3178                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3179
3180                 roce_set_field(context->qpc_bytes_188,
3181                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3182                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3183                                upper_32_bits(sq_ba));
3184                 roce_set_bit(context->qpc_bytes_188,
3185                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3186                 roce_set_field(context->qpc_bytes_188,
3187                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3188                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3189                                0);
3190         }
3191
3192         /* Every status migrate must change state */
3193         roce_set_field(context->qpc_bytes_144,
3194                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3195                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3196
3197         /* SW pass context to HW */
3198         ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3199                                     to_hns_roce_state(new_state), context,
3200                                     hr_qp);
3201         if (ret) {
3202                 dev_err(dev, "hns_roce_qp_modify failed\n");
3203                 goto out;
3204         }
3205
3206         /*
3207          * Use rst2init to instead of init2init with drv,
3208          * need to hw to flash RQ HEAD by DB again
3209          */
3210         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3211                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3212                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3213                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3214                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3215                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3216                                RQ_DOORBELL_U32_8_CMD_S, 1);
3217                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3218
3219                 if (ibqp->uobject) {
3220                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3221                                      hr_dev->odb_offset +
3222                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3223                 }
3224
3225                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3226         }
3227
3228         hr_qp->state = new_state;
3229
3230         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3231                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3232         if (attr_mask & IB_QP_PORT) {
3233                 hr_qp->port = attr->port_num - 1;
3234                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3235         }
3236
3237         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3238                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3239                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3240                 if (ibqp->send_cq != ibqp->recv_cq)
3241                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3242                                              hr_qp->qpn, NULL);
3243
3244                 hr_qp->rq.head = 0;
3245                 hr_qp->rq.tail = 0;
3246                 hr_qp->sq.head = 0;
3247                 hr_qp->sq.tail = 0;
3248         }
3249 out:
3250         kfree(context);
3251         return ret;
3252 }
3253
3254 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3255                                  const struct ib_qp_attr *attr, int attr_mask,
3256                                  enum ib_qp_state cur_state,
3257                                  enum ib_qp_state new_state)
3258 {
3259         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
3260                 return -EOPNOTSUPP;
3261
3262         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3263                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3264                                          new_state);
3265         else
3266                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3267                                         new_state);
3268 }
3269
3270 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3271 {
3272         switch (state) {
3273         case HNS_ROCE_QP_STATE_RST:
3274                 return IB_QPS_RESET;
3275         case HNS_ROCE_QP_STATE_INIT:
3276                 return IB_QPS_INIT;
3277         case HNS_ROCE_QP_STATE_RTR:
3278                 return IB_QPS_RTR;
3279         case HNS_ROCE_QP_STATE_RTS:
3280                 return IB_QPS_RTS;
3281         case HNS_ROCE_QP_STATE_SQD:
3282                 return IB_QPS_SQD;
3283         case HNS_ROCE_QP_STATE_ERR:
3284                 return IB_QPS_ERR;
3285         default:
3286                 return IB_QPS_ERR;
3287         }
3288 }
3289
3290 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3291                                  struct hns_roce_qp *hr_qp,
3292                                  struct hns_roce_qp_context *hr_context)
3293 {
3294         struct hns_roce_cmd_mailbox *mailbox;
3295         int ret;
3296
3297         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3298         if (IS_ERR(mailbox))
3299                 return PTR_ERR(mailbox);
3300
3301         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3302                                 HNS_ROCE_CMD_QUERY_QP,
3303                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3304         if (!ret)
3305                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3306         else
3307                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3308
3309         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3310
3311         return ret;
3312 }
3313
3314 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3315                              int qp_attr_mask,
3316                              struct ib_qp_init_attr *qp_init_attr)
3317 {
3318         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3319         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3320         struct hns_roce_sqp_context context;
3321         u32 addr;
3322
3323         mutex_lock(&hr_qp->mutex);
3324
3325         if (hr_qp->state == IB_QPS_RESET) {
3326                 qp_attr->qp_state = IB_QPS_RESET;
3327                 goto done;
3328         }
3329
3330         addr = ROCEE_QP1C_CFG0_0_REG +
3331                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3332         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3333         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3334         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3335         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3336         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3337         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3338         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3339         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3340         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3341         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3342
3343         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3344                                       QP1C_BYTES_4_QP_STATE_M,
3345                                       QP1C_BYTES_4_QP_STATE_S);
3346         qp_attr->qp_state       = hr_qp->state;
3347         qp_attr->path_mtu       = IB_MTU_256;
3348         qp_attr->path_mig_state = IB_MIG_ARMED;
3349         qp_attr->qkey           = QKEY_VAL;
3350         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3351         qp_attr->rq_psn         = 0;
3352         qp_attr->sq_psn         = 0;
3353         qp_attr->dest_qp_num    = 1;
3354         qp_attr->qp_access_flags = 6;
3355
3356         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3357                                              QP1C_BYTES_20_PKEY_IDX_M,
3358                                              QP1C_BYTES_20_PKEY_IDX_S);
3359         qp_attr->port_num = hr_qp->port + 1;
3360         qp_attr->sq_draining = 0;
3361         qp_attr->max_rd_atomic = 0;
3362         qp_attr->max_dest_rd_atomic = 0;
3363         qp_attr->min_rnr_timer = 0;
3364         qp_attr->timeout = 0;
3365         qp_attr->retry_cnt = 0;
3366         qp_attr->rnr_retry = 0;
3367         qp_attr->alt_timeout = 0;
3368
3369 done:
3370         qp_attr->cur_qp_state = qp_attr->qp_state;
3371         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3372         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3373         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3374         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3375         qp_attr->cap.max_inline_data = 0;
3376         qp_init_attr->cap = qp_attr->cap;
3377         qp_init_attr->create_flags = 0;
3378
3379         mutex_unlock(&hr_qp->mutex);
3380
3381         return 0;
3382 }
3383
3384 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3385                             int qp_attr_mask,
3386                             struct ib_qp_init_attr *qp_init_attr)
3387 {
3388         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3389         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3390         struct device *dev = &hr_dev->pdev->dev;
3391         struct hns_roce_qp_context *context;
3392         int tmp_qp_state;
3393         int ret = 0;
3394         int state;
3395
3396         context = kzalloc(sizeof(*context), GFP_KERNEL);
3397         if (!context)
3398                 return -ENOMEM;
3399
3400         memset(qp_attr, 0, sizeof(*qp_attr));
3401         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3402
3403         mutex_lock(&hr_qp->mutex);
3404
3405         if (hr_qp->state == IB_QPS_RESET) {
3406                 qp_attr->qp_state = IB_QPS_RESET;
3407                 goto done;
3408         }
3409
3410         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3411         if (ret) {
3412                 dev_err(dev, "query qpc error\n");
3413                 ret = -EINVAL;
3414                 goto out;
3415         }
3416
3417         state = roce_get_field(context->qpc_bytes_144,
3418                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3419                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3420         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3421         if (tmp_qp_state == -1) {
3422                 dev_err(dev, "to_ib_qp_state error\n");
3423                 ret = -EINVAL;
3424                 goto out;
3425         }
3426         hr_qp->state = (u8)tmp_qp_state;
3427         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3428         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3429                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3430                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3431         qp_attr->path_mig_state = IB_MIG_ARMED;
3432         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3433         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3434                 qp_attr->qkey = QKEY_VAL;
3435
3436         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3437                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3438                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3439         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3440                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3441                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3442         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3443                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3444                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3445         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3446                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3447                                    ((roce_get_bit(context->qpc_bytes_4,
3448                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3449                                    ((roce_get_bit(context->qpc_bytes_4,
3450                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3451
3452         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3453             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3454                 struct ib_global_route *grh =
3455                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3456
3457                 rdma_ah_set_sl(&qp_attr->ah_attr,
3458                                roce_get_field(context->qpc_bytes_156,
3459                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3460                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3461                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3462                 grh->flow_label =
3463                         roce_get_field(context->qpc_bytes_48,
3464                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3465                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3466                 grh->sgid_index =
3467                         roce_get_field(context->qpc_bytes_36,
3468                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3469                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3470                 grh->hop_limit =
3471                         roce_get_field(context->qpc_bytes_44,
3472                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3473                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3474                 grh->traffic_class =
3475                         roce_get_field(context->qpc_bytes_48,
3476                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3477                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3478
3479                 memcpy(grh->dgid.raw, context->dgid,
3480                        sizeof(grh->dgid.raw));
3481         }
3482
3483         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3484                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3485                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3486         qp_attr->port_num = hr_qp->port + 1;
3487         qp_attr->sq_draining = 0;
3488         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3489                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3490                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3491         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3492                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3493                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3494         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3495                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3496                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3497         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3498                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3499                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3500         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3501                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3502                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3503         qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3504
3505 done:
3506         qp_attr->cur_qp_state = qp_attr->qp_state;
3507         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3508         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3509
3510         if (!ibqp->uobject) {
3511                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3512                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3513         } else {
3514                 qp_attr->cap.max_send_wr = 0;
3515                 qp_attr->cap.max_send_sge = 0;
3516         }
3517
3518         qp_init_attr->cap = qp_attr->cap;
3519
3520 out:
3521         mutex_unlock(&hr_qp->mutex);
3522         kfree(context);
3523         return ret;
3524 }
3525
3526 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3527                                 int qp_attr_mask,
3528                                 struct ib_qp_init_attr *qp_init_attr)
3529 {
3530         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3531
3532         return hr_qp->doorbell_qpn <= 1 ?
3533                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3534                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3535 }
3536
3537 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3538 {
3539         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3540         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3541         struct hns_roce_cq *send_cq, *recv_cq;
3542         int ret;
3543
3544         ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3545         if (ret)
3546                 return ret;
3547
3548         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3549         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3550
3551         hns_roce_lock_cqs(send_cq, recv_cq);
3552         if (!udata) {
3553                 if (recv_cq)
3554                         __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3555                                                (hr_qp->ibqp.srq ?
3556                                                 to_hr_srq(hr_qp->ibqp.srq) :
3557                                                 NULL));
3558
3559                 if (send_cq && send_cq != recv_cq)
3560                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3561         }
3562         hns_roce_qp_remove(hr_dev, hr_qp);
3563         hns_roce_unlock_cqs(send_cq, recv_cq);
3564
3565         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3566
3567         return 0;
3568 }
3569
3570 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3571 {
3572         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3573         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3574         struct device *dev = &hr_dev->pdev->dev;
3575         u32 cqe_cnt_ori;
3576         u32 cqe_cnt_cur;
3577         int wait_time = 0;
3578
3579         /*
3580          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3581          * have been written by checking the CQE counter.
3582          */
3583         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3584         while (1) {
3585                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3586                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3587                         break;
3588
3589                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3590                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3591                         break;
3592
3593                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3594                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3595                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3596                                 hr_cq->cqn);
3597                         break;
3598                 }
3599                 wait_time++;
3600         }
3601         return 0;
3602 }
3603
3604 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
3605 {
3606         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3607                        (req_not << eq->log_entries), eq->doorbell);
3608 }
3609
3610 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3611                                             struct hns_roce_aeqe *aeqe, int qpn)
3612 {
3613         struct device *dev = &hr_dev->pdev->dev;
3614
3615         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3616         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3617                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3618         case HNS_ROCE_LWQCE_QPC_ERROR:
3619                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3620                 break;
3621         case HNS_ROCE_LWQCE_MTU_ERROR:
3622                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3623                 break;
3624         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3625                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3626                 break;
3627         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3628                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3629                 break;
3630         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3631                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3632                 break;
3633         case HNS_ROCE_LWQCE_SL_ERROR:
3634                 dev_warn(dev, "QP %d, SL error.\n", qpn);
3635                 break;
3636         case HNS_ROCE_LWQCE_PORT_ERROR:
3637                 dev_warn(dev, "QP %d, port error.\n", qpn);
3638                 break;
3639         default:
3640                 break;
3641         }
3642 }
3643
3644 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3645                                                    struct hns_roce_aeqe *aeqe,
3646                                                    int qpn)
3647 {
3648         struct device *dev = &hr_dev->pdev->dev;
3649
3650         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3651         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3652                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3653         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3654                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3655                 break;
3656         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3657                 dev_warn(dev, "QP %d, length error.\n", qpn);
3658                 break;
3659         case HNS_ROCE_LAVWQE_VA_ERROR:
3660                 dev_warn(dev, "QP %d, VA error.\n", qpn);
3661                 break;
3662         case HNS_ROCE_LAVWQE_PD_ERROR:
3663                 dev_err(dev, "QP %d, PD error.\n", qpn);
3664                 break;
3665         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3666                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3667                 break;
3668         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3669                 dev_warn(dev, "QP %d, key state error.\n", qpn);
3670                 break;
3671         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3672                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3673                 break;
3674         default:
3675                 break;
3676         }
3677 }
3678
3679 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3680                                       struct hns_roce_aeqe *aeqe,
3681                                       int event_type)
3682 {
3683         struct device *dev = &hr_dev->pdev->dev;
3684         int phy_port;
3685         int qpn;
3686
3687         qpn = roce_get_field(aeqe->event.queue_event.num,
3688                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3689                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3690         phy_port = roce_get_field(aeqe->event.queue_event.num,
3691                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3692                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3693         if (qpn <= 1)
3694                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3695
3696         switch (event_type) {
3697         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3698                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3699                          "QP %d, phy_port %d.\n", qpn, phy_port);
3700                 break;
3701         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3702                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3703                 break;
3704         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3705                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3706                 break;
3707         default:
3708                 break;
3709         }
3710
3711         hns_roce_qp_event(hr_dev, qpn, event_type);
3712 }
3713
3714 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3715                                       struct hns_roce_aeqe *aeqe,
3716                                       int event_type)
3717 {
3718         struct device *dev = &hr_dev->pdev->dev;
3719         u32 cqn;
3720
3721         cqn = roce_get_field(aeqe->event.queue_event.num,
3722                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3723                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3724
3725         switch (event_type) {
3726         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3727                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3728                 break;
3729         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3730                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3731                 break;
3732         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3733                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3734                 break;
3735         default:
3736                 break;
3737         }
3738
3739         hns_roce_cq_event(hr_dev, cqn, event_type);
3740 }
3741
3742 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3743                                            struct hns_roce_aeqe *aeqe)
3744 {
3745         struct device *dev = &hr_dev->pdev->dev;
3746
3747         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3748                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3749         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3750                 dev_warn(dev, "SDB overflow.\n");
3751                 break;
3752         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3753                 dev_warn(dev, "SDB almost overflow.\n");
3754                 break;
3755         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3756                 dev_warn(dev, "SDB almost empty.\n");
3757                 break;
3758         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3759                 dev_warn(dev, "ODB overflow.\n");
3760                 break;
3761         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3762                 dev_warn(dev, "ODB almost overflow.\n");
3763                 break;
3764         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3765                 dev_warn(dev, "SDB almost empty.\n");
3766                 break;
3767         default:
3768                 break;
3769         }
3770 }
3771
3772 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3773 {
3774         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3775
3776         return (struct hns_roce_aeqe *)((u8 *)
3777                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3778                 off % HNS_ROCE_BA_SIZE);
3779 }
3780
3781 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3782 {
3783         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3784
3785         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3786                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3787 }
3788
3789 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3790                                struct hns_roce_eq *eq)
3791 {
3792         struct device *dev = &hr_dev->pdev->dev;
3793         struct hns_roce_aeqe *aeqe;
3794         int aeqes_found = 0;
3795         int event_type;
3796
3797         while ((aeqe = next_aeqe_sw_v1(eq))) {
3798                 /* Make sure we read the AEQ entry after we have checked the
3799                  * ownership bit
3800                  */
3801                 dma_rmb();
3802
3803                 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3804                         aeqe,
3805                         roce_get_field(aeqe->asyn,
3806                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3807                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3808                 event_type = roce_get_field(aeqe->asyn,
3809                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3810                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3811                 switch (event_type) {
3812                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3813                         dev_warn(dev, "PATH MIG not supported\n");
3814                         break;
3815                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3816                         dev_warn(dev, "COMMUNICATION established\n");
3817                         break;
3818                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3819                         dev_warn(dev, "SQ DRAINED not supported\n");
3820                         break;
3821                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3822                         dev_warn(dev, "PATH MIG failed\n");
3823                         break;
3824                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3825                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3826                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3827                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3828                         break;
3829                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3830                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3831                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3832                         dev_warn(dev, "SRQ not support!\n");
3833                         break;
3834                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3835                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3836                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3837                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3838                         break;
3839                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3840                         dev_warn(dev, "port change.\n");
3841                         break;
3842                 case HNS_ROCE_EVENT_TYPE_MB:
3843                         hns_roce_cmd_event(hr_dev,
3844                                            le16_to_cpu(aeqe->event.cmd.token),
3845                                            aeqe->event.cmd.status,
3846                                            le64_to_cpu(aeqe->event.cmd.out_param
3847                                            ));
3848                         break;
3849                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3850                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3851                         break;
3852                 default:
3853                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3854                                  event_type, eq->eqn, eq->cons_index);
3855                         break;
3856                 }
3857
3858                 eq->cons_index++;
3859                 aeqes_found = 1;
3860
3861                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3862                         eq->cons_index = 0;
3863         }
3864
3865         set_eq_cons_index_v1(eq, 0);
3866
3867         return aeqes_found;
3868 }
3869
3870 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3871 {
3872         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3873
3874         return (struct hns_roce_ceqe *)((u8 *)
3875                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3876                         off % HNS_ROCE_BA_SIZE);
3877 }
3878
3879 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3880 {
3881         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3882
3883         return (!!(roce_get_bit(ceqe->comp,
3884                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3885                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3886 }
3887
3888 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3889                                struct hns_roce_eq *eq)
3890 {
3891         struct hns_roce_ceqe *ceqe;
3892         int ceqes_found = 0;
3893         u32 cqn;
3894
3895         while ((ceqe = next_ceqe_sw_v1(eq))) {
3896                 /* Make sure we read CEQ entry after we have checked the
3897                  * ownership bit
3898                  */
3899                 dma_rmb();
3900
3901                 cqn = roce_get_field(ceqe->comp,
3902                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3903                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3904                 hns_roce_cq_completion(hr_dev, cqn);
3905
3906                 ++eq->cons_index;
3907                 ceqes_found = 1;
3908
3909                 if (eq->cons_index >
3910                     EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3911                         eq->cons_index = 0;
3912         }
3913
3914         set_eq_cons_index_v1(eq, 0);
3915
3916         return ceqes_found;
3917 }
3918
3919 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3920 {
3921         struct hns_roce_eq  *eq  = eq_ptr;
3922         struct hns_roce_dev *hr_dev = eq->hr_dev;
3923         int int_work;
3924
3925         if (eq->type_flag == HNS_ROCE_CEQ)
3926                 /* CEQ irq routine, CEQ is pulse irq, not clear */
3927                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
3928         else
3929                 /* AEQ irq routine, AEQ is pulse irq, not clear */
3930                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
3931
3932         return IRQ_RETVAL(int_work);
3933 }
3934
3935 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
3936 {
3937         struct hns_roce_dev *hr_dev = dev_id;
3938         struct device *dev = &hr_dev->pdev->dev;
3939         int int_work = 0;
3940         u32 caepaemask_val;
3941         u32 cealmovf_val;
3942         u32 caepaest_val;
3943         u32 aeshift_val;
3944         u32 ceshift_val;
3945         u32 cemask_val;
3946         __le32 tmp;
3947         int i;
3948
3949         /*
3950          * Abnormal interrupt:
3951          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
3952          * interrupt, mask irq, clear irq, cancel mask operation
3953          */
3954         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
3955         tmp = cpu_to_le32(aeshift_val);
3956
3957         /* AEQE overflow */
3958         if (roce_get_bit(tmp,
3959                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
3960                 dev_warn(dev, "AEQ overflow!\n");
3961
3962                 /* Set mask */
3963                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3964                 tmp = cpu_to_le32(caepaemask_val);
3965                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3966                              HNS_ROCE_INT_MASK_ENABLE);
3967                 caepaemask_val = le32_to_cpu(tmp);
3968                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3969
3970                 /* Clear int state(INT_WC : write 1 clear) */
3971                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
3972                 tmp = cpu_to_le32(caepaest_val);
3973                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
3974                 caepaest_val = le32_to_cpu(tmp);
3975                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
3976
3977                 /* Clear mask */
3978                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
3979                 tmp = cpu_to_le32(caepaemask_val);
3980                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
3981                              HNS_ROCE_INT_MASK_DISABLE);
3982                 caepaemask_val = le32_to_cpu(tmp);
3983                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
3984         }
3985
3986         /* CEQ almost overflow */
3987         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
3988                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
3989                                         i * CEQ_REG_OFFSET);
3990                 tmp = cpu_to_le32(ceshift_val);
3991
3992                 if (roce_get_bit(tmp,
3993                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
3994                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
3995                         int_work++;
3996
3997                         /* Set mask */
3998                         cemask_val = roce_read(hr_dev,
3999                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4000                                                i * CEQ_REG_OFFSET);
4001                         tmp = cpu_to_le32(cemask_val);
4002                         roce_set_bit(tmp,
4003                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4004                                 HNS_ROCE_INT_MASK_ENABLE);
4005                         cemask_val = le32_to_cpu(tmp);
4006                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4007                                    i * CEQ_REG_OFFSET, cemask_val);
4008
4009                         /* Clear int state(INT_WC : write 1 clear) */
4010                         cealmovf_val = roce_read(hr_dev,
4011                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4012                                        i * CEQ_REG_OFFSET);
4013                         tmp = cpu_to_le32(cealmovf_val);
4014                         roce_set_bit(tmp,
4015                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4016                                      1);
4017                         cealmovf_val = le32_to_cpu(tmp);
4018                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4019                                    i * CEQ_REG_OFFSET, cealmovf_val);
4020
4021                         /* Clear mask */
4022                         cemask_val = roce_read(hr_dev,
4023                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4024                                      i * CEQ_REG_OFFSET);
4025                         tmp = cpu_to_le32(cemask_val);
4026                         roce_set_bit(tmp,
4027                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4028                                HNS_ROCE_INT_MASK_DISABLE);
4029                         cemask_val = le32_to_cpu(tmp);
4030                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4031                                    i * CEQ_REG_OFFSET, cemask_val);
4032                 }
4033         }
4034
4035         /* ECC multi-bit error alarm */
4036         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4037                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4038                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4039                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4040
4041         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4042                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4043                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4044                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4045
4046         return IRQ_RETVAL(int_work);
4047 }
4048
4049 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4050 {
4051         u32 aemask_val;
4052         int masken = 0;
4053         __le32 tmp;
4054         int i;
4055
4056         /* AEQ INT */
4057         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4058         tmp = cpu_to_le32(aemask_val);
4059         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4060                      masken);
4061         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4062         aemask_val = le32_to_cpu(tmp);
4063         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4064
4065         /* CEQ INT */
4066         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4067                 /* IRQ mask */
4068                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4069                            i * CEQ_REG_OFFSET, masken);
4070         }
4071 }
4072
4073 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4074                                 struct hns_roce_eq *eq)
4075 {
4076         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4077                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4078         int i;
4079
4080         if (!eq->buf_list)
4081                 return;
4082
4083         for (i = 0; i < npages; ++i)
4084                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4085                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4086
4087         kfree(eq->buf_list);
4088 }
4089
4090 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4091                                   int enable_flag)
4092 {
4093         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4094         __le32 tmp;
4095         u32 val;
4096
4097         val = readl(eqc);
4098         tmp = cpu_to_le32(val);
4099
4100         if (enable_flag)
4101                 roce_set_field(tmp,
4102                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4103                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4104                                HNS_ROCE_EQ_STAT_VALID);
4105         else
4106                 roce_set_field(tmp,
4107                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4108                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4109                                HNS_ROCE_EQ_STAT_INVALID);
4110
4111         val = le32_to_cpu(tmp);
4112         writel(val, eqc);
4113 }
4114
4115 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4116                                  struct hns_roce_eq *eq)
4117 {
4118         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4119         struct device *dev = &hr_dev->pdev->dev;
4120         dma_addr_t tmp_dma_addr;
4121         u32 eqcuridx_val;
4122         u32 eqconsindx_val;
4123         u32 eqshift_val;
4124         __le32 tmp2 = 0;
4125         __le32 tmp1 = 0;
4126         __le32 tmp = 0;
4127         int num_bas;
4128         int ret;
4129         int i;
4130
4131         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4132                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4133
4134         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4135                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4136                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4137                         num_bas);
4138                 return -EINVAL;
4139         }
4140
4141         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4142         if (!eq->buf_list)
4143                 return -ENOMEM;
4144
4145         for (i = 0; i < num_bas; ++i) {
4146                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4147                                                          &tmp_dma_addr,
4148                                                          GFP_KERNEL);
4149                 if (!eq->buf_list[i].buf) {
4150                         ret = -ENOMEM;
4151                         goto err_out_free_pages;
4152                 }
4153
4154                 eq->buf_list[i].map = tmp_dma_addr;
4155         }
4156         eq->cons_index = 0;
4157         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4158                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4159                        HNS_ROCE_EQ_STAT_INVALID);
4160         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4161                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4162                        eq->log_entries);
4163         eqshift_val = le32_to_cpu(tmp);
4164         writel(eqshift_val, eqc);
4165
4166         /* Configure eq extended address 12~44bit */
4167         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4168
4169         /*
4170          * Configure eq extended address 45~49 bit.
4171          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4172          * using 4K page, and shift more 32 because of
4173          * caculating the high 32 bit value evaluated to hardware.
4174          */
4175         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4176                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4177                        eq->buf_list[0].map >> 44);
4178         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4179                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4180         eqcuridx_val = le32_to_cpu(tmp1);
4181         writel(eqcuridx_val, eqc + 8);
4182
4183         /* Configure eq consumer index */
4184         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4185                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4186         eqconsindx_val = le32_to_cpu(tmp2);
4187         writel(eqconsindx_val, eqc + 0xc);
4188
4189         return 0;
4190
4191 err_out_free_pages:
4192         for (i -= 1; i >= 0; i--)
4193                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4194                                   eq->buf_list[i].map);
4195
4196         kfree(eq->buf_list);
4197         return ret;
4198 }
4199
4200 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4201 {
4202         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4203         struct device *dev = &hr_dev->pdev->dev;
4204         struct hns_roce_eq *eq;
4205         int irq_num;
4206         int eq_num;
4207         int ret;
4208         int i, j;
4209
4210         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4211         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4212
4213         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4214         if (!eq_table->eq)
4215                 return -ENOMEM;
4216
4217         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4218                                      GFP_KERNEL);
4219         if (!eq_table->eqc_base) {
4220                 ret = -ENOMEM;
4221                 goto err_eqc_base_alloc_fail;
4222         }
4223
4224         for (i = 0; i < eq_num; i++) {
4225                 eq = &eq_table->eq[i];
4226                 eq->hr_dev = hr_dev;
4227                 eq->eqn = i;
4228                 eq->irq = hr_dev->irq[i];
4229                 eq->log_page_size = PAGE_SHIFT;
4230
4231                 if (i < hr_dev->caps.num_comp_vectors) {
4232                         /* CEQ */
4233                         eq_table->eqc_base[i] = hr_dev->reg_base +
4234                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4235                                                 CEQ_REG_OFFSET * i;
4236                         eq->type_flag = HNS_ROCE_CEQ;
4237                         eq->doorbell = hr_dev->reg_base +
4238                                        ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4239                                        CEQ_REG_OFFSET * i;
4240                         eq->entries = hr_dev->caps.ceqe_depth;
4241                         eq->log_entries = ilog2(eq->entries);
4242                         eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4243                 } else {
4244                         /* AEQ */
4245                         eq_table->eqc_base[i] = hr_dev->reg_base +
4246                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4247                         eq->type_flag = HNS_ROCE_AEQ;
4248                         eq->doorbell = hr_dev->reg_base +
4249                                        ROCEE_CAEP_AEQE_CONS_IDX_REG;
4250                         eq->entries = hr_dev->caps.aeqe_depth;
4251                         eq->log_entries = ilog2(eq->entries);
4252                         eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4253                 }
4254         }
4255
4256         /* Disable irq */
4257         hns_roce_v1_int_mask_enable(hr_dev);
4258
4259         /* Configure ce int interval */
4260         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4261                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4262
4263         /* Configure ce int burst num */
4264         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4265                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4266
4267         for (i = 0; i < eq_num; i++) {
4268                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4269                 if (ret) {
4270                         dev_err(dev, "eq create failed\n");
4271                         goto err_create_eq_fail;
4272                 }
4273         }
4274
4275         for (j = 0; j < irq_num; j++) {
4276                 if (j < eq_num)
4277                         ret = request_irq(hr_dev->irq[j],
4278                                           hns_roce_v1_msix_interrupt_eq, 0,
4279                                           hr_dev->irq_names[j],
4280                                           &eq_table->eq[j]);
4281                 else
4282                         ret = request_irq(hr_dev->irq[j],
4283                                           hns_roce_v1_msix_interrupt_abn, 0,
4284                                           hr_dev->irq_names[j], hr_dev);
4285
4286                 if (ret) {
4287                         dev_err(dev, "request irq error!\n");
4288                         goto err_request_irq_fail;
4289                 }
4290         }
4291
4292         for (i = 0; i < eq_num; i++)
4293                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4294
4295         return 0;
4296
4297 err_request_irq_fail:
4298         for (j -= 1; j >= 0; j--)
4299                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4300
4301 err_create_eq_fail:
4302         for (i -= 1; i >= 0; i--)
4303                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4304
4305         kfree(eq_table->eqc_base);
4306
4307 err_eqc_base_alloc_fail:
4308         kfree(eq_table->eq);
4309
4310         return ret;
4311 }
4312
4313 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4314 {
4315         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4316         int irq_num;
4317         int eq_num;
4318         int i;
4319
4320         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4321         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4322         for (i = 0; i < eq_num; i++) {
4323                 /* Disable EQ */
4324                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4325
4326                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4327
4328                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4329         }
4330         for (i = eq_num; i < irq_num; i++)
4331                 free_irq(hr_dev->irq[i], hr_dev);
4332
4333         kfree(eq_table->eqc_base);
4334         kfree(eq_table->eq);
4335 }
4336
4337 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4338         .destroy_qp = hns_roce_v1_destroy_qp,
4339         .poll_cq = hns_roce_v1_poll_cq,
4340         .post_recv = hns_roce_v1_post_recv,
4341         .post_send = hns_roce_v1_post_send,
4342         .query_qp = hns_roce_v1_query_qp,
4343         .req_notify_cq = hns_roce_v1_req_notify_cq,
4344 };
4345
4346 static const struct hns_roce_hw hns_roce_hw_v1 = {
4347         .reset = hns_roce_v1_reset,
4348         .hw_profile = hns_roce_v1_profile,
4349         .hw_init = hns_roce_v1_init,
4350         .hw_exit = hns_roce_v1_exit,
4351         .post_mbox = hns_roce_v1_post_mbox,
4352         .chk_mbox = hns_roce_v1_chk_mbox,
4353         .set_gid = hns_roce_v1_set_gid,
4354         .set_mac = hns_roce_v1_set_mac,
4355         .set_mtu = hns_roce_v1_set_mtu,
4356         .write_mtpt = hns_roce_v1_write_mtpt,
4357         .write_cqc = hns_roce_v1_write_cqc,
4358         .clear_hem = hns_roce_v1_clear_hem,
4359         .modify_qp = hns_roce_v1_modify_qp,
4360         .query_qp = hns_roce_v1_query_qp,
4361         .destroy_qp = hns_roce_v1_destroy_qp,
4362         .post_send = hns_roce_v1_post_send,
4363         .post_recv = hns_roce_v1_post_recv,
4364         .req_notify_cq = hns_roce_v1_req_notify_cq,
4365         .poll_cq = hns_roce_v1_poll_cq,
4366         .dereg_mr = hns_roce_v1_dereg_mr,
4367         .destroy_cq = hns_roce_v1_destroy_cq,
4368         .init_eq = hns_roce_v1_init_eq_table,
4369         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4370         .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4371 };
4372
4373 static const struct of_device_id hns_roce_of_match[] = {
4374         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4375         {},
4376 };
4377 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4378
4379 static const struct acpi_device_id hns_roce_acpi_match[] = {
4380         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4381         {},
4382 };
4383 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4384
4385 static struct
4386 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4387 {
4388         struct device *dev;
4389
4390         /* get the 'device' corresponding to the matching 'fwnode' */
4391         dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4392         /* get the platform device */
4393         return dev ? to_platform_device(dev) : NULL;
4394 }
4395
4396 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4397 {
4398         struct device *dev = &hr_dev->pdev->dev;
4399         struct platform_device *pdev = NULL;
4400         struct net_device *netdev = NULL;
4401         struct device_node *net_node;
4402         int port_cnt = 0;
4403         u8 phy_port;
4404         int ret;
4405         int i;
4406
4407         /* check if we are compatible with the underlying SoC */
4408         if (dev_of_node(dev)) {
4409                 const struct of_device_id *of_id;
4410
4411                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4412                 if (!of_id) {
4413                         dev_err(dev, "device is not compatible!\n");
4414                         return -ENXIO;
4415                 }
4416                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4417                 if (!hr_dev->hw) {
4418                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4419                         return -ENXIO;
4420                 }
4421         } else if (is_acpi_device_node(dev->fwnode)) {
4422                 const struct acpi_device_id *acpi_id;
4423
4424                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4425                 if (!acpi_id) {
4426                         dev_err(dev, "device is not compatible!\n");
4427                         return -ENXIO;
4428                 }
4429                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4430                 if (!hr_dev->hw) {
4431                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4432                         return -ENXIO;
4433                 }
4434         } else {
4435                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4436                 return -ENXIO;
4437         }
4438
4439         /* get the mapped register base address */
4440         hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4441         if (IS_ERR(hr_dev->reg_base))
4442                 return PTR_ERR(hr_dev->reg_base);
4443
4444         /* read the node_guid of IB device from the DT or ACPI */
4445         ret = device_property_read_u8_array(dev, "node-guid",
4446                                             (u8 *)&hr_dev->ib_dev.node_guid,
4447                                             GUID_LEN);
4448         if (ret) {
4449                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4450                 return ret;
4451         }
4452
4453         /* get the RoCE associated ethernet ports or netdevices */
4454         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4455                 if (dev_of_node(dev)) {
4456                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4457                                                     i);
4458                         if (!net_node)
4459                                 continue;
4460                         pdev = of_find_device_by_node(net_node);
4461                 } else if (is_acpi_device_node(dev->fwnode)) {
4462                         struct fwnode_reference_args args;
4463
4464                         ret = acpi_node_get_property_reference(dev->fwnode,
4465                                                                "eth-handle",
4466                                                                i, &args);
4467                         if (ret)
4468                                 continue;
4469                         pdev = hns_roce_find_pdev(args.fwnode);
4470                 } else {
4471                         dev_err(dev, "cannot read data from DT or ACPI\n");
4472                         return -ENXIO;
4473                 }
4474
4475                 if (pdev) {
4476                         netdev = platform_get_drvdata(pdev);
4477                         phy_port = (u8)i;
4478                         if (netdev) {
4479                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4480                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4481                         } else {
4482                                 dev_err(dev, "no netdev found with pdev %s\n",
4483                                         pdev->name);
4484                                 return -ENODEV;
4485                         }
4486                         port_cnt++;
4487                 }
4488         }
4489
4490         if (port_cnt == 0) {
4491                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4492                 return -EINVAL;
4493         }
4494
4495         hr_dev->caps.num_ports = port_cnt;
4496
4497         /* cmd issue mode: 0 is poll, 1 is event */
4498         hr_dev->cmd_mod = 1;
4499         hr_dev->loop_idc = 0;
4500         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4501         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4502
4503         /* read the interrupt names from the DT or ACPI */
4504         ret = device_property_read_string_array(dev, "interrupt-names",
4505                                                 hr_dev->irq_names,
4506                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4507         if (ret < 0) {
4508                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4509                 return ret;
4510         }
4511
4512         /* fetch the interrupt numbers */
4513         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4514                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4515                 if (hr_dev->irq[i] <= 0)
4516                         return -EINVAL;
4517         }
4518
4519         return 0;
4520 }
4521
4522 /**
4523  * hns_roce_probe - RoCE driver entrance
4524  * @pdev: pointer to platform device
4525  * Return : int
4526  *
4527  */
4528 static int hns_roce_probe(struct platform_device *pdev)
4529 {
4530         int ret;
4531         struct hns_roce_dev *hr_dev;
4532         struct device *dev = &pdev->dev;
4533
4534         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4535         if (!hr_dev)
4536                 return -ENOMEM;
4537
4538         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4539         if (!hr_dev->priv) {
4540                 ret = -ENOMEM;
4541                 goto error_failed_kzalloc;
4542         }
4543
4544         hr_dev->pdev = pdev;
4545         hr_dev->dev = dev;
4546         platform_set_drvdata(pdev, hr_dev);
4547
4548         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4549             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4550                 dev_err(dev, "Not usable DMA addressing mode\n");
4551                 ret = -EIO;
4552                 goto error_failed_get_cfg;
4553         }
4554
4555         ret = hns_roce_get_cfg(hr_dev);
4556         if (ret) {
4557                 dev_err(dev, "Get Configuration failed!\n");
4558                 goto error_failed_get_cfg;
4559         }
4560
4561         ret = hns_roce_init(hr_dev);
4562         if (ret) {
4563                 dev_err(dev, "RoCE engine init failed!\n");
4564                 goto error_failed_get_cfg;
4565         }
4566
4567         return 0;
4568
4569 error_failed_get_cfg:
4570         kfree(hr_dev->priv);
4571
4572 error_failed_kzalloc:
4573         ib_dealloc_device(&hr_dev->ib_dev);
4574
4575         return ret;
4576 }
4577
4578 /**
4579  * hns_roce_remove - remove RoCE device
4580  * @pdev: pointer to platform device
4581  */
4582 static int hns_roce_remove(struct platform_device *pdev)
4583 {
4584         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4585
4586         hns_roce_exit(hr_dev);
4587         kfree(hr_dev->priv);
4588         ib_dealloc_device(&hr_dev->ib_dev);
4589
4590         return 0;
4591 }
4592
4593 static struct platform_driver hns_roce_driver = {
4594         .probe = hns_roce_probe,
4595         .remove = hns_roce_remove,
4596         .driver = {
4597                 .name = DRV_NAME,
4598                 .of_match_table = hns_roce_of_match,
4599                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4600         },
4601 };
4602
4603 module_platform_driver(hns_roce_driver);
4604
4605 MODULE_LICENSE("Dual BSD/GPL");
4606 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4607 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4608 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4609 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");