drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 /**
  47  * hns_get_gid_index - Get gid index.
  48  * @hr_dev: pointer to structure hns_roce_dev.
  49  * @port:  port, value range: 0 ~ MAX
  50  * @gid_index:  gid_index, value range: 0 ~ MAX
  51  * Description:
  52  *    N ports shared gids, allocation method as follow:
  53  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  54  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  55  *              And so on
  56  */
  57 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index)
  58 {
  59         return gid_index * hr_dev->caps.num_ports + port;
  60 }
  61
  62 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  63 {
  64         dseg->lkey = cpu_to_le32(sg->lkey);
  65         dseg->addr = cpu_to_le64(sg->addr);
  66         dseg->len  = cpu_to_le32(sg->length);
  67 }
  68
  69 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  70                           u32 rkey)
  71 {
  72         rseg->raddr = cpu_to_le64(remote_addr);
  73         rseg->rkey  = cpu_to_le32(rkey);
  74         rseg->len   = 0;
  75 }
  76
  77 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  78                                  const struct ib_send_wr *wr,
  79                                  const struct ib_send_wr **bad_wr)
  80 {
  81         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  82         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  83         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  84         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  85         struct hns_roce_wqe_data_seg *dseg = NULL;
  86         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  87         struct device *dev = &hr_dev->pdev->dev;
  88         struct hns_roce_sq_db sq_db = {};
  89         int ps_opcode, i;
  90         unsigned long flags = 0;
  91         void *wqe = NULL;
  92         __le32 doorbell[2];
  93         int ret = 0;
  94         int loopback;
  95         u32 wqe_idx;
  96         int nreq;
  97         u8 *smac;
  98
  99         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
 100                 ibqp->qp_type != IB_QPT_RC)) {
 101                 dev_err(dev, "un-supported QP type\n");
 102                 *bad_wr = NULL;
 103                 return -EOPNOTSUPP;
 104         }
 105
 106         spin_lock_irqsave(&qp->sq.lock, flags);
 107
 108         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 109                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
 110                         ret = -ENOMEM;
 111                         *bad_wr = wr;
 112                         goto out;
 113                 }
 114
 115                 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
 116
 117                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 118                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 119                                 wr->num_sge, qp->sq.max_gs);
 120                         ret = -EINVAL;
 121                         *bad_wr = wr;
 122                         goto out;
 123                 }
 124
 125                 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
 126                 qp->sq.wrid[wqe_idx] = wr->wr_id;
 127
 128                 /* Corresponding to the RC and RD type wqe process separately */
 129                 if (ibqp->qp_type == IB_QPT_GSI) {
 130                         ud_sq_wqe = wqe;
 131                         roce_set_field(ud_sq_wqe->dmac_h,
 132                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 133                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 134                                        ah->av.mac[0]);
 135                         roce_set_field(ud_sq_wqe->dmac_h,
 136                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 137                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 138                                        ah->av.mac[1]);
 139                         roce_set_field(ud_sq_wqe->dmac_h,
 140                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 141                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 142                                        ah->av.mac[2]);
 143                         roce_set_field(ud_sq_wqe->dmac_h,
 144                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 145                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 146                                        ah->av.mac[3]);
 147
 148                         roce_set_field(ud_sq_wqe->u32_8,
 149                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 150                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 151                                        ah->av.mac[4]);
 152                         roce_set_field(ud_sq_wqe->u32_8,
 153                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 154                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 155                                        ah->av.mac[5]);
 156
 157                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 158                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 159                                                               smac) ? 1 : 0;
 160                         roce_set_bit(ud_sq_wqe->u32_8,
 161                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 162                                      loopback);
 163
 164                         roce_set_field(ud_sq_wqe->u32_8,
 165                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 166                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 167                                        HNS_ROCE_WQE_OPCODE_SEND);
 168                         roce_set_field(ud_sq_wqe->u32_8,
 169                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 170                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 171                                        2);
 172                         roce_set_bit(ud_sq_wqe->u32_8,
 173                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 174                                 1);
 175
 176                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 177                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 178                                 (wr->send_flags & IB_SEND_SOLICITED ?
 179                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 180                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 181                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 182
 183                         roce_set_field(ud_sq_wqe->u32_16,
 184                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 185                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 186                                        ud_wr(wr)->remote_qpn);
 187                         roce_set_field(ud_sq_wqe->u32_16,
 188                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 189                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 190                                        ah->av.stat_rate);
 191
 192                         roce_set_field(ud_sq_wqe->u32_36,
 193                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 194                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 195                                        ah->av.flowlabel);
 196                         roce_set_field(ud_sq_wqe->u32_36,
 197                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 198                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 199                                       ah->av.sl);
 200                         roce_set_field(ud_sq_wqe->u32_36,
 201                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 202                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 203                                        hns_get_gid_index(hr_dev, qp->phy_port,
 204                                                          ah->av.gid_index));
 205
 206                         roce_set_field(ud_sq_wqe->u32_40,
 207                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 208                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 209                                        ah->av.hop_limit);
 210                         roce_set_field(ud_sq_wqe->u32_40,
 211                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 212                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 213                                        ah->av.tclass);
 214
 215                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 216
 217                         ud_sq_wqe->va0_l =
 218                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 219                         ud_sq_wqe->va0_h =
 220                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 221                         ud_sq_wqe->l_key0 =
 222                                        cpu_to_le32(wr->sg_list[0].lkey);
 223
 224                         ud_sq_wqe->va1_l =
 225                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 226                         ud_sq_wqe->va1_h =
 227                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 228                         ud_sq_wqe->l_key1 =
 229                                        cpu_to_le32(wr->sg_list[1].lkey);
 230                 } else if (ibqp->qp_type == IB_QPT_RC) {
 231                         u32 tmp_len = 0;
 232
 233                         ctrl = wqe;
 234                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 235                         for (i = 0; i < wr->num_sge; i++)
 236                                 tmp_len += wr->sg_list[i].length;
 237
 238                         ctrl->msg_length =
 239                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 240
 241                         ctrl->sgl_pa_h = 0;
 242                         ctrl->flag = 0;
 243
 244                         switch (wr->opcode) {
 245                         case IB_WR_SEND_WITH_IMM:
 246                         case IB_WR_RDMA_WRITE_WITH_IMM:
 247                                 ctrl->imm_data = wr->ex.imm_data;
 248                                 break;
 249                         case IB_WR_SEND_WITH_INV:
 250                                 ctrl->inv_key =
 251                                         cpu_to_le32(wr->ex.invalidate_rkey);
 252                                 break;
 253                         default:
 254                                 ctrl->imm_data = 0;
 255                                 break;
 256                         }
 257
 258                         /* Ctrl field, ctrl set type: sig, solic, imm, fence */
 259                         /* SO wait for conforming application scenarios */
 260                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 261                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 262                                       (wr->send_flags & IB_SEND_SOLICITED ?
 263                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 264                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 265                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 266                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 267                                       (wr->send_flags & IB_SEND_FENCE ?
 268                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 269
 270                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 271
 272                         switch (wr->opcode) {
 273                         case IB_WR_RDMA_READ:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 275                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 276                                                rdma_wr(wr)->rkey);
 277                                 break;
 278                         case IB_WR_RDMA_WRITE:
 279                         case IB_WR_RDMA_WRITE_WITH_IMM:
 280                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 281                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 282                                               rdma_wr(wr)->rkey);
 283                                 break;
 284                         case IB_WR_SEND:
 285                         case IB_WR_SEND_WITH_INV:
 286                         case IB_WR_SEND_WITH_IMM:
 287                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 288                                 break;
 289                         case IB_WR_LOCAL_INV:
 290                         case IB_WR_ATOMIC_CMP_AND_SWP:
 291                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 292                         case IB_WR_LSO:
 293                         default:
 294                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 295                                 break;
 296                         }
 297                         ctrl->flag |= cpu_to_le32(ps_opcode);
 298                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 299
 300                         dseg = wqe;
 301                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 302                                 if (le32_to_cpu(ctrl->msg_length) >
 303                                     hr_dev->caps.max_sq_inline) {
 304                                         ret = -EINVAL;
 305                                         *bad_wr = wr;
 306                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 307                                                 le32_to_cpu(ctrl->msg_length),
 308                                                 hr_dev->caps.max_sq_inline);
 309                                         goto out;
 310                                 }
 311                                 for (i = 0; i < wr->num_sge; i++) {
 312                                         memcpy(wqe, ((void *) (uintptr_t)
 313                                                wr->sg_list[i].addr),
 314                                                wr->sg_list[i].length);
 315                                         wqe += wr->sg_list[i].length;
 316                                 }
 317                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 318                         } else {
 319                                 /* sqe num is two */
 320                                 for (i = 0; i < wr->num_sge; i++)
 321                                         set_data_seg(dseg + i, wr->sg_list + i);
 322
 323                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 324                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 325                         }
 326                 }
 327         }
 328
 329 out:
 330         /* Set DB return */
 331         if (likely(nreq)) {
 332                 qp->sq.head += nreq;
 333
 334                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 335                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 336                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 337                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 338                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 339                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 340                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 341                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 342                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 343                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 344
 345                 doorbell[0] = sq_db.u32_4;
 346                 doorbell[1] = sq_db.u32_8;
 347
 348                 hns_roce_write64_k(doorbell, qp->sq.db_reg);
 349         }
 350
 351         spin_unlock_irqrestore(&qp->sq.lock, flags);
 352
 353         return ret;
 354 }
 355
 356 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 357                                  const struct ib_recv_wr *wr,
 358                                  const struct ib_recv_wr **bad_wr)
 359 {
 360         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 361         struct hns_roce_wqe_data_seg *scat = NULL;
 362         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 363         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 364         struct device *dev = &hr_dev->pdev->dev;
 365         struct hns_roce_rq_db rq_db = {};
 366         __le32 doorbell[2] = {0};
 367         unsigned long flags = 0;
 368         unsigned int wqe_idx;
 369         int ret = 0;
 370         int nreq;
 371         int i;
 372         u32 reg_val;
 373
 374         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 375
 376         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 377                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 378                         hr_qp->ibqp.recv_cq)) {
 379                         ret = -ENOMEM;
 380                         *bad_wr = wr;
 381                         goto out;
 382                 }
 383
 384                 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
 385
 386                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 387                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 388                                 wr->num_sge, hr_qp->rq.max_gs);
 389                         ret = -EINVAL;
 390                         *bad_wr = wr;
 391                         goto out;
 392                 }
 393
 394                 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
 395
 396                 roce_set_field(ctrl->rwqe_byte_12,
 397                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 398                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 399                                wr->num_sge);
 400
 401                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 402
 403                 for (i = 0; i < wr->num_sge; i++)
 404                         set_data_seg(scat + i, wr->sg_list + i);
 405
 406                 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
 407         }
 408
 409 out:
 410         if (likely(nreq)) {
 411                 hr_qp->rq.head += nreq;
 412
 413                 if (ibqp->qp_type == IB_QPT_GSI) {
 414                         __le32 tmp;
 415
 416                         /* SW update GSI rq header */
 417                         reg_val = roce_read(to_hr_dev(ibqp->device),
 418                                             ROCEE_QP1C_CFG3_0_REG +
 419                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 420                         tmp = cpu_to_le32(reg_val);
 421                         roce_set_field(tmp,
 422                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 423                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 424                                        hr_qp->rq.head);
 425                         reg_val = le32_to_cpu(tmp);
 426                         roce_write(to_hr_dev(ibqp->device),
 427                                    ROCEE_QP1C_CFG3_0_REG +
 428                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 429                 } else {
 430                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 431                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 432                                        hr_qp->rq.head);
 433                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 434                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 435                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 436                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 437                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 438                                      1);
 439
 440                         doorbell[0] = rq_db.u32_4;
 441                         doorbell[1] = rq_db.u32_8;
 442
 443                         hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
 444                 }
 445         }
 446         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 447
 448         return ret;
 449 }
 450
 451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 452                                        int sdb_mode, int odb_mode)
 453 {
 454         __le32 tmp;
 455         u32 val;
 456
 457         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 458         tmp = cpu_to_le32(val);
 459         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 461         val = le32_to_cpu(tmp);
 462         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 463 }
 464
 465 static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
 466                                struct hns_roce_hem_table *table, int obj,
 467                                int step_idx)
 468 {
 469         spinlock_t *lock = &hr_dev->bt_cmd_lock;
 470         struct device *dev = hr_dev->dev;
 471         struct hns_roce_hem_iter iter;
 472         void __iomem *bt_cmd;
 473         __le32 bt_cmd_val[2];
 474         __le32 bt_cmd_h = 0;
 475         unsigned long flags;
 476         __le32 bt_cmd_l;
 477         int ret = 0;
 478         u64 bt_ba;
 479         long end;
 480
 481         /* Find the HEM(Hardware Entry Memory) entry */
 482         unsigned long i = obj / (table->table_chunk_size / table->obj_size);
 483
 484         switch (table->type) {
 485         case HEM_TYPE_QPC:
 486         case HEM_TYPE_MTPT:
 487         case HEM_TYPE_CQC:
 488         case HEM_TYPE_SRQC:
 489                 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
 490                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
 491                 break;
 492         default:
 493                 return ret;
 494         }
 495
 496         roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
 497                        ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
 498         roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
 499         roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
 500
 501         /* Currently iter only a chunk */
 502         for (hns_roce_hem_first(table->hem[i], &iter);
 503              !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
 504                 bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
 505
 506                 spin_lock_irqsave(lock, flags);
 507
 508                 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
 509
 510                 end = HW_SYNC_TIMEOUT_MSECS;
 511                 while (end > 0) {
 512                         if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
 513                                 break;
 514
 515                         mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
 516                         end -= HW_SYNC_SLEEP_TIME_INTERVAL;
 517                 }
 518
 519                 if (end <= 0) {
 520                         dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
 521                         spin_unlock_irqrestore(lock, flags);
 522                         return -EBUSY;
 523                 }
 524
 525                 bt_cmd_l = cpu_to_le32(bt_ba);
 526                 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
 527                                ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
 528                                upper_32_bits(bt_ba));
 529
 530                 bt_cmd_val[0] = bt_cmd_l;
 531                 bt_cmd_val[1] = bt_cmd_h;
 532                 hns_roce_write64_k(bt_cmd_val,
 533                                    hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
 534                 spin_unlock_irqrestore(lock, flags);
 535         }
 536
 537         return ret;
 538 }
 539
 540 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 541                                      u32 odb_mode)
 542 {
 543         __le32 tmp;
 544         u32 val;
 545
 546         /* Configure SDB/ODB extend mode */
 547         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 548         tmp = cpu_to_le32(val);
 549         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 550         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 551         val = le32_to_cpu(tmp);
 552         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 553 }
 554
 555 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 556                              u32 sdb_alful)
 557 {
 558         __le32 tmp;
 559         u32 val;
 560
 561         /* Configure SDB */
 562         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 563         tmp = cpu_to_le32(val);
 564         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 565                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 566         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 567                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 568         val = le32_to_cpu(tmp);
 569         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 570 }
 571
 572 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 573                              u32 odb_alful)
 574 {
 575         __le32 tmp;
 576         u32 val;
 577
 578         /* Configure ODB */
 579         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 580         tmp = cpu_to_le32(val);
 581         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 582                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 583         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 584                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 585         val = le32_to_cpu(tmp);
 586         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 587 }
 588
 589 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 590                                  u32 ext_sdb_alful)
 591 {
 592         struct hns_roce_v1_priv *priv = hr_dev->priv;
 593         struct hns_roce_db_table *db = &priv->db_table;
 594         struct device *dev = &hr_dev->pdev->dev;
 595         dma_addr_t sdb_dma_addr;
 596         __le32 tmp;
 597         u32 val;
 598
 599         /* Configure extend SDB threshold */
 600         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 601         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 602
 603         /* Configure extend SDB base addr */
 604         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 605         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 606
 607         /* Configure extend SDB depth */
 608         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 609         tmp = cpu_to_le32(val);
 610         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 611                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 612                        db->ext_db->esdb_dep);
 613         /*
 614          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 615          * using 4K page, and shift more 32 because of
 616          * calculating the high 32 bit value evaluated to hardware.
 617          */
 618         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 619                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 620         val = le32_to_cpu(tmp);
 621         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 622
 623         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 624         dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
 625                 ext_sdb_alept, ext_sdb_alful);
 626 }
 627
 628 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 629                                  u32 ext_odb_alful)
 630 {
 631         struct hns_roce_v1_priv *priv = hr_dev->priv;
 632         struct hns_roce_db_table *db = &priv->db_table;
 633         struct device *dev = &hr_dev->pdev->dev;
 634         dma_addr_t odb_dma_addr;
 635         __le32 tmp;
 636         u32 val;
 637
 638         /* Configure extend ODB threshold */
 639         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 640         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 641
 642         /* Configure extend ODB base addr */
 643         odb_dma_addr = db->ext_db->odb_buf_list->map;
 644         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 645
 646         /* Configure extend ODB depth */
 647         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 648         tmp = cpu_to_le32(val);
 649         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 650                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 651                        db->ext_db->eodb_dep);
 652         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 653                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 654                        db->ext_db->eodb_dep);
 655         val = le32_to_cpu(tmp);
 656         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 657
 658         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 659         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 660                 ext_odb_alept, ext_odb_alful);
 661 }
 662
 663 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 664                                 u32 odb_ext_mod)
 665 {
 666         struct hns_roce_v1_priv *priv = hr_dev->priv;
 667         struct hns_roce_db_table *db = &priv->db_table;
 668         struct device *dev = &hr_dev->pdev->dev;
 669         dma_addr_t sdb_dma_addr;
 670         dma_addr_t odb_dma_addr;
 671         int ret = 0;
 672
 673         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 674         if (!db->ext_db)
 675                 return -ENOMEM;
 676
 677         if (sdb_ext_mod) {
 678                 db->ext_db->sdb_buf_list = kmalloc(
 679                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 680                 if (!db->ext_db->sdb_buf_list) {
 681                         ret = -ENOMEM;
 682                         goto ext_sdb_buf_fail_out;
 683                 }
 684
 685                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 686                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 687                                                      &sdb_dma_addr, GFP_KERNEL);
 688                 if (!db->ext_db->sdb_buf_list->buf) {
 689                         ret = -ENOMEM;
 690                         goto alloc_sq_db_buf_fail;
 691                 }
 692                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 693
 694                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 695                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 696                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 697         } else
 698                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 699                                  HNS_ROCE_V1_SDB_ALFUL);
 700
 701         if (odb_ext_mod) {
 702                 db->ext_db->odb_buf_list = kmalloc(
 703                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 704                 if (!db->ext_db->odb_buf_list) {
 705                         ret = -ENOMEM;
 706                         goto ext_odb_buf_fail_out;
 707                 }
 708
 709                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 710                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 711                                                      &odb_dma_addr, GFP_KERNEL);
 712                 if (!db->ext_db->odb_buf_list->buf) {
 713                         ret = -ENOMEM;
 714                         goto alloc_otr_db_buf_fail;
 715                 }
 716                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 717
 718                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 719                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 720                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 721         } else
 722                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 723                                  HNS_ROCE_V1_ODB_ALFUL);
 724
 725         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 726
 727         return 0;
 728
 729 alloc_otr_db_buf_fail:
 730         kfree(db->ext_db->odb_buf_list);
 731
 732 ext_odb_buf_fail_out:
 733         if (sdb_ext_mod) {
 734                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 735                                   db->ext_db->sdb_buf_list->buf,
 736                                   db->ext_db->sdb_buf_list->map);
 737         }
 738
 739 alloc_sq_db_buf_fail:
 740         if (sdb_ext_mod)
 741                 kfree(db->ext_db->sdb_buf_list);
 742
 743 ext_sdb_buf_fail_out:
 744         kfree(db->ext_db);
 745         return ret;
 746 }
 747
 748 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 749                                                     struct ib_pd *pd)
 750 {
 751         struct device *dev = &hr_dev->pdev->dev;
 752         struct ib_qp_init_attr init_attr;
 753         struct ib_qp *qp;
 754
 755         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 756         init_attr.qp_type               = IB_QPT_RC;
 757         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 758         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 759         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 760
 761         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 762         if (IS_ERR(qp)) {
 763                 dev_err(dev, "Create loop qp for mr free failed!");
 764                 return NULL;
 765         }
 766
 767         return to_hr_qp(qp);
 768 }
 769
 770 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 771 {
 772         struct hns_roce_v1_priv *priv = hr_dev->priv;
 773         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 774         struct hns_roce_caps *caps = &hr_dev->caps;
 775         struct ib_device *ibdev = &hr_dev->ib_dev;
 776         struct device *dev = &hr_dev->pdev->dev;
 777         struct ib_cq_init_attr cq_init_attr;
 778         struct ib_qp_attr attr = { 0 };
 779         struct hns_roce_qp *hr_qp;
 780         struct ib_cq *cq;
 781         struct ib_pd *pd;
 782         union ib_gid dgid;
 783         __be64 subnet_prefix;
 784         int attr_mask = 0;
 785         int ret;
 786         int i, j;
 787         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 788         u8 phy_port;
 789         u32 port = 0;
 790         u8 sl;
 791
 792         /* Reserved cq for loop qp */
 793         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 794         cq_init_attr.comp_vector        = 0;
 795
 796         cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
 797         if (!cq)
 798                 return -ENOMEM;
 799
 800         ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
 801         if (ret) {
 802                 dev_err(dev, "Create cq for reserved loop qp failed!");
 803                 goto alloc_cq_failed;
 804         }
 805         free_mr->mr_free_cq = to_hr_cq(cq);
 806         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 807         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 808         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 809         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 810         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 811         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 812
 813         pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
 814         if (!pd) {
 815                 ret = -ENOMEM;
 816                 goto alloc_mem_failed;
 817         }
 818
 819         pd->device  = ibdev;
 820         ret = hns_roce_alloc_pd(pd, NULL);
 821         if (ret)
 822                 goto alloc_pd_failed;
 823
 824         free_mr->mr_free_pd = to_hr_pd(pd);
 825         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 826         free_mr->mr_free_pd->ibpd.uobject = NULL;
 827         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 828         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 829
 830         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 831         attr.pkey_index         = 0;
 832         attr.min_rnr_timer      = 0;
 833         /* Disable read ability */
 834         attr.max_dest_rd_atomic = 0;
 835         attr.max_rd_atomic      = 0;
 836         /* Use arbitrary values as rq_psn and sq_psn */
 837         attr.rq_psn             = 0x0808;
 838         attr.sq_psn             = 0x0808;
 839         attr.retry_cnt          = 7;
 840         attr.rnr_retry          = 7;
 841         attr.timeout            = 0x12;
 842         attr.path_mtu           = IB_MTU_256;
 843         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 844         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 845         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 846
 847         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 848         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 849                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 850                                 (i % HNS_ROCE_MAX_PORTS);
 851                 sl = i / HNS_ROCE_MAX_PORTS;
 852
 853                 for (j = 0; j < caps->num_ports; j++) {
 854                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 855                                 queue_en[i] = 1;
 856                                 port = j;
 857                                 break;
 858                         }
 859                 }
 860
 861                 if (!queue_en[i])
 862                         continue;
 863
 864                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 865                 if (!free_mr->mr_free_qp[i]) {
 866                         dev_err(dev, "Create loop qp failed!\n");
 867                         ret = -ENOMEM;
 868                         goto create_lp_qp_failed;
 869                 }
 870                 hr_qp = free_mr->mr_free_qp[i];
 871
 872                 hr_qp->port             = port;
 873                 hr_qp->phy_port         = phy_port;
 874                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 875                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 876                 hr_qp->ibqp.uobject     = NULL;
 877                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 878                 hr_qp->ibqp.pd          = pd;
 879                 hr_qp->ibqp.recv_cq     = cq;
 880                 hr_qp->ibqp.send_cq     = cq;
 881
 882                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 883                 rdma_ah_set_sl(&attr.ah_attr, sl);
 884                 attr.port_num           = port + 1;
 885
 886                 attr.dest_qp_num        = hr_qp->qpn;
 887                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 888                        hr_dev->dev_addr[port],
 889                        ETH_ALEN);
 890
 891                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 892                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 893                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 894                 dgid.raw[11] = 0xff;
 895                 dgid.raw[12] = 0xfe;
 896                 dgid.raw[8] ^= 2;
 897                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 898
 899                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 900                                             IB_QPS_RESET, IB_QPS_INIT);
 901                 if (ret) {
 902                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 903                         goto create_lp_qp_failed;
 904                 }
 905
 906                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 907                                             IB_QPS_INIT, IB_QPS_RTR);
 908                 if (ret) {
 909                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 910                         goto create_lp_qp_failed;
 911                 }
 912
 913                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 914                                             IB_QPS_RTR, IB_QPS_RTS);
 915                 if (ret) {
 916                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 917                         goto create_lp_qp_failed;
 918                 }
 919         }
 920
 921         return 0;
 922
 923 create_lp_qp_failed:
 924         for (i -= 1; i >= 0; i--) {
 925                 hr_qp = free_mr->mr_free_qp[i];
 926                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
 927                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 928         }
 929
 930         hns_roce_dealloc_pd(pd, NULL);
 931
 932 alloc_pd_failed:
 933         kfree(pd);
 934
 935 alloc_mem_failed:
 936         hns_roce_destroy_cq(cq, NULL);
 937 alloc_cq_failed:
 938         kfree(cq);
 939         return ret;
 940 }
 941
 942 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 943 {
 944         struct hns_roce_v1_priv *priv = hr_dev->priv;
 945         struct hns_roce_free_mr *free_mr = &priv->free_mr;
 946         struct device *dev = &hr_dev->pdev->dev;
 947         struct hns_roce_qp *hr_qp;
 948         int ret;
 949         int i;
 950
 951         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 952                 hr_qp = free_mr->mr_free_qp[i];
 953                 if (!hr_qp)
 954                         continue;
 955
 956                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
 957                 if (ret)
 958                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 959                                 i, ret);
 960         }
 961
 962         hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
 963         kfree(&free_mr->mr_free_cq->ib_cq);
 964         hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
 965         kfree(&free_mr->mr_free_pd->ibpd);
 966 }
 967
 968 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 969 {
 970         struct hns_roce_v1_priv *priv = hr_dev->priv;
 971         struct hns_roce_db_table *db = &priv->db_table;
 972         struct device *dev = &hr_dev->pdev->dev;
 973         u32 sdb_ext_mod;
 974         u32 odb_ext_mod;
 975         u32 sdb_evt_mod;
 976         u32 odb_evt_mod;
 977         int ret;
 978
 979         memset(db, 0, sizeof(*db));
 980
 981         /* Default DB mode */
 982         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 983         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 984         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 985         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 986
 987         db->sdb_ext_mod = sdb_ext_mod;
 988         db->odb_ext_mod = odb_ext_mod;
 989
 990         /* Init extend DB */
 991         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 992         if (ret) {
 993                 dev_err(dev, "Failed in extend DB configuration.\n");
 994                 return ret;
 995         }
 996
 997         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 998
 999         return 0;
1000 }
1001
1002 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
1003 {
1004         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
1005         struct hns_roce_dev *hr_dev;
1006
1007         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
1008                                   work);
1009         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
1010
1011         hns_roce_v1_release_lp_qp(hr_dev);
1012
1013         if (hns_roce_v1_rsv_lp_qp(hr_dev))
1014                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
1015
1016         if (lp_qp_work->comp_flag)
1017                 complete(lp_qp_work->comp);
1018
1019         kfree(lp_qp_work);
1020 }
1021
1022 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
1023 {
1024         long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
1025         struct hns_roce_v1_priv *priv = hr_dev->priv;
1026         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1027         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
1028         struct device *dev = &hr_dev->pdev->dev;
1029         struct completion comp;
1030
1031         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
1032                              GFP_KERNEL);
1033         if (!lp_qp_work)
1034                 return -ENOMEM;
1035
1036         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
1037
1038         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
1039         lp_qp_work->comp = &comp;
1040         lp_qp_work->comp_flag = 1;
1041
1042         init_completion(lp_qp_work->comp);
1043
1044         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
1045
1046         while (end > 0) {
1047                 if (try_wait_for_completion(&comp))
1048                         return 0;
1049                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
1050                 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
1051         }
1052
1053         lp_qp_work->comp_flag = 0;
1054         if (try_wait_for_completion(&comp))
1055                 return 0;
1056
1057         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1058         return -ETIMEDOUT;
1059 }
1060
1061 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1062 {
1063         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1064         struct device *dev = &hr_dev->pdev->dev;
1065         struct ib_send_wr send_wr;
1066         const struct ib_send_wr *bad_wr;
1067         int ret;
1068
1069         memset(&send_wr, 0, sizeof(send_wr));
1070         send_wr.next    = NULL;
1071         send_wr.num_sge = 0;
1072         send_wr.send_flags = 0;
1073         send_wr.sg_list = NULL;
1074         send_wr.wr_id   = (unsigned long long)&send_wr;
1075         send_wr.opcode  = IB_WR_RDMA_WRITE;
1076
1077         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1078         if (ret) {
1079                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1080                 return ret;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1087 {
1088         unsigned long end =
1089                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1090         struct hns_roce_mr_free_work *mr_work =
1091                 container_of(work, struct hns_roce_mr_free_work, work);
1092         struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1093         struct hns_roce_v1_priv *priv = hr_dev->priv;
1094         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1095         struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1096         struct hns_roce_mr *hr_mr = mr_work->mr;
1097         struct device *dev = &hr_dev->pdev->dev;
1098         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1099         struct hns_roce_qp *hr_qp;
1100         int ne = 0;
1101         int ret;
1102         int i;
1103
1104         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1105                 hr_qp = free_mr->mr_free_qp[i];
1106                 if (!hr_qp)
1107                         continue;
1108                 ne++;
1109
1110                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1111                 if (ret) {
1112                         dev_err(dev,
1113                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1114                              hr_qp->qpn, ret);
1115                         goto free_work;
1116                 }
1117         }
1118
1119         if (!ne) {
1120                 dev_err(dev, "Reserved loop qp is absent!\n");
1121                 goto free_work;
1122         }
1123
1124         do {
1125                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1126                 if (ret < 0 && hr_qp) {
1127                         dev_err(dev,
1128                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1129                            hr_qp->qpn, ret, hr_mr->key, ne);
1130                         goto free_work;
1131                 }
1132                 ne -= ret;
1133                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1134                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1135         } while (ne && time_before_eq(jiffies, end));
1136
1137         if (ne != 0)
1138                 dev_err(dev,
1139                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1140                         hr_mr->key, ne);
1141
1142 free_work:
1143         if (mr_work->comp_flag)
1144                 complete(mr_work->comp);
1145         kfree(mr_work);
1146 }
1147
1148 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1149                                 struct hns_roce_mr *mr, struct ib_udata *udata)
1150 {
1151         struct hns_roce_v1_priv *priv = hr_dev->priv;
1152         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1153         long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1154         struct device *dev = &hr_dev->pdev->dev;
1155         struct hns_roce_mr_free_work *mr_work;
1156         unsigned long start = jiffies;
1157         struct completion comp;
1158         int ret = 0;
1159
1160         if (mr->enabled) {
1161                 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1162                                             key_to_hw_index(mr->key) &
1163                                             (hr_dev->caps.num_mtpts - 1)))
1164                         dev_warn(dev, "DESTROY_MPT failed!\n");
1165         }
1166
1167         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1168         if (!mr_work) {
1169                 ret = -ENOMEM;
1170                 goto free_mr;
1171         }
1172
1173         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1174
1175         mr_work->ib_dev = &(hr_dev->ib_dev);
1176         mr_work->comp = &comp;
1177         mr_work->comp_flag = 1;
1178         mr_work->mr = (void *)mr;
1179         init_completion(mr_work->comp);
1180
1181         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1182
1183         while (end > 0) {
1184                 if (try_wait_for_completion(&comp))
1185                         goto free_mr;
1186                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1187                 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1188         }
1189
1190         mr_work->comp_flag = 0;
1191         if (try_wait_for_completion(&comp))
1192                 goto free_mr;
1193
1194         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1195         ret = -ETIMEDOUT;
1196
1197 free_mr:
1198         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1199                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1200
1201         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1202                              key_to_hw_index(mr->key));
1203         hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1204         kfree(mr);
1205
1206         return ret;
1207 }
1208
1209 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1210 {
1211         struct hns_roce_v1_priv *priv = hr_dev->priv;
1212         struct hns_roce_db_table *db = &priv->db_table;
1213         struct device *dev = &hr_dev->pdev->dev;
1214
1215         if (db->sdb_ext_mod) {
1216                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1217                                   db->ext_db->sdb_buf_list->buf,
1218                                   db->ext_db->sdb_buf_list->map);
1219                 kfree(db->ext_db->sdb_buf_list);
1220         }
1221
1222         if (db->odb_ext_mod) {
1223                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1224                                   db->ext_db->odb_buf_list->buf,
1225                                   db->ext_db->odb_buf_list->map);
1226                 kfree(db->ext_db->odb_buf_list);
1227         }
1228
1229         kfree(db->ext_db);
1230 }
1231
1232 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1233 {
1234         struct hns_roce_v1_priv *priv = hr_dev->priv;
1235         struct hns_roce_raq_table *raq = &priv->raq_table;
1236         struct device *dev = &hr_dev->pdev->dev;
1237         dma_addr_t addr;
1238         int raq_shift;
1239         __le32 tmp;
1240         u32 val;
1241         int ret;
1242
1243         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1244         if (!raq->e_raq_buf)
1245                 return -ENOMEM;
1246
1247         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1248                                                  &addr, GFP_KERNEL);
1249         if (!raq->e_raq_buf->buf) {
1250                 ret = -ENOMEM;
1251                 goto err_dma_alloc_raq;
1252         }
1253         raq->e_raq_buf->map = addr;
1254
1255         /* Configure raq extended address. 48bit 4K align */
1256         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1257
1258         /* Configure raq_shift */
1259         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1260         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1261         tmp = cpu_to_le32(val);
1262         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1263                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1264         /*
1265          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1266          * using 4K page, and shift more 32 because of
1267          * calculating the high 32 bit value evaluated to hardware.
1268          */
1269         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1270                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1271                        raq->e_raq_buf->map >> 44);
1272         val = le32_to_cpu(tmp);
1273         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1274         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1275
1276         /* Configure raq threshold */
1277         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1278         tmp = cpu_to_le32(val);
1279         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1280                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1281                        HNS_ROCE_V1_EXT_RAQ_WF);
1282         val = le32_to_cpu(tmp);
1283         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1284         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1285
1286         /* Enable extend raq */
1287         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1288         tmp = cpu_to_le32(val);
1289         roce_set_field(tmp,
1290                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1291                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1292                        POL_TIME_INTERVAL_VAL);
1293         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1294         roce_set_field(tmp,
1295                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1296                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1297                        2);
1298         roce_set_bit(tmp,
1299                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1300         val = le32_to_cpu(tmp);
1301         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1302         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1303
1304         /* Enable raq drop */
1305         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1306         tmp = cpu_to_le32(val);
1307         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1308         val = le32_to_cpu(tmp);
1309         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1310         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1311
1312         return 0;
1313
1314 err_dma_alloc_raq:
1315         kfree(raq->e_raq_buf);
1316         return ret;
1317 }
1318
1319 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1320 {
1321         struct hns_roce_v1_priv *priv = hr_dev->priv;
1322         struct hns_roce_raq_table *raq = &priv->raq_table;
1323         struct device *dev = &hr_dev->pdev->dev;
1324
1325         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1326                           raq->e_raq_buf->map);
1327         kfree(raq->e_raq_buf);
1328 }
1329
1330 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1331 {
1332         __le32 tmp;
1333         u32 val;
1334
1335         if (enable_flag) {
1336                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1337                  /* Open all ports */
1338                 tmp = cpu_to_le32(val);
1339                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1340                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1341                                ALL_PORT_VAL_OPEN);
1342                 val = le32_to_cpu(tmp);
1343                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1344         } else {
1345                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1346                 /* Close all ports */
1347                 tmp = cpu_to_le32(val);
1348                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1349                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1350                 val = le32_to_cpu(tmp);
1351                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1352         }
1353 }
1354
1355 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1356 {
1357         struct hns_roce_v1_priv *priv = hr_dev->priv;
1358         struct device *dev = &hr_dev->pdev->dev;
1359         int ret;
1360
1361         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1362                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1363                 GFP_KERNEL);
1364         if (!priv->bt_table.qpc_buf.buf)
1365                 return -ENOMEM;
1366
1367         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1368                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1369                 GFP_KERNEL);
1370         if (!priv->bt_table.mtpt_buf.buf) {
1371                 ret = -ENOMEM;
1372                 goto err_failed_alloc_mtpt_buf;
1373         }
1374
1375         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1376                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1377                 GFP_KERNEL);
1378         if (!priv->bt_table.cqc_buf.buf) {
1379                 ret = -ENOMEM;
1380                 goto err_failed_alloc_cqc_buf;
1381         }
1382
1383         return 0;
1384
1385 err_failed_alloc_cqc_buf:
1386         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1387                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1388
1389 err_failed_alloc_mtpt_buf:
1390         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1391                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1392
1393         return ret;
1394 }
1395
1396 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1397 {
1398         struct hns_roce_v1_priv *priv = hr_dev->priv;
1399         struct device *dev = &hr_dev->pdev->dev;
1400
1401         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1402                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1403
1404         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1405                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1406
1407         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1408                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1409 }
1410
1411 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1412 {
1413         struct hns_roce_v1_priv *priv = hr_dev->priv;
1414         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1415         struct device *dev = &hr_dev->pdev->dev;
1416
1417         /*
1418          * This buffer will be used for CQ's tptr(tail pointer), also
1419          * named ci(customer index). Every CQ will use 2 bytes to save
1420          * cqe ci in hip06. Hardware will read this area to get new ci
1421          * when the queue is almost full.
1422          */
1423         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1424                                            &tptr_buf->map, GFP_KERNEL);
1425         if (!tptr_buf->buf)
1426                 return -ENOMEM;
1427
1428         hr_dev->tptr_dma_addr = tptr_buf->map;
1429         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1430
1431         return 0;
1432 }
1433
1434 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1435 {
1436         struct hns_roce_v1_priv *priv = hr_dev->priv;
1437         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1438         struct device *dev = &hr_dev->pdev->dev;
1439
1440         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1441                           tptr_buf->buf, tptr_buf->map);
1442 }
1443
1444 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1445 {
1446         struct hns_roce_v1_priv *priv = hr_dev->priv;
1447         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1448         struct device *dev = &hr_dev->pdev->dev;
1449         int ret;
1450
1451         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1452         if (!free_mr->free_mr_wq) {
1453                 dev_err(dev, "Create free mr workqueue failed!\n");
1454                 return -ENOMEM;
1455         }
1456
1457         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1458         if (ret) {
1459                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1460                 destroy_workqueue(free_mr->free_mr_wq);
1461         }
1462
1463         return ret;
1464 }
1465
1466 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1467 {
1468         struct hns_roce_v1_priv *priv = hr_dev->priv;
1469         struct hns_roce_free_mr *free_mr = &priv->free_mr;
1470
1471         destroy_workqueue(free_mr->free_mr_wq);
1472
1473         hns_roce_v1_release_lp_qp(hr_dev);
1474 }
1475
1476 /**
1477  * hns_roce_v1_reset - reset RoCE
1478  * @hr_dev: RoCE device struct pointer
1479  * @dereset: true -- drop reset, false -- reset
1480  * return 0 - success , negative --fail
1481  */
1482 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1483 {
1484         struct device_node *dsaf_node;
1485         struct device *dev = &hr_dev->pdev->dev;
1486         struct device_node *np = dev->of_node;
1487         struct fwnode_handle *fwnode;
1488         int ret;
1489
1490         /* check if this is DT/ACPI case */
1491         if (dev_of_node(dev)) {
1492                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1493                 if (!dsaf_node) {
1494                         dev_err(dev, "could not find dsaf-handle\n");
1495                         return -EINVAL;
1496                 }
1497                 fwnode = &dsaf_node->fwnode;
1498         } else if (is_acpi_device_node(dev->fwnode)) {
1499                 struct fwnode_reference_args args;
1500
1501                 ret = acpi_node_get_property_reference(dev->fwnode,
1502                                                        "dsaf-handle", 0, &args);
1503                 if (ret) {
1504                         dev_err(dev, "could not find dsaf-handle\n");
1505                         return ret;
1506                 }
1507                 fwnode = args.fwnode;
1508         } else {
1509                 dev_err(dev, "cannot read data from DT or ACPI\n");
1510                 return -ENXIO;
1511         }
1512
1513         ret = hns_dsaf_roce_reset(fwnode, false);
1514         if (ret)
1515                 return ret;
1516
1517         if (dereset) {
1518                 msleep(SLEEP_TIME_INTERVAL);
1519                 ret = hns_dsaf_roce_reset(fwnode, true);
1520         }
1521
1522         return ret;
1523 }
1524
1525 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1526 {
1527         struct hns_roce_caps *caps = &hr_dev->caps;
1528         int i;
1529
1530         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1531         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1532         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1533                                 ((u64)roce_read(hr_dev,
1534                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1535         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1536
1537         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1538         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1539         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1540         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1541         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1542         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1543         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1544         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1545         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1546         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1547         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1548         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1549         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1550         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1551         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1552         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1553         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1554         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1555         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1556         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1557         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1558         caps->qpc_sz            = HNS_ROCE_V1_QPC_SIZE;
1559         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1560         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1561         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1562         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1563         caps->cqe_sz            = HNS_ROCE_V1_CQE_SIZE;
1564         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1565         caps->reserved_lkey     = 0;
1566         caps->reserved_pds      = 0;
1567         caps->reserved_mrws     = 1;
1568         caps->reserved_uars     = 0;
1569         caps->reserved_cqs      = 0;
1570         caps->reserved_qps      = 12; /* 2 SQP per port, six ports total 12 */
1571         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1572
1573         for (i = 0; i < caps->num_ports; i++)
1574                 caps->pkey_table_len[i] = 1;
1575
1576         for (i = 0; i < caps->num_ports; i++) {
1577                 /* Six ports shared 16 GID in v1 engine */
1578                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1579                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1580                                                  caps->num_ports;
1581                 else
1582                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1583                                                  caps->num_ports + 1;
1584         }
1585
1586         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1587         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1588         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1589         caps->max_mtu = IB_MTU_2048;
1590
1591         return 0;
1592 }
1593
1594 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1595 {
1596         int ret;
1597         u32 val;
1598         __le32 tmp;
1599         struct device *dev = &hr_dev->pdev->dev;
1600
1601         /* DMAE user config */
1602         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1603         tmp = cpu_to_le32(val);
1604         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1605                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1606         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1607                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1608                        1 << PAGES_SHIFT_16);
1609         val = le32_to_cpu(tmp);
1610         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1611
1612         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1613         tmp = cpu_to_le32(val);
1614         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1615                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1616         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1617                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1618                        1 << PAGES_SHIFT_16);
1619
1620         ret = hns_roce_db_init(hr_dev);
1621         if (ret) {
1622                 dev_err(dev, "doorbell init failed!\n");
1623                 return ret;
1624         }
1625
1626         ret = hns_roce_raq_init(hr_dev);
1627         if (ret) {
1628                 dev_err(dev, "raq init failed!\n");
1629                 goto error_failed_raq_init;
1630         }
1631
1632         ret = hns_roce_bt_init(hr_dev);
1633         if (ret) {
1634                 dev_err(dev, "bt init failed!\n");
1635                 goto error_failed_bt_init;
1636         }
1637
1638         ret = hns_roce_tptr_init(hr_dev);
1639         if (ret) {
1640                 dev_err(dev, "tptr init failed!\n");
1641                 goto error_failed_tptr_init;
1642         }
1643
1644         ret = hns_roce_free_mr_init(hr_dev);
1645         if (ret) {
1646                 dev_err(dev, "free mr init failed!\n");
1647                 goto error_failed_free_mr_init;
1648         }
1649
1650         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1651
1652         return 0;
1653
1654 error_failed_free_mr_init:
1655         hns_roce_tptr_free(hr_dev);
1656
1657 error_failed_tptr_init:
1658         hns_roce_bt_free(hr_dev);
1659
1660 error_failed_bt_init:
1661         hns_roce_raq_free(hr_dev);
1662
1663 error_failed_raq_init:
1664         hns_roce_db_free(hr_dev);
1665         return ret;
1666 }
1667
1668 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1669 {
1670         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1671         hns_roce_free_mr_free(hr_dev);
1672         hns_roce_tptr_free(hr_dev);
1673         hns_roce_bt_free(hr_dev);
1674         hns_roce_raq_free(hr_dev);
1675         hns_roce_db_free(hr_dev);
1676 }
1677
1678 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1679 {
1680         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1681
1682         return (!!(status & (1 << HCR_GO_BIT)));
1683 }
1684
1685 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1686                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1687                                  u16 op, u16 token, int event)
1688 {
1689         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1690         unsigned long end;
1691         u32 val = 0;
1692         __le32 tmp;
1693
1694         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1695         while (hns_roce_v1_cmd_pending(hr_dev)) {
1696                 if (time_after(jiffies, end)) {
1697                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1698                                 (int)jiffies, (int)end);
1699                         return -EAGAIN;
1700                 }
1701                 cond_resched();
1702         }
1703
1704         tmp = cpu_to_le32(val);
1705         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1706                        op);
1707         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1708                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1709         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1710         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1711         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1712                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1713
1714         val = le32_to_cpu(tmp);
1715         writeq(in_param, hcr + 0);
1716         writeq(out_param, hcr + 2);
1717         writel(in_modifier, hcr + 4);
1718         /* Memory barrier */
1719         wmb();
1720
1721         writel(val, hcr + 5);
1722
1723         return 0;
1724 }
1725
1726 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1727                                 unsigned int timeout)
1728 {
1729         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1730         unsigned long end;
1731         u32 status = 0;
1732
1733         end = msecs_to_jiffies(timeout) + jiffies;
1734         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1735                 cond_resched();
1736
1737         if (hns_roce_v1_cmd_pending(hr_dev)) {
1738                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1739                 return -ETIMEDOUT;
1740         }
1741
1742         status = le32_to_cpu((__force __le32)
1743                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1744         if ((status & STATUS_MASK) != 0x1) {
1745                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1746                 return -EBUSY;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u32 port,
1753                                int gid_index, const union ib_gid *gid,
1754                                const struct ib_gid_attr *attr)
1755 {
1756         unsigned long flags;
1757         u32 *p = NULL;
1758         u8 gid_idx;
1759
1760         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1761
1762         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1763
1764         p = (u32 *)&gid->raw[0];
1765         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1766                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1767
1768         p = (u32 *)&gid->raw[4];
1769         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1770                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1771
1772         p = (u32 *)&gid->raw[8];
1773         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1774                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1775
1776         p = (u32 *)&gid->raw[0xc];
1777         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1778                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1779
1780         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1781
1782         return 0;
1783 }
1784
1785 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1786                                u8 *addr)
1787 {
1788         u32 reg_smac_l;
1789         u16 reg_smac_h;
1790         __le32 tmp;
1791         u16 *p_h;
1792         u32 *p;
1793         u32 val;
1794
1795         /*
1796          * When mac changed, loopback may fail
1797          * because of smac not equal to dmac.
1798          * We Need to release and create reserved qp again.
1799          */
1800         if (hr_dev->hw->dereg_mr) {
1801                 int ret;
1802
1803                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1804                 if (ret && ret != -ETIMEDOUT)
1805                         return ret;
1806         }
1807
1808         p = (u32 *)(&addr[0]);
1809         reg_smac_l = *p;
1810         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1811                        PHY_PORT_OFFSET * phy_port);
1812
1813         val = roce_read(hr_dev,
1814                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1815         tmp = cpu_to_le32(val);
1816         p_h = (u16 *)(&addr[4]);
1817         reg_smac_h  = *p_h;
1818         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1819                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1820         val = le32_to_cpu(tmp);
1821         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1822                    val);
1823
1824         return 0;
1825 }
1826
1827 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1828                                 enum ib_mtu mtu)
1829 {
1830         __le32 tmp;
1831         u32 val;
1832
1833         val = roce_read(hr_dev,
1834                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1835         tmp = cpu_to_le32(val);
1836         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1837                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1838         val = le32_to_cpu(tmp);
1839         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1840                    val);
1841 }
1842
1843 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1844                                   struct hns_roce_mr *mr,
1845                                   unsigned long mtpt_idx)
1846 {
1847         u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1848         struct ib_device *ibdev = &hr_dev->ib_dev;
1849         struct hns_roce_v1_mpt_entry *mpt_entry;
1850         dma_addr_t pbl_ba;
1851         int count;
1852         int i;
1853
1854         /* MPT filled into mailbox buf */
1855         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1856         memset(mpt_entry, 0, sizeof(*mpt_entry));
1857
1858         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1859                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1860         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1861                        MPT_BYTE_4_KEY_S, mr->key);
1862         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1863                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1864         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1865         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1866                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1867         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1868         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1869                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1870         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1871         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1872                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1873         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1874                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1875         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1876                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1877         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1878                      0);
1879         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1880
1881         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1882                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1883         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1884                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1885
1886         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1887         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1888         mpt_entry->length = cpu_to_le32((u32)mr->size);
1889
1890         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1891                        MPT_BYTE_28_PD_S, mr->pd);
1892         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1893                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1894         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1895                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1896
1897         /* DMA memory register */
1898         if (mr->type == MR_TYPE_DMA)
1899                 return 0;
1900
1901         count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1902                                   ARRAY_SIZE(pages), &pbl_ba);
1903         if (count < 1) {
1904                 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1905                 return -ENOBUFS;
1906         }
1907
1908         /* Register user mr */
1909         for (i = 0; i < count; i++) {
1910                 switch (i) {
1911                 case 0:
1912                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1913                         roce_set_field(mpt_entry->mpt_byte_36,
1914                                 MPT_BYTE_36_PA0_H_M,
1915                                 MPT_BYTE_36_PA0_H_S,
1916                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1917                         break;
1918                 case 1:
1919                         roce_set_field(mpt_entry->mpt_byte_36,
1920                                        MPT_BYTE_36_PA1_L_M,
1921                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1922                         roce_set_field(mpt_entry->mpt_byte_40,
1923                                 MPT_BYTE_40_PA1_H_M,
1924                                 MPT_BYTE_40_PA1_H_S,
1925                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1926                         break;
1927                 case 2:
1928                         roce_set_field(mpt_entry->mpt_byte_40,
1929                                        MPT_BYTE_40_PA2_L_M,
1930                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1931                         roce_set_field(mpt_entry->mpt_byte_44,
1932                                 MPT_BYTE_44_PA2_H_M,
1933                                 MPT_BYTE_44_PA2_H_S,
1934                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1935                         break;
1936                 case 3:
1937                         roce_set_field(mpt_entry->mpt_byte_44,
1938                                        MPT_BYTE_44_PA3_L_M,
1939                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1940                         roce_set_field(mpt_entry->mpt_byte_48,
1941                                 MPT_BYTE_48_PA3_H_M,
1942                                 MPT_BYTE_48_PA3_H_S,
1943                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1944                         break;
1945                 case 4:
1946                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1947                         roce_set_field(mpt_entry->mpt_byte_56,
1948                                 MPT_BYTE_56_PA4_H_M,
1949                                 MPT_BYTE_56_PA4_H_S,
1950                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1951                         break;
1952                 case 5:
1953                         roce_set_field(mpt_entry->mpt_byte_56,
1954                                        MPT_BYTE_56_PA5_L_M,
1955                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1956                         roce_set_field(mpt_entry->mpt_byte_60,
1957                                 MPT_BYTE_60_PA5_H_M,
1958                                 MPT_BYTE_60_PA5_H_S,
1959                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1960                         break;
1961                 case 6:
1962                         roce_set_field(mpt_entry->mpt_byte_60,
1963                                        MPT_BYTE_60_PA6_L_M,
1964                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1965                         roce_set_field(mpt_entry->mpt_byte_64,
1966                                 MPT_BYTE_64_PA6_H_M,
1967                                 MPT_BYTE_64_PA6_H_S,
1968                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1969                         break;
1970                 default:
1971                         break;
1972                 }
1973         }
1974
1975         mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1976         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1977                        MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1978
1979         return 0;
1980 }
1981
1982 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1983 {
1984         return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1985 }
1986
1987 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1988 {
1989         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1990
1991         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1992         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1993                 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1994 }
1995
1996 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1997 {
1998         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1999 }
2000
2001 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2002 {
2003         __le32 doorbell[2];
2004
2005         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2006         doorbell[1] = 0;
2007         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2008         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2009                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2010         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2011                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2012         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2013                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2014
2015         hns_roce_write64_k(doorbell, hr_cq->db_reg);
2016 }
2017
2018 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2019                                    struct hns_roce_srq *srq)
2020 {
2021         struct hns_roce_cqe *cqe, *dest;
2022         u32 prod_index;
2023         int nfreed = 0;
2024         u8 owner_bit;
2025
2026         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2027              ++prod_index) {
2028                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2029                         break;
2030         }
2031
2032         /*
2033          * Now backwards through the CQ, removing CQ entries
2034          * that match our QP by overwriting them with next entries.
2035          */
2036         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2037                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2038                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2039                                      CQE_BYTE_16_LOCAL_QPN_S) &
2040                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
2041                         /* In v1 engine, not support SRQ */
2042                         ++nfreed;
2043                 } else if (nfreed) {
2044                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
2045                                        hr_cq->ib_cq.cqe);
2046                         owner_bit = roce_get_bit(dest->cqe_byte_4,
2047                                                  CQE_BYTE_4_OWNER_S);
2048                         memcpy(dest, cqe, sizeof(*cqe));
2049                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2050                                      owner_bit);
2051                 }
2052         }
2053
2054         if (nfreed) {
2055                 hr_cq->cons_index += nfreed;
2056                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2057         }
2058 }
2059
2060 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2061                                  struct hns_roce_srq *srq)
2062 {
2063         spin_lock_irq(&hr_cq->lock);
2064         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2065         spin_unlock_irq(&hr_cq->lock);
2066 }
2067
2068 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2069                                   struct hns_roce_cq *hr_cq, void *mb_buf,
2070                                   u64 *mtts, dma_addr_t dma_handle)
2071 {
2072         struct hns_roce_v1_priv *priv = hr_dev->priv;
2073         struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
2074         struct hns_roce_cq_context *cq_context = mb_buf;
2075         dma_addr_t tptr_dma_addr;
2076         int offset;
2077
2078         memset(cq_context, 0, sizeof(*cq_context));
2079
2080         /* Get the tptr for this CQ. */
2081         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2082         tptr_dma_addr = tptr_buf->map + offset;
2083         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2084
2085         /* Register cq_context members */
2086         roce_set_field(cq_context->cqc_byte_4,
2087                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2088                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2089         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2090                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2091
2092         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2093
2094         roce_set_field(cq_context->cqc_byte_12,
2095                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2096                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2097                        ((u64)dma_handle >> 32));
2098         roce_set_field(cq_context->cqc_byte_12,
2099                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2100                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2101                        ilog2(hr_cq->cq_depth));
2102         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2103                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2104
2105         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2106
2107         roce_set_field(cq_context->cqc_byte_20,
2108                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2109                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2110         /* Dedicated hardware, directly set 0 */
2111         roce_set_field(cq_context->cqc_byte_20,
2112                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2113                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2114         /**
2115          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2116          * using 4K page, and shift more 32 because of
2117          * calculating the high 32 bit value evaluated to hardware.
2118          */
2119         roce_set_field(cq_context->cqc_byte_20,
2120                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2121                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2122                        tptr_dma_addr >> 44);
2123
2124         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2125
2126         roce_set_field(cq_context->cqc_byte_32,
2127                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2128                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2129         roce_set_bit(cq_context->cqc_byte_32,
2130                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2131         roce_set_bit(cq_context->cqc_byte_32,
2132                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2133         roce_set_bit(cq_context->cqc_byte_32,
2134                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2135         roce_set_bit(cq_context->cqc_byte_32,
2136                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2137                      0);
2138         /* The initial value of cq's ci is 0 */
2139         roce_set_field(cq_context->cqc_byte_32,
2140                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2141                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2142 }
2143
2144 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2145                                      enum ib_cq_notify_flags flags)
2146 {
2147         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2148         u32 notification_flag;
2149         __le32 doorbell[2] = {};
2150
2151         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2152                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2153         /*
2154          * flags = 0; Notification Flag = 1, next
2155          * flags = 1; Notification Flag = 0, solocited
2156          */
2157         doorbell[0] =
2158                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2159         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2160         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2161                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2162         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2163                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2164         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2165                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2166                        hr_cq->cqn | notification_flag);
2167
2168         hns_roce_write64_k(doorbell, hr_cq->db_reg);
2169
2170         return 0;
2171 }
2172
2173 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2174                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2175 {
2176         int qpn;
2177         int is_send;
2178         u16 wqe_ctr;
2179         u32 status;
2180         u32 opcode;
2181         struct hns_roce_cqe *cqe;
2182         struct hns_roce_qp *hr_qp;
2183         struct hns_roce_wq *wq;
2184         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2185         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2186         struct device *dev = &hr_dev->pdev->dev;
2187
2188         /* Find cqe according consumer index */
2189         cqe = next_cqe_sw(hr_cq);
2190         if (!cqe)
2191                 return -EAGAIN;
2192
2193         ++hr_cq->cons_index;
2194         /* Memory barrier */
2195         rmb();
2196         /* 0->SQ, 1->RQ */
2197         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2198
2199         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2200         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2201                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2202                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2203                                      CQE_BYTE_20_PORT_NUM_S) +
2204                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2205                                      CQE_BYTE_16_LOCAL_QPN_S) *
2206                                      HNS_ROCE_MAX_PORTS;
2207         } else {
2208                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2209                                      CQE_BYTE_16_LOCAL_QPN_S);
2210         }
2211
2212         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2213                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2214                 if (unlikely(!hr_qp)) {
2215                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2216                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2217                         return -EINVAL;
2218                 }
2219
2220                 *cur_qp = hr_qp;
2221         }
2222
2223         wc->qp = &(*cur_qp)->ibqp;
2224         wc->vendor_err = 0;
2225
2226         status = roce_get_field(cqe->cqe_byte_4,
2227                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2228                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2229                                 HNS_ROCE_CQE_STATUS_MASK;
2230         switch (status) {
2231         case HNS_ROCE_CQE_SUCCESS:
2232                 wc->status = IB_WC_SUCCESS;
2233                 break;
2234         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2235                 wc->status = IB_WC_LOC_LEN_ERR;
2236                 break;
2237         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2238                 wc->status = IB_WC_LOC_QP_OP_ERR;
2239                 break;
2240         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2241                 wc->status = IB_WC_LOC_PROT_ERR;
2242                 break;
2243         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2244                 wc->status = IB_WC_WR_FLUSH_ERR;
2245                 break;
2246         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2247                 wc->status = IB_WC_MW_BIND_ERR;
2248                 break;
2249         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2250                 wc->status = IB_WC_BAD_RESP_ERR;
2251                 break;
2252         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2253                 wc->status = IB_WC_LOC_ACCESS_ERR;
2254                 break;
2255         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2256                 wc->status = IB_WC_REM_INV_REQ_ERR;
2257                 break;
2258         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2259                 wc->status = IB_WC_REM_ACCESS_ERR;
2260                 break;
2261         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2262                 wc->status = IB_WC_REM_OP_ERR;
2263                 break;
2264         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2265                 wc->status = IB_WC_RETRY_EXC_ERR;
2266                 break;
2267         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2268                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2269                 break;
2270         default:
2271                 wc->status = IB_WC_GENERAL_ERR;
2272                 break;
2273         }
2274
2275         /* CQE status error, directly return */
2276         if (wc->status != IB_WC_SUCCESS)
2277                 return 0;
2278
2279         if (is_send) {
2280                 /* SQ conrespond to CQE */
2281                 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2282                                                 roce_get_field(cqe->cqe_byte_4,
2283                                                 CQE_BYTE_4_WQE_INDEX_M,
2284                                                 CQE_BYTE_4_WQE_INDEX_S) &
2285                                                 ((*cur_qp)->sq.wqe_cnt-1));
2286                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2287                 case HNS_ROCE_WQE_OPCODE_SEND:
2288                         wc->opcode = IB_WC_SEND;
2289                         break;
2290                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2291                         wc->opcode = IB_WC_RDMA_READ;
2292                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2293                         break;
2294                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2295                         wc->opcode = IB_WC_RDMA_WRITE;
2296                         break;
2297                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2298                         wc->opcode = IB_WC_LOCAL_INV;
2299                         break;
2300                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2301                         wc->opcode = IB_WC_SEND;
2302                         break;
2303                 default:
2304                         wc->status = IB_WC_GENERAL_ERR;
2305                         break;
2306                 }
2307                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2308                                 IB_WC_WITH_IMM : 0);
2309
2310                 wq = &(*cur_qp)->sq;
2311                 if ((*cur_qp)->sq_signal_bits) {
2312                         /*
2313                          * If sg_signal_bit is 1,
2314                          * firstly tail pointer updated to wqe
2315                          * which current cqe correspond to
2316                          */
2317                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2318                                                       CQE_BYTE_4_WQE_INDEX_M,
2319                                                       CQE_BYTE_4_WQE_INDEX_S);
2320                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2321                                     (wq->wqe_cnt - 1);
2322                 }
2323                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2324                 ++wq->tail;
2325         } else {
2326                 /* RQ conrespond to CQE */
2327                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2328                 opcode = roce_get_field(cqe->cqe_byte_4,
2329                                         CQE_BYTE_4_OPERATION_TYPE_M,
2330                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2331                                         HNS_ROCE_CQE_OPCODE_MASK;
2332                 switch (opcode) {
2333                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2334                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2335                         wc->wc_flags = IB_WC_WITH_IMM;
2336                         wc->ex.imm_data =
2337                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2338                         break;
2339                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2340                         if (roce_get_bit(cqe->cqe_byte_4,
2341                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2342                                 wc->opcode = IB_WC_RECV;
2343                                 wc->wc_flags = IB_WC_WITH_IMM;
2344                                 wc->ex.imm_data = cpu_to_be32(
2345                                         le32_to_cpu(cqe->immediate_data));
2346                         } else {
2347                                 wc->opcode = IB_WC_RECV;
2348                                 wc->wc_flags = 0;
2349                         }
2350                         break;
2351                 default:
2352                         wc->status = IB_WC_GENERAL_ERR;
2353                         break;
2354                 }
2355
2356                 /* Update tail pointer, record wr_id */
2357                 wq = &(*cur_qp)->rq;
2358                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2359                 ++wq->tail;
2360                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2361                                             CQE_BYTE_20_SL_S);
2362                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2363                                                 CQE_BYTE_20_REMOTE_QPN_M,
2364                                                 CQE_BYTE_20_REMOTE_QPN_S);
2365                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2366                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2367                                               IB_WC_GRH : 0);
2368                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2369                                                      CQE_BYTE_28_P_KEY_IDX_M,
2370                                                      CQE_BYTE_28_P_KEY_IDX_S);
2371         }
2372
2373         return 0;
2374 }
2375
2376 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2377 {
2378         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2379         struct hns_roce_qp *cur_qp = NULL;
2380         unsigned long flags;
2381         int npolled;
2382         int ret;
2383
2384         spin_lock_irqsave(&hr_cq->lock, flags);
2385
2386         for (npolled = 0; npolled < num_entries; ++npolled) {
2387                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2388                 if (ret)
2389                         break;
2390         }
2391
2392         if (npolled) {
2393                 *hr_cq->tptr_addr = hr_cq->cons_index &
2394                         ((hr_cq->cq_depth << 1) - 1);
2395
2396                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2397         }
2398
2399         spin_unlock_irqrestore(&hr_cq->lock, flags);
2400
2401         if (ret == 0 || ret == -EAGAIN)
2402                 return npolled;
2403         else
2404                 return ret;
2405 }
2406
2407 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2408                                  struct hns_roce_hem_table *table, int obj,
2409                                  int step_idx)
2410 {
2411         struct hns_roce_v1_priv *priv = hr_dev->priv;
2412         struct device *dev = &hr_dev->pdev->dev;
2413         long end = HW_SYNC_TIMEOUT_MSECS;
2414         __le32 bt_cmd_val[2] = {0};
2415         unsigned long flags = 0;
2416         void __iomem *bt_cmd;
2417         u64 bt_ba = 0;
2418
2419         switch (table->type) {
2420         case HEM_TYPE_QPC:
2421                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2422                 break;
2423         case HEM_TYPE_MTPT:
2424                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2425                 break;
2426         case HEM_TYPE_CQC:
2427                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2428                 break;
2429         case HEM_TYPE_SRQC:
2430                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2431                 return -EINVAL;
2432         default:
2433                 return 0;
2434         }
2435         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2436                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2437         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2438                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2439         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2440         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2441
2442         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2443
2444         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2445
2446         while (1) {
2447                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2448                         if (!end) {
2449                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2450                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2451                                         flags);
2452                                 return -EBUSY;
2453                         }
2454                 } else {
2455                         break;
2456                 }
2457                 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2458                 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2459         }
2460
2461         bt_cmd_val[0] = cpu_to_le32(bt_ba);
2462         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2463                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2464         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2465
2466         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2467
2468         return 0;
2469 }
2470
2471 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2472                                  enum hns_roce_qp_state cur_state,
2473                                  enum hns_roce_qp_state new_state,
2474                                  struct hns_roce_qp_context *context,
2475                                  struct hns_roce_qp *hr_qp)
2476 {
2477         static const u16
2478         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2479                 [HNS_ROCE_QP_STATE_RST] = {
2480                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2481                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2482                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2483                 },
2484                 [HNS_ROCE_QP_STATE_INIT] = {
2485                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2486                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2487                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2488                  * We use RST2INIT cmd instead of INIT2INIT.
2489                  */
2490                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2491                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2492                 },
2493                 [HNS_ROCE_QP_STATE_RTR] = {
2494                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2495                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2496                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2497                 },
2498                 [HNS_ROCE_QP_STATE_RTS] = {
2499                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2500                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2501                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2502                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2503                 },
2504                 [HNS_ROCE_QP_STATE_SQD] = {
2505                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2506                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2507                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2508                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2509                 },
2510                 [HNS_ROCE_QP_STATE_ERR] = {
2511                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2512                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2513                 }
2514         };
2515
2516         struct hns_roce_cmd_mailbox *mailbox;
2517         struct device *dev = &hr_dev->pdev->dev;
2518         int ret;
2519
2520         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2521             new_state >= HNS_ROCE_QP_NUM_STATE ||
2522             !op[cur_state][new_state]) {
2523                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2524                         cur_state, new_state);
2525                 return -EINVAL;
2526         }
2527
2528         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2529                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2530                                          HNS_ROCE_CMD_2RST_QP,
2531                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2532
2533         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2534                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2535                                          HNS_ROCE_CMD_2ERR_QP,
2536                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2537
2538         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2539         if (IS_ERR(mailbox))
2540                 return PTR_ERR(mailbox);
2541
2542         memcpy(mailbox->buf, context, sizeof(*context));
2543
2544         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2545                                 op[cur_state][new_state],
2546                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2547
2548         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2549         return ret;
2550 }
2551
2552 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2553                         u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2554 {
2555         struct ib_device *ibdev = &hr_dev->ib_dev;
2556         int count;
2557
2558         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2559         if (count < 1) {
2560                 ibdev_err(ibdev, "Failed to find SQ ba\n");
2561                 return -ENOBUFS;
2562         }
2563
2564         count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2565                                   1, NULL);
2566         if (!count) {
2567                 ibdev_err(ibdev, "Failed to find RQ ba\n");
2568                 return -ENOBUFS;
2569         }
2570
2571         return 0;
2572 }
2573
2574 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2575                              int attr_mask, enum ib_qp_state cur_state,
2576                              enum ib_qp_state new_state)
2577 {
2578         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2579         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2580         struct hns_roce_sqp_context *context;
2581         dma_addr_t dma_handle = 0;
2582         u32 __iomem *addr;
2583         u64 sq_ba = 0;
2584         u64 rq_ba = 0;
2585         __le32 tmp;
2586         u32 reg_val;
2587
2588         context = kzalloc(sizeof(*context), GFP_KERNEL);
2589         if (!context)
2590                 return -ENOMEM;
2591
2592         /* Search QP buf's MTTs */
2593         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2594                 goto out;
2595
2596         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2597                 roce_set_field(context->qp1c_bytes_4,
2598                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2599                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2600                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2601                 roce_set_field(context->qp1c_bytes_4,
2602                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2603                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2604                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2605                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2606                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2607
2608                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2609                 roce_set_field(context->qp1c_bytes_12,
2610                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2611                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2612                                upper_32_bits(dma_handle));
2613
2614                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2615                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2616                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2617                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2618                 roce_set_bit(context->qp1c_bytes_16,
2619                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2620                              hr_qp->sq_signal_bits);
2621                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2622                              1);
2623                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2624                              1);
2625                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2626                              0);
2627
2628                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2629                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2630                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2631                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2632
2633                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2634
2635                 roce_set_field(context->qp1c_bytes_28,
2636                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2637                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2638                                upper_32_bits(rq_ba));
2639                 roce_set_field(context->qp1c_bytes_28,
2640                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2641                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2642
2643                 roce_set_field(context->qp1c_bytes_32,
2644                                QP1C_BYTES_32_RX_CQ_NUM_M,
2645                                QP1C_BYTES_32_RX_CQ_NUM_S,
2646                                to_hr_cq(ibqp->recv_cq)->cqn);
2647                 roce_set_field(context->qp1c_bytes_32,
2648                                QP1C_BYTES_32_TX_CQ_NUM_M,
2649                                QP1C_BYTES_32_TX_CQ_NUM_S,
2650                                to_hr_cq(ibqp->send_cq)->cqn);
2651
2652                 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2653
2654                 roce_set_field(context->qp1c_bytes_40,
2655                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2656                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2657                                upper_32_bits(sq_ba));
2658                 roce_set_field(context->qp1c_bytes_40,
2659                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2660                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2661
2662                 /* Copy context to QP1C register */
2663                 addr = (u32 __iomem *)(hr_dev->reg_base +
2664                                        ROCEE_QP1C_CFG0_0_REG +
2665                                        hr_qp->phy_port * sizeof(*context));
2666
2667                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2668                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2669                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2670                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2671                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2672                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2673                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2674                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2675                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2676                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2677         }
2678
2679         /* Modify QP1C status */
2680         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2681                             hr_qp->phy_port * sizeof(*context));
2682         tmp = cpu_to_le32(reg_val);
2683         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2684                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2685         reg_val = le32_to_cpu(tmp);
2686         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2687                     hr_qp->phy_port * sizeof(*context), reg_val);
2688
2689         hr_qp->state = new_state;
2690         if (new_state == IB_QPS_RESET) {
2691                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2692                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2693                 if (ibqp->send_cq != ibqp->recv_cq)
2694                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2695                                              hr_qp->qpn, NULL);
2696
2697                 hr_qp->rq.head = 0;
2698                 hr_qp->rq.tail = 0;
2699                 hr_qp->sq.head = 0;
2700                 hr_qp->sq.tail = 0;
2701         }
2702
2703         kfree(context);
2704         return 0;
2705
2706 out:
2707         kfree(context);
2708         return -EINVAL;
2709 }
2710
2711 static bool check_qp_state(enum ib_qp_state cur_state,
2712                            enum ib_qp_state new_state)
2713 {
2714         static const bool sm[][IB_QPS_ERR + 1] = {
2715                 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2716                                    [IB_QPS_INIT] = true },
2717                 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2718                                   [IB_QPS_INIT] = true,
2719                                   [IB_QPS_RTR] = true,
2720                                   [IB_QPS_ERR] = true },
2721                 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2722                                  [IB_QPS_RTS] = true,
2723                                  [IB_QPS_ERR] = true },
2724                 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2725                 [IB_QPS_SQD] = {},
2726                 [IB_QPS_SQE] = {},
2727                 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2728         };
2729
2730         return sm[cur_state][new_state];
2731 }
2732
2733 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2734                             int attr_mask, enum ib_qp_state cur_state,
2735                             enum ib_qp_state new_state)
2736 {
2737         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2738         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2739         struct device *dev = &hr_dev->pdev->dev;
2740         struct hns_roce_qp_context *context;
2741         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2742         dma_addr_t dma_handle_2 = 0;
2743         dma_addr_t dma_handle = 0;
2744         __le32 doorbell[2] = {0};
2745         u64 *mtts_2 = NULL;
2746         int ret = -EINVAL;
2747         u64 sq_ba = 0;
2748         u64 rq_ba = 0;
2749         u32 port;
2750         u32 port_num;
2751         u8 *dmac;
2752         u8 *smac;
2753
2754         if (!check_qp_state(cur_state, new_state)) {
2755                 ibdev_err(ibqp->device,
2756                           "not support QP(%u) status from %d to %d\n",
2757                           ibqp->qp_num, cur_state, new_state);
2758                 return -EINVAL;
2759         }
2760
2761         context = kzalloc(sizeof(*context), GFP_KERNEL);
2762         if (!context)
2763                 return -ENOMEM;
2764
2765         /* Search qp buf's mtts */
2766         if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2767                 goto out;
2768
2769         /* Search IRRL's mtts */
2770         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2771                                      hr_qp->qpn, &dma_handle_2);
2772         if (mtts_2 == NULL) {
2773                 dev_err(dev, "qp irrl_table find failed\n");
2774                 goto out;
2775         }
2776
2777         /*
2778          * Reset to init
2779          *      Mandatory param:
2780          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2781          *      Optional param: NA
2782          */
2783         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2784                 roce_set_field(context->qpc_bytes_4,
2785                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2786                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2787                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2788
2789                 roce_set_bit(context->qpc_bytes_4,
2790                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2791                 roce_set_bit(context->qpc_bytes_4,
2792                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2793                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2794                 roce_set_bit(context->qpc_bytes_4,
2795                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2796                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2797                              );
2798                 roce_set_bit(context->qpc_bytes_4,
2799                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2800                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2801                              );
2802                 roce_set_bit(context->qpc_bytes_4,
2803                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2804                 roce_set_field(context->qpc_bytes_4,
2805                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2806                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2807                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2808                 roce_set_field(context->qpc_bytes_4,
2809                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2810                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2811                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2812                 roce_set_field(context->qpc_bytes_4,
2813                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2814                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2815                                to_hr_pd(ibqp->pd)->pdn);
2816                 hr_qp->access_flags = attr->qp_access_flags;
2817                 roce_set_field(context->qpc_bytes_8,
2818                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2819                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2820                                to_hr_cq(ibqp->send_cq)->cqn);
2821                 roce_set_field(context->qpc_bytes_8,
2822                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2823                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2824                                to_hr_cq(ibqp->recv_cq)->cqn);
2825
2826                 if (ibqp->srq)
2827                         roce_set_field(context->qpc_bytes_12,
2828                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2829                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2830                                        to_hr_srq(ibqp->srq)->srqn);
2831
2832                 roce_set_field(context->qpc_bytes_12,
2833                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2834                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2835                                attr->pkey_index);
2836                 hr_qp->pkey_index = attr->pkey_index;
2837                 roce_set_field(context->qpc_bytes_16,
2838                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2839                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2840         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2841                 roce_set_field(context->qpc_bytes_4,
2842                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2843                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2844                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2845                 roce_set_bit(context->qpc_bytes_4,
2846                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2847                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2848                         roce_set_bit(context->qpc_bytes_4,
2849                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2850                                      !!(attr->qp_access_flags &
2851                                      IB_ACCESS_REMOTE_READ));
2852                         roce_set_bit(context->qpc_bytes_4,
2853                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2854                                      !!(attr->qp_access_flags &
2855                                      IB_ACCESS_REMOTE_WRITE));
2856                 } else {
2857                         roce_set_bit(context->qpc_bytes_4,
2858                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2859                                      !!(hr_qp->access_flags &
2860                                      IB_ACCESS_REMOTE_READ));
2861                         roce_set_bit(context->qpc_bytes_4,
2862                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2863                                      !!(hr_qp->access_flags &
2864                                      IB_ACCESS_REMOTE_WRITE));
2865                 }
2866
2867                 roce_set_bit(context->qpc_bytes_4,
2868                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2869                 roce_set_field(context->qpc_bytes_4,
2870                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2871                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2872                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2873                 roce_set_field(context->qpc_bytes_4,
2874                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2875                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2876                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2877                 roce_set_field(context->qpc_bytes_4,
2878                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2879                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2880                                to_hr_pd(ibqp->pd)->pdn);
2881
2882                 roce_set_field(context->qpc_bytes_8,
2883                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2884                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2885                                to_hr_cq(ibqp->send_cq)->cqn);
2886                 roce_set_field(context->qpc_bytes_8,
2887                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2888                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2889                                to_hr_cq(ibqp->recv_cq)->cqn);
2890
2891                 if (ibqp->srq)
2892                         roce_set_field(context->qpc_bytes_12,
2893                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2894                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2895                                        to_hr_srq(ibqp->srq)->srqn);
2896                 if (attr_mask & IB_QP_PKEY_INDEX)
2897                         roce_set_field(context->qpc_bytes_12,
2898                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2899                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2900                                        attr->pkey_index);
2901                 else
2902                         roce_set_field(context->qpc_bytes_12,
2903                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2904                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2905                                        hr_qp->pkey_index);
2906
2907                 roce_set_field(context->qpc_bytes_16,
2908                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2909                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2910         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2911                 if ((attr_mask & IB_QP_ALT_PATH) ||
2912                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2913                     (attr_mask & IB_QP_PKEY_INDEX) ||
2914                     (attr_mask & IB_QP_QKEY)) {
2915                         dev_err(dev, "INIT2RTR attr_mask error\n");
2916                         goto out;
2917                 }
2918
2919                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2920
2921                 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2922                 roce_set_field(context->qpc_bytes_24,
2923                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2924                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2925                                upper_32_bits(dma_handle));
2926                 roce_set_bit(context->qpc_bytes_24,
2927                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2928                              1);
2929                 roce_set_field(context->qpc_bytes_24,
2930                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2931                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2932                                attr->min_rnr_timer);
2933                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2934                 roce_set_field(context->qpc_bytes_32,
2935                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2936                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2937                                ((u32)(dma_handle_2 >> 32)) &
2938                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2939                 roce_set_field(context->qpc_bytes_32,
2940                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2941                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2942                 roce_set_bit(context->qpc_bytes_32,
2943                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2944                              1);
2945                 roce_set_bit(context->qpc_bytes_32,
2946                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2947                              hr_qp->sq_signal_bits);
2948
2949                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2950                         hr_qp->port;
2951                 smac = (u8 *)hr_dev->dev_addr[port];
2952                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2953                 if (ether_addr_equal_unaligned(dmac, smac) ||
2954                     hr_dev->loop_idc == 0x1)
2955                         roce_set_bit(context->qpc_bytes_32,
2956                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2957
2958                 roce_set_bit(context->qpc_bytes_32,
2959                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2960                              rdma_ah_get_ah_flags(&attr->ah_attr));
2961                 roce_set_field(context->qpc_bytes_32,
2962                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2963                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2964                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2965
2966                 if (attr_mask & IB_QP_DEST_QPN)
2967                         roce_set_field(context->qpc_bytes_36,
2968                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2969                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2970                                        attr->dest_qp_num);
2971
2972                 /* Configure GID index */
2973                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2974                 roce_set_field(context->qpc_bytes_36,
2975                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2976                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2977                                 hns_get_gid_index(hr_dev,
2978                                                   port_num - 1,
2979                                                   grh->sgid_index));
2980
2981                 memcpy(&(context->dmac_l), dmac, 4);
2982
2983                 roce_set_field(context->qpc_bytes_44,
2984                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2985                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2986                                *((u16 *)(&dmac[4])));
2987                 roce_set_field(context->qpc_bytes_44,
2988                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2989                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2990                                rdma_ah_get_static_rate(&attr->ah_attr));
2991                 roce_set_field(context->qpc_bytes_44,
2992                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2993                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2994                                grh->hop_limit);
2995
2996                 roce_set_field(context->qpc_bytes_48,
2997                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2998                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2999                                grh->flow_label);
3000                 roce_set_field(context->qpc_bytes_48,
3001                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3002                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3003                                grh->traffic_class);
3004                 roce_set_field(context->qpc_bytes_48,
3005                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3006                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3007
3008                 memcpy(context->dgid, grh->dgid.raw,
3009                        sizeof(grh->dgid.raw));
3010
3011                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3012                         roce_get_field(context->qpc_bytes_44,
3013                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3014                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3015
3016                 roce_set_field(context->qpc_bytes_68,
3017                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3018                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3019                                hr_qp->rq.head);
3020                 roce_set_field(context->qpc_bytes_68,
3021                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3022                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3023
3024                 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
3025
3026                 roce_set_field(context->qpc_bytes_76,
3027                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3028                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3029                         upper_32_bits(rq_ba));
3030                 roce_set_field(context->qpc_bytes_76,
3031                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3032                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3033
3034                 context->rx_rnr_time = 0;
3035
3036                 roce_set_field(context->qpc_bytes_84,
3037                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3038                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3039                                attr->rq_psn - 1);
3040                 roce_set_field(context->qpc_bytes_84,
3041                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3042                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3043
3044                 roce_set_field(context->qpc_bytes_88,
3045                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3046                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3047                                attr->rq_psn);
3048                 roce_set_bit(context->qpc_bytes_88,
3049                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3050                 roce_set_bit(context->qpc_bytes_88,
3051                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3052                 roce_set_field(context->qpc_bytes_88,
3053                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3054                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3055                         0);
3056                 roce_set_field(context->qpc_bytes_88,
3057                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3058                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3059                                0);
3060
3061                 context->dma_length = 0;
3062                 context->r_key = 0;
3063                 context->va_l = 0;
3064                 context->va_h = 0;
3065
3066                 roce_set_field(context->qpc_bytes_108,
3067                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3068                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3069                 roce_set_bit(context->qpc_bytes_108,
3070                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3071                 roce_set_bit(context->qpc_bytes_108,
3072                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3073
3074                 roce_set_field(context->qpc_bytes_112,
3075                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3076                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3077                 roce_set_field(context->qpc_bytes_112,
3078                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3079                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3080
3081                 /* For chip resp ack */
3082                 roce_set_field(context->qpc_bytes_156,
3083                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3084                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3085                                hr_qp->phy_port);
3086                 roce_set_field(context->qpc_bytes_156,
3087                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3088                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3089                                rdma_ah_get_sl(&attr->ah_attr));
3090                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3091         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3092                 /* If exist optional param, return error */
3093                 if ((attr_mask & IB_QP_ALT_PATH) ||
3094                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3095                     (attr_mask & IB_QP_QKEY) ||
3096                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3097                     (attr_mask & IB_QP_CUR_STATE) ||
3098                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3099                         dev_err(dev, "RTR2RTS attr_mask error\n");
3100                         goto out;
3101                 }
3102
3103                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3104
3105                 roce_set_field(context->qpc_bytes_120,
3106                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3107                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3108                                upper_32_bits(sq_ba));
3109
3110                 roce_set_field(context->qpc_bytes_124,
3111                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3112                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3113                 roce_set_field(context->qpc_bytes_124,
3114                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3115                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3116
3117                 roce_set_field(context->qpc_bytes_128,
3118                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3119                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3120                                attr->sq_psn);
3121                 roce_set_bit(context->qpc_bytes_128,
3122                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3123                 roce_set_field(context->qpc_bytes_128,
3124                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3125                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3126                              0);
3127                 roce_set_bit(context->qpc_bytes_128,
3128                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3129
3130                 roce_set_field(context->qpc_bytes_132,
3131                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3132                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3133                 roce_set_field(context->qpc_bytes_132,
3134                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3135                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3136
3137                 roce_set_field(context->qpc_bytes_136,
3138                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3139                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3140                                attr->sq_psn);
3141                 roce_set_field(context->qpc_bytes_136,
3142                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3143                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3144                                attr->sq_psn);
3145
3146                 roce_set_field(context->qpc_bytes_140,
3147                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3148                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3149                                (attr->sq_psn >> SQ_PSN_SHIFT));
3150                 roce_set_field(context->qpc_bytes_140,
3151                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3152                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3153                 roce_set_bit(context->qpc_bytes_140,
3154                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3155
3156                 roce_set_field(context->qpc_bytes_148,
3157                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3158                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3159                 roce_set_field(context->qpc_bytes_148,
3160                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3161                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3162                                attr->retry_cnt);
3163                 roce_set_field(context->qpc_bytes_148,
3164                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3165                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3166                                attr->rnr_retry);
3167                 roce_set_field(context->qpc_bytes_148,
3168                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3169                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3170
3171                 context->rnr_retry = 0;
3172
3173                 roce_set_field(context->qpc_bytes_156,
3174                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3175                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3176                                attr->retry_cnt);
3177                 if (attr->timeout < 0x12) {
3178                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3179                                  attr->timeout);
3180                         roce_set_field(context->qpc_bytes_156,
3181                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3182                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3183                                        0x12);
3184                 } else {
3185                         roce_set_field(context->qpc_bytes_156,
3186                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3187                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3188                                        attr->timeout);
3189                 }
3190                 roce_set_field(context->qpc_bytes_156,
3191                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3192                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3193                                attr->rnr_retry);
3194                 roce_set_field(context->qpc_bytes_156,
3195                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3196                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3197                                hr_qp->phy_port);
3198                 roce_set_field(context->qpc_bytes_156,
3199                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3200                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3201                                rdma_ah_get_sl(&attr->ah_attr));
3202                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3203                 roce_set_field(context->qpc_bytes_156,
3204                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3205                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3206                                ilog2((unsigned int)attr->max_rd_atomic));
3207                 roce_set_field(context->qpc_bytes_156,
3208                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3209                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3210                 context->pkt_use_len = 0;
3211
3212                 roce_set_field(context->qpc_bytes_164,
3213                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3214                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3215                 roce_set_field(context->qpc_bytes_164,
3216                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3217                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3218
3219                 roce_set_field(context->qpc_bytes_168,
3220                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3221                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3222                                attr->sq_psn);
3223                 roce_set_field(context->qpc_bytes_168,
3224                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3225                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3226                 roce_set_field(context->qpc_bytes_168,
3227                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3228                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3229                 roce_set_bit(context->qpc_bytes_168,
3230                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3231                 roce_set_bit(context->qpc_bytes_168,
3232                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3233                 roce_set_bit(context->qpc_bytes_168,
3234                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3235                 context->sge_use_len = 0;
3236
3237                 roce_set_field(context->qpc_bytes_176,
3238                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3239                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3240                 roce_set_field(context->qpc_bytes_176,
3241                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3242                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3243                                0);
3244                 roce_set_field(context->qpc_bytes_180,
3245                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3246                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3247                 roce_set_field(context->qpc_bytes_180,
3248                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3249                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3250
3251                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3252
3253                 roce_set_field(context->qpc_bytes_188,
3254                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3255                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3256                                upper_32_bits(sq_ba));
3257                 roce_set_bit(context->qpc_bytes_188,
3258                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3259                 roce_set_field(context->qpc_bytes_188,
3260                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3261                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3262                                0);
3263         }
3264
3265         /* Every status migrate must change state */
3266         roce_set_field(context->qpc_bytes_144,
3267                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3268                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3269
3270         /* SW pass context to HW */
3271         ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3272                                     to_hns_roce_state(new_state), context,
3273                                     hr_qp);
3274         if (ret) {
3275                 dev_err(dev, "hns_roce_qp_modify failed\n");
3276                 goto out;
3277         }
3278
3279         /*
3280          * Use rst2init to instead of init2init with drv,
3281          * need to hw to flash RQ HEAD by DB again
3282          */
3283         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3284                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3285                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3286                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3287                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3288                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3289                                RQ_DOORBELL_U32_8_CMD_S, 1);
3290                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3291
3292                 if (ibqp->uobject) {
3293                         hr_qp->rq.db_reg = hr_dev->reg_base +
3294                                      hr_dev->odb_offset +
3295                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3296                 }
3297
3298                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
3299         }
3300
3301         hr_qp->state = new_state;
3302
3303         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3304                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3305         if (attr_mask & IB_QP_PORT) {
3306                 hr_qp->port = attr->port_num - 1;
3307                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3308         }
3309
3310         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3311                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3312                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3313                 if (ibqp->send_cq != ibqp->recv_cq)
3314                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3315                                              hr_qp->qpn, NULL);
3316
3317                 hr_qp->rq.head = 0;
3318                 hr_qp->rq.tail = 0;
3319                 hr_qp->sq.head = 0;
3320                 hr_qp->sq.tail = 0;
3321         }
3322 out:
3323         kfree(context);
3324         return ret;
3325 }
3326
3327 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3328                                  const struct ib_qp_attr *attr, int attr_mask,
3329                                  enum ib_qp_state cur_state,
3330                                  enum ib_qp_state new_state)
3331 {
3332         if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
3333                 return -EOPNOTSUPP;
3334
3335         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3336                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3337                                          new_state);
3338         else
3339                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3340                                         new_state);
3341 }
3342
3343 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3344 {
3345         switch (state) {
3346         case HNS_ROCE_QP_STATE_RST:
3347                 return IB_QPS_RESET;
3348         case HNS_ROCE_QP_STATE_INIT:
3349                 return IB_QPS_INIT;
3350         case HNS_ROCE_QP_STATE_RTR:
3351                 return IB_QPS_RTR;
3352         case HNS_ROCE_QP_STATE_RTS:
3353                 return IB_QPS_RTS;
3354         case HNS_ROCE_QP_STATE_SQD:
3355                 return IB_QPS_SQD;
3356         case HNS_ROCE_QP_STATE_ERR:
3357                 return IB_QPS_ERR;
3358         default:
3359                 return IB_QPS_ERR;
3360         }
3361 }
3362
3363 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3364                                  struct hns_roce_qp *hr_qp,
3365                                  struct hns_roce_qp_context *hr_context)
3366 {
3367         struct hns_roce_cmd_mailbox *mailbox;
3368         int ret;
3369
3370         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3371         if (IS_ERR(mailbox))
3372                 return PTR_ERR(mailbox);
3373
3374         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3375                                 HNS_ROCE_CMD_QUERY_QP,
3376                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3377         if (!ret)
3378                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3379         else
3380                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3381
3382         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3383
3384         return ret;
3385 }
3386
3387 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3388                              int qp_attr_mask,
3389                              struct ib_qp_init_attr *qp_init_attr)
3390 {
3391         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3392         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3393         struct hns_roce_sqp_context context;
3394         u32 addr;
3395
3396         mutex_lock(&hr_qp->mutex);
3397
3398         if (hr_qp->state == IB_QPS_RESET) {
3399                 qp_attr->qp_state = IB_QPS_RESET;
3400                 goto done;
3401         }
3402
3403         addr = ROCEE_QP1C_CFG0_0_REG +
3404                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3405         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3406         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3407         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3408         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3409         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3410         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3411         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3412         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3413         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3414         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3415
3416         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3417                                       QP1C_BYTES_4_QP_STATE_M,
3418                                       QP1C_BYTES_4_QP_STATE_S);
3419         qp_attr->qp_state       = hr_qp->state;
3420         qp_attr->path_mtu       = IB_MTU_256;
3421         qp_attr->path_mig_state = IB_MIG_ARMED;
3422         qp_attr->qkey           = QKEY_VAL;
3423         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3424         qp_attr->rq_psn         = 0;
3425         qp_attr->sq_psn         = 0;
3426         qp_attr->dest_qp_num    = 1;
3427         qp_attr->qp_access_flags = 6;
3428
3429         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3430                                              QP1C_BYTES_20_PKEY_IDX_M,
3431                                              QP1C_BYTES_20_PKEY_IDX_S);
3432         qp_attr->port_num = hr_qp->port + 1;
3433         qp_attr->sq_draining = 0;
3434         qp_attr->max_rd_atomic = 0;
3435         qp_attr->max_dest_rd_atomic = 0;
3436         qp_attr->min_rnr_timer = 0;
3437         qp_attr->timeout = 0;
3438         qp_attr->retry_cnt = 0;
3439         qp_attr->rnr_retry = 0;
3440         qp_attr->alt_timeout = 0;
3441
3442 done:
3443         qp_attr->cur_qp_state = qp_attr->qp_state;
3444         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3445         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3446         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3447         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3448         qp_attr->cap.max_inline_data = 0;
3449         qp_init_attr->cap = qp_attr->cap;
3450         qp_init_attr->create_flags = 0;
3451
3452         mutex_unlock(&hr_qp->mutex);
3453
3454         return 0;
3455 }
3456
3457 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3458                             int qp_attr_mask,
3459                             struct ib_qp_init_attr *qp_init_attr)
3460 {
3461         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3462         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3463         struct device *dev = &hr_dev->pdev->dev;
3464         struct hns_roce_qp_context *context;
3465         int tmp_qp_state;
3466         int ret = 0;
3467         int state;
3468
3469         context = kzalloc(sizeof(*context), GFP_KERNEL);
3470         if (!context)
3471                 return -ENOMEM;
3472
3473         memset(qp_attr, 0, sizeof(*qp_attr));
3474         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3475
3476         mutex_lock(&hr_qp->mutex);
3477
3478         if (hr_qp->state == IB_QPS_RESET) {
3479                 qp_attr->qp_state = IB_QPS_RESET;
3480                 goto done;
3481         }
3482
3483         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3484         if (ret) {
3485                 dev_err(dev, "query qpc error\n");
3486                 ret = -EINVAL;
3487                 goto out;
3488         }
3489
3490         state = roce_get_field(context->qpc_bytes_144,
3491                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3492                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3493         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3494         if (tmp_qp_state == -1) {
3495                 dev_err(dev, "to_ib_qp_state error\n");
3496                 ret = -EINVAL;
3497                 goto out;
3498         }
3499         hr_qp->state = (u8)tmp_qp_state;
3500         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3501         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3502                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3503                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3504         qp_attr->path_mig_state = IB_MIG_ARMED;
3505         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3506         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3507                 qp_attr->qkey = QKEY_VAL;
3508
3509         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3510                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3511                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3512         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3513                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3514                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3515         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3516                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3517                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3518         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3519                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3520                                    ((roce_get_bit(context->qpc_bytes_4,
3521                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3522                                    ((roce_get_bit(context->qpc_bytes_4,
3523                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3524
3525         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3526                 struct ib_global_route *grh =
3527                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3528
3529                 rdma_ah_set_sl(&qp_attr->ah_attr,
3530                                roce_get_field(context->qpc_bytes_156,
3531                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3532                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3533                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3534                 grh->flow_label =
3535                         roce_get_field(context->qpc_bytes_48,
3536                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3537                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3538                 grh->sgid_index =
3539                         roce_get_field(context->qpc_bytes_36,
3540                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3541                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3542                 grh->hop_limit =
3543                         roce_get_field(context->qpc_bytes_44,
3544                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3545                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3546                 grh->traffic_class =
3547                         roce_get_field(context->qpc_bytes_48,
3548                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3549                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3550
3551                 memcpy(grh->dgid.raw, context->dgid,
3552                        sizeof(grh->dgid.raw));
3553         }
3554
3555         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3556                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3557                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3558         qp_attr->port_num = hr_qp->port + 1;
3559         qp_attr->sq_draining = 0;
3560         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3561                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3562                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3563         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3564                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3565                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3566         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3567                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3568                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3569         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3570                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3571                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3572         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3573                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3574                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3575         qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3576
3577 done:
3578         qp_attr->cur_qp_state = qp_attr->qp_state;
3579         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3580         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3581
3582         if (!ibqp->uobject) {
3583                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3584                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3585         } else {
3586                 qp_attr->cap.max_send_wr = 0;
3587                 qp_attr->cap.max_send_sge = 0;
3588         }
3589
3590         qp_init_attr->cap = qp_attr->cap;
3591
3592 out:
3593         mutex_unlock(&hr_qp->mutex);
3594         kfree(context);
3595         return ret;
3596 }
3597
3598 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3599                                 int qp_attr_mask,
3600                                 struct ib_qp_init_attr *qp_init_attr)
3601 {
3602         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3603
3604         return hr_qp->doorbell_qpn <= 1 ?
3605                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3606                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3607 }
3608
3609 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3610 {
3611         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3612         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3613         struct hns_roce_cq *send_cq, *recv_cq;
3614         int ret;
3615
3616         ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3617         if (ret)
3618                 return ret;
3619
3620         send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3621         recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3622
3623         hns_roce_lock_cqs(send_cq, recv_cq);
3624         if (!udata) {
3625                 if (recv_cq)
3626                         __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3627                                                (hr_qp->ibqp.srq ?
3628                                                 to_hr_srq(hr_qp->ibqp.srq) :
3629                                                 NULL));
3630
3631                 if (send_cq && send_cq != recv_cq)
3632                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3633         }
3634         hns_roce_qp_remove(hr_dev, hr_qp);
3635         hns_roce_unlock_cqs(send_cq, recv_cq);
3636
3637         hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3638
3639         return 0;
3640 }
3641
3642 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3643 {
3644         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3645         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3646         struct device *dev = &hr_dev->pdev->dev;
3647         u32 cqe_cnt_ori;
3648         u32 cqe_cnt_cur;
3649         int wait_time = 0;
3650
3651         /*
3652          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3653          * have been written by checking the CQE counter.
3654          */
3655         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3656         while (1) {
3657                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3658                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3659                         break;
3660
3661                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3662                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3663                         break;
3664
3665                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3666                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3667                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3668                                 hr_cq->cqn);
3669                         break;
3670                 }
3671                 wait_time++;
3672         }
3673         return 0;
3674 }
3675
3676 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
3677 {
3678         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3679                        (req_not << eq->log_entries), eq->db_reg);
3680 }
3681
3682 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3683                                             struct hns_roce_aeqe *aeqe, int qpn)
3684 {
3685         struct device *dev = &hr_dev->pdev->dev;
3686
3687         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3688         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3689                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3690         case HNS_ROCE_LWQCE_QPC_ERROR:
3691                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3692                 break;
3693         case HNS_ROCE_LWQCE_MTU_ERROR:
3694                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3695                 break;
3696         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3697                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3698                 break;
3699         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3700                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3701                 break;
3702         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3703                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3704                 break;
3705         case HNS_ROCE_LWQCE_SL_ERROR:
3706                 dev_warn(dev, "QP %d, SL error.\n", qpn);
3707                 break;
3708         case HNS_ROCE_LWQCE_PORT_ERROR:
3709                 dev_warn(dev, "QP %d, port error.\n", qpn);
3710                 break;
3711         default:
3712                 break;
3713         }
3714 }
3715
3716 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3717                                                    struct hns_roce_aeqe *aeqe,
3718                                                    int qpn)
3719 {
3720         struct device *dev = &hr_dev->pdev->dev;
3721
3722         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3723         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3724                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3725         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3726                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3727                 break;
3728         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3729                 dev_warn(dev, "QP %d, length error.\n", qpn);
3730                 break;
3731         case HNS_ROCE_LAVWQE_VA_ERROR:
3732                 dev_warn(dev, "QP %d, VA error.\n", qpn);
3733                 break;
3734         case HNS_ROCE_LAVWQE_PD_ERROR:
3735                 dev_err(dev, "QP %d, PD error.\n", qpn);
3736                 break;
3737         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3738                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3739                 break;
3740         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3741                 dev_warn(dev, "QP %d, key state error.\n", qpn);
3742                 break;
3743         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3744                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3745                 break;
3746         default:
3747                 break;
3748         }
3749 }
3750
3751 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3752                                       struct hns_roce_aeqe *aeqe,
3753                                       int event_type)
3754 {
3755         struct device *dev = &hr_dev->pdev->dev;
3756         int phy_port;
3757         int qpn;
3758
3759         qpn = roce_get_field(aeqe->event.queue_event.num,
3760                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3761                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3762         phy_port = roce_get_field(aeqe->event.queue_event.num,
3763                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3764                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3765         if (qpn <= 1)
3766                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3767
3768         switch (event_type) {
3769         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3770                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3771                          "QP %d, phy_port %d.\n", qpn, phy_port);
3772                 break;
3773         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3774                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3775                 break;
3776         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3777                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3778                 break;
3779         default:
3780                 break;
3781         }
3782
3783         hns_roce_qp_event(hr_dev, qpn, event_type);
3784 }
3785
3786 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3787                                       struct hns_roce_aeqe *aeqe,
3788                                       int event_type)
3789 {
3790         struct device *dev = &hr_dev->pdev->dev;
3791         u32 cqn;
3792
3793         cqn = roce_get_field(aeqe->event.queue_event.num,
3794                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3795                              HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3796
3797         switch (event_type) {
3798         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3799                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3800                 break;
3801         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3802                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3803                 break;
3804         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3805                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3806                 break;
3807         default:
3808                 break;
3809         }
3810
3811         hns_roce_cq_event(hr_dev, cqn, event_type);
3812 }
3813
3814 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3815                                            struct hns_roce_aeqe *aeqe)
3816 {
3817         struct device *dev = &hr_dev->pdev->dev;
3818
3819         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3820                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3821         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3822                 dev_warn(dev, "SDB overflow.\n");
3823                 break;
3824         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3825                 dev_warn(dev, "SDB almost overflow.\n");
3826                 break;
3827         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3828                 dev_warn(dev, "SDB almost empty.\n");
3829                 break;
3830         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3831                 dev_warn(dev, "ODB overflow.\n");
3832                 break;
3833         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3834                 dev_warn(dev, "ODB almost overflow.\n");
3835                 break;
3836         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3837                 dev_warn(dev, "SDB almost empty.\n");
3838                 break;
3839         default:
3840                 break;
3841         }
3842 }
3843
3844 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3845 {
3846         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3847
3848         return (struct hns_roce_aeqe *)((u8 *)
3849                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3850                 off % HNS_ROCE_BA_SIZE);
3851 }
3852
3853 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3854 {
3855         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3856
3857         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3858                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3859 }
3860
3861 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3862                                struct hns_roce_eq *eq)
3863 {
3864         struct device *dev = &hr_dev->pdev->dev;
3865         struct hns_roce_aeqe *aeqe;
3866         int aeqes_found = 0;
3867         int event_type;
3868
3869         while ((aeqe = next_aeqe_sw_v1(eq))) {
3870                 /* Make sure we read the AEQ entry after we have checked the
3871                  * ownership bit
3872                  */
3873                 dma_rmb();
3874
3875                 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3876                         aeqe,
3877                         roce_get_field(aeqe->asyn,
3878                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3879                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3880                 event_type = roce_get_field(aeqe->asyn,
3881                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3882                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3883                 switch (event_type) {
3884                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3885                         dev_warn(dev, "PATH MIG not supported\n");
3886                         break;
3887                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3888                         dev_warn(dev, "COMMUNICATION established\n");
3889                         break;
3890                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3891                         dev_warn(dev, "SQ DRAINED not supported\n");
3892                         break;
3893                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3894                         dev_warn(dev, "PATH MIG failed\n");
3895                         break;
3896                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3897                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3898                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3899                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3900                         break;
3901                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3902                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3903                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3904                         dev_warn(dev, "SRQ not support!\n");
3905                         break;
3906                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3907                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3908                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3909                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3910                         break;
3911                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3912                         dev_warn(dev, "port change.\n");
3913                         break;
3914                 case HNS_ROCE_EVENT_TYPE_MB:
3915                         hns_roce_cmd_event(hr_dev,
3916                                            le16_to_cpu(aeqe->event.cmd.token),
3917                                            aeqe->event.cmd.status,
3918                                            le64_to_cpu(aeqe->event.cmd.out_param
3919                                            ));
3920                         break;
3921                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3922                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3923                         break;
3924                 default:
3925                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3926                                  event_type, eq->eqn, eq->cons_index);
3927                         break;
3928                 }
3929
3930                 eq->cons_index++;
3931                 aeqes_found = 1;
3932
3933                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3934                         eq->cons_index = 0;
3935         }
3936
3937         set_eq_cons_index_v1(eq, 0);
3938
3939         return aeqes_found;
3940 }
3941
3942 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3943 {
3944         unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3945
3946         return (struct hns_roce_ceqe *)((u8 *)
3947                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3948                         off % HNS_ROCE_BA_SIZE);
3949 }
3950
3951 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3952 {
3953         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3954
3955         return (!!(roce_get_bit(ceqe->comp,
3956                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3957                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3958 }
3959
3960 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3961                                struct hns_roce_eq *eq)
3962 {
3963         struct hns_roce_ceqe *ceqe;
3964         int ceqes_found = 0;
3965         u32 cqn;
3966
3967         while ((ceqe = next_ceqe_sw_v1(eq))) {
3968                 /* Make sure we read CEQ entry after we have checked the
3969                  * ownership bit
3970                  */
3971                 dma_rmb();
3972
3973                 cqn = roce_get_field(ceqe->comp,
3974                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3975                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3976                 hns_roce_cq_completion(hr_dev, cqn);
3977
3978                 ++eq->cons_index;
3979                 ceqes_found = 1;
3980
3981                 if (eq->cons_index >
3982                     EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3983                         eq->cons_index = 0;
3984         }
3985
3986         set_eq_cons_index_v1(eq, 0);
3987
3988         return ceqes_found;
3989 }
3990
3991 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3992 {
3993         struct hns_roce_eq  *eq  = eq_ptr;
3994         struct hns_roce_dev *hr_dev = eq->hr_dev;
3995         int int_work;
3996
3997         if (eq->type_flag == HNS_ROCE_CEQ)
3998                 /* CEQ irq routine, CEQ is pulse irq, not clear */
3999                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4000         else
4001                 /* AEQ irq routine, AEQ is pulse irq, not clear */
4002                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4003
4004         return IRQ_RETVAL(int_work);
4005 }
4006
4007 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4008 {
4009         struct hns_roce_dev *hr_dev = dev_id;
4010         struct device *dev = &hr_dev->pdev->dev;
4011         int int_work = 0;
4012         u32 caepaemask_val;
4013         u32 cealmovf_val;
4014         u32 caepaest_val;
4015         u32 aeshift_val;
4016         u32 ceshift_val;
4017         u32 cemask_val;
4018         __le32 tmp;
4019         int i;
4020
4021         /*
4022          * Abnormal interrupt:
4023          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4024          * interrupt, mask irq, clear irq, cancel mask operation
4025          */
4026         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4027         tmp = cpu_to_le32(aeshift_val);
4028
4029         /* AEQE overflow */
4030         if (roce_get_bit(tmp,
4031                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4032                 dev_warn(dev, "AEQ overflow!\n");
4033
4034                 /* Set mask */
4035                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4036                 tmp = cpu_to_le32(caepaemask_val);
4037                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4038                              HNS_ROCE_INT_MASK_ENABLE);
4039                 caepaemask_val = le32_to_cpu(tmp);
4040                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4041
4042                 /* Clear int state(INT_WC : write 1 clear) */
4043                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4044                 tmp = cpu_to_le32(caepaest_val);
4045                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4046                 caepaest_val = le32_to_cpu(tmp);
4047                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4048
4049                 /* Clear mask */
4050                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4051                 tmp = cpu_to_le32(caepaemask_val);
4052                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4053                              HNS_ROCE_INT_MASK_DISABLE);
4054                 caepaemask_val = le32_to_cpu(tmp);
4055                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4056         }
4057
4058         /* CEQ almost overflow */
4059         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4060                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4061                                         i * CEQ_REG_OFFSET);
4062                 tmp = cpu_to_le32(ceshift_val);
4063
4064                 if (roce_get_bit(tmp,
4065                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4066                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4067                         int_work++;
4068
4069                         /* Set mask */
4070                         cemask_val = roce_read(hr_dev,
4071                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4072                                                i * CEQ_REG_OFFSET);
4073                         tmp = cpu_to_le32(cemask_val);
4074                         roce_set_bit(tmp,
4075                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4076                                 HNS_ROCE_INT_MASK_ENABLE);
4077                         cemask_val = le32_to_cpu(tmp);
4078                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4079                                    i * CEQ_REG_OFFSET, cemask_val);
4080
4081                         /* Clear int state(INT_WC : write 1 clear) */
4082                         cealmovf_val = roce_read(hr_dev,
4083                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4084                                        i * CEQ_REG_OFFSET);
4085                         tmp = cpu_to_le32(cealmovf_val);
4086                         roce_set_bit(tmp,
4087                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4088                                      1);
4089                         cealmovf_val = le32_to_cpu(tmp);
4090                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4091                                    i * CEQ_REG_OFFSET, cealmovf_val);
4092
4093                         /* Clear mask */
4094                         cemask_val = roce_read(hr_dev,
4095                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4096                                      i * CEQ_REG_OFFSET);
4097                         tmp = cpu_to_le32(cemask_val);
4098                         roce_set_bit(tmp,
4099                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4100                                HNS_ROCE_INT_MASK_DISABLE);
4101                         cemask_val = le32_to_cpu(tmp);
4102                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4103                                    i * CEQ_REG_OFFSET, cemask_val);
4104                 }
4105         }
4106
4107         /* ECC multi-bit error alarm */
4108         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4109                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4110                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4111                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4112
4113         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4114                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4115                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4116                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4117
4118         return IRQ_RETVAL(int_work);
4119 }
4120
4121 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4122 {
4123         u32 aemask_val;
4124         int masken = 0;
4125         __le32 tmp;
4126         int i;
4127
4128         /* AEQ INT */
4129         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4130         tmp = cpu_to_le32(aemask_val);
4131         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4132                      masken);
4133         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4134         aemask_val = le32_to_cpu(tmp);
4135         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4136
4137         /* CEQ INT */
4138         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4139                 /* IRQ mask */
4140                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4141                            i * CEQ_REG_OFFSET, masken);
4142         }
4143 }
4144
4145 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4146                                 struct hns_roce_eq *eq)
4147 {
4148         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4149                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4150         int i;
4151
4152         if (!eq->buf_list)
4153                 return;
4154
4155         for (i = 0; i < npages; ++i)
4156                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4157                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4158
4159         kfree(eq->buf_list);
4160 }
4161
4162 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4163                                   int enable_flag)
4164 {
4165         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4166         __le32 tmp;
4167         u32 val;
4168
4169         val = readl(eqc);
4170         tmp = cpu_to_le32(val);
4171
4172         if (enable_flag)
4173                 roce_set_field(tmp,
4174                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4175                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4176                                HNS_ROCE_EQ_STAT_VALID);
4177         else
4178                 roce_set_field(tmp,
4179                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4180                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4181                                HNS_ROCE_EQ_STAT_INVALID);
4182
4183         val = le32_to_cpu(tmp);
4184         writel(val, eqc);
4185 }
4186
4187 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4188                                  struct hns_roce_eq *eq)
4189 {
4190         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4191         struct device *dev = &hr_dev->pdev->dev;
4192         dma_addr_t tmp_dma_addr;
4193         u32 eqcuridx_val;
4194         u32 eqconsindx_val;
4195         u32 eqshift_val;
4196         __le32 tmp2 = 0;
4197         __le32 tmp1 = 0;
4198         __le32 tmp = 0;
4199         int num_bas;
4200         int ret;
4201         int i;
4202
4203         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4204                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4205
4206         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4207                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4208                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4209                         num_bas);
4210                 return -EINVAL;
4211         }
4212
4213         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4214         if (!eq->buf_list)
4215                 return -ENOMEM;
4216
4217         for (i = 0; i < num_bas; ++i) {
4218                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4219                                                          &tmp_dma_addr,
4220                                                          GFP_KERNEL);
4221                 if (!eq->buf_list[i].buf) {
4222                         ret = -ENOMEM;
4223                         goto err_out_free_pages;
4224                 }
4225
4226                 eq->buf_list[i].map = tmp_dma_addr;
4227         }
4228         eq->cons_index = 0;
4229         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4230                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4231                        HNS_ROCE_EQ_STAT_INVALID);
4232         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4233                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4234                        eq->log_entries);
4235         eqshift_val = le32_to_cpu(tmp);
4236         writel(eqshift_val, eqc);
4237
4238         /* Configure eq extended address 12~44bit */
4239         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4240
4241         /*
4242          * Configure eq extended address 45~49 bit.
4243          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4244          * using 4K page, and shift more 32 because of
4245          * calculating the high 32 bit value evaluated to hardware.
4246          */
4247         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4248                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4249                        eq->buf_list[0].map >> 44);
4250         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4251                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4252         eqcuridx_val = le32_to_cpu(tmp1);
4253         writel(eqcuridx_val, eqc + 8);
4254
4255         /* Configure eq consumer index */
4256         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4257                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4258         eqconsindx_val = le32_to_cpu(tmp2);
4259         writel(eqconsindx_val, eqc + 0xc);
4260
4261         return 0;
4262
4263 err_out_free_pages:
4264         for (i -= 1; i >= 0; i--)
4265                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4266                                   eq->buf_list[i].map);
4267
4268         kfree(eq->buf_list);
4269         return ret;
4270 }
4271
4272 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4273 {
4274         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4275         struct device *dev = &hr_dev->pdev->dev;
4276         struct hns_roce_eq *eq;
4277         int irq_num;
4278         int eq_num;
4279         int ret;
4280         int i, j;
4281
4282         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4283         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4284
4285         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4286         if (!eq_table->eq)
4287                 return -ENOMEM;
4288
4289         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4290                                      GFP_KERNEL);
4291         if (!eq_table->eqc_base) {
4292                 ret = -ENOMEM;
4293                 goto err_eqc_base_alloc_fail;
4294         }
4295
4296         for (i = 0; i < eq_num; i++) {
4297                 eq = &eq_table->eq[i];
4298                 eq->hr_dev = hr_dev;
4299                 eq->eqn = i;
4300                 eq->irq = hr_dev->irq[i];
4301                 eq->log_page_size = PAGE_SHIFT;
4302
4303                 if (i < hr_dev->caps.num_comp_vectors) {
4304                         /* CEQ */
4305                         eq_table->eqc_base[i] = hr_dev->reg_base +
4306                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4307                                                 CEQ_REG_OFFSET * i;
4308                         eq->type_flag = HNS_ROCE_CEQ;
4309                         eq->db_reg = hr_dev->reg_base +
4310                                      ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4311                                      CEQ_REG_OFFSET * i;
4312                         eq->entries = hr_dev->caps.ceqe_depth;
4313                         eq->log_entries = ilog2(eq->entries);
4314                         eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4315                 } else {
4316                         /* AEQ */
4317                         eq_table->eqc_base[i] = hr_dev->reg_base +
4318                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4319                         eq->type_flag = HNS_ROCE_AEQ;
4320                         eq->db_reg = hr_dev->reg_base +
4321                                      ROCEE_CAEP_AEQE_CONS_IDX_REG;
4322                         eq->entries = hr_dev->caps.aeqe_depth;
4323                         eq->log_entries = ilog2(eq->entries);
4324                         eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4325                 }
4326         }
4327
4328         /* Disable irq */
4329         hns_roce_v1_int_mask_enable(hr_dev);
4330
4331         /* Configure ce int interval */
4332         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4333                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4334
4335         /* Configure ce int burst num */
4336         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4337                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4338
4339         for (i = 0; i < eq_num; i++) {
4340                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4341                 if (ret) {
4342                         dev_err(dev, "eq create failed\n");
4343                         goto err_create_eq_fail;
4344                 }
4345         }
4346
4347         for (j = 0; j < irq_num; j++) {
4348                 if (j < eq_num)
4349                         ret = request_irq(hr_dev->irq[j],
4350                                           hns_roce_v1_msix_interrupt_eq, 0,
4351                                           hr_dev->irq_names[j],
4352                                           &eq_table->eq[j]);
4353                 else
4354                         ret = request_irq(hr_dev->irq[j],
4355                                           hns_roce_v1_msix_interrupt_abn, 0,
4356                                           hr_dev->irq_names[j], hr_dev);
4357
4358                 if (ret) {
4359                         dev_err(dev, "request irq error!\n");
4360                         goto err_request_irq_fail;
4361                 }
4362         }
4363
4364         for (i = 0; i < eq_num; i++)
4365                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4366
4367         return 0;
4368
4369 err_request_irq_fail:
4370         for (j -= 1; j >= 0; j--)
4371                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4372
4373 err_create_eq_fail:
4374         for (i -= 1; i >= 0; i--)
4375                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4376
4377         kfree(eq_table->eqc_base);
4378
4379 err_eqc_base_alloc_fail:
4380         kfree(eq_table->eq);
4381
4382         return ret;
4383 }
4384
4385 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4386 {
4387         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4388         int irq_num;
4389         int eq_num;
4390         int i;
4391
4392         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4393         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4394         for (i = 0; i < eq_num; i++) {
4395                 /* Disable EQ */
4396                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4397
4398                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4399
4400                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4401         }
4402         for (i = eq_num; i < irq_num; i++)
4403                 free_irq(hr_dev->irq[i], hr_dev);
4404
4405         kfree(eq_table->eqc_base);
4406         kfree(eq_table->eq);
4407 }
4408
4409 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4410         .destroy_qp = hns_roce_v1_destroy_qp,
4411         .poll_cq = hns_roce_v1_poll_cq,
4412         .post_recv = hns_roce_v1_post_recv,
4413         .post_send = hns_roce_v1_post_send,
4414         .query_qp = hns_roce_v1_query_qp,
4415         .req_notify_cq = hns_roce_v1_req_notify_cq,
4416 };
4417
4418 static const struct hns_roce_hw hns_roce_hw_v1 = {
4419         .reset = hns_roce_v1_reset,
4420         .hw_profile = hns_roce_v1_profile,
4421         .hw_init = hns_roce_v1_init,
4422         .hw_exit = hns_roce_v1_exit,
4423         .post_mbox = hns_roce_v1_post_mbox,
4424         .poll_mbox_done = hns_roce_v1_chk_mbox,
4425         .set_gid = hns_roce_v1_set_gid,
4426         .set_mac = hns_roce_v1_set_mac,
4427         .set_mtu = hns_roce_v1_set_mtu,
4428         .write_mtpt = hns_roce_v1_write_mtpt,
4429         .write_cqc = hns_roce_v1_write_cqc,
4430         .set_hem = hns_roce_v1_set_hem,
4431         .clear_hem = hns_roce_v1_clear_hem,
4432         .modify_qp = hns_roce_v1_modify_qp,
4433         .dereg_mr = hns_roce_v1_dereg_mr,
4434         .destroy_cq = hns_roce_v1_destroy_cq,
4435         .init_eq = hns_roce_v1_init_eq_table,
4436         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4437         .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4438 };
4439
4440 static const struct of_device_id hns_roce_of_match[] = {
4441         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4442         {},
4443 };
4444 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4445
4446 static const struct acpi_device_id hns_roce_acpi_match[] = {
4447         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4448         {},
4449 };
4450 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4451
4452 static struct
4453 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4454 {
4455         struct device *dev;
4456
4457         /* get the 'device' corresponding to the matching 'fwnode' */
4458         dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4459         /* get the platform device */
4460         return dev ? to_platform_device(dev) : NULL;
4461 }
4462
4463 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4464 {
4465         struct device *dev = &hr_dev->pdev->dev;
4466         struct platform_device *pdev = NULL;
4467         struct net_device *netdev = NULL;
4468         struct device_node *net_node;
4469         int port_cnt = 0;
4470         u8 phy_port;
4471         int ret;
4472         int i;
4473
4474         /* check if we are compatible with the underlying SoC */
4475         if (dev_of_node(dev)) {
4476                 const struct of_device_id *of_id;
4477
4478                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4479                 if (!of_id) {
4480                         dev_err(dev, "device is not compatible!\n");
4481                         return -ENXIO;
4482                 }
4483                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4484                 if (!hr_dev->hw) {
4485                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4486                         return -ENXIO;
4487                 }
4488         } else if (is_acpi_device_node(dev->fwnode)) {
4489                 const struct acpi_device_id *acpi_id;
4490
4491                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4492                 if (!acpi_id) {
4493                         dev_err(dev, "device is not compatible!\n");
4494                         return -ENXIO;
4495                 }
4496                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4497                 if (!hr_dev->hw) {
4498                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4499                         return -ENXIO;
4500                 }
4501         } else {
4502                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4503                 return -ENXIO;
4504         }
4505
4506         /* get the mapped register base address */
4507         hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4508         if (IS_ERR(hr_dev->reg_base))
4509                 return PTR_ERR(hr_dev->reg_base);
4510
4511         /* read the node_guid of IB device from the DT or ACPI */
4512         ret = device_property_read_u8_array(dev, "node-guid",
4513                                             (u8 *)&hr_dev->ib_dev.node_guid,
4514                                             GUID_LEN);
4515         if (ret) {
4516                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4517                 return ret;
4518         }
4519
4520         /* get the RoCE associated ethernet ports or netdevices */
4521         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4522                 if (dev_of_node(dev)) {
4523                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4524                                                     i);
4525                         if (!net_node)
4526                                 continue;
4527                         pdev = of_find_device_by_node(net_node);
4528                 } else if (is_acpi_device_node(dev->fwnode)) {
4529                         struct fwnode_reference_args args;
4530
4531                         ret = acpi_node_get_property_reference(dev->fwnode,
4532                                                                "eth-handle",
4533                                                                i, &args);
4534                         if (ret)
4535                                 continue;
4536                         pdev = hns_roce_find_pdev(args.fwnode);
4537                 } else {
4538                         dev_err(dev, "cannot read data from DT or ACPI\n");
4539                         return -ENXIO;
4540                 }
4541
4542                 if (pdev) {
4543                         netdev = platform_get_drvdata(pdev);
4544                         phy_port = (u8)i;
4545                         if (netdev) {
4546                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4547                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4548                         } else {
4549                                 dev_err(dev, "no netdev found with pdev %s\n",
4550                                         pdev->name);
4551                                 return -ENODEV;
4552                         }
4553                         port_cnt++;
4554                 }
4555         }
4556
4557         if (port_cnt == 0) {
4558                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4559                 return -EINVAL;
4560         }
4561
4562         hr_dev->caps.num_ports = port_cnt;
4563
4564         /* cmd issue mode: 0 is poll, 1 is event */
4565         hr_dev->cmd_mod = 1;
4566         hr_dev->loop_idc = 0;
4567         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4568         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4569
4570         /* read the interrupt names from the DT or ACPI */
4571         ret = device_property_read_string_array(dev, "interrupt-names",
4572                                                 hr_dev->irq_names,
4573                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4574         if (ret < 0) {
4575                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4576                 return ret;
4577         }
4578
4579         /* fetch the interrupt numbers */
4580         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4581                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4582                 if (hr_dev->irq[i] <= 0)
4583                         return -EINVAL;
4584         }
4585
4586         return 0;
4587 }
4588
4589 /**
4590  * hns_roce_probe - RoCE driver entrance
4591  * @pdev: pointer to platform device
4592  * Return : int
4593  *
4594  */
4595 static int hns_roce_probe(struct platform_device *pdev)
4596 {
4597         int ret;
4598         struct hns_roce_dev *hr_dev;
4599         struct device *dev = &pdev->dev;
4600
4601         hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4602         if (!hr_dev)
4603                 return -ENOMEM;
4604
4605         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4606         if (!hr_dev->priv) {
4607                 ret = -ENOMEM;
4608                 goto error_failed_kzalloc;
4609         }
4610
4611         hr_dev->pdev = pdev;
4612         hr_dev->dev = dev;
4613         platform_set_drvdata(pdev, hr_dev);
4614
4615         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4616             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4617                 dev_err(dev, "Not usable DMA addressing mode\n");
4618                 ret = -EIO;
4619                 goto error_failed_get_cfg;
4620         }
4621
4622         ret = hns_roce_get_cfg(hr_dev);
4623         if (ret) {
4624                 dev_err(dev, "Get Configuration failed!\n");
4625                 goto error_failed_get_cfg;
4626         }
4627
4628         ret = hns_roce_init(hr_dev);
4629         if (ret) {
4630                 dev_err(dev, "RoCE engine init failed!\n");
4631                 goto error_failed_get_cfg;
4632         }
4633
4634         return 0;
4635
4636 error_failed_get_cfg:
4637         kfree(hr_dev->priv);
4638
4639 error_failed_kzalloc:
4640         ib_dealloc_device(&hr_dev->ib_dev);
4641
4642         return ret;
4643 }
4644
4645 /**
4646  * hns_roce_remove - remove RoCE device
4647  * @pdev: pointer to platform device
4648  */
4649 static int hns_roce_remove(struct platform_device *pdev)
4650 {
4651         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4652
4653         hns_roce_exit(hr_dev);
4654         kfree(hr_dev->priv);
4655         ib_dealloc_device(&hr_dev->ib_dev);
4656
4657         return 0;
4658 }
4659
4660 static struct platform_driver hns_roce_driver = {
4661         .probe = hns_roce_probe,
4662         .remove = hns_roce_remove,
4663         .driver = {
4664                 .name = DRV_NAME,
4665                 .of_match_table = hns_roce_of_match,
4666                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4667         },
4668 };
4669
4670 module_platform_driver(hns_roce_driver);
4671
4672 MODULE_LICENSE("Dual BSD/GPL");
4673 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4674 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4675 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4676 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");