drivers/infiniband/hw/efa/efa_com.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
   2 /*
   3  * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
   4  */
   5
   6 #include "efa_com.h"
   7 #include "efa_regs_defs.h"
   8
   9 #define ADMIN_CMD_TIMEOUT_US 30000000 /* usecs */
  10
  11 #define EFA_REG_READ_TIMEOUT_US 50000 /* usecs */
  12 #define EFA_MMIO_READ_INVALID 0xffffffff
  13
  14 #define EFA_POLL_INTERVAL_MS 100 /* msecs */
  15
  16 #define EFA_ASYNC_QUEUE_DEPTH 16
  17 #define EFA_ADMIN_QUEUE_DEPTH 32
  18
  19 #define MIN_EFA_VER\
  20         ((EFA_ADMIN_API_VERSION_MAJOR << EFA_REGS_VERSION_MAJOR_VERSION_SHIFT) | \
  21          (EFA_ADMIN_API_VERSION_MINOR & EFA_REGS_VERSION_MINOR_VERSION_MASK))
  22
  23 #define EFA_CTRL_MAJOR          0
  24 #define EFA_CTRL_MINOR          0
  25 #define EFA_CTRL_SUB_MINOR      1
  26
  27 #define MIN_EFA_CTRL_VER \
  28         (((EFA_CTRL_MAJOR) << \
  29         (EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  30         ((EFA_CTRL_MINOR) << \
  31         (EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  32         (EFA_CTRL_SUB_MINOR))
  33
  34 #define EFA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  35 #define EFA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  36
  37 #define EFA_REGS_ADMIN_INTR_MASK 1
  38
  39 enum efa_cmd_status {
  40         EFA_CMD_SUBMITTED,
  41         EFA_CMD_COMPLETED,
  42 };
  43
  44 struct efa_comp_ctx {
  45         struct completion wait_event;
  46         struct efa_admin_acq_entry *user_cqe;
  47         u32 comp_size;
  48         enum efa_cmd_status status;
  49         /* status from the device */
  50         u8 comp_status;
  51         u8 cmd_opcode;
  52         u8 occupied;
  53 };
  54
  55 static const char *efa_com_cmd_str(u8 cmd)
  56 {
  57 #define EFA_CMD_STR_CASE(_cmd) case EFA_ADMIN_##_cmd: return #_cmd
  58
  59         switch (cmd) {
  60         EFA_CMD_STR_CASE(CREATE_QP);
  61         EFA_CMD_STR_CASE(MODIFY_QP);
  62         EFA_CMD_STR_CASE(QUERY_QP);
  63         EFA_CMD_STR_CASE(DESTROY_QP);
  64         EFA_CMD_STR_CASE(CREATE_AH);
  65         EFA_CMD_STR_CASE(DESTROY_AH);
  66         EFA_CMD_STR_CASE(REG_MR);
  67         EFA_CMD_STR_CASE(DEREG_MR);
  68         EFA_CMD_STR_CASE(CREATE_CQ);
  69         EFA_CMD_STR_CASE(DESTROY_CQ);
  70         EFA_CMD_STR_CASE(GET_FEATURE);
  71         EFA_CMD_STR_CASE(SET_FEATURE);
  72         EFA_CMD_STR_CASE(GET_STATS);
  73         EFA_CMD_STR_CASE(ALLOC_PD);
  74         EFA_CMD_STR_CASE(DEALLOC_PD);
  75         EFA_CMD_STR_CASE(ALLOC_UAR);
  76         EFA_CMD_STR_CASE(DEALLOC_UAR);
  77         default: return "unknown command opcode";
  78         }
  79 #undef EFA_CMD_STR_CASE
  80 }
  81
  82 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset)
  83 {
  84         struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
  85         struct efa_admin_mmio_req_read_less_resp *read_resp;
  86         unsigned long exp_time;
  87         u32 mmio_read_reg;
  88         u32 err;
  89
  90         read_resp = mmio_read->read_resp;
  91
  92         spin_lock(&mmio_read->lock);
  93         mmio_read->seq_num++;
  94
  95         /* trash DMA req_id to identify when hardware is done */
  96         read_resp->req_id = mmio_read->seq_num + 0x9aL;
  97         mmio_read_reg = (offset << EFA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
  98                         EFA_REGS_MMIO_REG_READ_REG_OFF_MASK;
  99         mmio_read_reg |= mmio_read->seq_num &
 100                          EFA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 101
 102         writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);
 103
 104         exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout);
 105         do {
 106                 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
 107                         break;
 108                 udelay(1);
 109         } while (time_is_after_jiffies(exp_time));
 110
 111         if (read_resp->req_id != mmio_read->seq_num) {
 112                 ibdev_err_ratelimited(
 113                         edev->efa_dev,
 114                         "Reading register timed out. expected: req id[%u] offset[%#x] actual: req id[%u] offset[%#x]\n",
 115                         mmio_read->seq_num, offset, read_resp->req_id,
 116                         read_resp->reg_off);
 117                 err = EFA_MMIO_READ_INVALID;
 118                 goto out;
 119         }
 120
 121         if (read_resp->reg_off != offset) {
 122                 ibdev_err_ratelimited(
 123                         edev->efa_dev,
 124                         "Reading register failed: wrong offset provided\n");
 125                 err = EFA_MMIO_READ_INVALID;
 126                 goto out;
 127         }
 128
 129         err = read_resp->reg_val;
 130 out:
 131         spin_unlock(&mmio_read->lock);
 132         return err;
 133 }
 134
 135 static int efa_com_admin_init_sq(struct efa_com_dev *edev)
 136 {
 137         struct efa_com_admin_queue *aq = &edev->aq;
 138         struct efa_com_admin_sq *sq = &aq->sq;
 139         u16 size = aq->depth * sizeof(*sq->entries);
 140         u32 addr_high;
 141         u32 addr_low;
 142         u32 aq_caps;
 143
 144         sq->entries =
 145                 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL);
 146         if (!sq->entries)
 147                 return -ENOMEM;
 148
 149         spin_lock_init(&sq->lock);
 150
 151         sq->cc = 0;
 152         sq->pc = 0;
 153         sq->phase = 1;
 154
 155         sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);
 156
 157         addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(sq->dma_addr);
 158         addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(sq->dma_addr);
 159
 160         writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);
 161         writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);
 162
 163         aq_caps = aq->depth & EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
 164         aq_caps |= (sizeof(struct efa_admin_aq_entry) <<
 165                         EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
 166                         EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
 167
 168         writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);
 169
 170         return 0;
 171 }
 172
 173 static int efa_com_admin_init_cq(struct efa_com_dev *edev)
 174 {
 175         struct efa_com_admin_queue *aq = &edev->aq;
 176         struct efa_com_admin_cq *cq = &aq->cq;
 177         u16 size = aq->depth * sizeof(*cq->entries);
 178         u32 addr_high;
 179         u32 addr_low;
 180         u32 acq_caps;
 181
 182         cq->entries =
 183                 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL);
 184         if (!cq->entries)
 185                 return -ENOMEM;
 186
 187         spin_lock_init(&cq->lock);
 188
 189         cq->cc = 0;
 190         cq->phase = 1;
 191
 192         addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(cq->dma_addr);
 193         addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(cq->dma_addr);
 194
 195         writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);
 196         writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);
 197
 198         acq_caps = aq->depth & EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
 199         acq_caps |= (sizeof(struct efa_admin_acq_entry) <<
 200                         EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
 201                         EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
 202         acq_caps |= (aq->msix_vector_idx <<
 203                         EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_SHIFT) &
 204                         EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK;
 205
 206         writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);
 207
 208         return 0;
 209 }
 210
 211 static int efa_com_admin_init_aenq(struct efa_com_dev *edev,
 212                                    struct efa_aenq_handlers *aenq_handlers)
 213 {
 214         struct efa_com_aenq *aenq = &edev->aenq;
 215         u32 addr_low, addr_high, aenq_caps;
 216         u16 size;
 217
 218         if (!aenq_handlers) {
 219                 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
 220                 return -EINVAL;
 221         }
 222
 223         size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries);
 224         aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
 225                                            GFP_KERNEL);
 226         if (!aenq->entries)
 227                 return -ENOMEM;
 228
 229         aenq->aenq_handlers = aenq_handlers;
 230         aenq->depth = EFA_ASYNC_QUEUE_DEPTH;
 231         aenq->cc = 0;
 232         aenq->phase = 1;
 233
 234         addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 235         addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 236
 237         writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);
 238         writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);
 239
 240         aenq_caps = aenq->depth & EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 241         aenq_caps |= (sizeof(struct efa_admin_aenq_entry) <<
 242                 EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 243                 EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 244         aenq_caps |= (aenq->msix_vector_idx
 245                       << EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_SHIFT) &
 246                      EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK;
 247         writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);
 248
 249         /*
 250          * Init cons_db to mark that all entries in the queue
 251          * are initially available
 252          */
 253         writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
 254
 255         return 0;
 256 }
 257
 258 /* ID to be used with efa_com_get_comp_ctx */
 259 static u16 efa_com_alloc_ctx_id(struct efa_com_admin_queue *aq)
 260 {
 261         u16 ctx_id;
 262
 263         spin_lock(&aq->comp_ctx_lock);
 264         ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next];
 265         aq->comp_ctx_pool_next++;
 266         spin_unlock(&aq->comp_ctx_lock);
 267
 268         return ctx_id;
 269 }
 270
 271 static void efa_com_dealloc_ctx_id(struct efa_com_admin_queue *aq,
 272                                    u16 ctx_id)
 273 {
 274         spin_lock(&aq->comp_ctx_lock);
 275         aq->comp_ctx_pool_next--;
 276         aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id;
 277         spin_unlock(&aq->comp_ctx_lock);
 278 }
 279
 280 static inline void efa_com_put_comp_ctx(struct efa_com_admin_queue *aq,
 281                                         struct efa_comp_ctx *comp_ctx)
 282 {
 283         u16 cmd_id = comp_ctx->user_cqe->acq_common_descriptor.command &
 284                      EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 285         u16 ctx_id = cmd_id & (aq->depth - 1);
 286
 287         ibdev_dbg(aq->efa_dev, "Put completion command_id %#x\n", cmd_id);
 288         comp_ctx->occupied = 0;
 289         efa_com_dealloc_ctx_id(aq, ctx_id);
 290 }
 291
 292 static struct efa_comp_ctx *efa_com_get_comp_ctx(struct efa_com_admin_queue *aq,
 293                                                  u16 cmd_id, bool capture)
 294 {
 295         u16 ctx_id = cmd_id & (aq->depth - 1);
 296
 297         if (aq->comp_ctx[ctx_id].occupied && capture) {
 298                 ibdev_err_ratelimited(
 299                         aq->efa_dev,
 300                         "Completion context for command_id %#x is occupied\n",
 301                         cmd_id);
 302                 return NULL;
 303         }
 304
 305         if (capture) {
 306                 aq->comp_ctx[ctx_id].occupied = 1;
 307                 ibdev_dbg(aq->efa_dev,
 308                           "Take completion ctxt for command_id %#x\n", cmd_id);
 309         }
 310
 311         return &aq->comp_ctx[ctx_id];
 312 }
 313
 314 static struct efa_comp_ctx *__efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
 315                                                        struct efa_admin_aq_entry *cmd,
 316                                                        size_t cmd_size_in_bytes,
 317                                                        struct efa_admin_acq_entry *comp,
 318                                                        size_t comp_size_in_bytes)
 319 {
 320         struct efa_comp_ctx *comp_ctx;
 321         u16 queue_size_mask;
 322         u16 cmd_id;
 323         u16 ctx_id;
 324         u16 pi;
 325
 326         queue_size_mask = aq->depth - 1;
 327         pi = aq->sq.pc & queue_size_mask;
 328
 329         ctx_id = efa_com_alloc_ctx_id(aq);
 330
 331         /* cmd_id LSBs are the ctx_id and MSBs are entropy bits from pc */
 332         cmd_id = ctx_id & queue_size_mask;
 333         cmd_id |= aq->sq.pc & ~queue_size_mask;
 334         cmd_id &= EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 335
 336         cmd->aq_common_descriptor.command_id = cmd_id;
 337         cmd->aq_common_descriptor.flags |= aq->sq.phase &
 338                 EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 339
 340         comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, true);
 341         if (!comp_ctx) {
 342                 efa_com_dealloc_ctx_id(aq, ctx_id);
 343                 return ERR_PTR(-EINVAL);
 344         }
 345
 346         comp_ctx->status = EFA_CMD_SUBMITTED;
 347         comp_ctx->comp_size = comp_size_in_bytes;
 348         comp_ctx->user_cqe = comp;
 349         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 350
 351         reinit_completion(&comp_ctx->wait_event);
 352
 353         memcpy(&aq->sq.entries[pi], cmd, cmd_size_in_bytes);
 354
 355         aq->sq.pc++;
 356         atomic64_inc(&aq->stats.submitted_cmd);
 357
 358         if ((aq->sq.pc & queue_size_mask) == 0)
 359                 aq->sq.phase = !aq->sq.phase;
 360
 361         /* barrier not needed in case of writel */
 362         writel(aq->sq.pc, aq->sq.db_addr);
 363
 364         return comp_ctx;
 365 }
 366
 367 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq)
 368 {
 369         size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool);
 370         size_t size = aq->depth * sizeof(struct efa_comp_ctx);
 371         struct efa_comp_ctx *comp_ctx;
 372         u16 i;
 373
 374         aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL);
 375         aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL);
 376         if (!aq->comp_ctx || !aq->comp_ctx_pool) {
 377                 devm_kfree(aq->dmadev, aq->comp_ctx_pool);
 378                 devm_kfree(aq->dmadev, aq->comp_ctx);
 379                 return -ENOMEM;
 380         }
 381
 382         for (i = 0; i < aq->depth; i++) {
 383                 comp_ctx = efa_com_get_comp_ctx(aq, i, false);
 384                 if (comp_ctx)
 385                         init_completion(&comp_ctx->wait_event);
 386
 387                 aq->comp_ctx_pool[i] = i;
 388         }
 389
 390         spin_lock_init(&aq->comp_ctx_lock);
 391
 392         aq->comp_ctx_pool_next = 0;
 393
 394         return 0;
 395 }
 396
 397 static struct efa_comp_ctx *efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
 398                                                      struct efa_admin_aq_entry *cmd,
 399                                                      size_t cmd_size_in_bytes,
 400                                                      struct efa_admin_acq_entry *comp,
 401                                                      size_t comp_size_in_bytes)
 402 {
 403         struct efa_comp_ctx *comp_ctx;
 404
 405         spin_lock(&aq->sq.lock);
 406         if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) {
 407                 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n");
 408                 spin_unlock(&aq->sq.lock);
 409                 return ERR_PTR(-ENODEV);
 410         }
 411
 412         comp_ctx = __efa_com_submit_admin_cmd(aq, cmd, cmd_size_in_bytes, comp,
 413                                               comp_size_in_bytes);
 414         spin_unlock(&aq->sq.lock);
 415         if (IS_ERR(comp_ctx))
 416                 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 417
 418         return comp_ctx;
 419 }
 420
 421 static void efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq,
 422                                                    struct efa_admin_acq_entry *cqe)
 423 {
 424         struct efa_comp_ctx *comp_ctx;
 425         u16 cmd_id;
 426
 427         cmd_id = cqe->acq_common_descriptor.command &
 428                  EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 429
 430         comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, false);
 431         if (!comp_ctx) {
 432                 ibdev_err(aq->efa_dev,
 433                           "comp_ctx is NULL. Changing the admin queue running state\n");
 434                 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 435                 return;
 436         }
 437
 438         comp_ctx->status = EFA_CMD_COMPLETED;
 439         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 440         if (comp_ctx->user_cqe)
 441                 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size);
 442
 443         if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
 444                 complete(&comp_ctx->wait_event);
 445 }
 446
 447 static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq)
 448 {
 449         struct efa_admin_acq_entry *cqe;
 450         u16 queue_size_mask;
 451         u16 comp_num = 0;
 452         u8 phase;
 453         u16 ci;
 454
 455         queue_size_mask = aq->depth - 1;
 456
 457         ci = aq->cq.cc & queue_size_mask;
 458         phase = aq->cq.phase;
 459
 460         cqe = &aq->cq.entries[ci];
 461
 462         /* Go over all the completions */
 463         while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
 464                 EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 465                 /*
 466                  * Do not read the rest of the completion entry before the
 467                  * phase bit was validated
 468                  */
 469                 dma_rmb();
 470                 efa_com_handle_single_admin_completion(aq, cqe);
 471
 472                 ci++;
 473                 comp_num++;
 474                 if (ci == aq->depth) {
 475                         ci = 0;
 476                         phase = !phase;
 477                 }
 478
 479                 cqe = &aq->cq.entries[ci];
 480         }
 481
 482         aq->cq.cc += comp_num;
 483         aq->cq.phase = phase;
 484         aq->sq.cc += comp_num;
 485         atomic64_add(comp_num, &aq->stats.completed_cmd);
 486 }
 487
 488 static int efa_com_comp_status_to_errno(u8 comp_status)
 489 {
 490         switch (comp_status) {
 491         case EFA_ADMIN_SUCCESS:
 492                 return 0;
 493         case EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 494                 return -ENOMEM;
 495         case EFA_ADMIN_UNSUPPORTED_OPCODE:
 496                 return -EOPNOTSUPP;
 497         case EFA_ADMIN_BAD_OPCODE:
 498         case EFA_ADMIN_MALFORMED_REQUEST:
 499         case EFA_ADMIN_ILLEGAL_PARAMETER:
 500         case EFA_ADMIN_UNKNOWN_ERROR:
 501                 return -EINVAL;
 502         default:
 503                 return -EINVAL;
 504         }
 505 }
 506
 507 static int efa_com_wait_and_process_admin_cq_polling(struct efa_comp_ctx *comp_ctx,
 508                                                      struct efa_com_admin_queue *aq)
 509 {
 510         unsigned long timeout;
 511         unsigned long flags;
 512         int err;
 513
 514         timeout = jiffies + usecs_to_jiffies(aq->completion_timeout);
 515
 516         while (1) {
 517                 spin_lock_irqsave(&aq->cq.lock, flags);
 518                 efa_com_handle_admin_completion(aq);
 519                 spin_unlock_irqrestore(&aq->cq.lock, flags);
 520
 521                 if (comp_ctx->status != EFA_CMD_SUBMITTED)
 522                         break;
 523
 524                 if (time_is_before_jiffies(timeout)) {
 525                         ibdev_err_ratelimited(
 526                                 aq->efa_dev,
 527                                 "Wait for completion (polling) timeout\n");
 528                         /* EFA didn't have any completion */
 529                         atomic64_inc(&aq->stats.no_completion);
 530
 531                         clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 532                         err = -ETIME;
 533                         goto out;
 534                 }
 535
 536                 msleep(aq->poll_interval);
 537         }
 538
 539         err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
 540 out:
 541         efa_com_put_comp_ctx(aq, comp_ctx);
 542         return err;
 543 }
 544
 545 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx,
 546                                                         struct efa_com_admin_queue *aq)
 547 {
 548         unsigned long flags;
 549         int err;
 550
 551         wait_for_completion_timeout(&comp_ctx->wait_event,
 552                                     usecs_to_jiffies(aq->completion_timeout));
 553
 554         /*
 555          * In case the command wasn't completed find out the root cause.
 556          * There might be 2 kinds of errors
 557          * 1) No completion (timeout reached)
 558          * 2) There is completion but the device didn't get any msi-x interrupt.
 559          */
 560         if (comp_ctx->status == EFA_CMD_SUBMITTED) {
 561                 spin_lock_irqsave(&aq->cq.lock, flags);
 562                 efa_com_handle_admin_completion(aq);
 563                 spin_unlock_irqrestore(&aq->cq.lock, flags);
 564
 565                 atomic64_inc(&aq->stats.no_completion);
 566
 567                 if (comp_ctx->status == EFA_CMD_COMPLETED)
 568                         ibdev_err_ratelimited(
 569                                 aq->efa_dev,
 570                                 "The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%d) status %d (ctx: 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
 571                                 efa_com_cmd_str(comp_ctx->cmd_opcode),
 572                                 comp_ctx->cmd_opcode, comp_ctx->status,
 573                                 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
 574                 else
 575                         ibdev_err_ratelimited(
 576                                 aq->efa_dev,
 577                                 "The device didn't send any completion for admin cmd %s(%d) status %d (ctx 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
 578                                 efa_com_cmd_str(comp_ctx->cmd_opcode),
 579                                 comp_ctx->cmd_opcode, comp_ctx->status,
 580                                 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
 581
 582                 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 583                 err = -ETIME;
 584                 goto out;
 585         }
 586
 587         err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
 588 out:
 589         efa_com_put_comp_ctx(aq, comp_ctx);
 590         return err;
 591 }
 592
 593 /*
 594  * There are two types to wait for completion.
 595  * Polling mode - wait until the completion is available.
 596  * Async mode - wait on wait queue until the completion is ready
 597  * (or the timeout expired).
 598  * It is expected that the IRQ called efa_com_handle_admin_completion
 599  * to mark the completions.
 600  */
 601 static int efa_com_wait_and_process_admin_cq(struct efa_comp_ctx *comp_ctx,
 602                                              struct efa_com_admin_queue *aq)
 603 {
 604         if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
 605                 return efa_com_wait_and_process_admin_cq_polling(comp_ctx, aq);
 606
 607         return efa_com_wait_and_process_admin_cq_interrupts(comp_ctx, aq);
 608 }
 609
 610 /**
 611  * efa_com_cmd_exec - Execute admin command
 612  * @aq: admin queue.
 613  * @cmd: the admin command to execute.
 614  * @cmd_size: the command size.
 615  * @comp: command completion return entry.
 616  * @comp_size: command completion size.
 617  * Submit an admin command and then wait until the device will return a
 618  * completion.
 619  * The completion will be copied into comp.
 620  *
 621  * @return - 0 on success, negative value on failure.
 622  */
 623 int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
 624                      struct efa_admin_aq_entry *cmd,
 625                      size_t cmd_size,
 626                      struct efa_admin_acq_entry *comp,
 627                      size_t comp_size)
 628 {
 629         struct efa_comp_ctx *comp_ctx;
 630         int err;
 631
 632         might_sleep();
 633
 634         /* In case of queue FULL */
 635         down(&aq->avail_cmds);
 636
 637         ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n",
 638                   efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
 639                   cmd->aq_common_descriptor.opcode);
 640         comp_ctx = efa_com_submit_admin_cmd(aq, cmd, cmd_size, comp, comp_size);
 641         if (IS_ERR(comp_ctx)) {
 642                 ibdev_err_ratelimited(
 643                         aq->efa_dev,
 644                         "Failed to submit command %s (opcode %u) err %ld\n",
 645                         efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
 646                         cmd->aq_common_descriptor.opcode, PTR_ERR(comp_ctx));
 647
 648                 up(&aq->avail_cmds);
 649                 return PTR_ERR(comp_ctx);
 650         }
 651
 652         err = efa_com_wait_and_process_admin_cq(comp_ctx, aq);
 653         if (err)
 654                 ibdev_err_ratelimited(
 655                         aq->efa_dev,
 656                         "Failed to process command %s (opcode %u) comp_status %d err %d\n",
 657                         efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
 658                         cmd->aq_common_descriptor.opcode, comp_ctx->comp_status,
 659                         err);
 660
 661         up(&aq->avail_cmds);
 662
 663         return err;
 664 }
 665
 666 /**
 667  * efa_com_admin_destroy - Destroy the admin and the async events queues.
 668  * @edev: EFA communication layer struct
 669  */
 670 void efa_com_admin_destroy(struct efa_com_dev *edev)
 671 {
 672         struct efa_com_admin_queue *aq = &edev->aq;
 673         struct efa_com_aenq *aenq = &edev->aenq;
 674         struct efa_com_admin_cq *cq = &aq->cq;
 675         struct efa_com_admin_sq *sq = &aq->sq;
 676         u16 size;
 677
 678         clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 679
 680         devm_kfree(edev->dmadev, aq->comp_ctx_pool);
 681         devm_kfree(edev->dmadev, aq->comp_ctx);
 682
 683         size = aq->depth * sizeof(*sq->entries);
 684         dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr);
 685
 686         size = aq->depth * sizeof(*cq->entries);
 687         dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr);
 688
 689         size = aenq->depth * sizeof(*aenq->entries);
 690         dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
 691 }
 692
 693 /**
 694  * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode
 695  * @edev: EFA communication layer struct
 696  * @polling: Enable/Disable polling mode
 697  *
 698  * Set the admin completion mode.
 699  */
 700 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling)
 701 {
 702         u32 mask_value = 0;
 703
 704         if (polling)
 705                 mask_value = EFA_REGS_ADMIN_INTR_MASK;
 706
 707         writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);
 708         if (polling)
 709                 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
 710         else
 711                 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
 712 }
 713
 714 static void efa_com_stats_init(struct efa_com_dev *edev)
 715 {
 716         atomic64_t *s = (atomic64_t *)&edev->aq.stats;
 717         int i;
 718
 719         for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++)
 720                 atomic64_set(s, 0);
 721 }
 722
 723 /**
 724  * efa_com_admin_init - Init the admin and the async queues
 725  * @edev: EFA communication layer struct
 726  * @aenq_handlers: Those handlers to be called upon event.
 727  *
 728  * Initialize the admin submission and completion queues.
 729  * Initialize the asynchronous events notification queues.
 730  *
 731  * @return - 0 on success, negative value on failure.
 732  */
 733 int efa_com_admin_init(struct efa_com_dev *edev,
 734                        struct efa_aenq_handlers *aenq_handlers)
 735 {
 736         struct efa_com_admin_queue *aq = &edev->aq;
 737         u32 timeout;
 738         u32 dev_sts;
 739         u32 cap;
 740         int err;
 741
 742         dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
 743         if (!(dev_sts & EFA_REGS_DEV_STS_READY_MASK)) {
 744                 ibdev_err(edev->efa_dev,
 745                           "Device isn't ready, abort com init %#x\n", dev_sts);
 746                 return -ENODEV;
 747         }
 748
 749         aq->depth = EFA_ADMIN_QUEUE_DEPTH;
 750
 751         aq->dmadev = edev->dmadev;
 752         aq->efa_dev = edev->efa_dev;
 753         set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state);
 754
 755         sema_init(&aq->avail_cmds, aq->depth);
 756
 757         efa_com_stats_init(edev);
 758
 759         err = efa_com_init_comp_ctxt(aq);
 760         if (err)
 761                 return err;
 762
 763         err = efa_com_admin_init_sq(edev);
 764         if (err)
 765                 goto err_destroy_comp_ctxt;
 766
 767         err = efa_com_admin_init_cq(edev);
 768         if (err)
 769                 goto err_destroy_sq;
 770
 771         efa_com_set_admin_polling_mode(edev, false);
 772
 773         err = efa_com_admin_init_aenq(edev, aenq_handlers);
 774         if (err)
 775                 goto err_destroy_cq;
 776
 777         cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
 778         timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
 779                   EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
 780         if (timeout)
 781                 /* the resolution of timeout reg is 100ms */
 782                 aq->completion_timeout = timeout * 100000;
 783         else
 784                 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US;
 785
 786         aq->poll_interval = EFA_POLL_INTERVAL_MS;
 787
 788         set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
 789
 790         return 0;
 791
 792 err_destroy_cq:
 793         dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries),
 794                           aq->cq.entries, aq->cq.dma_addr);
 795 err_destroy_sq:
 796         dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries),
 797                           aq->sq.entries, aq->sq.dma_addr);
 798 err_destroy_comp_ctxt:
 799         devm_kfree(edev->dmadev, aq->comp_ctx);
 800
 801         return err;
 802 }
 803
 804 /**
 805  * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler
 806  * @edev: EFA communication layer struct
 807  *
 808  * This method goes over the admin completion queue and wakes up
 809  * all the pending threads that wait on the commands wait event.
 810  *
 811  * @note: Should be called after MSI-X interrupt.
 812  */
 813 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev)
 814 {
 815         unsigned long flags;
 816
 817         spin_lock_irqsave(&edev->aq.cq.lock, flags);
 818         efa_com_handle_admin_completion(&edev->aq);
 819         spin_unlock_irqrestore(&edev->aq.cq.lock, flags);
 820 }
 821
 822 /*
 823  * efa_handle_specific_aenq_event:
 824  * return the handler that is relevant to the specific event group
 825  */
 826 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev,
 827                                                      u16 group)
 828 {
 829         struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
 830
 831         if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group])
 832                 return aenq_handlers->handlers[group];
 833
 834         return aenq_handlers->unimplemented_handler;
 835 }
 836
 837 /**
 838  * efa_com_aenq_intr_handler - AENQ interrupt handler
 839  * @edev: EFA communication layer struct
 840  * @data: Data of interrupt handler.
 841  *
 842  * Go over the async event notification queue and call the proper aenq handler.
 843  */
 844 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data)
 845 {
 846         struct efa_admin_aenq_common_desc *aenq_common;
 847         struct efa_com_aenq *aenq = &edev->aenq;
 848         struct efa_admin_aenq_entry *aenq_e;
 849         efa_aenq_handler handler_cb;
 850         u32 processed = 0;
 851         u8 phase;
 852         u32 ci;
 853
 854         ci = aenq->cc & (aenq->depth - 1);
 855         phase = aenq->phase;
 856         aenq_e = &aenq->entries[ci]; /* Get first entry */
 857         aenq_common = &aenq_e->aenq_common_desc;
 858
 859         /* Go over all the events */
 860         while ((READ_ONCE(aenq_common->flags) &
 861                 EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
 862                 /*
 863                  * Do not read the rest of the completion entry before the
 864                  * phase bit was validated
 865                  */
 866                 dma_rmb();
 867
 868                 /* Handle specific event*/
 869                 handler_cb = efa_com_get_specific_aenq_cb(edev,
 870                                                           aenq_common->group);
 871                 handler_cb(data, aenq_e); /* call the actual event handler*/
 872
 873                 /* Get next event entry */
 874                 ci++;
 875                 processed++;
 876
 877                 if (ci == aenq->depth) {
 878                         ci = 0;
 879                         phase = !phase;
 880                 }
 881                 aenq_e = &aenq->entries[ci];
 882                 aenq_common = &aenq_e->aenq_common_desc;
 883         }
 884
 885         aenq->cc += processed;
 886         aenq->phase = phase;
 887
 888         /* Don't update aenq doorbell if there weren't any processed events */
 889         if (!processed)
 890                 return;
 891
 892         /* barrier not needed in case of writel */
 893         writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
 894 }
 895
 896 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev)
 897 {
 898         struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
 899         u32 addr_high;
 900         u32 addr_low;
 901
 902         /* dma_addr_bits is unknown at this point */
 903         addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0);
 904         addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0);
 905
 906         writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);
 907         writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);
 908 }
 909
 910 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev)
 911 {
 912         struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
 913
 914         spin_lock_init(&mmio_read->lock);
 915         mmio_read->read_resp =
 916                 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
 917                                    &mmio_read->read_resp_dma_addr, GFP_KERNEL);
 918         if (!mmio_read->read_resp)
 919                 return -ENOMEM;
 920
 921         efa_com_mmio_reg_read_resp_addr_init(edev);
 922
 923         mmio_read->read_resp->req_id = 0;
 924         mmio_read->seq_num = 0;
 925         mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US;
 926
 927         return 0;
 928 }
 929
 930 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev)
 931 {
 932         struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
 933
 934         dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
 935                           mmio_read->read_resp, mmio_read->read_resp_dma_addr);
 936 }
 937
 938 int efa_com_validate_version(struct efa_com_dev *edev)
 939 {
 940         u32 ctrl_ver_masked;
 941         u32 ctrl_ver;
 942         u32 ver;
 943
 944         /*
 945          * Make sure the EFA version and the controller version are at least
 946          * as the driver expects
 947          */
 948         ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF);
 949         ctrl_ver = efa_com_reg_read32(edev,
 950                                       EFA_REGS_CONTROLLER_VERSION_OFF);
 951
 952         ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n",
 953                   (ver & EFA_REGS_VERSION_MAJOR_VERSION_MASK) >>
 954                           EFA_REGS_VERSION_MAJOR_VERSION_SHIFT,
 955                   ver & EFA_REGS_VERSION_MINOR_VERSION_MASK);
 956
 957         if (ver < MIN_EFA_VER) {
 958                 ibdev_err(edev->efa_dev,
 959                           "EFA version is lower than the minimal version the driver supports\n");
 960                 return -EOPNOTSUPP;
 961         }
 962
 963         ibdev_dbg(edev->efa_dev,
 964                   "efa controller version: %d.%d.%d implementation version %d\n",
 965                   (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
 966                           EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
 967                   (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
 968                           EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
 969                   (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
 970                   (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
 971                           EFA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
 972
 973         ctrl_ver_masked =
 974                 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
 975                 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
 976                 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
 977
 978         /* Validate the ctrl version without the implementation ID */
 979         if (ctrl_ver_masked < MIN_EFA_CTRL_VER) {
 980                 ibdev_err(edev->efa_dev,
 981                           "EFA ctrl version is lower than the minimal ctrl version the driver supports\n");
 982                 return -EOPNOTSUPP;
 983         }
 984
 985         return 0;
 986 }
 987
 988 /**
 989  * efa_com_get_dma_width - Retrieve physical dma address width the device
 990  * supports.
 991  * @edev: EFA communication layer struct
 992  *
 993  * Retrieve the maximum physical address bits the device can handle.
 994  *
 995  * @return: > 0 on Success and negative value otherwise.
 996  */
 997 int efa_com_get_dma_width(struct efa_com_dev *edev)
 998 {
 999         u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1000         int width;
1001
1002         width = (caps & EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1003                 EFA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1004
1005         ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width);
1006
1007         if (width < 32 || width > 64) {
1008                 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width);
1009                 return -EINVAL;
1010         }
1011
1012         edev->dma_addr_bits = width;
1013
1014         return width;
1015 }
1016
1017 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout,
1018                                 u16 exp_state)
1019 {
1020         u32 val, i;
1021
1022         for (i = 0; i < timeout; i++) {
1023                 val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1024
1025                 if ((val & EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
1026                     exp_state)
1027                         return 0;
1028
1029                 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val);
1030                 msleep(EFA_POLL_INTERVAL_MS);
1031         }
1032
1033         return -ETIME;
1034 }
1035
1036 /**
1037  * efa_com_dev_reset - Perform device FLR to the device.
1038  * @edev: EFA communication layer struct
1039  * @reset_reason: Specify what is the trigger for the reset in case of an error.
1040  *
1041  * @return - 0 on success, negative value on failure.
1042  */
1043 int efa_com_dev_reset(struct efa_com_dev *edev,
1044                       enum efa_regs_reset_reason_types reset_reason)
1045 {
1046         u32 stat, timeout, cap, reset_val;
1047         int err;
1048
1049         stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1050         cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1051
1052         if (!(stat & EFA_REGS_DEV_STS_READY_MASK)) {
1053                 ibdev_err(edev->efa_dev,
1054                           "Device isn't ready, can't reset device\n");
1055                 return -EINVAL;
1056         }
1057
1058         timeout = (cap & EFA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1059                   EFA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1060         if (!timeout) {
1061                 ibdev_err(edev->efa_dev, "Invalid timeout value\n");
1062                 return -EINVAL;
1063         }
1064
1065         /* start reset */
1066         reset_val = EFA_REGS_DEV_CTL_DEV_RESET_MASK;
1067         reset_val |= (reset_reason << EFA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
1068                      EFA_REGS_DEV_CTL_RESET_REASON_MASK;
1069         writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1070
1071         /* reset clears the mmio readless address, restore it */
1072         efa_com_mmio_reg_read_resp_addr_init(edev);
1073
1074         err = wait_for_reset_state(edev, timeout,
1075                                    EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1076         if (err) {
1077                 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n");
1078                 return err;
1079         }
1080
1081         /* reset done */
1082         writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1083         err = wait_for_reset_state(edev, timeout, 0);
1084         if (err) {
1085                 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n");
1086                 return err;
1087         }
1088
1089         timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
1090                   EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
1091         if (timeout)
1092                 /* the resolution of timeout reg is 100ms */
1093                 edev->aq.completion_timeout = timeout * 100000;
1094         else
1095                 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US;
1096
1097         return 0;
1098 }