2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
70 spin_unlock_irq(&dev->lock);
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
79 static void free_ird(struct c4iw_dev *dev, int ird)
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
110 dealloc_host_sq(rdev, sq);
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
143 ret = alloc_oc_sq(rdev, sq);
145 ret = alloc_host_sq(rdev, sq);
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
182 &bar2_qoffset, pbar2_qid);
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
189 if (is_t4(rdev->lldi.adapter_type))
192 return rdev->bar2_kva + bar2_qoffset;
195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx,
198 struct c4iw_wr_wait *wr_waitp)
200 int user = (uctx != &rdev->uctx);
201 struct fw_ri_res_wr *res_wr;
202 struct fw_ri_res *res;
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
235 * RQT must be a power of 2 and at least 16 deep.
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
244 ret = alloc_sq(rdev, &wq->sq, user);
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
257 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
259 (unsigned long long)virt_to_phys(wq->sq.queue),
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
265 wq->db = rdev->lldi.db_reg;
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
272 user ? &wq->rq.bar2_pa : NULL);
275 * User mode must have bar2 access.
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
289 skb = alloc_skb(wr_len, GFP_KERNEL);
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
296 res_wr = __skb_put_zero(skb, wr_len);
297 res_wr->op_nres = cpu_to_be32(
298 FW_WR_OP_V(FW_RI_RES_WR) |
299 FW_RI_RES_WR_NRES_V(2) |
301 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
302 res_wr->cookie = (uintptr_t)wr_waitp;
304 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
305 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
308 * eqsize is the number of 64B entries plus the status page size.
310 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
311 rdev->hw_queue.t4_eq_status_entries;
313 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
314 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
315 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
316 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
317 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
318 FW_RI_RES_WR_IQID_V(scq->cqid));
319 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
320 FW_RI_RES_WR_DCAEN_V(0) |
321 FW_RI_RES_WR_DCACPU_V(0) |
322 FW_RI_RES_WR_FBMIN_V(2) |
323 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
324 FW_RI_RES_WR_FBMAX_V(3)) |
325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
326 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
327 FW_RI_RES_WR_EQSIZE_V(eqsize));
328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
332 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
335 * eqsize is the number of 64B entries plus the status page size.
337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
338 rdev->hw_queue.t4_eq_status_entries;
339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
343 FW_RI_RES_WR_IQID_V(rcq->cqid));
344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
345 FW_RI_RES_WR_DCAEN_V(0) |
346 FW_RI_RES_WR_DCACPU_V(0) |
347 FW_RI_RES_WR_FBMIN_V(2) |
348 FW_RI_RES_WR_FBMAX_V(3) |
349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
350 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
351 FW_RI_RES_WR_EQSIZE_V(eqsize));
352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
355 c4iw_init_wr_wait(wr_waitp);
356 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__);
360 pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
361 wq->sq.qid, wq->rq.qid, wq->db,
362 wq->sq.bar2_va, wq->rq.bar2_va);
366 dma_free_coherent(&(rdev->lldi.pdev->dev),
367 wq->rq.memsize, wq->rq.queue,
368 dma_unmap_addr(&wq->rq, mapping));
370 dealloc_sq(rdev, &wq->sq);
372 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
378 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
380 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
384 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
385 struct ib_send_wr *wr, int max, u32 *plenp)
392 dstp = (u8 *)immdp->data;
393 for (i = 0; i < wr->num_sge; i++) {
394 if ((plen + wr->sg_list[i].length) > max)
396 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
397 plen += wr->sg_list[i].length;
398 rem = wr->sg_list[i].length;
400 if (dstp == (u8 *)&sq->queue[sq->size])
401 dstp = (u8 *)sq->queue;
402 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
405 len = (u8 *)&sq->queue[sq->size] - dstp;
406 memcpy(dstp, srcp, len);
412 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
414 memset(dstp, 0, len);
415 immdp->op = FW_RI_DATA_IMMD;
418 immdp->immdlen = cpu_to_be32(plen);
423 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
424 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
425 int num_sge, u32 *plenp)
430 __be64 *flitp = (__be64 *)isglp->sge;
432 for (i = 0; i < num_sge; i++) {
433 if ((plen + sg_list[i].length) < plen)
435 plen += sg_list[i].length;
436 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
438 if (++flitp == queue_end)
440 *flitp = cpu_to_be64(sg_list[i].addr);
441 if (++flitp == queue_end)
444 *flitp = (__force __be64)0;
445 isglp->op = FW_RI_DATA_ISGL;
447 isglp->nsge = cpu_to_be16(num_sge);
454 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
455 struct ib_send_wr *wr, u8 *len16)
461 if (wr->num_sge > T4_MAX_SEND_SGE)
463 switch (wr->opcode) {
465 if (wr->send_flags & IB_SEND_SOLICITED)
466 wqe->send.sendop_pkd = cpu_to_be32(
467 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
469 wqe->send.sendop_pkd = cpu_to_be32(
470 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
471 wqe->send.stag_inv = 0;
473 case IB_WR_SEND_WITH_INV:
474 if (wr->send_flags & IB_SEND_SOLICITED)
475 wqe->send.sendop_pkd = cpu_to_be32(
476 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
478 wqe->send.sendop_pkd = cpu_to_be32(
479 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
480 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
491 if (wr->send_flags & IB_SEND_INLINE) {
492 ret = build_immd(sq, wqe->send.u.immd_src, wr,
493 T4_MAX_SEND_INLINE, &plen);
496 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
499 ret = build_isgl((__be64 *)sq->queue,
500 (__be64 *)&sq->queue[sq->size],
501 wqe->send.u.isgl_src,
502 wr->sg_list, wr->num_sge, &plen);
505 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
506 wr->num_sge * sizeof(struct fw_ri_sge);
509 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
510 wqe->send.u.immd_src[0].r1 = 0;
511 wqe->send.u.immd_src[0].r2 = 0;
512 wqe->send.u.immd_src[0].immdlen = 0;
513 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
516 *len16 = DIV_ROUND_UP(size, 16);
517 wqe->send.plen = cpu_to_be32(plen);
521 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
522 struct ib_send_wr *wr, u8 *len16)
528 if (wr->num_sge > T4_MAX_SEND_SGE)
531 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
532 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
534 if (wr->send_flags & IB_SEND_INLINE) {
535 ret = build_immd(sq, wqe->write.u.immd_src, wr,
536 T4_MAX_WRITE_INLINE, &plen);
539 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
542 ret = build_isgl((__be64 *)sq->queue,
543 (__be64 *)&sq->queue[sq->size],
544 wqe->write.u.isgl_src,
545 wr->sg_list, wr->num_sge, &plen);
548 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
549 wr->num_sge * sizeof(struct fw_ri_sge);
552 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
553 wqe->write.u.immd_src[0].r1 = 0;
554 wqe->write.u.immd_src[0].r2 = 0;
555 wqe->write.u.immd_src[0].immdlen = 0;
556 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
559 *len16 = DIV_ROUND_UP(size, 16);
560 wqe->write.plen = cpu_to_be32(plen);
564 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
568 if (wr->num_sge && wr->sg_list[0].length) {
569 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
570 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
572 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
573 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
574 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
575 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
577 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
579 wqe->read.stag_src = cpu_to_be32(2);
580 wqe->read.to_src_hi = 0;
581 wqe->read.to_src_lo = 0;
582 wqe->read.stag_sink = cpu_to_be32(2);
584 wqe->read.to_sink_hi = 0;
585 wqe->read.to_sink_lo = 0;
589 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
593 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
594 struct ib_recv_wr *wr, u8 *len16)
598 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
599 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
600 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
603 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
604 wr->num_sge * sizeof(struct fw_ri_sge), 16);
608 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
609 struct ib_reg_wr *wr, struct c4iw_mr *mhp,
612 __be64 *p = (__be64 *)fr->pbl;
614 fr->r2 = cpu_to_be32(0);
615 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
617 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
618 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
619 FW_RI_TPTE_STAGSTATE_V(1) |
620 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
621 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
622 fr->tpte.locread_to_qpid = cpu_to_be32(
623 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
624 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
625 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
626 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
627 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
628 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
629 fr->tpte.len_hi = cpu_to_be32(0);
630 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
631 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
632 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
634 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
635 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
637 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
640 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
641 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
644 struct fw_ri_immd *imdp;
647 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
650 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
653 wqe->fr.qpbinde_to_dcacpu = 0;
654 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
655 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
656 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
658 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
659 wqe->fr.stag = cpu_to_be32(wr->key);
660 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
661 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
664 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
665 struct fw_ri_dsgl *sglp;
667 for (i = 0; i < mhp->mpl_len; i++)
668 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
670 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
671 sglp->op = FW_RI_DATA_DSGL;
673 sglp->nsge = cpu_to_be16(1);
674 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
675 sglp->len0 = cpu_to_be32(pbllen);
677 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
679 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
680 imdp->op = FW_RI_DATA_IMMD;
683 imdp->immdlen = cpu_to_be32(pbllen);
684 p = (__be64 *)(imdp + 1);
686 for (i = 0; i < mhp->mpl_len; i++) {
687 *p = cpu_to_be64((u64)mhp->mpl[i]);
689 if (++p == (__be64 *)&sq->queue[sq->size])
690 p = (__be64 *)sq->queue;
695 if (++p == (__be64 *)&sq->queue[sq->size])
696 p = (__be64 *)sq->queue;
698 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
704 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
706 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
708 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
712 static void free_qp_work(struct work_struct *work)
714 struct c4iw_ucontext *ucontext;
716 struct c4iw_dev *rhp;
718 qhp = container_of(work, struct c4iw_qp, free_work);
719 ucontext = qhp->ucontext;
722 pr_debug("qhp %p ucontext %p\n", qhp, ucontext);
723 destroy_qp(&rhp->rdev, &qhp->wq,
724 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
727 c4iw_put_ucontext(ucontext);
728 c4iw_put_wr_wait(qhp->wr_waitp);
732 static void queue_qp_free(struct kref *kref)
736 qhp = container_of(kref, struct c4iw_qp, kref);
737 pr_debug("qhp %p\n", qhp);
738 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
741 void c4iw_qp_add_ref(struct ib_qp *qp)
743 pr_debug("ib_qp %p\n", qp);
744 kref_get(&to_c4iw_qp(qp)->kref);
747 void c4iw_qp_rem_ref(struct ib_qp *qp)
749 pr_debug("ib_qp %p\n", qp);
750 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
753 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
755 if (list_empty(entry))
756 list_add_tail(entry, head);
759 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
763 spin_lock_irqsave(&qhp->rhp->lock, flags);
764 spin_lock(&qhp->lock);
765 if (qhp->rhp->db_state == NORMAL)
766 t4_ring_sq_db(&qhp->wq, inc, NULL);
768 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
769 qhp->wq.sq.wq_pidx_inc += inc;
771 spin_unlock(&qhp->lock);
772 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
776 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
780 spin_lock_irqsave(&qhp->rhp->lock, flags);
781 spin_lock(&qhp->lock);
782 if (qhp->rhp->db_state == NORMAL)
783 t4_ring_rq_db(&qhp->wq, inc, NULL);
785 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
786 qhp->wq.rq.wq_pidx_inc += inc;
788 spin_unlock(&qhp->lock);
789 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
793 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
795 struct t4_cqe cqe = {};
796 struct c4iw_cq *schp;
800 schp = to_c4iw_cq(qhp->ibqp.send_cq);
803 cqe.u.drain_cookie = wr->wr_id;
804 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
805 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
808 CQE_QPID_V(qhp->wq.sq.qid));
810 spin_lock_irqsave(&schp->lock, flag);
811 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
812 cq->sw_queue[cq->sw_pidx] = cqe;
814 spin_unlock_irqrestore(&schp->lock, flag);
816 if (t4_clear_cq_armed(&schp->cq)) {
817 spin_lock_irqsave(&schp->comp_handler_lock, flag);
818 (*schp->ibcq.comp_handler)(&schp->ibcq,
819 schp->ibcq.cq_context);
820 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
824 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
826 struct t4_cqe cqe = {};
827 struct c4iw_cq *rchp;
831 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
834 cqe.u.drain_cookie = wr->wr_id;
835 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
836 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
839 CQE_QPID_V(qhp->wq.sq.qid));
841 spin_lock_irqsave(&rchp->lock, flag);
842 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
843 cq->sw_queue[cq->sw_pidx] = cqe;
845 spin_unlock_irqrestore(&rchp->lock, flag);
847 if (t4_clear_cq_armed(&rchp->cq)) {
848 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
849 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
850 rchp->ibcq.cq_context);
851 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
855 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
856 struct ib_send_wr **bad_wr)
860 enum fw_wr_opcodes fw_opcode = 0;
861 enum fw_ri_wr_flags fw_flags;
863 union t4_wr *wqe = NULL;
865 struct t4_swsqe *swsqe;
869 qhp = to_c4iw_qp(ibqp);
870 spin_lock_irqsave(&qhp->lock, flag);
873 * If the qp has been flushed, then just insert a special
876 if (qhp->wq.flushed) {
877 spin_unlock_irqrestore(&qhp->lock, flag);
878 complete_sq_drain_wr(qhp, wr);
881 num_wrs = t4_sq_avail(&qhp->wq);
883 spin_unlock_irqrestore(&qhp->lock, flag);
893 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
894 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
897 if (wr->send_flags & IB_SEND_SOLICITED)
898 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
899 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
900 fw_flags |= FW_RI_COMPLETION_FLAG;
901 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
902 switch (wr->opcode) {
903 case IB_WR_SEND_WITH_INV:
905 if (wr->send_flags & IB_SEND_FENCE)
906 fw_flags |= FW_RI_READ_FENCE_FLAG;
907 fw_opcode = FW_RI_SEND_WR;
908 if (wr->opcode == IB_WR_SEND)
909 swsqe->opcode = FW_RI_SEND;
911 swsqe->opcode = FW_RI_SEND_WITH_INV;
912 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
914 case IB_WR_RDMA_WRITE:
915 fw_opcode = FW_RI_RDMA_WRITE_WR;
916 swsqe->opcode = FW_RI_RDMA_WRITE;
917 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
919 case IB_WR_RDMA_READ:
920 case IB_WR_RDMA_READ_WITH_INV:
921 fw_opcode = FW_RI_RDMA_READ_WR;
922 swsqe->opcode = FW_RI_READ_REQ;
923 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
924 c4iw_invalidate_mr(qhp->rhp,
925 wr->sg_list[0].lkey);
926 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
930 err = build_rdma_read(wqe, wr, &len16);
933 swsqe->read_len = wr->sg_list[0].length;
934 if (!qhp->wq.sq.oldest_read)
935 qhp->wq.sq.oldest_read = swsqe;
938 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
940 swsqe->opcode = FW_RI_FAST_REGISTER;
941 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
942 !mhp->attr.state && mhp->mpl_len <= 2) {
943 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
944 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
947 fw_opcode = FW_RI_FR_NSMR_WR;
948 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
950 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
957 case IB_WR_LOCAL_INV:
958 if (wr->send_flags & IB_SEND_FENCE)
959 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
960 fw_opcode = FW_RI_INV_LSTAG_WR;
961 swsqe->opcode = FW_RI_LOCAL_INV;
962 err = build_inv_stag(wqe, wr, &len16);
963 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
966 pr_warn("%s post of type=%d TBD!\n", __func__,
974 swsqe->idx = qhp->wq.sq.pidx;
976 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
979 swsqe->wr_id = wr->wr_id;
981 swsqe->sge_ts = cxgb4_read_sge_timestamp(
982 qhp->rhp->rdev.lldi.ports[0]);
983 getnstimeofday(&swsqe->host_ts);
986 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
988 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
989 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
990 swsqe->opcode, swsqe->read_len);
993 t4_sq_produce(&qhp->wq, len16);
994 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
996 if (!qhp->rhp->rdev.status_page->db_off) {
997 t4_ring_sq_db(&qhp->wq, idx, wqe);
998 spin_unlock_irqrestore(&qhp->lock, flag);
1000 spin_unlock_irqrestore(&qhp->lock, flag);
1001 ring_kernel_sq_db(qhp, idx);
1006 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1007 struct ib_recv_wr **bad_wr)
1010 struct c4iw_qp *qhp;
1011 union t4_recv_wr *wqe = NULL;
1017 qhp = to_c4iw_qp(ibqp);
1018 spin_lock_irqsave(&qhp->lock, flag);
1021 * If the qp has been flushed, then just insert a special
1024 if (qhp->wq.flushed) {
1025 spin_unlock_irqrestore(&qhp->lock, flag);
1026 complete_rq_drain_wr(qhp, wr);
1029 num_wrs = t4_rq_avail(&qhp->wq);
1031 spin_unlock_irqrestore(&qhp->lock, flag);
1036 if (wr->num_sge > T4_MAX_RECV_SGE) {
1041 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1042 qhp->wq.rq.wq_pidx *
1045 err = build_rdma_recv(qhp, wqe, wr, &len16);
1053 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1055 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1056 cxgb4_read_sge_timestamp(
1057 qhp->rhp->rdev.lldi.ports[0]);
1059 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
1062 wqe->recv.opcode = FW_RI_RECV_WR;
1064 wqe->recv.wrid = qhp->wq.rq.pidx;
1065 wqe->recv.r2[0] = 0;
1066 wqe->recv.r2[1] = 0;
1067 wqe->recv.r2[2] = 0;
1068 wqe->recv.len16 = len16;
1069 pr_debug("cookie 0x%llx pidx %u\n",
1070 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1071 t4_rq_produce(&qhp->wq, len16);
1072 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1076 if (!qhp->rhp->rdev.status_page->db_off) {
1077 t4_ring_rq_db(&qhp->wq, idx, wqe);
1078 spin_unlock_irqrestore(&qhp->lock, flag);
1080 spin_unlock_irqrestore(&qhp->lock, flag);
1081 ring_kernel_rq_db(qhp, idx);
1086 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1096 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1101 status = CQE_STATUS(err_cqe);
1102 opcode = CQE_OPCODE(err_cqe);
1103 rqtype = RQ_TYPE(err_cqe);
1104 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1105 (opcode == FW_RI_SEND_WITH_SE_INV);
1106 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1107 (rqtype && (opcode == FW_RI_READ_RESP));
1112 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1113 *ecode = RDMAP_CANT_INV_STAG;
1115 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1116 *ecode = RDMAP_INV_STAG;
1120 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1121 if ((opcode == FW_RI_SEND_WITH_INV) ||
1122 (opcode == FW_RI_SEND_WITH_SE_INV))
1123 *ecode = RDMAP_CANT_INV_STAG;
1125 *ecode = RDMAP_STAG_NOT_ASSOC;
1128 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1129 *ecode = RDMAP_STAG_NOT_ASSOC;
1132 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1133 *ecode = RDMAP_ACC_VIOL;
1136 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1137 *ecode = RDMAP_TO_WRAP;
1141 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1142 *ecode = DDPT_BASE_BOUNDS;
1144 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1145 *ecode = RDMAP_BASE_BOUNDS;
1148 case T4_ERR_INVALIDATE_SHARED_MR:
1149 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1150 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1151 *ecode = RDMAP_CANT_INV_STAG;
1154 case T4_ERR_ECC_PSTAG:
1155 case T4_ERR_INTERNAL_ERR:
1156 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1159 case T4_ERR_OUT_OF_RQE:
1160 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1161 *ecode = DDPU_INV_MSN_NOBUF;
1163 case T4_ERR_PBL_ADDR_BOUND:
1164 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1165 *ecode = DDPT_BASE_BOUNDS;
1168 *layer_type = LAYER_MPA|DDP_LLP;
1169 *ecode = MPA_CRC_ERR;
1172 *layer_type = LAYER_MPA|DDP_LLP;
1173 *ecode = MPA_MARKER_ERR;
1175 case T4_ERR_PDU_LEN_ERR:
1176 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1177 *ecode = DDPU_MSG_TOOBIG;
1179 case T4_ERR_DDP_VERSION:
1181 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1182 *ecode = DDPT_INV_VERS;
1184 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1185 *ecode = DDPU_INV_VERS;
1188 case T4_ERR_RDMA_VERSION:
1189 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1190 *ecode = RDMAP_INV_VERS;
1193 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1194 *ecode = RDMAP_INV_OPCODE;
1196 case T4_ERR_DDP_QUEUE_NUM:
1197 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1198 *ecode = DDPU_INV_QN;
1201 case T4_ERR_MSN_GAP:
1202 case T4_ERR_MSN_RANGE:
1203 case T4_ERR_IRD_OVERFLOW:
1204 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1205 *ecode = DDPU_INV_MSN_RANGE;
1208 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1212 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1213 *ecode = DDPU_INV_MO;
1216 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1222 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1225 struct fw_ri_wr *wqe;
1226 struct sk_buff *skb;
1227 struct terminate_message *term;
1229 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid,
1232 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1236 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1238 wqe = __skb_put(skb, sizeof(*wqe));
1239 memset(wqe, 0, sizeof *wqe);
1240 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1241 wqe->flowid_len16 = cpu_to_be32(
1242 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1243 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1245 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1246 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1247 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1248 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1249 term->layer_etype = qhp->attr.layer_etype;
1250 term->ecode = qhp->attr.ecode;
1252 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1253 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1257 * Assumes qhp lock is held.
1259 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1260 struct c4iw_cq *schp)
1263 int rq_flushed, sq_flushed;
1266 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp);
1268 /* locking hierarchy: cqs lock first, then qp lock. */
1269 spin_lock_irqsave(&rchp->lock, flag);
1271 spin_lock(&schp->lock);
1272 spin_lock(&qhp->lock);
1274 if (qhp->wq.flushed) {
1275 spin_unlock(&qhp->lock);
1277 spin_unlock(&schp->lock);
1278 spin_unlock_irqrestore(&rchp->lock, flag);
1281 qhp->wq.flushed = 1;
1282 t4_set_wq_in_error(&qhp->wq);
1284 c4iw_flush_hw_cq(rchp);
1285 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1286 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1289 c4iw_flush_hw_cq(schp);
1290 sq_flushed = c4iw_flush_sq(qhp);
1292 spin_unlock(&qhp->lock);
1294 spin_unlock(&schp->lock);
1295 spin_unlock_irqrestore(&rchp->lock, flag);
1298 if ((rq_flushed || sq_flushed) &&
1299 t4_clear_cq_armed(&rchp->cq)) {
1300 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1301 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1302 rchp->ibcq.cq_context);
1303 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1306 if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1307 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1308 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1309 rchp->ibcq.cq_context);
1310 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1312 if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1313 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1314 (*schp->ibcq.comp_handler)(&schp->ibcq,
1315 schp->ibcq.cq_context);
1316 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1321 static void flush_qp(struct c4iw_qp *qhp)
1323 struct c4iw_cq *rchp, *schp;
1326 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1327 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1329 if (qhp->ibqp.uobject) {
1330 t4_set_wq_in_error(&qhp->wq);
1331 t4_set_cq_in_error(&rchp->cq);
1332 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1333 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1334 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1336 t4_set_cq_in_error(&schp->cq);
1337 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1338 (*schp->ibcq.comp_handler)(&schp->ibcq,
1339 schp->ibcq.cq_context);
1340 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1344 __flush_qp(qhp, rchp, schp);
1347 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1350 struct fw_ri_wr *wqe;
1352 struct sk_buff *skb;
1354 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid);
1356 skb = skb_dequeue(&ep->com.ep_skb_list);
1360 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1362 wqe = __skb_put(skb, sizeof(*wqe));
1363 memset(wqe, 0, sizeof *wqe);
1364 wqe->op_compl = cpu_to_be32(
1365 FW_WR_OP_V(FW_RI_INIT_WR) |
1367 wqe->flowid_len16 = cpu_to_be32(
1368 FW_WR_FLOWID_V(ep->hwtid) |
1369 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1370 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1372 wqe->u.fini.type = FW_RI_TYPE_FINI;
1374 ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp,
1375 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1377 pr_debug("ret %d\n", ret);
1381 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1383 pr_debug("p2p_type = %d\n", p2p_type);
1384 memset(&init->u, 0, sizeof init->u);
1386 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1387 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1388 init->u.write.stag_sink = cpu_to_be32(1);
1389 init->u.write.to_sink = cpu_to_be64(1);
1390 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1391 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1392 sizeof(struct fw_ri_immd),
1395 case FW_RI_INIT_P2PTYPE_READ_REQ:
1396 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1397 init->u.read.stag_src = cpu_to_be32(1);
1398 init->u.read.to_src_lo = cpu_to_be32(1);
1399 init->u.read.stag_sink = cpu_to_be32(1);
1400 init->u.read.to_sink_lo = cpu_to_be32(1);
1401 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1406 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1408 struct fw_ri_wr *wqe;
1410 struct sk_buff *skb;
1412 pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp,
1413 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1415 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1420 ret = alloc_ird(rhp, qhp->attr.max_ird);
1422 qhp->attr.max_ird = 0;
1426 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1428 wqe = __skb_put(skb, sizeof(*wqe));
1429 memset(wqe, 0, sizeof *wqe);
1430 wqe->op_compl = cpu_to_be32(
1431 FW_WR_OP_V(FW_RI_INIT_WR) |
1433 wqe->flowid_len16 = cpu_to_be32(
1434 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1435 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1437 wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp;
1439 wqe->u.init.type = FW_RI_TYPE_INIT;
1440 wqe->u.init.mpareqbit_p2ptype =
1441 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1442 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1443 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1444 if (qhp->attr.mpa_attr.recv_marker_enabled)
1445 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1446 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1447 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1448 if (qhp->attr.mpa_attr.crc_enabled)
1449 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1451 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1452 FW_RI_QP_RDMA_WRITE_ENABLE |
1453 FW_RI_QP_BIND_ENABLE;
1454 if (!qhp->ibqp.uobject)
1455 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1456 FW_RI_QP_STAG0_ENABLE;
1457 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1458 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1459 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1460 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1461 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1462 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1463 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1464 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1465 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1466 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1467 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1468 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1469 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1470 rhp->rdev.lldi.vr->rq.start);
1471 if (qhp->attr.mpa_attr.initiator)
1472 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1474 ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp,
1475 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1479 free_ird(rhp, qhp->attr.max_ird);
1481 pr_debug("ret %d\n", ret);
1485 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1486 enum c4iw_qp_attr_mask mask,
1487 struct c4iw_qp_attributes *attrs,
1491 struct c4iw_qp_attributes newattr = qhp->attr;
1496 struct c4iw_ep *ep = NULL;
1498 pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1499 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1500 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1502 mutex_lock(&qhp->mutex);
1504 /* Process attr changes if in IDLE */
1505 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1506 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1510 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1511 newattr.enable_rdma_read = attrs->enable_rdma_read;
1512 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1513 newattr.enable_rdma_write = attrs->enable_rdma_write;
1514 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1515 newattr.enable_bind = attrs->enable_bind;
1516 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1517 if (attrs->max_ord > c4iw_max_read_depth) {
1521 newattr.max_ord = attrs->max_ord;
1523 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1524 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1528 newattr.max_ird = attrs->max_ird;
1530 qhp->attr = newattr;
1533 if (mask & C4IW_QP_ATTR_SQ_DB) {
1534 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1537 if (mask & C4IW_QP_ATTR_RQ_DB) {
1538 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1542 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1544 if (qhp->attr.state == attrs->next_state)
1547 switch (qhp->attr.state) {
1548 case C4IW_QP_STATE_IDLE:
1549 switch (attrs->next_state) {
1550 case C4IW_QP_STATE_RTS:
1551 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1555 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1559 qhp->attr.mpa_attr = attrs->mpa_attr;
1560 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1561 qhp->ep = qhp->attr.llp_stream_handle;
1562 set_state(qhp, C4IW_QP_STATE_RTS);
1565 * Ref the endpoint here and deref when we
1566 * disassociate the endpoint from the QP. This
1567 * happens in CLOSING->IDLE transition or *->ERROR
1570 c4iw_get_ep(&qhp->ep->com);
1571 ret = rdma_init(rhp, qhp);
1575 case C4IW_QP_STATE_ERROR:
1576 set_state(qhp, C4IW_QP_STATE_ERROR);
1584 case C4IW_QP_STATE_RTS:
1585 switch (attrs->next_state) {
1586 case C4IW_QP_STATE_CLOSING:
1587 t4_set_wq_in_error(&qhp->wq);
1588 set_state(qhp, C4IW_QP_STATE_CLOSING);
1593 c4iw_get_ep(&qhp->ep->com);
1595 ret = rdma_fini(rhp, qhp, ep);
1599 case C4IW_QP_STATE_TERMINATE:
1600 t4_set_wq_in_error(&qhp->wq);
1601 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1602 qhp->attr.layer_etype = attrs->layer_etype;
1603 qhp->attr.ecode = attrs->ecode;
1606 c4iw_get_ep(&qhp->ep->com);
1610 terminate = qhp->attr.send_term;
1611 ret = rdma_fini(rhp, qhp, ep);
1616 case C4IW_QP_STATE_ERROR:
1617 t4_set_wq_in_error(&qhp->wq);
1618 set_state(qhp, C4IW_QP_STATE_ERROR);
1623 c4iw_get_ep(&qhp->ep->com);
1632 case C4IW_QP_STATE_CLOSING:
1635 * Allow kernel users to move to ERROR for qp draining.
1637 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1638 C4IW_QP_STATE_ERROR)) {
1642 switch (attrs->next_state) {
1643 case C4IW_QP_STATE_IDLE:
1645 set_state(qhp, C4IW_QP_STATE_IDLE);
1646 qhp->attr.llp_stream_handle = NULL;
1647 c4iw_put_ep(&qhp->ep->com);
1649 wake_up(&qhp->wait);
1651 case C4IW_QP_STATE_ERROR:
1658 case C4IW_QP_STATE_ERROR:
1659 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1663 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1667 set_state(qhp, C4IW_QP_STATE_IDLE);
1669 case C4IW_QP_STATE_TERMINATE:
1677 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1684 pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep,
1687 /* disassociate the LLP connection */
1688 qhp->attr.llp_stream_handle = NULL;
1692 set_state(qhp, C4IW_QP_STATE_ERROR);
1696 wake_up(&qhp->wait);
1698 mutex_unlock(&qhp->mutex);
1701 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1704 * If disconnect is 1, then we need to initiate a disconnect
1705 * on the EP. This can be a normal close (RTS->CLOSING) or
1706 * an abnormal close (RTS/CLOSING->ERROR).
1709 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1711 c4iw_put_ep(&ep->com);
1715 * If free is 1, then we've disassociated the EP from the QP
1716 * and we need to dereference the EP.
1719 c4iw_put_ep(&ep->com);
1720 pr_debug("exit state %d\n", qhp->attr.state);
1724 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1726 struct c4iw_dev *rhp;
1727 struct c4iw_qp *qhp;
1728 struct c4iw_qp_attributes attrs;
1730 qhp = to_c4iw_qp(ib_qp);
1733 attrs.next_state = C4IW_QP_STATE_ERROR;
1734 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1735 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1737 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1738 wait_event(qhp->wait, !qhp->ep);
1740 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1742 spin_lock_irq(&rhp->lock);
1743 if (!list_empty(&qhp->db_fc_entry))
1744 list_del_init(&qhp->db_fc_entry);
1745 spin_unlock_irq(&rhp->lock);
1746 free_ird(rhp, qhp->attr.max_ird);
1748 c4iw_qp_rem_ref(ib_qp);
1750 pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid);
1754 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1755 struct ib_udata *udata)
1757 struct c4iw_dev *rhp;
1758 struct c4iw_qp *qhp;
1759 struct c4iw_pd *php;
1760 struct c4iw_cq *schp;
1761 struct c4iw_cq *rchp;
1762 struct c4iw_create_qp_resp uresp;
1763 unsigned int sqsize, rqsize;
1764 struct c4iw_ucontext *ucontext;
1766 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1767 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1769 pr_debug("ib_pd %p\n", pd);
1771 if (attrs->qp_type != IB_QPT_RC)
1772 return ERR_PTR(-EINVAL);
1774 php = to_c4iw_pd(pd);
1776 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1777 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1779 return ERR_PTR(-EINVAL);
1781 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1782 return ERR_PTR(-EINVAL);
1784 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1785 return ERR_PTR(-E2BIG);
1786 rqsize = attrs->cap.max_recv_wr + 1;
1790 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1791 return ERR_PTR(-E2BIG);
1792 sqsize = attrs->cap.max_send_wr + 1;
1796 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1798 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1800 return ERR_PTR(-ENOMEM);
1802 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
1803 if (!qhp->wr_waitp) {
1808 qhp->wq.sq.size = sqsize;
1809 qhp->wq.sq.memsize =
1810 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1811 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1812 qhp->wq.sq.flush_cidx = -1;
1813 qhp->wq.rq.size = rqsize;
1814 qhp->wq.rq.memsize =
1815 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1816 sizeof(*qhp->wq.rq.queue);
1819 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1820 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1823 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1824 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1827 goto err_free_wr_wait;
1829 attrs->cap.max_recv_wr = rqsize - 1;
1830 attrs->cap.max_send_wr = sqsize - 1;
1831 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1834 qhp->attr.pd = php->pdid;
1835 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1836 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1837 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1838 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1839 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1840 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1841 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1842 qhp->attr.state = C4IW_QP_STATE_IDLE;
1843 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1844 qhp->attr.enable_rdma_read = 1;
1845 qhp->attr.enable_rdma_write = 1;
1846 qhp->attr.enable_bind = 1;
1847 qhp->attr.max_ord = 0;
1848 qhp->attr.max_ird = 0;
1849 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1850 spin_lock_init(&qhp->lock);
1851 mutex_init(&qhp->mutex);
1852 init_waitqueue_head(&qhp->wait);
1853 kref_init(&qhp->kref);
1854 INIT_WORK(&qhp->free_work, free_qp_work);
1856 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1858 goto err_destroy_qp;
1860 if (udata && ucontext) {
1861 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1864 goto err_remove_handle;
1866 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1869 goto err_free_sq_key;
1871 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1872 if (!sq_db_key_mm) {
1874 goto err_free_rq_key;
1876 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1877 if (!rq_db_key_mm) {
1879 goto err_free_sq_db_key;
1881 if (t4_sq_onchip(&qhp->wq.sq)) {
1882 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1884 if (!ma_sync_key_mm) {
1886 goto err_free_rq_db_key;
1888 uresp.flags = C4IW_QPF_ONCHIP;
1891 uresp.qid_mask = rhp->rdev.qpmask;
1892 uresp.sqid = qhp->wq.sq.qid;
1893 uresp.sq_size = qhp->wq.sq.size;
1894 uresp.sq_memsize = qhp->wq.sq.memsize;
1895 uresp.rqid = qhp->wq.rq.qid;
1896 uresp.rq_size = qhp->wq.rq.size;
1897 uresp.rq_memsize = qhp->wq.rq.memsize;
1898 spin_lock(&ucontext->mmap_lock);
1899 if (ma_sync_key_mm) {
1900 uresp.ma_sync_key = ucontext->key;
1901 ucontext->key += PAGE_SIZE;
1903 uresp.ma_sync_key = 0;
1905 uresp.sq_key = ucontext->key;
1906 ucontext->key += PAGE_SIZE;
1907 uresp.rq_key = ucontext->key;
1908 ucontext->key += PAGE_SIZE;
1909 uresp.sq_db_gts_key = ucontext->key;
1910 ucontext->key += PAGE_SIZE;
1911 uresp.rq_db_gts_key = ucontext->key;
1912 ucontext->key += PAGE_SIZE;
1913 spin_unlock(&ucontext->mmap_lock);
1914 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1916 goto err_free_ma_sync_key;
1917 sq_key_mm->key = uresp.sq_key;
1918 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1919 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1920 insert_mmap(ucontext, sq_key_mm);
1921 rq_key_mm->key = uresp.rq_key;
1922 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1923 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1924 insert_mmap(ucontext, rq_key_mm);
1925 sq_db_key_mm->key = uresp.sq_db_gts_key;
1926 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1927 sq_db_key_mm->len = PAGE_SIZE;
1928 insert_mmap(ucontext, sq_db_key_mm);
1929 rq_db_key_mm->key = uresp.rq_db_gts_key;
1930 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1931 rq_db_key_mm->len = PAGE_SIZE;
1932 insert_mmap(ucontext, rq_db_key_mm);
1933 if (ma_sync_key_mm) {
1934 ma_sync_key_mm->key = uresp.ma_sync_key;
1935 ma_sync_key_mm->addr =
1936 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1937 PCIE_MA_SYNC_A) & PAGE_MASK;
1938 ma_sync_key_mm->len = PAGE_SIZE;
1939 insert_mmap(ucontext, ma_sync_key_mm);
1942 c4iw_get_ucontext(ucontext);
1943 qhp->ucontext = ucontext;
1945 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1946 INIT_LIST_HEAD(&qhp->db_fc_entry);
1947 pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
1948 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1949 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1950 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1952 err_free_ma_sync_key:
1953 kfree(ma_sync_key_mm);
1955 kfree(rq_db_key_mm);
1957 kfree(sq_db_key_mm);
1963 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1965 destroy_qp(&rhp->rdev, &qhp->wq,
1966 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1968 c4iw_put_wr_wait(qhp->wr_waitp);
1971 return ERR_PTR(ret);
1974 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1975 int attr_mask, struct ib_udata *udata)
1977 struct c4iw_dev *rhp;
1978 struct c4iw_qp *qhp;
1979 enum c4iw_qp_attr_mask mask = 0;
1980 struct c4iw_qp_attributes attrs;
1982 pr_debug("ib_qp %p\n", ibqp);
1984 /* iwarp does not support the RTR state */
1985 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1986 attr_mask &= ~IB_QP_STATE;
1988 /* Make sure we still have something left to do */
1992 memset(&attrs, 0, sizeof attrs);
1993 qhp = to_c4iw_qp(ibqp);
1996 attrs.next_state = c4iw_convert_state(attr->qp_state);
1997 attrs.enable_rdma_read = (attr->qp_access_flags &
1998 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1999 attrs.enable_rdma_write = (attr->qp_access_flags &
2000 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2001 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2004 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2005 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2006 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2007 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2008 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2011 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2012 * ringing the queue db when we're in DB_FULL mode.
2013 * Only allow this on T4 devices.
2015 attrs.sq_db_inc = attr->sq_psn;
2016 attrs.rq_db_inc = attr->rq_psn;
2017 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2018 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2019 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2020 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2023 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2026 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2028 pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn);
2029 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2032 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2033 int attr_mask, struct ib_qp_init_attr *init_attr)
2035 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2037 memset(attr, 0, sizeof *attr);
2038 memset(init_attr, 0, sizeof *init_attr);
2039 attr->qp_state = to_ib_qp_state(qhp->attr.state);
2040 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2041 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2042 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2043 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
2044 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2045 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;