2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: QPLib resource manager
39 #define dev_fmt(fmt) "QPLIB: " fmt
41 #include <linux/spinlock.h>
42 #include <linux/pci.h>
43 #include <linux/interrupt.h>
44 #include <linux/inetdevice.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/if_vlan.h>
47 #include <linux/vmalloc.h>
48 #include <rdma/ib_verbs.h>
49 #include <rdma/ib_umem.h>
52 #include "qplib_res.h"
54 #include "qplib_rcfw.h"
56 static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev,
57 struct bnxt_qplib_stats *stats);
58 static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev,
59 struct bnxt_qplib_chip_ctx *cctx,
60 struct bnxt_qplib_stats *stats);
63 static void __free_pbl(struct bnxt_qplib_res *res, struct bnxt_qplib_pbl *pbl,
66 struct pci_dev *pdev = res->pdev;
70 for (i = 0; i < pbl->pg_count; i++) {
72 dma_free_coherent(&pdev->dev, pbl->pg_size,
73 (void *)((unsigned long)
79 "PBL free pg_arr[%d] empty?!\n", i);
80 pbl->pg_arr[i] = NULL;
85 vfree(pbl->pg_map_arr);
86 pbl->pg_map_arr = NULL;
91 static void bnxt_qplib_fill_user_dma_pages(struct bnxt_qplib_pbl *pbl,
92 struct bnxt_qplib_sg_info *sginfo)
94 struct ib_block_iter biter;
97 rdma_umem_for_each_dma_block(sginfo->umem, &biter, sginfo->pgsize) {
98 pbl->pg_map_arr[i] = rdma_block_iter_dma_address(&biter);
99 pbl->pg_arr[i] = NULL;
105 static int __alloc_pbl(struct bnxt_qplib_res *res,
106 struct bnxt_qplib_pbl *pbl,
107 struct bnxt_qplib_sg_info *sginfo)
109 struct pci_dev *pdev = res->pdev;
110 bool is_umem = false;
117 pages = ib_umem_num_dma_blocks(sginfo->umem, sginfo->pgsize);
119 pages = sginfo->npages;
120 /* page ptr arrays */
121 pbl->pg_arr = vmalloc_array(pages, sizeof(void *));
125 pbl->pg_map_arr = vmalloc_array(pages, sizeof(dma_addr_t));
126 if (!pbl->pg_map_arr) {
132 pbl->pg_size = sginfo->pgsize;
135 for (i = 0; i < pages; i++) {
136 pbl->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
146 bnxt_qplib_fill_user_dma_pages(pbl, sginfo);
151 __free_pbl(res, pbl, is_umem);
156 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
157 struct bnxt_qplib_hwq *hwq)
161 if (!hwq->max_elements)
163 if (hwq->level >= PBL_LVL_MAX)
166 for (i = 0; i < hwq->level + 1; i++) {
168 __free_pbl(res, &hwq->pbl[i], hwq->is_user);
170 __free_pbl(res, &hwq->pbl[i], false);
173 hwq->level = PBL_LVL_MAX;
174 hwq->max_elements = 0;
175 hwq->element_size = 0;
181 /* All HWQs are power of 2 in size */
183 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
184 struct bnxt_qplib_hwq_attr *hwq_attr)
186 u32 npages, aux_slots, pg_size, aux_pages = 0, aux_size = 0;
187 struct bnxt_qplib_sg_info sginfo = {};
188 u32 depth, stride, npbl, npde;
189 dma_addr_t *src_phys_ptr, **dst_virt_ptr;
190 struct bnxt_qplib_res *res;
191 struct pci_dev *pdev;
196 pg_size = hwq_attr->sginfo->pgsize;
197 hwq->level = PBL_LVL_MAX;
199 depth = roundup_pow_of_two(hwq_attr->depth);
200 stride = roundup_pow_of_two(hwq_attr->stride);
201 if (hwq_attr->aux_depth) {
202 aux_slots = hwq_attr->aux_depth;
203 aux_size = roundup_pow_of_two(hwq_attr->aux_stride);
204 aux_pages = (aux_slots * aux_size) / pg_size;
205 if ((aux_slots * aux_size) % pg_size)
209 if (!hwq_attr->sginfo->umem) {
210 hwq->is_user = false;
211 npages = (depth * stride) / pg_size + aux_pages;
212 if ((depth * stride) % pg_size)
216 hwq_attr->sginfo->npages = npages;
218 npages = ib_umem_num_dma_blocks(hwq_attr->sginfo->umem,
219 hwq_attr->sginfo->pgsize);
223 if (npages == MAX_PBL_LVL_0_PGS && !hwq_attr->sginfo->nopte) {
224 /* This request is Level 0, map PTE */
225 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_0], hwq_attr->sginfo);
228 hwq->level = PBL_LVL_0;
232 if (npages >= MAX_PBL_LVL_0_PGS) {
233 if (npages > MAX_PBL_LVL_1_PGS) {
234 u32 flag = (hwq_attr->type == HWQ_TYPE_L2_CMPL) ?
236 /* 2 levels of indirection */
237 npbl = npages >> MAX_PBL_LVL_1_PGS_SHIFT;
238 if (npages % BIT(MAX_PBL_LVL_1_PGS_SHIFT))
240 npde = npbl >> MAX_PDL_LVL_SHIFT;
241 if (npbl % BIT(MAX_PDL_LVL_SHIFT))
243 /* Alloc PDE pages */
244 sginfo.pgsize = npde * pg_size;
246 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_0], &sginfo);
248 /* Alloc PBL pages */
249 sginfo.npages = npbl;
250 sginfo.pgsize = PAGE_SIZE;
251 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_1], &sginfo);
254 /* Fill PDL with PBL page pointers */
256 (dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;
257 src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;
258 if (hwq_attr->type == HWQ_TYPE_MR) {
259 /* For MR it is expected that we supply only 1 contigous
260 * page i.e only 1 entry in the PDL that will contain
261 * all the PBLs for the user supplied memory region
263 for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
265 dst_virt_ptr[0][i] = src_phys_ptr[i] |
268 for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
270 dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
274 /* Alloc or init PTEs */
275 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_2],
279 hwq->level = PBL_LVL_2;
280 if (hwq_attr->sginfo->nopte)
282 /* Fill PBLs with PTE pointers */
284 (dma_addr_t **)hwq->pbl[PBL_LVL_1].pg_arr;
285 src_phys_ptr = hwq->pbl[PBL_LVL_2].pg_map_arr;
286 for (i = 0; i < hwq->pbl[PBL_LVL_2].pg_count; i++) {
287 dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
288 src_phys_ptr[i] | PTU_PTE_VALID;
290 if (hwq_attr->type == HWQ_TYPE_QUEUE) {
291 /* Find the last pg of the size */
292 i = hwq->pbl[PBL_LVL_2].pg_count;
293 dst_virt_ptr[PTR_PG(i - 1)][PTR_IDX(i - 1)] |=
296 dst_virt_ptr[PTR_PG(i - 2)]
298 PTU_PTE_NEXT_TO_LAST;
300 } else { /* pages < 512 npbl = 1, npde = 0 */
301 u32 flag = (hwq_attr->type == HWQ_TYPE_L2_CMPL) ?
304 /* 1 level of indirection */
305 npbl = npages >> MAX_PBL_LVL_1_PGS_SHIFT;
306 if (npages % BIT(MAX_PBL_LVL_1_PGS_SHIFT))
308 sginfo.npages = npbl;
309 sginfo.pgsize = PAGE_SIZE;
311 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_0], &sginfo);
314 /* Alloc or init PTEs */
315 rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_1],
319 hwq->level = PBL_LVL_1;
320 if (hwq_attr->sginfo->nopte)
322 /* Fill PBL with PTE pointers */
324 (dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;
325 src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;
326 for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count; i++)
327 dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
328 src_phys_ptr[i] | flag;
329 if (hwq_attr->type == HWQ_TYPE_QUEUE) {
330 /* Find the last pg of the size */
331 i = hwq->pbl[PBL_LVL_1].pg_count;
332 dst_virt_ptr[PTR_PG(i - 1)][PTR_IDX(i - 1)] |=
335 dst_virt_ptr[PTR_PG(i - 2)]
337 PTU_PTE_NEXT_TO_LAST;
345 hwq->depth = hwq_attr->depth;
346 hwq->max_elements = hwq->depth;
347 hwq->element_size = stride;
348 hwq->qe_ppg = pg_size / stride;
349 /* For direct access to the elements */
351 if (hwq_attr->sginfo->nopte && hwq->level)
352 lvl = hwq->level - 1;
353 hwq->pbl_ptr = hwq->pbl[lvl].pg_arr;
354 hwq->pbl_dma_ptr = hwq->pbl[lvl].pg_map_arr;
355 spin_lock_init(&hwq->lock);
359 bnxt_qplib_free_hwq(res, hwq);
364 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
365 struct bnxt_qplib_ctx *ctx)
369 bnxt_qplib_free_hwq(res, &ctx->qpc_tbl);
370 bnxt_qplib_free_hwq(res, &ctx->mrw_tbl);
371 bnxt_qplib_free_hwq(res, &ctx->srqc_tbl);
372 bnxt_qplib_free_hwq(res, &ctx->cq_tbl);
373 bnxt_qplib_free_hwq(res, &ctx->tim_tbl);
374 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
375 bnxt_qplib_free_hwq(res, &ctx->tqm_ctx.qtbl[i]);
376 /* restore original pde level before destroy */
377 ctx->tqm_ctx.pde.level = ctx->tqm_ctx.pde_level;
378 bnxt_qplib_free_hwq(res, &ctx->tqm_ctx.pde);
379 bnxt_qplib_free_stats_ctx(res->pdev, &ctx->stats);
382 static int bnxt_qplib_alloc_tqm_rings(struct bnxt_qplib_res *res,
383 struct bnxt_qplib_ctx *ctx)
385 struct bnxt_qplib_hwq_attr hwq_attr = {};
386 struct bnxt_qplib_sg_info sginfo = {};
387 struct bnxt_qplib_tqm_ctx *tqmctx;
391 tqmctx = &ctx->tqm_ctx;
393 sginfo.pgsize = PAGE_SIZE;
394 sginfo.pgshft = PAGE_SHIFT;
395 hwq_attr.sginfo = &sginfo;
397 hwq_attr.type = HWQ_TYPE_CTX;
398 hwq_attr.depth = 512;
399 hwq_attr.stride = sizeof(u64);
400 /* Alloc pdl buffer */
401 rc = bnxt_qplib_alloc_init_hwq(&tqmctx->pde, &hwq_attr);
404 /* Save original pdl level */
405 tqmctx->pde_level = tqmctx->pde.level;
408 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) {
409 if (!tqmctx->qcount[i])
411 hwq_attr.depth = ctx->qpc_count * tqmctx->qcount[i];
412 rc = bnxt_qplib_alloc_init_hwq(&tqmctx->qtbl[i], &hwq_attr);
420 static void bnxt_qplib_map_tqm_pgtbl(struct bnxt_qplib_tqm_ctx *ctx)
422 struct bnxt_qplib_hwq *tbl;
424 __le64 **pbl_ptr, *ptr;
429 pbl_ptr = (__le64 **)ctx->pde.pbl_ptr;
431 for (i = 0, j = 0; i < MAX_TQM_ALLOC_REQ;
432 i++, j += MAX_TQM_ALLOC_BLK_SIZE) {
434 if (!tbl->max_elements)
437 fnz_idx = i; /* first non-zero index */
438 switch (tbl->level) {
440 pg_count = tbl->pbl[PBL_LVL_1].pg_count;
441 for (k = 0; k < pg_count; k++) {
442 ptr = &pbl_ptr[PTR_PG(j + k)][PTR_IDX(j + k)];
443 dma_ptr = &tbl->pbl[PBL_LVL_1].pg_map_arr[k];
444 *ptr = cpu_to_le64(*dma_ptr | PTU_PTE_VALID);
450 ptr = &pbl_ptr[PTR_PG(j)][PTR_IDX(j)];
451 *ptr = cpu_to_le64(tbl->pbl[PBL_LVL_0].pg_map_arr[0] |
458 /* update pde level as per page table programming */
459 ctx->pde.level = (ctx->qtbl[fnz_idx].level == PBL_LVL_2) ? PBL_LVL_2 :
460 ctx->qtbl[fnz_idx].level + 1;
463 static int bnxt_qplib_setup_tqm_rings(struct bnxt_qplib_res *res,
464 struct bnxt_qplib_ctx *ctx)
468 rc = bnxt_qplib_alloc_tqm_rings(res, ctx);
472 bnxt_qplib_map_tqm_pgtbl(&ctx->tqm_ctx);
478 * Routine: bnxt_qplib_alloc_ctx
480 * Context tables are memories which are used by the chip fw.
481 * The 6 tables defined are:
482 * QPC ctx - holds QP states
483 * MRW ctx - holds memory region and window
484 * SRQ ctx - holds shared RQ states
485 * CQ ctx - holds completion queue states
486 * TQM ctx - holds Tx Queue Manager context
487 * TIM ctx - holds timer context
488 * Depending on the size of the tbl requested, either a 1 Page Buffer List
489 * or a 1-to-2-stage indirection Page Directory List + 1 PBL is used
491 * Table might be employed as follows:
492 * For 0 < ctx size <= 1 PAGE, 0 level of ind is used
493 * For 1 PAGE < ctx size <= 512 entries size, 1 level of ind is used
494 * For 512 < ctx size <= MAX, 2 levels of ind is used
496 * 0 if success, else -ERRORS
498 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
499 struct bnxt_qplib_ctx *ctx,
500 bool virt_fn, bool is_p5)
502 struct bnxt_qplib_hwq_attr hwq_attr = {};
503 struct bnxt_qplib_sg_info sginfo = {};
506 if (virt_fn || is_p5)
510 sginfo.pgsize = PAGE_SIZE;
511 sginfo.pgshft = PAGE_SHIFT;
512 hwq_attr.sginfo = &sginfo;
515 hwq_attr.depth = ctx->qpc_count;
516 hwq_attr.stride = BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE;
517 hwq_attr.type = HWQ_TYPE_CTX;
518 rc = bnxt_qplib_alloc_init_hwq(&ctx->qpc_tbl, &hwq_attr);
523 hwq_attr.depth = ctx->mrw_count;
524 hwq_attr.stride = BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE;
525 rc = bnxt_qplib_alloc_init_hwq(&ctx->mrw_tbl, &hwq_attr);
530 hwq_attr.depth = ctx->srqc_count;
531 hwq_attr.stride = BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE;
532 rc = bnxt_qplib_alloc_init_hwq(&ctx->srqc_tbl, &hwq_attr);
537 hwq_attr.depth = ctx->cq_count;
538 hwq_attr.stride = BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE;
539 rc = bnxt_qplib_alloc_init_hwq(&ctx->cq_tbl, &hwq_attr);
544 rc = bnxt_qplib_setup_tqm_rings(res, ctx);
548 ctx->tim_tbl.max_elements = ctx->qpc_count * 16;
549 hwq_attr.depth = ctx->qpc_count * 16;
551 rc = bnxt_qplib_alloc_init_hwq(&ctx->tim_tbl, &hwq_attr);
556 rc = bnxt_qplib_alloc_stats_ctx(res->pdev, res->cctx, &ctx->stats);
563 bnxt_qplib_free_ctx(res, ctx);
567 static void bnxt_qplib_free_sgid_tbl(struct bnxt_qplib_res *res,
568 struct bnxt_qplib_sgid_tbl *sgid_tbl)
570 kfree(sgid_tbl->tbl);
571 kfree(sgid_tbl->hw_id);
572 kfree(sgid_tbl->ctx);
573 kfree(sgid_tbl->vlan);
574 sgid_tbl->tbl = NULL;
575 sgid_tbl->hw_id = NULL;
576 sgid_tbl->ctx = NULL;
577 sgid_tbl->vlan = NULL;
579 sgid_tbl->active = 0;
582 static int bnxt_qplib_alloc_sgid_tbl(struct bnxt_qplib_res *res,
583 struct bnxt_qplib_sgid_tbl *sgid_tbl,
586 sgid_tbl->tbl = kcalloc(max, sizeof(*sgid_tbl->tbl), GFP_KERNEL);
590 sgid_tbl->hw_id = kcalloc(max, sizeof(u16), GFP_KERNEL);
591 if (!sgid_tbl->hw_id)
594 sgid_tbl->ctx = kcalloc(max, sizeof(void *), GFP_KERNEL);
598 sgid_tbl->vlan = kcalloc(max, sizeof(u8), GFP_KERNEL);
605 kfree(sgid_tbl->ctx);
606 sgid_tbl->ctx = NULL;
608 kfree(sgid_tbl->hw_id);
609 sgid_tbl->hw_id = NULL;
611 kfree(sgid_tbl->tbl);
612 sgid_tbl->tbl = NULL;
616 static void bnxt_qplib_cleanup_sgid_tbl(struct bnxt_qplib_res *res,
617 struct bnxt_qplib_sgid_tbl *sgid_tbl)
621 for (i = 0; i < sgid_tbl->max; i++) {
622 if (memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero,
623 sizeof(bnxt_qplib_gid_zero)))
624 bnxt_qplib_del_sgid(sgid_tbl, &sgid_tbl->tbl[i].gid,
625 sgid_tbl->tbl[i].vlan_id, true);
627 memset(sgid_tbl->tbl, 0, sizeof(*sgid_tbl->tbl) * sgid_tbl->max);
628 memset(sgid_tbl->hw_id, -1, sizeof(u16) * sgid_tbl->max);
629 memset(sgid_tbl->vlan, 0, sizeof(u8) * sgid_tbl->max);
630 sgid_tbl->active = 0;
633 static void bnxt_qplib_init_sgid_tbl(struct bnxt_qplib_sgid_tbl *sgid_tbl,
634 struct net_device *netdev)
638 for (i = 0; i < sgid_tbl->max; i++)
639 sgid_tbl->tbl[i].vlan_id = 0xffff;
641 memset(sgid_tbl->hw_id, -1, sizeof(u16) * sgid_tbl->max);
645 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, struct bnxt_qplib_pd *pd)
647 struct bnxt_qplib_pd_tbl *pdt = &res->pd_tbl;
651 mutex_lock(&res->pd_tbl_lock);
652 bit_num = find_first_bit(pdt->tbl, pdt->max);
653 if (bit_num == pdt->max) {
658 /* Found unused PD */
659 clear_bit(bit_num, pdt->tbl);
662 mutex_unlock(&res->pd_tbl_lock);
666 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
667 struct bnxt_qplib_pd_tbl *pdt,
668 struct bnxt_qplib_pd *pd)
672 mutex_lock(&res->pd_tbl_lock);
673 if (test_and_set_bit(pd->id, pdt->tbl)) {
674 dev_warn(&res->pdev->dev, "Freeing an unused PD? pdn = %d\n",
681 mutex_unlock(&res->pd_tbl_lock);
685 static void bnxt_qplib_free_pd_tbl(struct bnxt_qplib_pd_tbl *pdt)
692 static int bnxt_qplib_alloc_pd_tbl(struct bnxt_qplib_res *res,
693 struct bnxt_qplib_pd_tbl *pdt,
701 pdt->tbl = kmalloc(bytes, GFP_KERNEL);
706 memset((u8 *)pdt->tbl, 0xFF, bytes);
707 mutex_init(&res->pd_tbl_lock);
713 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res,
714 struct bnxt_qplib_dpi *dpi,
717 struct bnxt_qplib_dpi_tbl *dpit = &res->dpi_tbl;
718 struct bnxt_qplib_reg_desc *reg;
723 mutex_lock(&res->dpi_tbl_lock);
725 bit_num = find_first_bit(dpit->tbl, dpit->max);
726 if (bit_num == dpit->max) {
727 mutex_unlock(&res->dpi_tbl_lock);
731 /* Found unused DPI */
732 clear_bit(bit_num, dpit->tbl);
733 dpit->app_tbl[bit_num] = app;
736 dpi->dpi = bit_num + (reg->offset - dpit->ucreg.offset) / PAGE_SIZE;
738 umaddr = reg->bar_base + reg->offset + bit_num * PAGE_SIZE;
742 case BNXT_QPLIB_DPI_TYPE_KERNEL:
743 /* privileged dbr was already mapped just initialize it. */
744 dpi->umdbr = dpit->ucreg.bar_base +
745 dpit->ucreg.offset + bit_num * PAGE_SIZE;
746 dpi->dbr = dpit->priv_db;
749 case BNXT_QPLIB_DPI_TYPE_WC:
750 dpi->dbr = ioremap_wc(umaddr, PAGE_SIZE);
753 dpi->dbr = ioremap(umaddr, PAGE_SIZE);
758 mutex_unlock(&res->dpi_tbl_lock);
763 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
764 struct bnxt_qplib_dpi *dpi)
766 struct bnxt_qplib_dpi_tbl *dpit = &res->dpi_tbl;
768 mutex_lock(&res->dpi_tbl_lock);
769 if (dpi->dpi && dpi->type != BNXT_QPLIB_DPI_TYPE_KERNEL)
770 pci_iounmap(res->pdev, dpi->dbr);
772 if (test_and_set_bit(dpi->bit, dpit->tbl)) {
773 dev_warn(&res->pdev->dev,
774 "Freeing an unused DPI? dpi = %d, bit = %d\n",
776 mutex_unlock(&res->dpi_tbl_lock);
780 dpit->app_tbl[dpi->bit] = NULL;
781 memset(dpi, 0, sizeof(*dpi));
782 mutex_unlock(&res->dpi_tbl_lock);
786 static void bnxt_qplib_free_dpi_tbl(struct bnxt_qplib_res *res,
787 struct bnxt_qplib_dpi_tbl *dpit)
790 kfree(dpit->app_tbl);
792 dpit->app_tbl = NULL;
796 static int bnxt_qplib_alloc_dpi_tbl(struct bnxt_qplib_res *res,
797 struct bnxt_qplib_dev_attr *dev_attr)
799 struct bnxt_qplib_dpi_tbl *dpit;
800 struct bnxt_qplib_reg_desc *reg;
801 unsigned long bar_len;
805 dpit = &res->dpi_tbl;
808 if (!bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) {
809 /* Offest should come from L2 driver */
810 dbr_offset = dev_attr->l2_db_size;
811 dpit->ucreg.offset = dbr_offset;
812 dpit->wcreg.offset = dbr_offset;
815 bar_len = pci_resource_len(res->pdev, reg->bar_id);
816 dpit->max = (bar_len - reg->offset) / PAGE_SIZE;
817 if (dev_attr->max_dpi)
818 dpit->max = min_t(u32, dpit->max, dev_attr->max_dpi);
820 dpit->app_tbl = kcalloc(dpit->max, sizeof(void *), GFP_KERNEL);
824 bytes = dpit->max >> 3;
828 dpit->tbl = kmalloc(bytes, GFP_KERNEL);
830 kfree(dpit->app_tbl);
831 dpit->app_tbl = NULL;
835 memset((u8 *)dpit->tbl, 0xFF, bytes);
836 mutex_init(&res->dpi_tbl_lock);
837 dpit->priv_db = dpit->ucreg.bar_reg + dpit->ucreg.offset;
844 static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev,
845 struct bnxt_qplib_stats *stats)
848 dma_free_coherent(&pdev->dev, stats->size,
849 stats->dma, stats->dma_map);
851 memset(stats, 0, sizeof(*stats));
855 static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev,
856 struct bnxt_qplib_chip_ctx *cctx,
857 struct bnxt_qplib_stats *stats)
859 memset(stats, 0, sizeof(*stats));
861 stats->size = cctx->hw_stats_size;
862 stats->dma = dma_alloc_coherent(&pdev->dev, stats->size,
863 &stats->dma_map, GFP_KERNEL);
865 dev_err(&pdev->dev, "Stats DMA allocation failed\n");
871 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res)
873 bnxt_qplib_cleanup_sgid_tbl(res, &res->sgid_tbl);
876 int bnxt_qplib_init_res(struct bnxt_qplib_res *res)
878 bnxt_qplib_init_sgid_tbl(&res->sgid_tbl, res->netdev);
883 void bnxt_qplib_free_res(struct bnxt_qplib_res *res)
885 bnxt_qplib_free_sgid_tbl(res, &res->sgid_tbl);
886 bnxt_qplib_free_pd_tbl(&res->pd_tbl);
887 bnxt_qplib_free_dpi_tbl(res, &res->dpi_tbl);
890 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
891 struct net_device *netdev,
892 struct bnxt_qplib_dev_attr *dev_attr)
897 res->netdev = netdev;
899 rc = bnxt_qplib_alloc_sgid_tbl(res, &res->sgid_tbl, dev_attr->max_sgid);
903 rc = bnxt_qplib_alloc_pd_tbl(res, &res->pd_tbl, dev_attr->max_pd);
907 rc = bnxt_qplib_alloc_dpi_tbl(res, dev_attr);
913 bnxt_qplib_free_res(res);
917 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res)
919 struct bnxt_qplib_reg_desc *reg;
921 reg = &res->dpi_tbl.ucreg;
923 pci_iounmap(res->pdev, reg->bar_reg);
930 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res)
932 struct bnxt_qplib_reg_desc *ucreg;
933 struct bnxt_qplib_reg_desc *wcreg;
935 wcreg = &res->dpi_tbl.wcreg;
936 wcreg->bar_id = RCFW_DBR_PCI_BAR_REGION;
937 wcreg->bar_base = pci_resource_start(res->pdev, wcreg->bar_id);
939 ucreg = &res->dpi_tbl.ucreg;
940 ucreg->bar_id = RCFW_DBR_PCI_BAR_REGION;
941 ucreg->bar_base = pci_resource_start(res->pdev, ucreg->bar_id);
942 ucreg->len = ucreg->offset + PAGE_SIZE;
943 if (!ucreg->len || ((ucreg->len & (PAGE_SIZE - 1)) != 0)) {
944 dev_err(&res->pdev->dev, "QPLIB: invalid dbr length %d",
948 ucreg->bar_reg = ioremap(ucreg->bar_base, ucreg->len);
949 if (!ucreg->bar_reg) {
950 dev_err(&res->pdev->dev, "privileged dpi map failed!");
957 int bnxt_qplib_determine_atomics(struct pci_dev *dev)
962 comp = pci_enable_atomic_ops_to_root(dev,
963 PCI_EXP_DEVCAP2_ATOMIC_COMP32);
966 comp = pci_enable_atomic_ops_to_root(dev,
967 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
970 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2);
971 return !(ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);