drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RDMA Controller HW interface
  37  */
  38
  39 #define dev_fmt(fmt) "QPLIB: " fmt
  40
  41 #include <linux/interrupt.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/pci.h>
  44 #include <linux/prefetch.h>
  45 #include <linux/delay.h>
  46
  47 #include "roce_hsi.h"
  48 #include "qplib_res.h"
  49 #include "qplib_rcfw.h"
  50 #include "qplib_sp.h"
  51 #include "qplib_fp.h"
  52
  53 static void bnxt_qplib_service_creq(struct tasklet_struct *t);
  54
  55 /* Hardware communication channel */
  56 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
  57 {
  58         struct bnxt_qplib_cmdq_ctx *cmdq;
  59         u16 cbit;
  60         int rc;
  61
  62         cmdq = &rcfw->cmdq;
  63         cbit = cookie % rcfw->cmdq_depth;
  64         rc = wait_event_timeout(cmdq->waitq,
  65                                 !test_bit(cbit, cmdq->cmdq_bitmap),
  66                                 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
  67         return rc ? 0 : -ETIMEDOUT;
  68 };
  69
  70 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
  71 {
  72         u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
  73         struct bnxt_qplib_cmdq_ctx *cmdq;
  74         u16 cbit;
  75
  76         cmdq = &rcfw->cmdq;
  77         cbit = cookie % rcfw->cmdq_depth;
  78         if (!test_bit(cbit, cmdq->cmdq_bitmap))
  79                 goto done;
  80         do {
  81                 mdelay(1); /* 1m sec */
  82                 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
  83         } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count);
  84 done:
  85         return count ? 0 : -ETIMEDOUT;
  86 };
  87
  88 static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
  89                           struct creq_base *resp, void *sb, u8 is_block)
  90 {
  91         struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
  92         struct bnxt_qplib_hwq *hwq = &cmdq->hwq;
  93         struct bnxt_qplib_crsqe *crsqe;
  94         struct bnxt_qplib_cmdqe *cmdqe;
  95         u32 sw_prod, cmdq_prod;
  96         struct pci_dev *pdev;
  97         unsigned long flags;
  98         u32 size, opcode;
  99         u16 cookie, cbit;
 100         u8 *preq;
 101
 102         pdev = rcfw->pdev;
 103
 104         opcode = req->opcode;
 105         if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
 106             (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
 107              opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
 108              opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
 109                 dev_err(&pdev->dev,
 110                         "RCFW not initialized, reject opcode 0x%x\n", opcode);
 111                 return -EINVAL;
 112         }
 113
 114         if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
 115             opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
 116                 dev_err(&pdev->dev, "RCFW already initialized!\n");
 117                 return -EINVAL;
 118         }
 119
 120         if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags))
 121                 return -ETIMEDOUT;
 122
 123         /* Cmdq are in 16-byte units, each request can consume 1 or more
 124          * cmdqe
 125          */
 126         spin_lock_irqsave(&hwq->lock, flags);
 127         if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) {
 128                 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n");
 129                 spin_unlock_irqrestore(&hwq->lock, flags);
 130                 return -EAGAIN;
 131         }
 132
 133
 134         cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
 135         cbit = cookie % rcfw->cmdq_depth;
 136         if (is_block)
 137                 cookie |= RCFW_CMD_IS_BLOCKING;
 138
 139         set_bit(cbit, cmdq->cmdq_bitmap);
 140         req->cookie = cpu_to_le16(cookie);
 141         crsqe = &rcfw->crsqe_tbl[cbit];
 142         if (crsqe->resp) {
 143                 spin_unlock_irqrestore(&hwq->lock, flags);
 144                 return -EBUSY;
 145         }
 146
 147         size = req->cmd_size;
 148         /* change the cmd_size to the number of 16byte cmdq unit.
 149          * req->cmd_size is modified here
 150          */
 151         bnxt_qplib_set_cmd_slots(req);
 152
 153         memset(resp, 0, sizeof(*resp));
 154         crsqe->resp = (struct creq_qp_event *)resp;
 155         crsqe->resp->cookie = req->cookie;
 156         crsqe->req_size = req->cmd_size;
 157         if (req->resp_size && sb) {
 158                 struct bnxt_qplib_rcfw_sbuf *sbuf = sb;
 159
 160                 req->resp_addr = cpu_to_le64(sbuf->dma_addr);
 161                 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) /
 162                                   BNXT_QPLIB_CMDQE_UNITS;
 163         }
 164
 165         preq = (u8 *)req;
 166         do {
 167                 /* Locate the next cmdq slot */
 168                 sw_prod = HWQ_CMP(hwq->prod, hwq);
 169                 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
 170                 if (!cmdqe) {
 171                         dev_err(&pdev->dev,
 172                                 "RCFW request failed with no cmdqe!\n");
 173                         goto done;
 174                 }
 175                 /* Copy a segment of the req cmd to the cmdq */
 176                 memset(cmdqe, 0, sizeof(*cmdqe));
 177                 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe)));
 178                 preq += min_t(u32, size, sizeof(*cmdqe));
 179                 size -= min_t(u32, size, sizeof(*cmdqe));
 180                 hwq->prod++;
 181         } while (size > 0);
 182         cmdq->seq_num++;
 183
 184         cmdq_prod = hwq->prod;
 185         if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) {
 186                 /* The very first doorbell write
 187                  * is required to set this flag
 188                  * which prompts the FW to reset
 189                  * its internal pointers
 190                  */
 191                 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
 192                 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
 193         }
 194
 195         /* ring CMDQ DB */
 196         wmb();
 197         writel(cmdq_prod, cmdq->cmdq_mbox.prod);
 198         writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
 199 done:
 200         spin_unlock_irqrestore(&hwq->lock, flags);
 201         /* Return the CREQ response pointer */
 202         return 0;
 203 }
 204
 205 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
 206                                  struct cmdq_base *req,
 207                                  struct creq_base *resp,
 208                                  void *sb, u8 is_block)
 209 {
 210         struct creq_qp_event *evnt = (struct creq_qp_event *)resp;
 211         u16 cookie;
 212         u8 opcode, retry_cnt = 0xFF;
 213         int rc = 0;
 214
 215         /* Prevent posting if f/w is not in a state to process */
 216         if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags))
 217                 return 0;
 218
 219         do {
 220                 opcode = req->opcode;
 221                 rc = __send_message(rcfw, req, resp, sb, is_block);
 222                 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE;
 223                 if (!rc)
 224                         break;
 225
 226                 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) {
 227                         /* send failed */
 228                         dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n",
 229                                 cookie, opcode);
 230                         return rc;
 231                 }
 232                 is_block ? mdelay(1) : usleep_range(500, 1000);
 233
 234         } while (retry_cnt--);
 235
 236         if (is_block)
 237                 rc = __block_for_resp(rcfw, cookie);
 238         else
 239                 rc = __wait_for_resp(rcfw, cookie);
 240         if (rc) {
 241                 /* timed out */
 242                 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n",
 243                         cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
 244                 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags);
 245                 return rc;
 246         }
 247
 248         if (evnt->status) {
 249                 /* failed with status */
 250                 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
 251                         cookie, opcode, evnt->status);
 252                 rc = -EFAULT;
 253         }
 254
 255         return rc;
 256 }
 257 /* Completions */
 258 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
 259                                          struct creq_func_event *func_event)
 260 {
 261         int rc;
 262
 263         switch (func_event->event) {
 264         case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
 265                 break;
 266         case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
 267                 break;
 268         case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
 269                 break;
 270         case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
 271                 break;
 272         case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
 273                 break;
 274         case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
 275                 break;
 276         case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
 277                 break;
 278         case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
 279                 /* SRQ ctx error, call srq_handler??
 280                  * But there's no SRQ handle!
 281                  */
 282                 break;
 283         case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
 284                 break;
 285         case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
 286                 break;
 287         case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
 288                 break;
 289         case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
 290                 break;
 291         case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         }
 296
 297         rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL);
 298         return rc;
 299 }
 300
 301 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
 302                                        struct creq_qp_event *qp_event)
 303 {
 304         struct creq_qp_error_notification *err_event;
 305         struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq;
 306         struct bnxt_qplib_crsqe *crsqe;
 307         struct bnxt_qplib_qp *qp;
 308         u16 cbit, blocked = 0;
 309         struct pci_dev *pdev;
 310         unsigned long flags;
 311         __le16  mcookie;
 312         u16 cookie;
 313         int rc = 0;
 314         u32 qp_id, tbl_indx;
 315
 316         pdev = rcfw->pdev;
 317         switch (qp_event->event) {
 318         case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
 319                 err_event = (struct creq_qp_error_notification *)qp_event;
 320                 qp_id = le32_to_cpu(err_event->xid);
 321                 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);
 322                 qp = rcfw->qp_tbl[tbl_indx].qp_handle;
 323                 dev_dbg(&pdev->dev, "Received QP error notification\n");
 324                 dev_dbg(&pdev->dev,
 325                         "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
 326                         qp_id, err_event->req_err_state_reason,
 327                         err_event->res_err_state_reason);
 328                 if (!qp)
 329                         break;
 330                 bnxt_qplib_mark_qp_error(qp);
 331                 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);
 332                 break;
 333         default:
 334                 /*
 335                  * Command Response
 336                  * cmdq->lock needs to be acquired to synchronie
 337                  * the command send and completion reaping. This function
 338                  * is always called with creq->lock held. Using
 339                  * the nested variant of spin_lock.
 340                  *
 341                  */
 342
 343                 spin_lock_irqsave_nested(&hwq->lock, flags,
 344                                          SINGLE_DEPTH_NESTING);
 345                 cookie = le16_to_cpu(qp_event->cookie);
 346                 mcookie = qp_event->cookie;
 347                 blocked = cookie & RCFW_CMD_IS_BLOCKING;
 348                 cookie &= RCFW_MAX_COOKIE_VALUE;
 349                 cbit = cookie % rcfw->cmdq_depth;
 350                 crsqe = &rcfw->crsqe_tbl[cbit];
 351                 if (crsqe->resp &&
 352                     crsqe->resp->cookie  == mcookie) {
 353                         memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
 354                         crsqe->resp = NULL;
 355                 } else {
 356                         if (crsqe->resp && crsqe->resp->cookie)
 357                                 dev_err(&pdev->dev,
 358                                         "CMD %s cookie sent=%#x, recd=%#x\n",
 359                                         crsqe->resp ? "mismatch" : "collision",
 360                                         crsqe->resp ? crsqe->resp->cookie : 0,
 361                                         mcookie);
 362                 }
 363                 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap))
 364                         dev_warn(&pdev->dev,
 365                                  "CMD bit %d was not requested\n", cbit);
 366                 hwq->cons += crsqe->req_size;
 367                 crsqe->req_size = 0;
 368
 369                 if (!blocked)
 370                         wake_up(&rcfw->cmdq.waitq);
 371                 spin_unlock_irqrestore(&hwq->lock, flags);
 372         }
 373         return rc;
 374 }
 375
 376 /* SP - CREQ Completion handlers */
 377 static void bnxt_qplib_service_creq(struct tasklet_struct *t)
 378 {
 379         struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet);
 380         struct bnxt_qplib_creq_ctx *creq = &rcfw->creq;
 381         u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
 382         struct bnxt_qplib_hwq *hwq = &creq->hwq;
 383         struct creq_base *creqe;
 384         u32 sw_cons, raw_cons;
 385         unsigned long flags;
 386
 387         /* Service the CREQ until budget is over */
 388         spin_lock_irqsave(&hwq->lock, flags);
 389         raw_cons = hwq->cons;
 390         while (budget > 0) {
 391                 sw_cons = HWQ_CMP(raw_cons, hwq);
 392                 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);
 393                 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements))
 394                         break;
 395                 /* The valid test of the entry must be done first before
 396                  * reading any further.
 397                  */
 398                 dma_rmb();
 399
 400                 type = creqe->type & CREQ_BASE_TYPE_MASK;
 401                 switch (type) {
 402                 case CREQ_BASE_TYPE_QP_EVENT:
 403                         bnxt_qplib_process_qp_event
 404                                 (rcfw, (struct creq_qp_event *)creqe);
 405                         creq->stats.creq_qp_event_processed++;
 406                         break;
 407                 case CREQ_BASE_TYPE_FUNC_EVENT:
 408                         if (!bnxt_qplib_process_func_event
 409                             (rcfw, (struct creq_func_event *)creqe))
 410                                 creq->stats.creq_func_event_processed++;
 411                         else
 412                                 dev_warn(&rcfw->pdev->dev,
 413                                          "aeqe:%#x Not handled\n", type);
 414                         break;
 415                 default:
 416                         if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
 417                                 dev_warn(&rcfw->pdev->dev,
 418                                          "creqe with event 0x%x not handled\n",
 419                                          type);
 420                         break;
 421                 }
 422                 raw_cons++;
 423                 budget--;
 424         }
 425
 426         if (hwq->cons != raw_cons) {
 427                 hwq->cons = raw_cons;
 428                 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,
 429                                       rcfw->res->cctx, true);
 430         }
 431         spin_unlock_irqrestore(&hwq->lock, flags);
 432 }
 433
 434 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
 435 {
 436         struct bnxt_qplib_rcfw *rcfw = dev_instance;
 437         struct bnxt_qplib_creq_ctx *creq;
 438         struct bnxt_qplib_hwq *hwq;
 439         u32 sw_cons;
 440
 441         creq = &rcfw->creq;
 442         hwq = &creq->hwq;
 443         /* Prefetch the CREQ element */
 444         sw_cons = HWQ_CMP(hwq->cons, hwq);
 445         prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
 446
 447         tasklet_schedule(&creq->creq_tasklet);
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 /* RCFW */
 453 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
 454 {
 455         struct cmdq_deinitialize_fw req;
 456         struct creq_deinitialize_fw_resp resp;
 457         u16 cmd_flags = 0;
 458         int rc;
 459
 460         RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);
 461         rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
 462                                           NULL, 0);
 463         if (rc)
 464                 return rc;
 465
 466         clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
 467         return 0;
 468 }
 469
 470 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
 471                          struct bnxt_qplib_ctx *ctx, int is_virtfn)
 472 {
 473         struct creq_initialize_fw_resp resp;
 474         struct cmdq_initialize_fw req;
 475         u16 cmd_flags = 0;
 476         u8 pgsz, lvl;
 477         int rc;
 478
 479         RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
 480         /* Supply (log-base-2-of-host-page-size - base-page-shift)
 481          * to bono to adjust the doorbell page sizes.
 482          */
 483         req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
 484                                            RCFW_DBR_BASE_PAGE_SHIFT);
 485         /*
 486          * Gen P5 devices doesn't require this allocation
 487          * as the L2 driver does the same for RoCE also.
 488          * Also, VFs need not setup the HW context area, PF
 489          * shall setup this area for VF. Skipping the
 490          * HW programming
 491          */
 492         if (is_virtfn)
 493                 goto skip_ctx_setup;
 494         if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
 495                 goto config_vf_res;
 496
 497         lvl = ctx->qpc_tbl.level;
 498         pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl);
 499         req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 500                                    lvl;
 501         lvl = ctx->mrw_tbl.level;
 502         pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl);
 503         req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 504                                    lvl;
 505         lvl = ctx->srqc_tbl.level;
 506         pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl);
 507         req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 508                                    lvl;
 509         lvl = ctx->cq_tbl.level;
 510         pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl);
 511         req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 512                                  lvl;
 513         lvl = ctx->tim_tbl.level;
 514         pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl);
 515         req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 516                                    lvl;
 517         lvl = ctx->tqm_ctx.pde.level;
 518         pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde);
 519         req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
 520                                    lvl;
 521         req.qpc_page_dir =
 522                 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 523         req.mrw_page_dir =
 524                 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 525         req.srq_page_dir =
 526                 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 527         req.cq_page_dir =
 528                 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 529         req.tim_page_dir =
 530                 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
 531         req.tqm_page_dir =
 532                 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]);
 533
 534         req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
 535         req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
 536         req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
 537         req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
 538
 539 config_vf_res:
 540         req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
 541         req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
 542         req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
 543         req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
 544         req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
 545
 546 skip_ctx_setup:
 547         req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
 548         rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
 549                                           NULL, 0);
 550         if (rc)
 551                 return rc;
 552         set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
 553         return 0;
 554 }
 555
 556 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
 557 {
 558         kfree(rcfw->cmdq.cmdq_bitmap);
 559         kfree(rcfw->qp_tbl);
 560         kfree(rcfw->crsqe_tbl);
 561         bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
 562         bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq);
 563         rcfw->pdev = NULL;
 564 }
 565
 566 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
 567                                   struct bnxt_qplib_rcfw *rcfw,
 568                                   struct bnxt_qplib_ctx *ctx,
 569                                   int qp_tbl_sz)
 570 {
 571         struct bnxt_qplib_hwq_attr hwq_attr = {};
 572         struct bnxt_qplib_sg_info sginfo = {};
 573         struct bnxt_qplib_cmdq_ctx *cmdq;
 574         struct bnxt_qplib_creq_ctx *creq;
 575         u32 bmap_size = 0;
 576
 577         rcfw->pdev = res->pdev;
 578         cmdq = &rcfw->cmdq;
 579         creq = &rcfw->creq;
 580         rcfw->res = res;
 581
 582         sginfo.pgsize = PAGE_SIZE;
 583         sginfo.pgshft = PAGE_SHIFT;
 584
 585         hwq_attr.sginfo = &sginfo;
 586         hwq_attr.res = rcfw->res;
 587         hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT;
 588         hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS;
 589         hwq_attr.type = bnxt_qplib_get_hwq_type(res);
 590
 591         if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
 592                 dev_err(&rcfw->pdev->dev,
 593                         "HW channel CREQ allocation failed\n");
 594                 goto fail;
 595         }
 596         if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK)
 597                 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256;
 598         else
 599                 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192;
 600
 601         sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth);
 602         hwq_attr.depth = rcfw->cmdq_depth;
 603         hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS;
 604         hwq_attr.type = HWQ_TYPE_CTX;
 605         if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
 606                 dev_err(&rcfw->pdev->dev,
 607                         "HW channel CMDQ allocation failed\n");
 608                 goto fail;
 609         }
 610
 611         rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
 612                                   sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
 613         if (!rcfw->crsqe_tbl)
 614                 goto fail;
 615
 616         bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long);
 617         cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
 618         if (!cmdq->cmdq_bitmap)
 619                 goto fail;
 620
 621         cmdq->bmap_size = bmap_size;
 622
 623         /* Allocate one extra to hold the QP1 entries */
 624         rcfw->qp_tbl_size = qp_tbl_sz + 1;
 625         rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node),
 626                                GFP_KERNEL);
 627         if (!rcfw->qp_tbl)
 628                 goto fail;
 629
 630         return 0;
 631
 632 fail:
 633         bnxt_qplib_free_rcfw_channel(rcfw);
 634         return -ENOMEM;
 635 }
 636
 637 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
 638 {
 639         struct bnxt_qplib_creq_ctx *creq;
 640
 641         creq = &rcfw->creq;
 642         tasklet_disable(&creq->creq_tasklet);
 643         /* Mask h/w interrupts */
 644         bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false);
 645         /* Sync with last running IRQ-handler */
 646         synchronize_irq(creq->msix_vec);
 647         if (kill)
 648                 tasklet_kill(&creq->creq_tasklet);
 649
 650         if (creq->requested) {
 651                 free_irq(creq->msix_vec, rcfw);
 652                 creq->requested = false;
 653         }
 654 }
 655
 656 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
 657 {
 658         struct bnxt_qplib_creq_ctx *creq;
 659         struct bnxt_qplib_cmdq_ctx *cmdq;
 660         unsigned long indx;
 661
 662         creq = &rcfw->creq;
 663         cmdq = &rcfw->cmdq;
 664         /* Make sure the HW channel is stopped! */
 665         bnxt_qplib_rcfw_stop_irq(rcfw, true);
 666
 667         iounmap(cmdq->cmdq_mbox.reg.bar_reg);
 668         iounmap(creq->creq_db.reg.bar_reg);
 669
 670         indx = find_first_bit(cmdq->cmdq_bitmap, cmdq->bmap_size);
 671         if (indx != cmdq->bmap_size)
 672                 dev_err(&rcfw->pdev->dev,
 673                         "disabling RCFW with pending cmd-bit %lx\n", indx);
 674
 675         cmdq->cmdq_mbox.reg.bar_reg = NULL;
 676         creq->creq_db.reg.bar_reg = NULL;
 677         creq->aeq_handler = NULL;
 678         creq->msix_vec = 0;
 679 }
 680
 681 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
 682                               bool need_init)
 683 {
 684         struct bnxt_qplib_creq_ctx *creq;
 685         int rc;
 686
 687         creq = &rcfw->creq;
 688
 689         if (creq->requested)
 690                 return -EFAULT;
 691
 692         creq->msix_vec = msix_vector;
 693         if (need_init)
 694                 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq);
 695         else
 696                 tasklet_enable(&creq->creq_tasklet);
 697         rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0,
 698                          "bnxt_qplib_creq", rcfw);
 699         if (rc)
 700                 return rc;
 701         creq->requested = true;
 702
 703         bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true);
 704
 705         return 0;
 706 }
 707
 708 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf)
 709 {
 710         struct bnxt_qplib_cmdq_mbox *mbox;
 711         resource_size_t bar_reg;
 712         struct pci_dev *pdev;
 713         u16 prod_offt;
 714         int rc = 0;
 715
 716         pdev = rcfw->pdev;
 717         mbox = &rcfw->cmdq.cmdq_mbox;
 718
 719         mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;
 720         mbox->reg.len = RCFW_COMM_SIZE;
 721         mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);
 722         if (!mbox->reg.bar_base) {
 723                 dev_err(&pdev->dev,
 724                         "QPLIB: CMDQ BAR region %d resc start is 0!\n",
 725                         mbox->reg.bar_id);
 726                 return -ENOMEM;
 727         }
 728
 729         bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;
 730         mbox->reg.len = RCFW_COMM_SIZE;
 731         mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);
 732         if (!mbox->reg.bar_reg) {
 733                 dev_err(&pdev->dev,
 734                         "QPLIB: CMDQ BAR region %d mapping failed\n",
 735                         mbox->reg.bar_id);
 736                 return -ENOMEM;
 737         }
 738
 739         prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET :
 740                             RCFW_PF_COMM_PROD_OFFSET;
 741         mbox->prod = (void  __iomem *)(mbox->reg.bar_reg + prod_offt);
 742         mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET);
 743         return rc;
 744 }
 745
 746 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)
 747 {
 748         struct bnxt_qplib_creq_db *creq_db;
 749         resource_size_t bar_reg;
 750         struct pci_dev *pdev;
 751
 752         pdev = rcfw->pdev;
 753         creq_db = &rcfw->creq.creq_db;
 754
 755         creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;
 756         creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id);
 757         if (!creq_db->reg.bar_id)
 758                 dev_err(&pdev->dev,
 759                         "QPLIB: CREQ BAR region %d resc start is 0!",
 760                         creq_db->reg.bar_id);
 761
 762         bar_reg = creq_db->reg.bar_base + reg_offt;
 763         /* Unconditionally map 8 bytes to support 57500 series */
 764         creq_db->reg.len = 8;
 765         creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len);
 766         if (!creq_db->reg.bar_reg) {
 767                 dev_err(&pdev->dev,
 768                         "QPLIB: CREQ BAR region %d mapping failed",
 769                         creq_db->reg.bar_id);
 770                 return -ENOMEM;
 771         }
 772         creq_db->dbinfo.db = creq_db->reg.bar_reg;
 773         creq_db->dbinfo.hwq = &rcfw->creq.hwq;
 774         creq_db->dbinfo.xid = rcfw->creq.ring_id;
 775         return 0;
 776 }
 777
 778 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw)
 779 {
 780         struct bnxt_qplib_cmdq_ctx *cmdq;
 781         struct bnxt_qplib_creq_ctx *creq;
 782         struct bnxt_qplib_cmdq_mbox *mbox;
 783         struct cmdq_init init = {0};
 784
 785         cmdq = &rcfw->cmdq;
 786         creq = &rcfw->creq;
 787         mbox = &cmdq->cmdq_mbox;
 788
 789         init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
 790         init.cmdq_size_cmdq_lvl =
 791                         cpu_to_le16(((rcfw->cmdq_depth <<
 792                                       CMDQ_INIT_CMDQ_SIZE_SFT) &
 793                                     CMDQ_INIT_CMDQ_SIZE_MASK) |
 794                                     ((cmdq->hwq.level <<
 795                                       CMDQ_INIT_CMDQ_LVL_SFT) &
 796                                     CMDQ_INIT_CMDQ_LVL_MASK));
 797         init.creq_ring_id = cpu_to_le16(creq->ring_id);
 798         /* Write to the Bono mailbox register */
 799         __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);
 800 }
 801
 802 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
 803                                    int msix_vector,
 804                                    int cp_bar_reg_off, int virt_fn,
 805                                    aeq_handler_t aeq_handler)
 806 {
 807         struct bnxt_qplib_cmdq_ctx *cmdq;
 808         struct bnxt_qplib_creq_ctx *creq;
 809         int rc;
 810
 811         cmdq = &rcfw->cmdq;
 812         creq = &rcfw->creq;
 813
 814         /* Clear to defaults */
 815
 816         cmdq->seq_num = 0;
 817         set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
 818         init_waitqueue_head(&cmdq->waitq);
 819
 820         creq->stats.creq_qp_event_processed = 0;
 821         creq->stats.creq_func_event_processed = 0;
 822         creq->aeq_handler = aeq_handler;
 823
 824         rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn);
 825         if (rc)
 826                 return rc;
 827
 828         rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off);
 829         if (rc)
 830                 return rc;
 831
 832         rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
 833         if (rc) {
 834                 dev_err(&rcfw->pdev->dev,
 835                         "Failed to request IRQ for CREQ rc = 0x%x\n", rc);
 836                 bnxt_qplib_disable_rcfw_channel(rcfw);
 837                 return rc;
 838         }
 839
 840         bnxt_qplib_start_rcfw(rcfw);
 841
 842         return 0;
 843 }
 844
 845 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
 846                 struct bnxt_qplib_rcfw *rcfw,
 847                 u32 size)
 848 {
 849         struct bnxt_qplib_rcfw_sbuf *sbuf;
 850
 851         sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC);
 852         if (!sbuf)
 853                 return NULL;
 854
 855         sbuf->size = size;
 856         sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size,
 857                                       &sbuf->dma_addr, GFP_ATOMIC);
 858         if (!sbuf->sb)
 859                 goto bail;
 860
 861         return sbuf;
 862 bail:
 863         kfree(sbuf);
 864         return NULL;
 865 }
 866
 867 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
 868                                struct bnxt_qplib_rcfw_sbuf *sbuf)
 869 {
 870         if (sbuf->sb)
 871                 dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
 872                                   sbuf->sb, sbuf->dma_addr);
 873         kfree(sbuf);
 874 }