drivers/iio/dac/stm32-dac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file is part of STM32 DAC driver
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Authors: Amelie Delaunay <amelie.delaunay@st.com>
   7  *          Fabrice Gasnier <fabrice.gasnier@st.com>
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/delay.h>
  12 #include <linux/iio/iio.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17
  18 #include "stm32-dac-core.h"
  19
  20 #define STM32_DAC_CHANNEL_1             1
  21 #define STM32_DAC_CHANNEL_2             2
  22 #define STM32_DAC_IS_CHAN_1(ch)         ((ch) & STM32_DAC_CHANNEL_1)
  23
  24 #define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000
  25
  26 /**
  27  * struct stm32_dac - private data of DAC driver
  28  * @common:             reference to DAC common data
  29  * @lock:               lock to protect against potential races when reading
  30  *                      and update CR, to keep it in sync with pm_runtime
  31  */
  32 struct stm32_dac {
  33         struct stm32_dac_common *common;
  34         struct mutex            lock;
  35 };
  36
  37 static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
  38 {
  39         struct stm32_dac *dac = iio_priv(indio_dev);
  40         u32 en, val;
  41         int ret;
  42
  43         ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
  44         if (ret < 0)
  45                 return ret;
  46         if (STM32_DAC_IS_CHAN_1(channel))
  47                 en = FIELD_GET(STM32_DAC_CR_EN1, val);
  48         else
  49                 en = FIELD_GET(STM32_DAC_CR_EN2, val);
  50
  51         return !!en;
  52 }
  53
  54 static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
  55                                       bool enable)
  56 {
  57         struct stm32_dac *dac = iio_priv(indio_dev);
  58         struct device *dev = indio_dev->dev.parent;
  59         u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
  60         u32 en = enable ? msk : 0;
  61         int ret;
  62
  63         /* already enabled / disabled ? */
  64         mutex_lock(&dac->lock);
  65         ret = stm32_dac_is_enabled(indio_dev, ch);
  66         if (ret < 0 || enable == !!ret) {
  67                 mutex_unlock(&dac->lock);
  68                 return ret < 0 ? ret : 0;
  69         }
  70
  71         if (enable) {
  72                 ret = pm_runtime_resume_and_get(dev);
  73                 if (ret < 0) {
  74                         mutex_unlock(&dac->lock);
  75                         return ret;
  76                 }
  77         }
  78
  79         ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
  80         mutex_unlock(&dac->lock);
  81         if (ret < 0) {
  82                 dev_err(&indio_dev->dev, "%s failed\n", en ?
  83                         "Enable" : "Disable");
  84                 goto err_put_pm;
  85         }
  86
  87         /*
  88          * When HFSEL is set, it is not allowed to write the DHRx register
  89          * during 8 clock cycles after the ENx bit is set. It is not allowed
  90          * to make software/hardware trigger during this period either.
  91          */
  92         if (en && dac->common->hfsel)
  93                 udelay(1);
  94
  95         if (!enable) {
  96                 pm_runtime_mark_last_busy(dev);
  97                 pm_runtime_put_autosuspend(dev);
  98         }
  99
 100         return 0;
 101
 102 err_put_pm:
 103         if (enable) {
 104                 pm_runtime_mark_last_busy(dev);
 105                 pm_runtime_put_autosuspend(dev);
 106         }
 107
 108         return ret;
 109 }
 110
 111 static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
 112 {
 113         int ret;
 114
 115         if (STM32_DAC_IS_CHAN_1(channel))
 116                 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
 117         else
 118                 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
 119
 120         return ret ? ret : IIO_VAL_INT;
 121 }
 122
 123 static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
 124 {
 125         int ret;
 126
 127         if (STM32_DAC_IS_CHAN_1(channel))
 128                 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
 129         else
 130                 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
 131
 132         return ret;
 133 }
 134
 135 static int stm32_dac_read_raw(struct iio_dev *indio_dev,
 136                               struct iio_chan_spec const *chan,
 137                               int *val, int *val2, long mask)
 138 {
 139         struct stm32_dac *dac = iio_priv(indio_dev);
 140
 141         switch (mask) {
 142         case IIO_CHAN_INFO_RAW:
 143                 return stm32_dac_get_value(dac, chan->channel, val);
 144         case IIO_CHAN_INFO_SCALE:
 145                 *val = dac->common->vref_mv;
 146                 *val2 = chan->scan_type.realbits;
 147                 return IIO_VAL_FRACTIONAL_LOG2;
 148         default:
 149                 return -EINVAL;
 150         }
 151 }
 152
 153 static int stm32_dac_write_raw(struct iio_dev *indio_dev,
 154                                struct iio_chan_spec const *chan,
 155                                int val, int val2, long mask)
 156 {
 157         struct stm32_dac *dac = iio_priv(indio_dev);
 158
 159         switch (mask) {
 160         case IIO_CHAN_INFO_RAW:
 161                 return stm32_dac_set_value(dac, chan->channel, val);
 162         default:
 163                 return -EINVAL;
 164         }
 165 }
 166
 167 static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
 168                                         unsigned reg, unsigned writeval,
 169                                         unsigned *readval)
 170 {
 171         struct stm32_dac *dac = iio_priv(indio_dev);
 172
 173         if (!readval)
 174                 return regmap_write(dac->common->regmap, reg, writeval);
 175         else
 176                 return regmap_read(dac->common->regmap, reg, readval);
 177 }
 178
 179 static const struct iio_info stm32_dac_iio_info = {
 180         .read_raw = stm32_dac_read_raw,
 181         .write_raw = stm32_dac_write_raw,
 182         .debugfs_reg_access = stm32_dac_debugfs_reg_access,
 183 };
 184
 185 static const char * const stm32_dac_powerdown_modes[] = {
 186         "three_state",
 187 };
 188
 189 static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
 190                                         const struct iio_chan_spec *chan)
 191 {
 192         return 0;
 193 }
 194
 195 static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
 196                                         const struct iio_chan_spec *chan,
 197                                         unsigned int type)
 198 {
 199         return 0;
 200 }
 201
 202 static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
 203                                         uintptr_t private,
 204                                         const struct iio_chan_spec *chan,
 205                                         char *buf)
 206 {
 207         int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
 208
 209         if (ret < 0)
 210                 return ret;
 211
 212         return sysfs_emit(buf, "%d\n", ret ? 0 : 1);
 213 }
 214
 215 static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
 216                                          uintptr_t private,
 217                                          const struct iio_chan_spec *chan,
 218                                          const char *buf, size_t len)
 219 {
 220         bool powerdown;
 221         int ret;
 222
 223         ret = kstrtobool(buf, &powerdown);
 224         if (ret)
 225                 return ret;
 226
 227         ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
 228         if (ret)
 229                 return ret;
 230
 231         return len;
 232 }
 233
 234 static const struct iio_enum stm32_dac_powerdown_mode_en = {
 235         .items = stm32_dac_powerdown_modes,
 236         .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
 237         .get = stm32_dac_get_powerdown_mode,
 238         .set = stm32_dac_set_powerdown_mode,
 239 };
 240
 241 static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
 242         {
 243                 .name = "powerdown",
 244                 .read = stm32_dac_read_powerdown,
 245                 .write = stm32_dac_write_powerdown,
 246                 .shared = IIO_SEPARATE,
 247         },
 248         IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
 249         IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en),
 250         {},
 251 };
 252
 253 #define STM32_DAC_CHANNEL(chan, name) {                 \
 254         .type = IIO_VOLTAGE,                            \
 255         .indexed = 1,                                   \
 256         .output = 1,                                    \
 257         .channel = chan,                                \
 258         .info_mask_separate =                           \
 259                 BIT(IIO_CHAN_INFO_RAW) |                \
 260                 BIT(IIO_CHAN_INFO_SCALE),               \
 261         /* scan_index is always 0 as num_channels is 1 */ \
 262         .scan_type = {                                  \
 263                 .sign = 'u',                            \
 264                 .realbits = 12,                         \
 265                 .storagebits = 16,                      \
 266         },                                              \
 267         .datasheet_name = name,                         \
 268         .ext_info = stm32_dac_ext_info                  \
 269 }
 270
 271 static const struct iio_chan_spec stm32_dac_channels[] = {
 272         STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
 273         STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
 274 };
 275
 276 static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
 277 {
 278         struct device_node *np = indio_dev->dev.of_node;
 279         unsigned int i;
 280         u32 channel;
 281         int ret;
 282
 283         ret = of_property_read_u32(np, "reg", &channel);
 284         if (ret) {
 285                 dev_err(&indio_dev->dev, "Failed to read reg property\n");
 286                 return ret;
 287         }
 288
 289         for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
 290                 if (stm32_dac_channels[i].channel == channel)
 291                         break;
 292         }
 293         if (i >= ARRAY_SIZE(stm32_dac_channels)) {
 294                 dev_err(&indio_dev->dev, "Invalid reg property\n");
 295                 return -EINVAL;
 296         }
 297
 298         indio_dev->channels = &stm32_dac_channels[i];
 299         /*
 300          * Expose only one channel here, as they can be used independently,
 301          * with separate trigger. Then separate IIO devices are instantiated
 302          * to manage this.
 303          */
 304         indio_dev->num_channels = 1;
 305
 306         return 0;
 307 };
 308
 309 static int stm32_dac_probe(struct platform_device *pdev)
 310 {
 311         struct device_node *np = pdev->dev.of_node;
 312         struct device *dev = &pdev->dev;
 313         struct iio_dev *indio_dev;
 314         struct stm32_dac *dac;
 315         int ret;
 316
 317         if (!np)
 318                 return -ENODEV;
 319
 320         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
 321         if (!indio_dev)
 322                 return -ENOMEM;
 323         platform_set_drvdata(pdev, indio_dev);
 324
 325         dac = iio_priv(indio_dev);
 326         dac->common = dev_get_drvdata(pdev->dev.parent);
 327         indio_dev->name = dev_name(&pdev->dev);
 328         indio_dev->dev.of_node = pdev->dev.of_node;
 329         indio_dev->info = &stm32_dac_iio_info;
 330         indio_dev->modes = INDIO_DIRECT_MODE;
 331
 332         mutex_init(&dac->lock);
 333
 334         ret = stm32_dac_chan_of_init(indio_dev);
 335         if (ret < 0)
 336                 return ret;
 337
 338         /* Get stm32-dac-core PM online */
 339         pm_runtime_get_noresume(dev);
 340         pm_runtime_set_active(dev);
 341         pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
 342         pm_runtime_use_autosuspend(dev);
 343         pm_runtime_enable(dev);
 344
 345         ret = iio_device_register(indio_dev);
 346         if (ret)
 347                 goto err_pm_put;
 348
 349         pm_runtime_mark_last_busy(dev);
 350         pm_runtime_put_autosuspend(dev);
 351
 352         return 0;
 353
 354 err_pm_put:
 355         pm_runtime_disable(dev);
 356         pm_runtime_set_suspended(dev);
 357         pm_runtime_put_noidle(dev);
 358
 359         return ret;
 360 }
 361
 362 static int stm32_dac_remove(struct platform_device *pdev)
 363 {
 364         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 365
 366         pm_runtime_get_sync(&pdev->dev);
 367         iio_device_unregister(indio_dev);
 368         pm_runtime_disable(&pdev->dev);
 369         pm_runtime_set_suspended(&pdev->dev);
 370         pm_runtime_put_noidle(&pdev->dev);
 371
 372         return 0;
 373 }
 374
 375 static int stm32_dac_suspend(struct device *dev)
 376 {
 377         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 378         int channel = indio_dev->channels[0].channel;
 379         int ret;
 380
 381         /* Ensure DAC is disabled before suspend */
 382         ret = stm32_dac_is_enabled(indio_dev, channel);
 383         if (ret)
 384                 return ret < 0 ? ret : -EBUSY;
 385
 386         return pm_runtime_force_suspend(dev);
 387 }
 388
 389 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend,
 390                                 pm_runtime_force_resume);
 391
 392 static const struct of_device_id stm32_dac_of_match[] = {
 393         { .compatible = "st,stm32-dac", },
 394         {},
 395 };
 396 MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
 397
 398 static struct platform_driver stm32_dac_driver = {
 399         .probe = stm32_dac_probe,
 400         .remove = stm32_dac_remove,
 401         .driver = {
 402                 .name = "stm32-dac",
 403                 .of_match_table = stm32_dac_of_match,
 404                 .pm = pm_sleep_ptr(&stm32_dac_pm_ops),
 405         },
 406 };
 407 module_platform_driver(stm32_dac_driver);
 408
 409 MODULE_ALIAS("platform:stm32-dac");
 410 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 411 MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
 412 MODULE_LICENSE("GPL v2");