drivers/iio/addac/ad74413r.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Analog Devices, Inc.
   4  * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
   5  */
   6
   7 #include <asm/unaligned.h>
   8 #include <linux/bitfield.h>
   9 #include <linux/crc8.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/iio/buffer.h>
  14 #include <linux/iio/iio.h>
  15 #include <linux/iio/sysfs.h>
  16 #include <linux/iio/trigger.h>
  17 #include <linux/iio/trigger_consumer.h>
  18 #include <linux/iio/triggered_buffer.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/mod_devicetable.h>
  21 #include <linux/property.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include <dt-bindings/iio/addac/adi,ad74413r.h>
  27
  28 #define AD74413R_CRC_POLYNOMIAL 0x7
  29 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
  30
  31 #define AD74413R_CHANNEL_MAX    4
  32
  33 #define AD74413R_FRAME_SIZE     4
  34
  35 struct ad74413r_chip_info {
  36         const char      *name;
  37         bool            hart_support;
  38 };
  39
  40 struct ad74413r_channel_config {
  41         u32             func;
  42         bool            gpo_comparator;
  43         bool            initialized;
  44 };
  45
  46 struct ad74413r_channels {
  47         struct iio_chan_spec    *channels;
  48         unsigned int            num_channels;
  49 };
  50
  51 struct ad74413r_state {
  52         struct ad74413r_channel_config  channel_configs[AD74413R_CHANNEL_MAX];
  53         unsigned int                    gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
  54         unsigned int                    comp_gpio_offsets[AD74413R_CHANNEL_MAX];
  55         struct gpio_chip                gpo_gpiochip;
  56         struct gpio_chip                comp_gpiochip;
  57         struct completion               adc_data_completion;
  58         unsigned int                    num_gpo_gpios;
  59         unsigned int                    num_comparator_gpios;
  60         u32                             sense_resistor_ohms;
  61
  62         /*
  63          * Synchronize consecutive operations when doing a one-shot
  64          * conversion and when updating the ADC samples SPI message.
  65          */
  66         struct mutex                    lock;
  67
  68         const struct ad74413r_chip_info *chip_info;
  69         struct spi_device               *spi;
  70         struct regulator                *refin_reg;
  71         struct regmap                   *regmap;
  72         struct device                   *dev;
  73         struct iio_trigger              *trig;
  74
  75         size_t                  adc_active_channels;
  76         struct spi_message      adc_samples_msg;
  77         struct spi_transfer     adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
  78
  79         /*
  80          * DMA (thus cache coherency maintenance) requires the
  81          * transfer buffers to live in their own cache lines.
  82          */
  83         struct {
  84                 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
  85                 s64 timestamp;
  86         } adc_samples_buf ____cacheline_aligned;
  87
  88         u8      adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
  89         u8      reg_tx_buf[AD74413R_FRAME_SIZE];
  90         u8      reg_rx_buf[AD74413R_FRAME_SIZE];
  91 };
  92
  93 #define AD74413R_REG_NOP                0x00
  94
  95 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
  96 #define AD74413R_CH_FUNC_SETUP_MASK     GENMASK(3, 0)
  97
  98 #define AD74413R_REG_ADC_CONFIG_X(x)            (0x05 + (x))
  99 #define AD74413R_ADC_CONFIG_RANGE_MASK          GENMASK(7, 5)
 100 #define AD74413R_ADC_CONFIG_REJECTION_MASK      GENMASK(4, 3)
 101 #define AD74413R_ADC_RANGE_10V                  0b000
 102 #define AD74413R_ADC_RANGE_2P5V_EXT_POW         0b001
 103 #define AD74413R_ADC_RANGE_2P5V_INT_POW         0b010
 104 #define AD74413R_ADC_RANGE_5V_BI_DIR            0b011
 105 #define AD74413R_ADC_REJECTION_50_60            0b00
 106 #define AD74413R_ADC_REJECTION_NONE             0b01
 107 #define AD74413R_ADC_REJECTION_50_60_HART       0b10
 108 #define AD74413R_ADC_REJECTION_HART             0b11
 109
 110 #define AD74413R_REG_DIN_CONFIG_X(x)    (0x09 + (x))
 111 #define AD74413R_DIN_DEBOUNCE_MASK      GENMASK(4, 0)
 112 #define AD74413R_DIN_DEBOUNCE_LEN       BIT(5)
 113
 114 #define AD74413R_REG_DAC_CODE_X(x)      (0x16 + (x))
 115 #define AD74413R_DAC_CODE_MAX           GENMASK(12, 0)
 116 #define AD74413R_DAC_VOLTAGE_MAX        11000
 117
 118 #define AD74413R_REG_GPO_PAR_DATA               0x0d
 119 #define AD74413R_REG_GPO_CONFIG_X(x)            (0x0e + (x))
 120 #define AD74413R_GPO_CONFIG_DATA_MASK   BIT(3)
 121 #define AD74413R_GPO_CONFIG_SELECT_MASK         GENMASK(2, 0)
 122 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN      0b000
 123 #define AD74413R_GPO_CONFIG_LOGIC               0b001
 124 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL      0b010
 125 #define AD74413R_GPO_CONFIG_COMPARATOR          0b011
 126 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE      0b100
 127
 128 #define AD74413R_REG_ADC_CONV_CTRL      0x23
 129 #define AD74413R_CONV_SEQ_MASK          GENMASK(9, 8)
 130 #define AD74413R_CONV_SEQ_ON            0b00
 131 #define AD74413R_CONV_SEQ_SINGLE        0b01
 132 #define AD74413R_CONV_SEQ_CONTINUOUS    0b10
 133 #define AD74413R_CONV_SEQ_OFF           0b11
 134 #define AD74413R_CH_EN_MASK(x)          BIT(x)
 135
 136 #define AD74413R_REG_DIN_COMP_OUT               0x25
 137 #define AD74413R_DIN_COMP_OUT_SHIFT_X(x)        x
 138
 139 #define AD74413R_REG_ADC_RESULT_X(x)    (0x26 + (x))
 140 #define AD74413R_ADC_RESULT_MAX         GENMASK(15, 0)
 141
 142 #define AD74413R_REG_READ_SELECT        0x41
 143
 144 #define AD74413R_REG_CMD_KEY            0x44
 145 #define AD74413R_CMD_KEY_LDAC           0x953a
 146 #define AD74413R_CMD_KEY_RESET1         0x15fa
 147 #define AD74413R_CMD_KEY_RESET2         0xaf51
 148
 149 static const int ad74413r_adc_sampling_rates[] = {
 150         20, 4800,
 151 };
 152
 153 static const int ad74413r_adc_sampling_rates_hart[] = {
 154         10, 20, 1200, 4800,
 155 };
 156
 157 static int ad74413r_crc(u8 *buf)
 158 {
 159         return crc8(ad74413r_crc8_table, buf, 3, 0);
 160 }
 161
 162 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
 163 {
 164         buf[0] = reg;
 165         put_unaligned_be16(val, &buf[1]);
 166         buf[3] = ad74413r_crc(buf);
 167 }
 168
 169 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
 170 {
 171         struct ad74413r_state *st = context;
 172
 173         ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
 174
 175         return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
 176 }
 177
 178 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
 179 {
 180         u8 expected_crc = ad74413r_crc(buf);
 181
 182         if (buf[3] != expected_crc) {
 183                 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
 184                         buf[3], buf[0], buf[1], buf[2]);
 185                 return -EINVAL;
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
 192 {
 193         struct ad74413r_state *st = context;
 194         struct spi_transfer reg_read_xfer[] = {
 195                 {
 196                         .tx_buf = st->reg_tx_buf,
 197                         .len = AD74413R_FRAME_SIZE,
 198                         .cs_change = 1,
 199                 },
 200                 {
 201                         .rx_buf = st->reg_rx_buf,
 202                         .len = AD74413R_FRAME_SIZE,
 203                 },
 204         };
 205         int ret;
 206
 207         ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
 208                                   st->reg_tx_buf);
 209
 210         ret = spi_sync_transfer(st->spi, reg_read_xfer,
 211                                 ARRAY_SIZE(reg_read_xfer));
 212         if (ret)
 213                 return ret;
 214
 215         ret = ad74413r_crc_check(st, st->reg_rx_buf);
 216         if (ret)
 217                 return ret;
 218
 219         *val = get_unaligned_be16(&st->reg_rx_buf[1]);
 220
 221         return 0;
 222 }
 223
 224 static const struct regmap_config ad74413r_regmap_config = {
 225         .reg_bits = 8,
 226         .val_bits = 16,
 227         .reg_read = ad74413r_reg_read,
 228         .reg_write = ad74413r_reg_write,
 229 };
 230
 231 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
 232                                    unsigned int offset, u8 mode)
 233 {
 234         return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
 235                                   AD74413R_GPO_CONFIG_SELECT_MASK, mode);
 236 }
 237
 238 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
 239         0,     13,    18,    24,    32,    42,    56,    75,
 240         100,   130,   180,   240,   320,   420,   560,   750,
 241         1000,  1300,  1800,  2400,  3200,  4200,  5600,  7500,
 242         10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
 243 };
 244
 245 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
 246                                       unsigned int offset,
 247                                       unsigned int debounce)
 248 {
 249         unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
 250         unsigned int i;
 251
 252         for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
 253                 if (debounce <= ad74413r_debounce_map[i]) {
 254                         val = i;
 255                         break;
 256                 }
 257
 258         return regmap_update_bits(st->regmap,
 259                                   AD74413R_REG_DIN_CONFIG_X(offset),
 260                                   AD74413R_DIN_DEBOUNCE_MASK,
 261                                   val);
 262 }
 263
 264 static void ad74413r_gpio_set(struct gpio_chip *chip,
 265                               unsigned int offset, int val)
 266 {
 267         struct ad74413r_state *st = gpiochip_get_data(chip);
 268         unsigned int real_offset = st->gpo_gpio_offsets[offset];
 269         int ret;
 270
 271         ret = ad74413r_set_gpo_config(st, real_offset,
 272                                       AD74413R_GPO_CONFIG_LOGIC);
 273         if (ret)
 274                 return;
 275
 276         regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset),
 277                            AD74413R_GPO_CONFIG_DATA_MASK,
 278                            val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
 279 }
 280
 281 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip,
 282                                        unsigned long *mask,
 283                                        unsigned long *bits)
 284 {
 285         struct ad74413r_state *st = gpiochip_get_data(chip);
 286         unsigned long real_mask = 0;
 287         unsigned long real_bits = 0;
 288         unsigned int offset = 0;
 289         int ret;
 290
 291         for_each_set_bit_from(offset, mask, AD74413R_CHANNEL_MAX) {
 292                 unsigned int real_offset = st->gpo_gpio_offsets[offset];
 293
 294                 ret = ad74413r_set_gpo_config(st, real_offset,
 295                         AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
 296                 if (ret)
 297                         return;
 298
 299                 real_mask |= BIT(real_offset);
 300                 if (*bits & offset)
 301                         real_bits |= BIT(real_offset);
 302         }
 303
 304         regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
 305                            real_mask, real_bits);
 306 }
 307
 308 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
 309 {
 310         struct ad74413r_state *st = gpiochip_get_data(chip);
 311         unsigned int real_offset = st->comp_gpio_offsets[offset];
 312         unsigned int status;
 313         int ret;
 314
 315         ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
 316         if (ret)
 317                 return ret;
 318
 319         status &= AD74413R_DIN_COMP_OUT_SHIFT_X(real_offset);
 320
 321         return status ? 1 : 0;
 322 }
 323
 324 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
 325                                       unsigned long *mask,
 326                                       unsigned long *bits)
 327 {
 328         struct ad74413r_state *st = gpiochip_get_data(chip);
 329         unsigned int offset = 0;
 330         unsigned int val;
 331         int ret;
 332
 333         ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
 334         if (ret)
 335                 return ret;
 336
 337         for_each_set_bit_from(offset, mask, AD74413R_CHANNEL_MAX) {
 338                 unsigned int real_offset = st->comp_gpio_offsets[offset];
 339
 340                 if (val & BIT(real_offset))
 341                         *bits |= offset;
 342         }
 343
 344         return ret;
 345 }
 346
 347 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
 348                                            unsigned int offset)
 349 {
 350         return GPIO_LINE_DIRECTION_OUT;
 351 }
 352
 353 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
 354                                             unsigned int offset)
 355 {
 356         return GPIO_LINE_DIRECTION_IN;
 357 }
 358
 359 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
 360                                         unsigned int offset,
 361                                         unsigned long config)
 362 {
 363         struct ad74413r_state *st = gpiochip_get_data(chip);
 364         unsigned int real_offset = st->gpo_gpio_offsets[offset];
 365
 366         switch (pinconf_to_config_param(config)) {
 367         case PIN_CONFIG_BIAS_PULL_DOWN:
 368                 return ad74413r_set_gpo_config(st, real_offset,
 369                         AD74413R_GPO_CONFIG_100K_PULL_DOWN);
 370         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 371                 return ad74413r_set_gpo_config(st, real_offset,
 372                         AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
 373         default:
 374                 return -ENOTSUPP;
 375         }
 376 }
 377
 378 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
 379                                          unsigned int offset,
 380                                          unsigned long config)
 381 {
 382         struct ad74413r_state *st = gpiochip_get_data(chip);
 383         unsigned int real_offset = st->comp_gpio_offsets[offset];
 384
 385         switch (pinconf_to_config_param(config)) {
 386         case PIN_CONFIG_INPUT_DEBOUNCE:
 387                 return ad74413r_set_comp_debounce(st, real_offset,
 388                         pinconf_to_config_argument(config));
 389         default:
 390                 return -ENOTSUPP;
 391         }
 392 }
 393
 394 static int ad74413r_reset(struct ad74413r_state *st)
 395 {
 396         int ret;
 397
 398         ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
 399                            AD74413R_CMD_KEY_RESET1);
 400         if (ret)
 401                 return ret;
 402
 403         return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
 404                             AD74413R_CMD_KEY_RESET2);
 405 }
 406
 407 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
 408                                          unsigned int channel, int dac_code)
 409 {
 410         struct reg_sequence reg_seq[2] = {
 411                 { AD74413R_REG_DAC_CODE_X(channel), dac_code },
 412                 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
 413         };
 414
 415         return regmap_multi_reg_write(st->regmap, reg_seq, 2);
 416 }
 417
 418 static int ad74413r_set_channel_function(struct ad74413r_state *st,
 419                                          unsigned int channel, u8 func)
 420 {
 421         return regmap_update_bits(st->regmap,
 422                                   AD74413R_REG_CH_FUNC_SETUP_X(channel),
 423                                   AD74413R_CH_FUNC_SETUP_MASK, func);
 424 }
 425
 426 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
 427                                      unsigned int status)
 428 {
 429         int ret;
 430
 431         /*
 432          * These bits do not clear when a conversion completes.
 433          * To enable a subsequent conversion, repeat the write.
 434          */
 435         ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
 436                                 AD74413R_CONV_SEQ_MASK,
 437                                 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
 438         if (ret)
 439                 return ret;
 440
 441         /*
 442          * Wait 100us before starting conversions.
 443          */
 444         usleep_range(100, 120);
 445
 446         return 0;
 447 }
 448
 449 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
 450                                            unsigned int channel,
 451                                            bool status)
 452 {
 453         return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
 454                                   AD74413R_CH_EN_MASK(channel),
 455                                   status ? AD74413R_CH_EN_MASK(channel) : 0);
 456 }
 457
 458 static int ad74413r_get_adc_range(struct ad74413r_state *st,
 459                                   unsigned int channel,
 460                                   unsigned int *val)
 461 {
 462         int ret;
 463
 464         ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
 465         if (ret)
 466                 return ret;
 467
 468         *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
 469
 470         return 0;
 471 }
 472
 473 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
 474                                       unsigned int channel,
 475                                       unsigned int *val)
 476 {
 477         int ret;
 478
 479         ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
 480         if (ret)
 481                 return ret;
 482
 483         *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
 484
 485         return 0;
 486 }
 487
 488 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
 489                                       unsigned int channel,
 490                                       unsigned int val)
 491 {
 492         return regmap_update_bits(st->regmap,
 493                                   AD74413R_REG_ADC_CONFIG_X(channel),
 494                                   AD74413R_ADC_CONFIG_REJECTION_MASK,
 495                                   FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
 496                                              val));
 497 }
 498
 499 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
 500                                       unsigned int rej, int *val)
 501 {
 502         switch (rej) {
 503         case AD74413R_ADC_REJECTION_50_60:
 504                 *val = 20;
 505                 return 0;
 506         case AD74413R_ADC_REJECTION_NONE:
 507                 *val = 4800;
 508                 return 0;
 509         case AD74413R_ADC_REJECTION_50_60_HART:
 510                 *val = 10;
 511                 return 0;
 512         case AD74413R_ADC_REJECTION_HART:
 513                 *val = 1200;
 514                 return 0;
 515         default:
 516                 dev_err(st->dev, "ADC rejection invalid\n");
 517                 return -EINVAL;
 518         }
 519 }
 520
 521 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
 522                                       int rate, unsigned int *val)
 523 {
 524         switch (rate) {
 525         case 20:
 526                 *val = AD74413R_ADC_REJECTION_50_60;
 527                 return 0;
 528         case 4800:
 529                 *val = AD74413R_ADC_REJECTION_NONE;
 530                 return 0;
 531         case 10:
 532                 *val = AD74413R_ADC_REJECTION_50_60_HART;
 533                 return 0;
 534         case 1200:
 535                 *val = AD74413R_ADC_REJECTION_HART;
 536                 return 0;
 537         default:
 538                 dev_err(st->dev, "ADC rate invalid\n");
 539                 return -EINVAL;
 540         }
 541 }
 542
 543 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
 544                                            unsigned int range, int *val)
 545 {
 546         switch (range) {
 547         case AD74413R_ADC_RANGE_10V:
 548                 *val = 10000;
 549                 return 0;
 550         case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 551         case AD74413R_ADC_RANGE_2P5V_INT_POW:
 552                 *val = 2500;
 553                 return 0;
 554         case AD74413R_ADC_RANGE_5V_BI_DIR:
 555                 *val = 5000;
 556                 return 0;
 557         default:
 558                 dev_err(st->dev, "ADC range invalid\n");
 559                 return -EINVAL;
 560         }
 561 }
 562
 563 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
 564                                             unsigned int range, int *val)
 565 {
 566         switch (range) {
 567         case AD74413R_ADC_RANGE_10V:
 568         case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 569                 *val = 0;
 570                 return 0;
 571         case AD74413R_ADC_RANGE_2P5V_INT_POW:
 572         case AD74413R_ADC_RANGE_5V_BI_DIR:
 573                 *val = -2500;
 574                 return 0;
 575         default:
 576                 dev_err(st->dev, "ADC range invalid\n");
 577                 return -EINVAL;
 578         }
 579 }
 580
 581 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
 582                                                 unsigned int range, int *val)
 583 {
 584         switch (range) {
 585         case AD74413R_ADC_RANGE_10V:
 586         case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 587                 *val = 0;
 588                 return 0;
 589         case AD74413R_ADC_RANGE_2P5V_INT_POW:
 590                 *val = -((int)AD74413R_ADC_RESULT_MAX);
 591                 return 0;
 592         case AD74413R_ADC_RANGE_5V_BI_DIR:
 593                 *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
 594                 return 0;
 595         default:
 596                 dev_err(st->dev, "ADC range invalid\n");
 597                 return -EINVAL;
 598         }
 599 }
 600
 601 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
 602                                              int *val, int *val2)
 603 {
 604         *val = AD74413R_DAC_VOLTAGE_MAX;
 605         *val2 = AD74413R_DAC_CODE_MAX;
 606
 607         return IIO_VAL_FRACTIONAL;
 608 }
 609
 610 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
 611                                              int *val, int *val2)
 612 {
 613         *val = regulator_get_voltage(st->refin_reg);
 614         *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
 615
 616         return IIO_VAL_FRACTIONAL;
 617 }
 618
 619 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
 620                                             unsigned int channel,
 621                                             int *val, int *val2)
 622 {
 623         unsigned int range;
 624         int ret;
 625
 626         ret = ad74413r_get_adc_range(st, channel, &range);
 627         if (ret)
 628                 return ret;
 629
 630         ret = ad74413r_range_to_voltage_range(st, range, val);
 631         if (ret)
 632                 return ret;
 633
 634         *val2 = AD74413R_ADC_RESULT_MAX;
 635
 636         return IIO_VAL_FRACTIONAL;
 637 }
 638
 639 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
 640                                              unsigned int channel, int *val)
 641 {
 642         unsigned int range;
 643         int ret;
 644
 645         ret = ad74413r_get_adc_range(st, channel, &range);
 646         if (ret)
 647                 return ret;
 648
 649         ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
 650         if (ret)
 651                 return ret;
 652
 653         return IIO_VAL_INT;
 654 }
 655
 656 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
 657                                             unsigned int channel, int *val,
 658                                             int *val2)
 659 {
 660         unsigned int range;
 661         int ret;
 662
 663         ret = ad74413r_get_adc_range(st, channel, &range);
 664         if (ret)
 665                 return ret;
 666
 667         ret = ad74413r_range_to_voltage_range(st, range, val);
 668         if (ret)
 669                 return ret;
 670
 671         *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
 672
 673         return IIO_VAL_FRACTIONAL;
 674 }
 675
 676 static int ad74413_get_input_current_offset(struct ad74413r_state *st,
 677                                             unsigned int channel, int *val)
 678 {
 679         unsigned int range;
 680         int voltage_range;
 681         int voltage_offset;
 682         int ret;
 683
 684         ret = ad74413r_get_adc_range(st, channel, &range);
 685         if (ret)
 686                 return ret;
 687
 688         ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
 689         if (ret)
 690                 return ret;
 691
 692         ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
 693         if (ret)
 694                 return ret;
 695
 696         *val = voltage_offset * AD74413R_ADC_RESULT_MAX / voltage_range;
 697
 698         return IIO_VAL_INT;
 699 }
 700
 701 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
 702                                  unsigned int channel, int *val)
 703 {
 704         unsigned int rejection;
 705         int ret;
 706
 707         ret = ad74413r_get_adc_rejection(st, channel, &rejection);
 708         if (ret)
 709                 return ret;
 710
 711         ret = ad74413r_rejection_to_rate(st, rejection, val);
 712         if (ret)
 713                 return ret;
 714
 715         return IIO_VAL_INT;
 716 }
 717
 718 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
 719                                  unsigned int channel, int val)
 720 {
 721         unsigned int rejection;
 722         int ret;
 723
 724         ret = ad74413r_rate_to_rejection(st, val, &rejection);
 725         if (ret)
 726                 return ret;
 727
 728         return ad74413r_set_adc_rejection(st, channel, rejection);
 729 }
 730
 731 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
 732 {
 733         struct iio_poll_func *pf = p;
 734         struct iio_dev *indio_dev = pf->indio_dev;
 735         struct ad74413r_state *st = iio_priv(indio_dev);
 736         u8 *rx_buf = st->adc_samples_buf.rx_buf;
 737         unsigned int i;
 738         int ret;
 739
 740         ret = spi_sync(st->spi, &st->adc_samples_msg);
 741         if (ret)
 742                 goto out;
 743
 744         for (i = 0; i < st->adc_active_channels; i++)
 745                 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
 746
 747         iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
 748                                            iio_get_time_ns(indio_dev));
 749
 750 out:
 751         iio_trigger_notify_done(indio_dev->trig);
 752
 753         return IRQ_HANDLED;
 754 }
 755
 756 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
 757 {
 758         struct iio_dev *indio_dev = data;
 759         struct ad74413r_state *st = iio_priv(indio_dev);
 760
 761         if (iio_buffer_enabled(indio_dev))
 762                 iio_trigger_poll(st->trig);
 763         else
 764                 complete(&st->adc_data_completion);
 765
 766         return IRQ_HANDLED;
 767 }
 768
 769 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
 770                                            unsigned int channel, int *val)
 771 {
 772         unsigned int uval;
 773         int ret;
 774
 775         reinit_completion(&st->adc_data_completion);
 776
 777         ret = ad74413r_set_adc_channel_enable(st, channel, true);
 778         if (ret)
 779                 return ret;
 780
 781         ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
 782         if (ret)
 783                 return ret;
 784
 785         ret = wait_for_completion_timeout(&st->adc_data_completion,
 786                                           msecs_to_jiffies(1000));
 787         if (!ret) {
 788                 ret = -ETIMEDOUT;
 789                 return ret;
 790         }
 791
 792         ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
 793                           &uval);
 794         if (ret)
 795                 return ret;
 796
 797         ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
 798         if (ret)
 799                 return ret;
 800
 801         ret = ad74413r_set_adc_channel_enable(st, channel, false);
 802         if (ret)
 803                 return ret;
 804
 805         *val = uval;
 806
 807         return IIO_VAL_INT;
 808 }
 809
 810 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
 811                                           unsigned int channel, int *val)
 812 {
 813         struct ad74413r_state *st = iio_priv(indio_dev);
 814         int ret;
 815
 816         ret = iio_device_claim_direct_mode(indio_dev);
 817         if (ret)
 818                 return ret;
 819
 820         mutex_lock(&st->lock);
 821         ret = _ad74413r_get_single_adc_result(st, channel, val);
 822         mutex_unlock(&st->lock);
 823
 824         iio_device_release_direct_mode(indio_dev);
 825
 826         return ret;
 827 }
 828
 829 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
 830 {
 831         if (adc_result == AD74413R_ADC_RESULT_MAX)
 832                 adc_result = AD74413R_ADC_RESULT_MAX - 1;
 833
 834         *val = DIV_ROUND_CLOSEST(adc_result * 2100,
 835                                  AD74413R_ADC_RESULT_MAX - adc_result);
 836 }
 837
 838 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
 839                                      const unsigned long *active_scan_mask)
 840 {
 841         struct ad74413r_state *st = iio_priv(indio_dev);
 842         struct spi_transfer *xfer = st->adc_samples_xfer;
 843         u8 *rx_buf = &st->adc_samples_buf.rx_buf[-1 * AD74413R_FRAME_SIZE];
 844         u8 *tx_buf = st->adc_samples_tx_buf;
 845         unsigned int channel;
 846         int ret = -EINVAL;
 847
 848         mutex_lock(&st->lock);
 849
 850         spi_message_init(&st->adc_samples_msg);
 851         st->adc_active_channels = 0;
 852
 853         for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
 854                 ret = ad74413r_set_adc_channel_enable(st, channel, false);
 855                 if (ret)
 856                         goto out;
 857         }
 858
 859         if (*active_scan_mask == 0)
 860                 goto out;
 861
 862         /*
 863          * The read select register is used to select which register's value
 864          * will be sent by the slave on the next SPI frame.
 865          *
 866          * Create an SPI message that, on each step, writes to the read select
 867          * register to select the ADC result of the next enabled channel, and
 868          * reads the ADC result of the previous enabled channel.
 869          *
 870          * Example:
 871          * W: [WCH1] [WCH2] [WCH2] [WCH3] [    ]
 872          * R: [    ] [RCH1] [RCH2] [RCH3] [RCH4]
 873          */
 874
 875         for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
 876                 ret = ad74413r_set_adc_channel_enable(st, channel, true);
 877                 if (ret)
 878                         goto out;
 879
 880                 st->adc_active_channels++;
 881
 882                 if (xfer == st->adc_samples_xfer)
 883                         xfer->rx_buf = NULL;
 884                 else
 885                         xfer->rx_buf = rx_buf;
 886
 887                 xfer->tx_buf = tx_buf;
 888                 xfer->len = AD74413R_FRAME_SIZE;
 889                 xfer->cs_change = 1;
 890
 891                 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
 892                                           AD74413R_REG_ADC_RESULT_X(channel),
 893                                           tx_buf);
 894
 895                 spi_message_add_tail(xfer, &st->adc_samples_msg);
 896
 897                 xfer++;
 898                 tx_buf += AD74413R_FRAME_SIZE;
 899                 rx_buf += AD74413R_FRAME_SIZE;
 900         }
 901
 902         xfer->rx_buf = rx_buf;
 903         xfer->tx_buf = NULL;
 904         xfer->len = AD74413R_FRAME_SIZE;
 905         xfer->cs_change = 0;
 906
 907         spi_message_add_tail(xfer, &st->adc_samples_msg);
 908
 909 out:
 910         mutex_unlock(&st->lock);
 911
 912         return ret;
 913 }
 914
 915 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
 916 {
 917         struct ad74413r_state *st = iio_priv(indio_dev);
 918
 919         return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
 920 }
 921
 922 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
 923 {
 924         struct ad74413r_state *st = iio_priv(indio_dev);
 925
 926         return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
 927 }
 928
 929 static int ad74413r_read_raw(struct iio_dev *indio_dev,
 930                              struct iio_chan_spec const *chan,
 931                              int *val, int *val2, long info)
 932 {
 933         struct ad74413r_state *st = iio_priv(indio_dev);
 934
 935         switch (info) {
 936         case IIO_CHAN_INFO_SCALE:
 937                 switch (chan->type) {
 938                 case IIO_VOLTAGE:
 939                         if (chan->output)
 940                                 return ad74413r_get_output_voltage_scale(st,
 941                                         val, val2);
 942                         else
 943                                 return ad74413r_get_input_voltage_scale(st,
 944                                         chan->channel, val, val2);
 945                 case IIO_CURRENT:
 946                         if (chan->output)
 947                                 return ad74413r_get_output_current_scale(st,
 948                                         val, val2);
 949                         else
 950                                 return ad74413r_get_input_current_scale(st,
 951                                         chan->channel, val, val2);
 952                 default:
 953                         return -EINVAL;
 954                 }
 955         case IIO_CHAN_INFO_OFFSET:
 956                 switch (chan->type) {
 957                 case IIO_VOLTAGE:
 958                         return ad74413r_get_input_voltage_offset(st,
 959                                 chan->channel, val);
 960                 case IIO_CURRENT:
 961                         return ad74413_get_input_current_offset(st,
 962                                 chan->channel, val);
 963                 default:
 964                         return -EINVAL;
 965                 }
 966         case IIO_CHAN_INFO_RAW:
 967                 if (chan->output)
 968                         return -EINVAL;
 969
 970                 return ad74413r_get_single_adc_result(indio_dev, chan->channel,
 971                                                       val);
 972         case IIO_CHAN_INFO_PROCESSED: {
 973                 int ret;
 974
 975                 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
 976                                                      val);
 977                 if (ret)
 978                         return ret;
 979
 980                 ad74413r_adc_to_resistance_result(*val, val);
 981
 982                 return ret;
 983         }
 984         case IIO_CHAN_INFO_SAMP_FREQ:
 985                 return ad74413r_get_adc_rate(st, chan->channel, val);
 986         default:
 987                 return -EINVAL;
 988         }
 989 }
 990
 991 static int ad74413r_write_raw(struct iio_dev *indio_dev,
 992                               struct iio_chan_spec const *chan,
 993                               int val, int val2, long info)
 994 {
 995         struct ad74413r_state *st = iio_priv(indio_dev);
 996
 997         switch (info) {
 998         case IIO_CHAN_INFO_RAW:
 999                 if (!chan->output)
1000                         return -EINVAL;
1001
1002                 if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1003                         dev_err(st->dev, "Invalid DAC code\n");
1004                         return -EINVAL;
1005                 }
1006
1007                 return ad74413r_set_channel_dac_code(st, chan->channel, val);
1008         case IIO_CHAN_INFO_SAMP_FREQ:
1009                 return ad74413r_set_adc_rate(st, chan->channel, val);
1010         default:
1011                 return -EINVAL;
1012         }
1013 }
1014
1015 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1016                                struct iio_chan_spec const *chan,
1017                                const int **vals, int *type, int *length,
1018                                long info)
1019 {
1020         struct ad74413r_state *st = iio_priv(indio_dev);
1021
1022         switch (info) {
1023         case IIO_CHAN_INFO_SAMP_FREQ:
1024                 if (st->chip_info->hart_support) {
1025                         *vals = ad74413r_adc_sampling_rates_hart;
1026                         *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1027                 } else {
1028                         *vals = ad74413r_adc_sampling_rates;
1029                         *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1030                 }
1031                 *type = IIO_VAL_INT;
1032                 return IIO_AVAIL_LIST;
1033         default:
1034                 return -EINVAL;
1035         }
1036 }
1037
1038 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1039         .postenable = &ad74413r_buffer_postenable,
1040         .predisable = &ad74413r_buffer_predisable,
1041 };
1042
1043 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1044         .validate_device = iio_trigger_validate_own_device,
1045 };
1046
1047 static const struct iio_info ad74413r_info = {
1048         .read_raw = &ad74413r_read_raw,
1049         .write_raw = &ad74413r_write_raw,
1050         .read_avail = &ad74413r_read_avail,
1051         .update_scan_mode = &ad74413r_update_scan_mode,
1052 };
1053
1054 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate)                \
1055         {                                                               \
1056                 .type = (_type),                                        \
1057                 .indexed = 1,                                           \
1058                 .output = 1,                                            \
1059                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)            \
1060                                       | (extra_mask_separate),          \
1061         }
1062
1063 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate)                \
1064         {                                                               \
1065                 .type = (_type),                                        \
1066                 .indexed = 1,                                           \
1067                 .output = 0,                                            \
1068                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)            \
1069                                       | BIT(IIO_CHAN_INFO_SAMP_FREQ)    \
1070                                       | (extra_mask_separate),          \
1071                 .info_mask_separate_available =                         \
1072                                         BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
1073                 .scan_type = {                                          \
1074                         .sign = 'u',                                    \
1075                         .realbits = 16,                                 \
1076                         .storagebits = 32,                              \
1077                         .shift = 8,                                     \
1078                         .endianness = IIO_BE,                           \
1079                 },                                                      \
1080         }
1081
1082 #define AD74413R_ADC_VOLTAGE_CHANNEL                                    \
1083         AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)      \
1084                              | BIT(IIO_CHAN_INFO_OFFSET))
1085
1086 #define AD74413R_ADC_CURRENT_CHANNEL                                    \
1087         AD74413R_ADC_CHANNEL(IIO_CURRENT,  BIT(IIO_CHAN_INFO_SCALE)     \
1088                              | BIT(IIO_CHAN_INFO_OFFSET))
1089
1090 static struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1091         AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1092         AD74413R_ADC_CURRENT_CHANNEL,
1093 };
1094
1095 static struct iio_chan_spec ad74413r_current_output_channels[] = {
1096         AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1097         AD74413R_ADC_VOLTAGE_CHANNEL,
1098 };
1099
1100 static struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1101         AD74413R_ADC_VOLTAGE_CHANNEL,
1102 };
1103
1104 static struct iio_chan_spec ad74413r_current_input_channels[] = {
1105         AD74413R_ADC_CURRENT_CHANNEL,
1106 };
1107
1108 static struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1109         AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1110 };
1111
1112 static struct iio_chan_spec ad74413r_digital_input_channels[] = {
1113         AD74413R_ADC_VOLTAGE_CHANNEL,
1114 };
1115
1116 #define _AD74413R_CHANNELS(_channels)                   \
1117         {                                               \
1118                 .channels = _channels,                  \
1119                 .num_channels = ARRAY_SIZE(_channels),  \
1120         }
1121
1122 #define AD74413R_CHANNELS(name) \
1123         _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1124
1125 static const struct ad74413r_channels ad74413r_channels_map[] = {
1126         [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1127         [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1128         [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1129         [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1130         [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1131         [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input),
1132         [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1133         [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1134         [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1135         [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1136         [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1137 };
1138
1139 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1140                                          struct fwnode_handle *channel_node)
1141 {
1142         struct ad74413r_state *st = iio_priv(indio_dev);
1143         struct ad74413r_channel_config *config;
1144         u32 index;
1145         int ret;
1146
1147         ret = fwnode_property_read_u32(channel_node, "reg", &index);
1148         if (ret) {
1149                 dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1150                 return ret;
1151         }
1152
1153         if (index >= AD74413R_CHANNEL_MAX) {
1154                 dev_err(st->dev, "Channel index %u is too large\n", index);
1155                 return -EINVAL;
1156         }
1157
1158         config = &st->channel_configs[index];
1159         if (config->initialized) {
1160                 dev_err(st->dev, "Channel %u already initialized\n", index);
1161                 return -EINVAL;
1162         }
1163
1164         config->func = CH_FUNC_HIGH_IMPEDANCE;
1165         fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1166
1167         if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1168                 dev_err(st->dev, "Invalid channel function %u\n", config->func);
1169                 return -EINVAL;
1170         }
1171
1172         if (!st->chip_info->hart_support &&
1173             (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1174              config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1175                 dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1176                 return -EINVAL;
1177         }
1178
1179         if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1180             config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1181                 st->num_comparator_gpios++;
1182
1183         config->gpo_comparator = fwnode_property_read_bool(channel_node,
1184                 "adi,gpo-comparator");
1185
1186         if (!config->gpo_comparator)
1187                 st->num_gpo_gpios++;
1188
1189         indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1190
1191         config->initialized = true;
1192
1193         return 0;
1194 }
1195
1196 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1197 {
1198         struct ad74413r_state *st = iio_priv(indio_dev);
1199         struct fwnode_handle *channel_node = NULL;
1200         int ret;
1201
1202         fwnode_for_each_available_child_node(dev_fwnode(st->dev), channel_node) {
1203                 ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1204                 if (ret)
1205                         goto put_channel_node;
1206         }
1207
1208         return 0;
1209
1210 put_channel_node:
1211         fwnode_handle_put(channel_node);
1212
1213         return ret;
1214 }
1215
1216 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1217 {
1218         struct ad74413r_state *st = iio_priv(indio_dev);
1219         struct ad74413r_channel_config *config;
1220         struct iio_chan_spec *channels, *chans;
1221         unsigned int i, num_chans, chan_i;
1222         int ret;
1223
1224         channels = devm_kcalloc(st->dev, sizeof(*channels),
1225                                 indio_dev->num_channels, GFP_KERNEL);
1226         if (!channels)
1227                 return -ENOMEM;
1228
1229         indio_dev->channels = channels;
1230
1231         for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1232                 config = &st->channel_configs[i];
1233                 chans = ad74413r_channels_map[config->func].channels;
1234                 num_chans = ad74413r_channels_map[config->func].num_channels;
1235
1236                 memcpy(channels, chans, num_chans * sizeof(*chans));
1237
1238                 for (chan_i = 0; chan_i < num_chans; chan_i++) {
1239                         struct iio_chan_spec *chan = &channels[chan_i];
1240
1241                         chan->channel = i;
1242                         if (chan->output)
1243                                 chan->scan_index = -1;
1244                         else
1245                                 chan->scan_index = i;
1246                 }
1247
1248                 ret = ad74413r_set_channel_function(st, i, config->func);
1249                 if (ret)
1250                         return ret;
1251
1252                 channels += num_chans;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1259 {
1260         struct ad74413r_channel_config *config;
1261         unsigned int comp_gpio_i = 0;
1262         unsigned int gpo_gpio_i = 0;
1263         unsigned int i;
1264         u8 gpo_config;
1265         int ret;
1266
1267         for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1268                 config = &st->channel_configs[i];
1269
1270                 if (config->gpo_comparator) {
1271                         gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1272                 } else {
1273                         gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1274                         st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1275                 }
1276
1277                 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1278                     config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1279                         st->comp_gpio_offsets[comp_gpio_i++] = i;
1280
1281                 ret = ad74413r_set_gpo_config(st, i, gpo_config);
1282                 if (ret)
1283                         return ret;
1284         }
1285
1286         return 0;
1287 }
1288
1289 static void ad74413r_regulator_disable(void *regulator)
1290 {
1291         regulator_disable(regulator);
1292 }
1293
1294 static int ad74413r_probe(struct spi_device *spi)
1295 {
1296         struct ad74413r_state *st;
1297         struct iio_dev *indio_dev;
1298         int ret;
1299
1300         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1301         if (!indio_dev)
1302                 return -ENOMEM;
1303
1304         st = iio_priv(indio_dev);
1305
1306         st->spi = spi;
1307         st->dev = &spi->dev;
1308         st->chip_info = device_get_match_data(&spi->dev);
1309         mutex_init(&st->lock);
1310         init_completion(&st->adc_data_completion);
1311
1312         st->regmap = devm_regmap_init(st->dev, NULL, st,
1313                                       &ad74413r_regmap_config);
1314         if (IS_ERR(st->regmap))
1315                 return PTR_ERR(st->regmap);
1316
1317         st->refin_reg = devm_regulator_get(st->dev, "refin");
1318         if (IS_ERR(st->refin_reg))
1319                 return dev_err_probe(st->dev, PTR_ERR(st->refin_reg),
1320                                      "Failed to get refin regulator\n");
1321
1322         ret = regulator_enable(st->refin_reg);
1323         if (ret)
1324                 return ret;
1325
1326         ret = devm_add_action_or_reset(st->dev, ad74413r_regulator_disable,
1327                                        st->refin_reg);
1328         if (ret)
1329                 return ret;
1330
1331         st->sense_resistor_ohms = 100000000;
1332         device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1333                                  &st->sense_resistor_ohms);
1334         st->sense_resistor_ohms /= 1000000;
1335
1336         st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1337                                           st->chip_info->name, iio_device_id(indio_dev));
1338         if (!st->trig)
1339                 return -ENOMEM;
1340
1341         st->trig->ops = &ad74413r_trigger_ops;
1342         iio_trigger_set_drvdata(st->trig, st);
1343
1344         ret = devm_iio_trigger_register(st->dev, st->trig);
1345         if (ret)
1346                 return ret;
1347
1348         indio_dev->name = st->chip_info->name;
1349         indio_dev->modes = INDIO_DIRECT_MODE;
1350         indio_dev->info = &ad74413r_info;
1351         indio_dev->trig = iio_trigger_get(st->trig);
1352
1353         ret = ad74413r_reset(st);
1354         if (ret)
1355                 return ret;
1356
1357         ret = ad74413r_parse_channel_configs(indio_dev);
1358         if (ret)
1359                 return ret;
1360
1361         ret = ad74413r_setup_channels(indio_dev);
1362         if (ret)
1363                 return ret;
1364
1365         ret = ad74413r_setup_gpios(st);
1366         if (ret)
1367                 return ret;
1368
1369         if (st->num_gpo_gpios) {
1370                 st->gpo_gpiochip.owner = THIS_MODULE;
1371                 st->gpo_gpiochip.label = st->chip_info->name;
1372                 st->gpo_gpiochip.base = -1;
1373                 st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1374                 st->gpo_gpiochip.parent = st->dev;
1375                 st->gpo_gpiochip.can_sleep = true;
1376                 st->gpo_gpiochip.set = ad74413r_gpio_set;
1377                 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1378                 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1379                 st->gpo_gpiochip.get_direction =
1380                         ad74413r_gpio_get_gpo_direction;
1381
1382                 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1383                 if (ret)
1384                         return ret;
1385         }
1386
1387         if (st->num_comparator_gpios) {
1388                 st->comp_gpiochip.owner = THIS_MODULE;
1389                 st->comp_gpiochip.label = st->chip_info->name;
1390                 st->comp_gpiochip.base = -1;
1391                 st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1392                 st->comp_gpiochip.parent = st->dev;
1393                 st->comp_gpiochip.can_sleep = true;
1394                 st->comp_gpiochip.get = ad74413r_gpio_get;
1395                 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1396                 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1397                 st->comp_gpiochip.get_direction =
1398                         ad74413r_gpio_get_comp_direction;
1399
1400                 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1401                 if (ret)
1402                         return ret;
1403         }
1404
1405         ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1406         if (ret)
1407                 return ret;
1408
1409         ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1410                                0, st->chip_info->name, indio_dev);
1411         if (ret)
1412                 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1413
1414         ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1415                                               &iio_pollfunc_store_time,
1416                                               &ad74413r_trigger_handler,
1417                                               &ad74413r_buffer_ops);
1418         if (ret)
1419                 return ret;
1420
1421         return devm_iio_device_register(st->dev, indio_dev);
1422 }
1423
1424 static int ad74413r_unregister_driver(struct spi_driver *spi)
1425 {
1426         spi_unregister_driver(spi);
1427
1428         return 0;
1429 }
1430
1431 static int __init ad74413r_register_driver(struct spi_driver *spi)
1432 {
1433         crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1434
1435         return spi_register_driver(spi);
1436 }
1437
1438 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1439         .hart_support = false,
1440         .name = "ad74412r",
1441 };
1442
1443 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1444         .hart_support = true,
1445         .name = "ad74413r",
1446 };
1447
1448 static const struct of_device_id ad74413r_dt_id[] = {
1449         {
1450                 .compatible = "adi,ad74412r",
1451                 .data = &ad74412r_chip_info_data,
1452         },
1453         {
1454                 .compatible = "adi,ad74413r",
1455                 .data = &ad74413r_chip_info_data,
1456         },
1457         {},
1458 };
1459 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1460
1461 static struct spi_driver ad74413r_driver = {
1462         .driver = {
1463                    .name = "ad74413r",
1464                    .of_match_table = ad74413r_dt_id,
1465         },
1466         .probe = ad74413r_probe,
1467 };
1468
1469 module_driver(ad74413r_driver,
1470               ad74413r_register_driver,
1471               ad74413r_unregister_driver);
1472
1473 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1474 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1475 MODULE_LICENSE("GPL v2");