2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/module.h>
30 #include <linux/reset.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/iopoll.h>
35 #include <asm/unaligned.h>
37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
38 #define BYTES_PER_FIFO_WORD 4
40 #define I2C_CNFG 0x000
41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
42 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
43 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
44 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
45 #define I2C_STATUS 0x01C
46 #define I2C_SL_CNFG 0x020
47 #define I2C_SL_CNFG_NACK BIT(1)
48 #define I2C_SL_CNFG_NEWSL BIT(2)
49 #define I2C_SL_ADDR1 0x02c
50 #define I2C_SL_ADDR2 0x030
51 #define I2C_TX_FIFO 0x050
52 #define I2C_RX_FIFO 0x054
53 #define I2C_PACKET_TRANSFER_STATUS 0x058
54 #define I2C_FIFO_CONTROL 0x05c
55 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
56 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
59 #define I2C_FIFO_STATUS 0x060
60 #define I2C_FIFO_STATUS_TX_MASK 0xF0
61 #define I2C_FIFO_STATUS_TX_SHIFT 4
62 #define I2C_FIFO_STATUS_RX_MASK 0x0F
63 #define I2C_FIFO_STATUS_RX_SHIFT 0
64 #define I2C_INT_MASK 0x064
65 #define I2C_INT_STATUS 0x068
66 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6)
68 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5)
69 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4)
70 #define I2C_INT_NO_ACK BIT(3)
71 #define I2C_INT_ARBITRATION_LOST BIT(2)
72 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
73 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
74 #define I2C_CLK_DIVISOR 0x06c
75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
78 #define DVC_CTRL_REG1 0x000
79 #define DVC_CTRL_REG1_INTR_EN BIT(10)
80 #define DVC_CTRL_REG2 0x004
81 #define DVC_CTRL_REG3 0x008
82 #define DVC_CTRL_REG3_SW_PROG BIT(26)
83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
84 #define DVC_STATUS 0x00c
85 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
87 #define I2C_ERR_NONE 0x00
88 #define I2C_ERR_NO_ACK 0x01
89 #define I2C_ERR_ARBITRATION_LOST 0x02
90 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
93 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
94 #define PACKET_HEADER0_CONT_ID_SHIFT 12
95 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
97 #define I2C_HEADER_HIGHSPEED_MODE BIT(22)
98 #define I2C_HEADER_CONT_ON_NAK BIT(21)
99 #define I2C_HEADER_SEND_START_BYTE BIT(20)
100 #define I2C_HEADER_READ BIT(19)
101 #define I2C_HEADER_10BIT_ADDR BIT(18)
102 #define I2C_HEADER_IE_ENABLE BIT(17)
103 #define I2C_HEADER_REPEAT_START BIT(16)
104 #define I2C_HEADER_CONTINUE_XFER BIT(15)
105 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
106 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
108 #define I2C_CONFIG_LOAD 0x08C
109 #define I2C_MSTR_CONFIG_LOAD BIT(0)
110 #define I2C_SLV_CONFIG_LOAD BIT(1)
111 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2)
113 #define I2C_CLKEN_OVERRIDE 0x090
114 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
116 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
119 * msg_end_type: The bus control which need to be send at end of transfer.
120 * @MSG_END_STOP: Send stop pulse at end of transfer.
121 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
122 * @MSG_END_CONTINUE: The following on message is coming and so do not send
123 * stop or repeat start.
127 MSG_END_REPEAT_START,
132 * struct tegra_i2c_hw_feature : Different HW support on Tegra
133 * @has_continue_xfer_support: Continue transfer supports.
134 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
135 * complete interrupt per packet basis.
136 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
137 * and earlier Socs has two clock sources i.e. div-clk and
139 * @has_config_load_reg: Has the config load register to load the new
141 * @clk_divisor_hs_mode: Clock divisor in HS mode.
142 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
143 * applicable if there is no fast clock source i.e. single clock
147 struct tegra_i2c_hw_feature {
148 bool has_continue_xfer_support;
149 bool has_per_pkt_xfer_complete_irq;
150 bool has_single_clk_source;
151 bool has_config_load_reg;
152 int clk_divisor_hs_mode;
153 int clk_divisor_std_fast_mode;
154 u16 clk_divisor_fast_plus_mode;
155 bool has_multi_master_mode;
156 bool has_slcg_override_reg;
160 * struct tegra_i2c_dev - per device i2c context
161 * @dev: device reference for power management
162 * @hw: Tegra i2c hw feature.
163 * @adapter: core i2c layer adapter information
164 * @div_clk: clock reference for div clock of i2c controller.
165 * @fast_clk: clock reference for fast clock of i2c controller.
166 * @base: ioremapped registers cookie
167 * @cont_id: i2c controller id, used for for packet header
168 * @irq: irq number of transfer complete interrupt
169 * @is_dvc: identifies the DVC i2c controller, has a different register layout
170 * @msg_complete: transfer completion notifier
171 * @msg_err: error code for completed message
172 * @msg_buf: pointer to current message data
173 * @msg_buf_remaining: size of unsent data in the message buffer
174 * @msg_read: identifies read transfers
175 * @bus_clk_rate: current i2c bus clock rate
177 struct tegra_i2c_dev {
179 const struct tegra_i2c_hw_feature *hw;
180 struct i2c_adapter adapter;
182 struct clk *fast_clk;
183 struct reset_control *rst;
189 struct completion msg_complete;
192 size_t msg_buf_remaining;
195 u16 clk_divisor_non_hs_mode;
196 bool is_multimaster_mode;
197 spinlock_t xfer_lock;
200 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
203 writel(val, i2c_dev->base + reg);
206 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
208 return readl(i2c_dev->base + reg);
212 * i2c_writel and i2c_readl will offset the register if necessary to talk
213 * to the I2C block inside the DVC block
215 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
219 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
223 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
226 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
228 /* Read back register to make sure that register writes completed */
229 if (reg != I2C_TX_FIFO)
230 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
233 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
235 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
238 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
239 unsigned long reg, int len)
241 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
244 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
245 unsigned long reg, int len)
247 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
250 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
254 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
255 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
258 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
262 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
263 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
266 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
268 unsigned long timeout = jiffies + HZ;
269 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
271 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
272 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
274 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
275 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
276 if (time_after(jiffies, timeout)) {
277 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
285 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
289 u8 *buf = i2c_dev->msg_buf;
290 size_t buf_remaining = i2c_dev->msg_buf_remaining;
291 int words_to_transfer;
293 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
294 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
295 I2C_FIFO_STATUS_RX_SHIFT;
297 /* Rounds down to not include partial word at the end of buf */
298 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
299 if (words_to_transfer > rx_fifo_avail)
300 words_to_transfer = rx_fifo_avail;
302 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
304 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
305 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
306 rx_fifo_avail -= words_to_transfer;
309 * If there is a partial word at the end of buf, handle it manually to
310 * prevent overwriting past the end of buf
312 if (rx_fifo_avail > 0 && buf_remaining > 0) {
313 BUG_ON(buf_remaining > 3);
314 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
315 val = cpu_to_le32(val);
316 memcpy(buf, &val, buf_remaining);
321 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
322 i2c_dev->msg_buf_remaining = buf_remaining;
323 i2c_dev->msg_buf = buf;
327 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
331 u8 *buf = i2c_dev->msg_buf;
332 size_t buf_remaining = i2c_dev->msg_buf_remaining;
333 int words_to_transfer;
335 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
336 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
337 I2C_FIFO_STATUS_TX_SHIFT;
339 /* Rounds down to not include partial word at the end of buf */
340 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
342 /* It's very common to have < 4 bytes, so optimize that case. */
343 if (words_to_transfer) {
344 if (words_to_transfer > tx_fifo_avail)
345 words_to_transfer = tx_fifo_avail;
348 * Update state before writing to FIFO. If this casues us
349 * to finish writing all bytes (AKA buf_remaining goes to 0) we
350 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
351 * not maskable). We need to make sure that the isr sees
352 * buf_remaining as 0 and doesn't call us back re-entrantly.
354 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
355 tx_fifo_avail -= words_to_transfer;
356 i2c_dev->msg_buf_remaining = buf_remaining;
357 i2c_dev->msg_buf = buf +
358 words_to_transfer * BYTES_PER_FIFO_WORD;
361 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
363 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
367 * If there is a partial word at the end of buf, handle it manually to
368 * prevent reading past the end of buf, which could cross a page
369 * boundary and fault.
371 if (tx_fifo_avail > 0 && buf_remaining > 0) {
372 BUG_ON(buf_remaining > 3);
373 memcpy(&val, buf, buf_remaining);
374 val = le32_to_cpu(val);
376 /* Again update before writing to FIFO to make sure isr sees. */
377 i2c_dev->msg_buf_remaining = 0;
378 i2c_dev->msg_buf = NULL;
381 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
388 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
389 * block. This block is identical to the rest of the I2C blocks, except that
390 * it only supports master mode, it has registers moved around, and it needs
391 * some extra init to get it into I2C mode. The register moves are handled
392 * by i2c_readl and i2c_writel
394 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
398 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
399 val |= DVC_CTRL_REG3_SW_PROG;
400 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
401 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
403 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
404 val |= DVC_CTRL_REG1_INTR_EN;
405 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
408 static int tegra_i2c_runtime_resume(struct device *dev)
410 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
413 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
417 if (!i2c_dev->hw->has_single_clk_source) {
418 ret = clk_enable(i2c_dev->fast_clk);
420 dev_err(i2c_dev->dev,
421 "Enabling fast clk failed, err %d\n", ret);
426 ret = clk_enable(i2c_dev->div_clk);
428 dev_err(i2c_dev->dev,
429 "Enabling div clk failed, err %d\n", ret);
430 clk_disable(i2c_dev->fast_clk);
437 static int tegra_i2c_runtime_suspend(struct device *dev)
439 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
441 clk_disable(i2c_dev->div_clk);
442 if (!i2c_dev->hw->has_single_clk_source)
443 clk_disable(i2c_dev->fast_clk);
445 return pinctrl_pm_select_idle_state(i2c_dev->dev);
448 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
450 unsigned long reg_offset;
455 if (i2c_dev->hw->has_config_load_reg) {
456 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
457 addr = i2c_dev->base + reg_offset;
458 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
460 err = readl_poll_timeout_atomic(addr, val, val == 0,
461 1000, I2C_CONFIG_LOAD_TIMEOUT);
463 err = readl_poll_timeout(addr, val, val == 0,
464 1000, I2C_CONFIG_LOAD_TIMEOUT);
467 dev_warn(i2c_dev->dev,
468 "timeout waiting for config load\n");
476 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
482 err = pm_runtime_get_sync(i2c_dev->dev);
484 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
488 reset_control_assert(i2c_dev->rst);
490 reset_control_deassert(i2c_dev->rst);
493 tegra_dvc_init(i2c_dev);
495 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
496 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
498 if (i2c_dev->hw->has_multi_master_mode)
499 val |= I2C_CNFG_MULTI_MASTER_MODE;
501 i2c_writel(i2c_dev, val, I2C_CNFG);
502 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
504 /* Make sure clock divisor programmed correctly */
505 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
506 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
507 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
508 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
510 if (!i2c_dev->is_dvc) {
511 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
513 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
514 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
515 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
516 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
519 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
520 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
521 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
523 err = tegra_i2c_flush_fifos(i2c_dev);
527 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
528 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
530 err = tegra_i2c_wait_for_config_load(i2c_dev);
534 if (i2c_dev->irq_disabled) {
535 i2c_dev->irq_disabled = false;
536 enable_irq(i2c_dev->irq);
540 pm_runtime_put(i2c_dev->dev);
544 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
548 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
549 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
550 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
552 return tegra_i2c_wait_for_config_load(i2c_dev);
555 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
558 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
559 struct tegra_i2c_dev *i2c_dev = dev_id;
562 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
564 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
566 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
567 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
568 i2c_readl(i2c_dev, I2C_STATUS),
569 i2c_readl(i2c_dev, I2C_CNFG));
570 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
572 if (!i2c_dev->irq_disabled) {
573 disable_irq_nosync(i2c_dev->irq);
574 i2c_dev->irq_disabled = true;
579 if (unlikely(status & status_err)) {
580 tegra_i2c_disable_packet_mode(i2c_dev);
581 if (status & I2C_INT_NO_ACK)
582 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
583 if (status & I2C_INT_ARBITRATION_LOST)
584 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
588 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
589 if (i2c_dev->msg_buf_remaining)
590 tegra_i2c_empty_rx_fifo(i2c_dev);
595 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
596 if (i2c_dev->msg_buf_remaining)
597 tegra_i2c_fill_tx_fifo(i2c_dev);
599 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
602 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
604 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
606 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
607 BUG_ON(i2c_dev->msg_buf_remaining);
608 complete(&i2c_dev->msg_complete);
612 /* An error occurred, mask all interrupts */
613 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
614 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
615 I2C_INT_RX_FIFO_DATA_REQ);
616 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
618 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
620 complete(&i2c_dev->msg_complete);
622 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
626 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
627 struct i2c_msg *msg, enum msg_end_type end_state)
631 unsigned long time_left;
634 tegra_i2c_flush_fifos(i2c_dev);
639 i2c_dev->msg_buf = msg->buf;
640 i2c_dev->msg_buf_remaining = msg->len;
641 i2c_dev->msg_err = I2C_ERR_NONE;
642 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
643 reinit_completion(&i2c_dev->msg_complete);
645 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
647 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
648 tegra_i2c_unmask_irq(i2c_dev, int_mask);
650 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
651 PACKET_HEADER0_PROTOCOL_I2C |
652 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
653 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
654 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
656 packet_header = msg->len - 1;
657 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
659 packet_header = I2C_HEADER_IE_ENABLE;
660 if (end_state == MSG_END_CONTINUE)
661 packet_header |= I2C_HEADER_CONTINUE_XFER;
662 else if (end_state == MSG_END_REPEAT_START)
663 packet_header |= I2C_HEADER_REPEAT_START;
664 if (msg->flags & I2C_M_TEN) {
665 packet_header |= msg->addr;
666 packet_header |= I2C_HEADER_10BIT_ADDR;
668 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
670 if (msg->flags & I2C_M_IGNORE_NAK)
671 packet_header |= I2C_HEADER_CONT_ON_NAK;
672 if (msg->flags & I2C_M_RD)
673 packet_header |= I2C_HEADER_READ;
674 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
676 if (!(msg->flags & I2C_M_RD))
677 tegra_i2c_fill_tx_fifo(i2c_dev);
679 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
680 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
681 if (msg->flags & I2C_M_RD)
682 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
683 else if (i2c_dev->msg_buf_remaining)
684 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
686 tegra_i2c_unmask_irq(i2c_dev, int_mask);
687 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
688 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
689 i2c_readl(i2c_dev, I2C_INT_MASK));
691 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
693 tegra_i2c_mask_irq(i2c_dev, int_mask);
695 if (time_left == 0) {
696 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
698 tegra_i2c_init(i2c_dev);
702 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
703 time_left, completion_done(&i2c_dev->msg_complete),
706 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
710 * NACK interrupt is generated before the I2C controller generates
711 * the STOP condition on the bus. So wait for 2 clock periods
712 * before resetting the controller so that the STOP condition has
713 * been delivered properly.
715 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
716 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
718 tegra_i2c_init(i2c_dev);
719 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
720 if (msg->flags & I2C_M_IGNORE_NAK)
728 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
731 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
735 ret = pm_runtime_get_sync(i2c_dev->dev);
737 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
741 for (i = 0; i < num; i++) {
742 enum msg_end_type end_type = MSG_END_STOP;
745 if (msgs[i + 1].flags & I2C_M_NOSTART)
746 end_type = MSG_END_CONTINUE;
748 end_type = MSG_END_REPEAT_START;
750 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
755 pm_runtime_put(i2c_dev->dev);
760 static u32 tegra_i2c_func(struct i2c_adapter *adap)
762 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
763 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
764 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
766 if (i2c_dev->hw->has_continue_xfer_support)
767 ret |= I2C_FUNC_NOSTART;
771 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
773 struct device_node *np = i2c_dev->dev->of_node;
776 ret = of_property_read_u32(np, "clock-frequency",
777 &i2c_dev->bus_clk_rate);
779 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
781 i2c_dev->is_multimaster_mode = of_property_read_bool(np,
785 static const struct i2c_algorithm tegra_i2c_algo = {
786 .master_xfer = tegra_i2c_xfer,
787 .functionality = tegra_i2c_func,
790 /* payload size is only 12 bit */
791 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
792 .max_read_len = 4096,
793 .max_write_len = 4096,
796 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
797 .has_continue_xfer_support = false,
798 .has_per_pkt_xfer_complete_irq = false,
799 .has_single_clk_source = false,
800 .clk_divisor_hs_mode = 3,
801 .clk_divisor_std_fast_mode = 0,
802 .clk_divisor_fast_plus_mode = 0,
803 .has_config_load_reg = false,
804 .has_multi_master_mode = false,
805 .has_slcg_override_reg = false,
808 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
809 .has_continue_xfer_support = true,
810 .has_per_pkt_xfer_complete_irq = false,
811 .has_single_clk_source = false,
812 .clk_divisor_hs_mode = 3,
813 .clk_divisor_std_fast_mode = 0,
814 .clk_divisor_fast_plus_mode = 0,
815 .has_config_load_reg = false,
816 .has_multi_master_mode = false,
817 .has_slcg_override_reg = false,
820 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
821 .has_continue_xfer_support = true,
822 .has_per_pkt_xfer_complete_irq = true,
823 .has_single_clk_source = true,
824 .clk_divisor_hs_mode = 1,
825 .clk_divisor_std_fast_mode = 0x19,
826 .clk_divisor_fast_plus_mode = 0x10,
827 .has_config_load_reg = false,
828 .has_multi_master_mode = false,
829 .has_slcg_override_reg = false,
832 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
833 .has_continue_xfer_support = true,
834 .has_per_pkt_xfer_complete_irq = true,
835 .has_single_clk_source = true,
836 .clk_divisor_hs_mode = 1,
837 .clk_divisor_std_fast_mode = 0x19,
838 .clk_divisor_fast_plus_mode = 0x10,
839 .has_config_load_reg = true,
840 .has_multi_master_mode = false,
841 .has_slcg_override_reg = true,
844 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
845 .has_continue_xfer_support = true,
846 .has_per_pkt_xfer_complete_irq = true,
847 .has_single_clk_source = true,
848 .clk_divisor_hs_mode = 1,
849 .clk_divisor_std_fast_mode = 0x19,
850 .clk_divisor_fast_plus_mode = 0x10,
851 .has_config_load_reg = true,
852 .has_multi_master_mode = true,
853 .has_slcg_override_reg = true,
856 /* Match table for of_platform binding */
857 static const struct of_device_id tegra_i2c_of_match[] = {
858 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
859 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
860 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
861 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
862 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
863 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
866 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
868 static int tegra_i2c_probe(struct platform_device *pdev)
870 struct tegra_i2c_dev *i2c_dev;
871 struct resource *res;
873 struct clk *fast_clk;
877 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880 base = devm_ioremap_resource(&pdev->dev, res);
882 return PTR_ERR(base);
884 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
886 dev_err(&pdev->dev, "no irq resource\n");
891 div_clk = devm_clk_get(&pdev->dev, "div-clk");
892 if (IS_ERR(div_clk)) {
893 dev_err(&pdev->dev, "missing controller clock\n");
894 return PTR_ERR(div_clk);
897 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
901 i2c_dev->base = base;
902 i2c_dev->div_clk = div_clk;
903 i2c_dev->adapter.algo = &tegra_i2c_algo;
904 i2c_dev->adapter.quirks = &tegra_i2c_quirks;
906 i2c_dev->cont_id = pdev->id;
907 i2c_dev->dev = &pdev->dev;
909 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
910 if (IS_ERR(i2c_dev->rst)) {
911 dev_err(&pdev->dev, "missing controller reset\n");
912 return PTR_ERR(i2c_dev->rst);
915 tegra_i2c_parse_dt(i2c_dev);
917 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
918 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
919 "nvidia,tegra20-i2c-dvc");
920 init_completion(&i2c_dev->msg_complete);
921 spin_lock_init(&i2c_dev->xfer_lock);
923 if (!i2c_dev->hw->has_single_clk_source) {
924 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
925 if (IS_ERR(fast_clk)) {
926 dev_err(&pdev->dev, "missing fast clock\n");
927 return PTR_ERR(fast_clk);
929 i2c_dev->fast_clk = fast_clk;
932 platform_set_drvdata(pdev, i2c_dev);
934 if (!i2c_dev->hw->has_single_clk_source) {
935 ret = clk_prepare(i2c_dev->fast_clk);
937 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
942 i2c_dev->clk_divisor_non_hs_mode =
943 i2c_dev->hw->clk_divisor_std_fast_mode;
944 if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
945 (i2c_dev->bus_clk_rate == 1000000))
946 i2c_dev->clk_divisor_non_hs_mode =
947 i2c_dev->hw->clk_divisor_fast_plus_mode;
949 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
950 ret = clk_set_rate(i2c_dev->div_clk,
951 i2c_dev->bus_clk_rate * clk_multiplier);
953 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
954 goto unprepare_fast_clk;
957 ret = clk_prepare(i2c_dev->div_clk);
959 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
960 goto unprepare_fast_clk;
963 pm_runtime_enable(&pdev->dev);
964 if (!pm_runtime_enabled(&pdev->dev)) {
965 ret = tegra_i2c_runtime_resume(&pdev->dev);
967 dev_err(&pdev->dev, "runtime resume failed\n");
968 goto unprepare_div_clk;
972 if (i2c_dev->is_multimaster_mode) {
973 ret = clk_enable(i2c_dev->div_clk);
975 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
981 ret = tegra_i2c_init(i2c_dev);
983 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
984 goto disable_div_clk;
987 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
988 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
990 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
991 goto disable_div_clk;
994 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
995 i2c_dev->adapter.owner = THIS_MODULE;
996 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
997 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
998 sizeof(i2c_dev->adapter.name));
999 i2c_dev->adapter.dev.parent = &pdev->dev;
1000 i2c_dev->adapter.nr = pdev->id;
1001 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1003 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1005 goto disable_div_clk;
1010 if (i2c_dev->is_multimaster_mode)
1011 clk_disable(i2c_dev->div_clk);
1014 pm_runtime_disable(&pdev->dev);
1015 if (!pm_runtime_status_suspended(&pdev->dev))
1016 tegra_i2c_runtime_suspend(&pdev->dev);
1019 clk_unprepare(i2c_dev->div_clk);
1022 if (!i2c_dev->hw->has_single_clk_source)
1023 clk_unprepare(i2c_dev->fast_clk);
1028 static int tegra_i2c_remove(struct platform_device *pdev)
1030 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1032 i2c_del_adapter(&i2c_dev->adapter);
1034 if (i2c_dev->is_multimaster_mode)
1035 clk_disable(i2c_dev->div_clk);
1037 pm_runtime_disable(&pdev->dev);
1038 if (!pm_runtime_status_suspended(&pdev->dev))
1039 tegra_i2c_runtime_suspend(&pdev->dev);
1041 clk_unprepare(i2c_dev->div_clk);
1042 if (!i2c_dev->hw->has_single_clk_source)
1043 clk_unprepare(i2c_dev->fast_clk);
1048 #ifdef CONFIG_PM_SLEEP
1049 static const struct dev_pm_ops tegra_i2c_pm = {
1050 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1053 #define TEGRA_I2C_PM (&tegra_i2c_pm)
1055 #define TEGRA_I2C_PM NULL
1058 static struct platform_driver tegra_i2c_driver = {
1059 .probe = tegra_i2c_probe,
1060 .remove = tegra_i2c_remove,
1062 .name = "tegra-i2c",
1063 .of_match_table = tegra_i2c_of_match,
1068 static int __init tegra_i2c_init_driver(void)
1070 return platform_driver_register(&tegra_i2c_driver);
1073 static void __exit tegra_i2c_exit_driver(void)
1075 platform_driver_unregister(&tegra_i2c_driver);
1078 subsys_initcall(tegra_i2c_init_driver);
1079 module_exit(tegra_i2c_exit_driver);
1081 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1082 MODULE_AUTHOR("Colin Cross");
1083 MODULE_LICENSE("GPL v2");