drivers/i2c/busses/i2c-sirf.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * I2C bus driver for CSR SiRFprimaII
   4  *
   5  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/i2c.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17
  18 #define SIRFSOC_I2C_CLK_CTRL            0x00
  19 #define SIRFSOC_I2C_STATUS              0x0C
  20 #define SIRFSOC_I2C_CTRL                0x10
  21 #define SIRFSOC_I2C_IO_CTRL             0x14
  22 #define SIRFSOC_I2C_SDA_DELAY           0x18
  23 #define SIRFSOC_I2C_CMD_START           0x1C
  24 #define SIRFSOC_I2C_CMD_BUF             0x30
  25 #define SIRFSOC_I2C_DATA_BUF            0x80
  26
  27 #define SIRFSOC_I2C_CMD_BUF_MAX         16
  28 #define SIRFSOC_I2C_DATA_BUF_MAX        16
  29
  30 #define SIRFSOC_I2C_CMD(x)              (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
  31 #define SIRFSOC_I2C_DATA_MASK(x)        (0xFF<<(((x)&3)*8))
  32 #define SIRFSOC_I2C_DATA_SHIFT(x)       (((x)&3)*8)
  33
  34 #define SIRFSOC_I2C_DIV_MASK            (0xFFFF)
  35
  36 /* I2C status flags */
  37 #define SIRFSOC_I2C_STAT_BUSY           BIT(0)
  38 #define SIRFSOC_I2C_STAT_TIP            BIT(1)
  39 #define SIRFSOC_I2C_STAT_NACK           BIT(2)
  40 #define SIRFSOC_I2C_STAT_TR_INT         BIT(4)
  41 #define SIRFSOC_I2C_STAT_STOP           BIT(6)
  42 #define SIRFSOC_I2C_STAT_CMD_DONE       BIT(8)
  43 #define SIRFSOC_I2C_STAT_ERR            BIT(9)
  44 #define SIRFSOC_I2C_CMD_INDEX           (0x1F<<16)
  45
  46 /* I2C control flags */
  47 #define SIRFSOC_I2C_RESET               BIT(0)
  48 #define SIRFSOC_I2C_CORE_EN             BIT(1)
  49 #define SIRFSOC_I2C_MASTER_MODE         BIT(2)
  50 #define SIRFSOC_I2C_CMD_DONE_EN         BIT(11)
  51 #define SIRFSOC_I2C_ERR_INT_EN          BIT(12)
  52
  53 #define SIRFSOC_I2C_SDA_DELAY_MASK      (0xFF)
  54 #define SIRFSOC_I2C_SCLF_FILTER         (3<<8)
  55
  56 #define SIRFSOC_I2C_START_CMD           BIT(0)
  57
  58 #define SIRFSOC_I2C_CMD_RP(x)           ((x)&0x7)
  59 #define SIRFSOC_I2C_NACK                BIT(3)
  60 #define SIRFSOC_I2C_WRITE               BIT(4)
  61 #define SIRFSOC_I2C_READ                BIT(5)
  62 #define SIRFSOC_I2C_STOP                BIT(6)
  63 #define SIRFSOC_I2C_START               BIT(7)
  64
  65 #define SIRFSOC_I2C_ERR_NOACK      1
  66 #define SIRFSOC_I2C_ERR_TIMEOUT    2
  67
  68 struct sirfsoc_i2c {
  69         void __iomem *base;
  70         struct clk *clk;
  71         u32 cmd_ptr;            /* Current position in CMD buffer */
  72         u8 *buf;                /* Buffer passed by user */
  73         u32 msg_len;            /* Message length */
  74         u32 finished_len;       /* number of bytes read/written */
  75         u32 read_cmd_len;       /* number of read cmd sent */
  76         int msg_read;           /* 1 indicates a read message */
  77         int err_status;         /* 1 indicates an error on bus */
  78
  79         u32 sda_delay;          /* For suspend/resume */
  80         u32 clk_div;
  81         int last;               /* Last message in transfer, STOP cmd can be sent */
  82
  83         struct completion done; /* indicates completion of message transfer */
  84         struct i2c_adapter adapter;
  85 };
  86
  87 static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
  88 {
  89         u32 data = 0;
  90         int i;
  91
  92         for (i = 0; i < siic->read_cmd_len; i++) {
  93                 if (!(i & 0x3))
  94                         data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
  95                 siic->buf[siic->finished_len++] =
  96                         (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
  97                                 SIRFSOC_I2C_DATA_SHIFT(i));
  98         }
  99 }
 100
 101 static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
 102 {
 103         u32 regval;
 104         int i = 0;
 105
 106         if (siic->msg_read) {
 107                 while (((siic->finished_len + i) < siic->msg_len)
 108                                 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
 109                         regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
 110                         if (((siic->finished_len + i) ==
 111                                         (siic->msg_len - 1)) && siic->last)
 112                                 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
 113                         writel(regval,
 114                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 115                         i++;
 116                 }
 117
 118                 siic->read_cmd_len = i;
 119         } else {
 120                 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
 121                                 && (siic->finished_len < siic->msg_len)) {
 122                         regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
 123                         if ((siic->finished_len == (siic->msg_len - 1))
 124                                 && siic->last)
 125                                 regval |= SIRFSOC_I2C_STOP;
 126                         writel(regval,
 127                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 128                         writel(siic->buf[siic->finished_len++],
 129                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 130                 }
 131         }
 132         siic->cmd_ptr = 0;
 133
 134         /* Trigger the transfer */
 135         writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
 136 }
 137
 138 static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
 139 {
 140         struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
 141         u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
 142
 143         if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
 144                 /* Error conditions */
 145                 siic->err_status = SIRFSOC_I2C_ERR_NOACK;
 146                 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
 147
 148                 if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
 149                         dev_dbg(&siic->adapter.dev, "ACK not received\n");
 150                 else
 151                         dev_err(&siic->adapter.dev, "I2C error\n");
 152
 153                 /*
 154                  * Due to hardware ANOMALY, we need to reset I2C earlier after
 155                  * we get NOACK while accessing non-existing clients, otherwise
 156                  * we will get errors even we access existing clients later
 157                  */
 158                 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
 159                                 siic->base + SIRFSOC_I2C_CTRL);
 160                 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 161                         cpu_relax();
 162
 163                 complete(&siic->done);
 164         } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
 165                 /* CMD buffer execution complete */
 166                 if (siic->msg_read)
 167                         i2c_sirfsoc_read_data(siic);
 168                 if (siic->finished_len == siic->msg_len)
 169                         complete(&siic->done);
 170                 else /* Fill a new CMD buffer for left data */
 171                         i2c_sirfsoc_queue_cmd(siic);
 172
 173                 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
 174         }
 175
 176         return IRQ_HANDLED;
 177 }
 178
 179 static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
 180         struct i2c_msg *msg)
 181 {
 182         unsigned char addr;
 183         u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
 184
 185         /* no data and last message -> add STOP */
 186         if (siic->last && (msg->len == 0))
 187                 regval |= SIRFSOC_I2C_STOP;
 188
 189         writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 190
 191         addr = i2c_8bit_addr_from_msg(msg);
 192
 193         /* Reverse direction bit */
 194         if (msg->flags & I2C_M_REV_DIR_ADDR)
 195                 addr ^= 1;
 196
 197         writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 198 }
 199
 200 static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
 201 {
 202         u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
 203         /* timeout waiting for the xfer to finish or fail */
 204         int timeout = msecs_to_jiffies((msg->len + 1) * 50);
 205
 206         i2c_sirfsoc_set_address(siic, msg);
 207
 208         writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
 209                 siic->base + SIRFSOC_I2C_CTRL);
 210         i2c_sirfsoc_queue_cmd(siic);
 211
 212         if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
 213                 siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
 214                 dev_err(&siic->adapter.dev, "Transfer timeout\n");
 215         }
 216
 217         writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
 218                 siic->base + SIRFSOC_I2C_CTRL);
 219         writel(0, siic->base + SIRFSOC_I2C_CMD_START);
 220
 221         /* i2c control doesn't response, reset it */
 222         if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
 223                 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
 224                         siic->base + SIRFSOC_I2C_CTRL);
 225                 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 226                         cpu_relax();
 227         }
 228         return siic->err_status ? -EAGAIN : 0;
 229 }
 230
 231 static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
 232 {
 233         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 234 }
 235
 236 static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 237         int num)
 238 {
 239         struct sirfsoc_i2c *siic = adap->algo_data;
 240         int i, ret;
 241
 242         clk_enable(siic->clk);
 243
 244         for (i = 0; i < num; i++) {
 245                 siic->buf = msgs[i].buf;
 246                 siic->msg_len = msgs[i].len;
 247                 siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
 248                 siic->err_status = 0;
 249                 siic->cmd_ptr = 0;
 250                 siic->finished_len = 0;
 251                 siic->last = (i == (num - 1));
 252
 253                 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
 254                 if (ret) {
 255                         clk_disable(siic->clk);
 256                         return ret;
 257                 }
 258         }
 259
 260         clk_disable(siic->clk);
 261         return num;
 262 }
 263
 264 /* I2C algorithms associated with this master controller driver */
 265 static const struct i2c_algorithm i2c_sirfsoc_algo = {
 266         .master_xfer = i2c_sirfsoc_xfer,
 267         .functionality = i2c_sirfsoc_func,
 268 };
 269
 270 static int i2c_sirfsoc_probe(struct platform_device *pdev)
 271 {
 272         struct sirfsoc_i2c *siic;
 273         struct i2c_adapter *adap;
 274         struct clk *clk;
 275         int bitrate;
 276         int ctrl_speed;
 277         int irq;
 278
 279         int err;
 280         u32 regval;
 281
 282         clk = clk_get(&pdev->dev, NULL);
 283         if (IS_ERR(clk)) {
 284                 err = PTR_ERR(clk);
 285                 dev_err(&pdev->dev, "Clock get failed\n");
 286                 goto err_get_clk;
 287         }
 288
 289         err = clk_prepare(clk);
 290         if (err) {
 291                 dev_err(&pdev->dev, "Clock prepare failed\n");
 292                 goto err_clk_prep;
 293         }
 294
 295         err = clk_enable(clk);
 296         if (err) {
 297                 dev_err(&pdev->dev, "Clock enable failed\n");
 298                 goto err_clk_en;
 299         }
 300
 301         ctrl_speed = clk_get_rate(clk);
 302
 303         siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
 304         if (!siic) {
 305                 err = -ENOMEM;
 306                 goto out;
 307         }
 308         adap = &siic->adapter;
 309         adap->class = I2C_CLASS_DEPRECATED;
 310
 311         siic->base = devm_platform_ioremap_resource(pdev, 0);
 312         if (IS_ERR(siic->base)) {
 313                 err = PTR_ERR(siic->base);
 314                 goto out;
 315         }
 316
 317         irq = platform_get_irq(pdev, 0);
 318         if (irq < 0) {
 319                 err = irq;
 320                 goto out;
 321         }
 322         err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
 323                 dev_name(&pdev->dev), siic);
 324         if (err)
 325                 goto out;
 326
 327         adap->algo = &i2c_sirfsoc_algo;
 328         adap->algo_data = siic;
 329         adap->retries = 3;
 330
 331         adap->dev.of_node = pdev->dev.of_node;
 332         adap->dev.parent = &pdev->dev;
 333         adap->nr = pdev->id;
 334
 335         strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
 336
 337         platform_set_drvdata(pdev, adap);
 338         init_completion(&siic->done);
 339
 340         /* Controller initialisation */
 341
 342         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 343         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 344                 cpu_relax();
 345         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 346                 siic->base + SIRFSOC_I2C_CTRL);
 347
 348         siic->clk = clk;
 349
 350         err = of_property_read_u32(pdev->dev.of_node,
 351                 "clock-frequency", &bitrate);
 352         if (err < 0)
 353                 bitrate = I2C_MAX_STANDARD_MODE_FREQ;
 354
 355         /*
 356          * Due to some hardware design issues, we need to tune the formula.
 357          * Since i2c is open drain interface that allows the slave to
 358          * stall the transaction by holding the SCL line at '0', the RTL
 359          * implementation is waiting for SCL feedback from the pin after
 360          * setting it to High-Z ('1'). This wait adds to the high-time
 361          * interval counter few cycles of the input synchronization
 362          * (depending on the SCL_FILTER_REG field), and also the time it
 363          * takes for the board pull-up resistor to rise the SCL line.
 364          * For slow SCL settings these additions are negligible,
 365          * but they start to affect the speed when clock is set to faster
 366          * frequencies.
 367          * Through the actual tests, use the different user_div value(which
 368          * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
 369          * the different ranges of i2c bus clock frequency, to make the SCL
 370          * more accurate.
 371          */
 372         if (bitrate <= 30000)
 373                 regval = ctrl_speed / (bitrate * 5);
 374         else if (bitrate > 30000 && bitrate <= 280000)
 375                 regval = (2 * ctrl_speed) / (bitrate * 11);
 376         else
 377                 regval = ctrl_speed / (bitrate * 6);
 378
 379         writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
 380         if (regval > 0xFF)
 381                 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
 382         else
 383                 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
 384
 385         err = i2c_add_numbered_adapter(adap);
 386         if (err < 0)
 387                 goto out;
 388
 389         clk_disable(clk);
 390
 391         dev_info(&pdev->dev, " I2C adapter ready to operate\n");
 392
 393         return 0;
 394
 395 out:
 396         clk_disable(clk);
 397 err_clk_en:
 398         clk_unprepare(clk);
 399 err_clk_prep:
 400         clk_put(clk);
 401 err_get_clk:
 402         return err;
 403 }
 404
 405 static int i2c_sirfsoc_remove(struct platform_device *pdev)
 406 {
 407         struct i2c_adapter *adapter = platform_get_drvdata(pdev);
 408         struct sirfsoc_i2c *siic = adapter->algo_data;
 409
 410         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 411         i2c_del_adapter(adapter);
 412         clk_unprepare(siic->clk);
 413         clk_put(siic->clk);
 414         return 0;
 415 }
 416
 417 #ifdef CONFIG_PM
 418 static int i2c_sirfsoc_suspend(struct device *dev)
 419 {
 420         struct i2c_adapter *adapter = dev_get_drvdata(dev);
 421         struct sirfsoc_i2c *siic = adapter->algo_data;
 422
 423         clk_enable(siic->clk);
 424         siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
 425         siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
 426         clk_disable(siic->clk);
 427         return 0;
 428 }
 429
 430 static int i2c_sirfsoc_resume(struct device *dev)
 431 {
 432         struct i2c_adapter *adapter = dev_get_drvdata(dev);
 433         struct sirfsoc_i2c *siic = adapter->algo_data;
 434
 435         clk_enable(siic->clk);
 436         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 437         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 438                 cpu_relax();
 439         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 440                 siic->base + SIRFSOC_I2C_CTRL);
 441         writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
 442         writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
 443         clk_disable(siic->clk);
 444         return 0;
 445 }
 446
 447 static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
 448         .suspend = i2c_sirfsoc_suspend,
 449         .resume = i2c_sirfsoc_resume,
 450 };
 451 #endif
 452
 453 static const struct of_device_id sirfsoc_i2c_of_match[] = {
 454         { .compatible = "sirf,prima2-i2c", },
 455         {},
 456 };
 457 MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
 458
 459 static struct platform_driver i2c_sirfsoc_driver = {
 460         .driver = {
 461                 .name = "sirfsoc_i2c",
 462 #ifdef CONFIG_PM
 463                 .pm = &i2c_sirfsoc_pm_ops,
 464 #endif
 465                 .of_match_table = sirfsoc_i2c_of_match,
 466         },
 467         .probe = i2c_sirfsoc_probe,
 468         .remove = i2c_sirfsoc_remove,
 469 };
 470 module_platform_driver(i2c_sirfsoc_driver);
 471
 472 MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
 473 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
 474 MODULE_AUTHOR("Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
 475 MODULE_LICENSE("GPL v2");