drivers/hwtracing/coresight/coresight-etm4x.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
   7 #define _CORESIGHT_CORESIGHT_ETM_H
   8
   9 #include <asm/local.h>
  10 #include <linux/spinlock.h>
  11 #include <linux/types.h>
  12 #include "coresight-priv.h"
  13
  14 /*
  15  * Device registers:
  16  * 0x000 - 0x2FC: Trace         registers
  17  * 0x300 - 0x314: Management    registers
  18  * 0x318 - 0xEFC: Trace         registers
  19  * 0xF00: Management            registers
  20  * 0xFA0 - 0xFA4: Trace         registers
  21  * 0xFA8 - 0xFFC: Management    registers
  22  */
  23 /* Trace registers (0x000-0x2FC) */
  24 /* Main control and configuration registers */
  25 #define TRCPRGCTLR                      0x004
  26 #define TRCPROCSELR                     0x008
  27 #define TRCSTATR                        0x00C
  28 #define TRCCONFIGR                      0x010
  29 #define TRCAUXCTLR                      0x018
  30 #define TRCEVENTCTL0R                   0x020
  31 #define TRCEVENTCTL1R                   0x024
  32 #define TRCSTALLCTLR                    0x02C
  33 #define TRCTSCTLR                       0x030
  34 #define TRCSYNCPR                       0x034
  35 #define TRCCCCTLR                       0x038
  36 #define TRCBBCTLR                       0x03C
  37 #define TRCTRACEIDR                     0x040
  38 #define TRCQCTLR                        0x044
  39 /* Filtering control registers */
  40 #define TRCVICTLR                       0x080
  41 #define TRCVIIECTLR                     0x084
  42 #define TRCVISSCTLR                     0x088
  43 #define TRCVIPCSSCTLR                   0x08C
  44 #define TRCVDCTLR                       0x0A0
  45 #define TRCVDSACCTLR                    0x0A4
  46 #define TRCVDARCCTLR                    0x0A8
  47 /* Derived resources registers */
  48 #define TRCSEQEVRn(n)                   (0x100 + (n * 4))
  49 #define TRCSEQRSTEVR                    0x118
  50 #define TRCSEQSTR                       0x11C
  51 #define TRCEXTINSELR                    0x120
  52 #define TRCCNTRLDVRn(n)                 (0x140 + (n * 4))
  53 #define TRCCNTCTLRn(n)                  (0x150 + (n * 4))
  54 #define TRCCNTVRn(n)                    (0x160 + (n * 4))
  55 /* ID registers */
  56 #define TRCIDR8                         0x180
  57 #define TRCIDR9                         0x184
  58 #define TRCIDR10                        0x188
  59 #define TRCIDR11                        0x18C
  60 #define TRCIDR12                        0x190
  61 #define TRCIDR13                        0x194
  62 #define TRCIMSPEC0                      0x1C0
  63 #define TRCIMSPECn(n)                   (0x1C0 + (n * 4))
  64 #define TRCIDR0                         0x1E0
  65 #define TRCIDR1                         0x1E4
  66 #define TRCIDR2                         0x1E8
  67 #define TRCIDR3                         0x1EC
  68 #define TRCIDR4                         0x1F0
  69 #define TRCIDR5                         0x1F4
  70 #define TRCIDR6                         0x1F8
  71 #define TRCIDR7                         0x1FC
  72 /* Resource selection registers */
  73 #define TRCRSCTLRn(n)                   (0x200 + (n * 4))
  74 /* Single-shot comparator registers */
  75 #define TRCSSCCRn(n)                    (0x280 + (n * 4))
  76 #define TRCSSCSRn(n)                    (0x2A0 + (n * 4))
  77 #define TRCSSPCICRn(n)                  (0x2C0 + (n * 4))
  78 /* Management registers (0x300-0x314) */
  79 #define TRCOSLAR                        0x300
  80 #define TRCOSLSR                        0x304
  81 #define TRCPDCR                         0x310
  82 #define TRCPDSR                         0x314
  83 /* Trace registers (0x318-0xEFC) */
  84 /* Comparator registers */
  85 #define TRCACVRn(n)                     (0x400 + (n * 8))
  86 #define TRCACATRn(n)                    (0x480 + (n * 8))
  87 #define TRCDVCVRn(n)                    (0x500 + (n * 16))
  88 #define TRCDVCMRn(n)                    (0x580 + (n * 16))
  89 #define TRCCIDCVRn(n)                   (0x600 + (n * 8))
  90 #define TRCVMIDCVRn(n)                  (0x640 + (n * 8))
  91 #define TRCCIDCCTLR0                    0x680
  92 #define TRCCIDCCTLR1                    0x684
  93 #define TRCVMIDCCTLR0                   0x688
  94 #define TRCVMIDCCTLR1                   0x68C
  95 /* Management register (0xF00) */
  96 /* Integration control registers */
  97 #define TRCITCTRL                       0xF00
  98 /* Trace registers (0xFA0-0xFA4) */
  99 /* Claim tag registers */
 100 #define TRCCLAIMSET                     0xFA0
 101 #define TRCCLAIMCLR                     0xFA4
 102 /* Management registers (0xFA8-0xFFC) */
 103 #define TRCDEVAFF0                      0xFA8
 104 #define TRCDEVAFF1                      0xFAC
 105 #define TRCLAR                          0xFB0
 106 #define TRCLSR                          0xFB4
 107 #define TRCAUTHSTATUS                   0xFB8
 108 #define TRCDEVARCH                      0xFBC
 109 #define TRCDEVID                        0xFC8
 110 #define TRCDEVTYPE                      0xFCC
 111 #define TRCPIDR4                        0xFD0
 112 #define TRCPIDR5                        0xFD4
 113 #define TRCPIDR6                        0xFD8
 114 #define TRCPIDR7                        0xFDC
 115 #define TRCPIDR0                        0xFE0
 116 #define TRCPIDR1                        0xFE4
 117 #define TRCPIDR2                        0xFE8
 118 #define TRCPIDR3                        0xFEC
 119 #define TRCCIDR0                        0xFF0
 120 #define TRCCIDR1                        0xFF4
 121 #define TRCCIDR2                        0xFF8
 122 #define TRCCIDR3                        0xFFC
 123
 124 #define etm4x_relaxed_read32(csa, offset)               \
 125         readl_relaxed((csa)->base + (offset))
 126
 127 #define etm4x_read32(csa, offset)                       \
 128         readl((csa)->base + (offset))
 129
 130 #define etm4x_relaxed_write32(csa, val, offset)         \
 131         writel_relaxed((val), (csa)->base + (offset))
 132
 133 #define etm4x_write32(csa, val, offset)                 \
 134         writel((val), (csa)->base + (offset))
 135
 136 #define etm4x_relaxed_read64(csa, offset)               \
 137         readq_relaxed((csa)->base + (offset))
 138
 139 #define etm4x_read64(csa, offset)                       \
 140         readq((csa)->base + (offset))
 141
 142 #define etm4x_relaxed_write64(csa, val, offset)         \
 143         writeq_relaxed((val), (csa)->base + (offset))
 144
 145 #define etm4x_write64(csa, val, offset)                 \
 146         writeq((val), (csa)->base + (offset))
 147
 148 /* ETMv4 resources */
 149 #define ETM_MAX_NR_PE                   8
 150 #define ETMv4_MAX_CNTR                  4
 151 #define ETM_MAX_SEQ_STATES              4
 152 #define ETM_MAX_EXT_INP_SEL             4
 153 #define ETM_MAX_EXT_INP                 256
 154 #define ETM_MAX_EXT_OUT                 4
 155 #define ETM_MAX_SINGLE_ADDR_CMP         16
 156 #define ETM_MAX_ADDR_RANGE_CMP          (ETM_MAX_SINGLE_ADDR_CMP / 2)
 157 #define ETM_MAX_DATA_VAL_CMP            8
 158 #define ETMv4_MAX_CTXID_CMP             8
 159 #define ETM_MAX_VMID_CMP                8
 160 #define ETM_MAX_PE_CMP                  8
 161 #define ETM_MAX_RES_SEL                 32
 162 #define ETM_MAX_SS_CMP                  8
 163
 164 #define ETM_ARCH_V4                     0x40
 165 #define ETMv4_SYNC_MASK                 0x1F
 166 #define ETM_CYC_THRESHOLD_MASK          0xFFF
 167 #define ETM_CYC_THRESHOLD_DEFAULT       0x100
 168 #define ETMv4_EVENT_MASK                0xFF
 169 #define ETM_CNTR_MAX_VAL                0xFFFF
 170 #define ETM_TRACEID_MASK                0x3f
 171
 172 /* ETMv4 programming modes */
 173 #define ETM_MODE_EXCLUDE                BIT(0)
 174 #define ETM_MODE_LOAD                   BIT(1)
 175 #define ETM_MODE_STORE                  BIT(2)
 176 #define ETM_MODE_LOAD_STORE             BIT(3)
 177 #define ETM_MODE_BB                     BIT(4)
 178 #define ETMv4_MODE_CYCACC               BIT(5)
 179 #define ETMv4_MODE_CTXID                BIT(6)
 180 #define ETM_MODE_VMID                   BIT(7)
 181 #define ETM_MODE_COND(val)              BMVAL(val, 8, 10)
 182 #define ETMv4_MODE_TIMESTAMP            BIT(11)
 183 #define ETM_MODE_RETURNSTACK            BIT(12)
 184 #define ETM_MODE_QELEM(val)             BMVAL(val, 13, 14)
 185 #define ETM_MODE_DATA_TRACE_ADDR        BIT(15)
 186 #define ETM_MODE_DATA_TRACE_VAL         BIT(16)
 187 #define ETM_MODE_ISTALL                 BIT(17)
 188 #define ETM_MODE_DSTALL                 BIT(18)
 189 #define ETM_MODE_ATB_TRIGGER            BIT(19)
 190 #define ETM_MODE_LPOVERRIDE             BIT(20)
 191 #define ETM_MODE_ISTALL_EN              BIT(21)
 192 #define ETM_MODE_DSTALL_EN              BIT(22)
 193 #define ETM_MODE_INSTPRIO               BIT(23)
 194 #define ETM_MODE_NOOVERFLOW             BIT(24)
 195 #define ETM_MODE_TRACE_RESET            BIT(25)
 196 #define ETM_MODE_TRACE_ERR              BIT(26)
 197 #define ETM_MODE_VIEWINST_STARTSTOP     BIT(27)
 198 #define ETMv4_MODE_ALL                  (GENMASK(27, 0) | \
 199                                          ETM_MODE_EXCL_KERN | \
 200                                          ETM_MODE_EXCL_USER)
 201
 202 #define TRCSTATR_IDLE_BIT               0
 203 #define TRCSTATR_PMSTABLE_BIT           1
 204 #define ETM_DEFAULT_ADDR_COMP           0
 205
 206 #define TRCSSCSRn_PC                    BIT(3)
 207
 208 /* PowerDown Control Register bits */
 209 #define TRCPDCR_PU                      BIT(3)
 210
 211 /* secure state access levels - TRCACATRn */
 212 #define ETM_EXLEVEL_S_APP               BIT(8)
 213 #define ETM_EXLEVEL_S_OS                BIT(9)
 214 #define ETM_EXLEVEL_S_HYP               BIT(10)
 215 #define ETM_EXLEVEL_S_MON               BIT(11)
 216 /* non-secure state access levels - TRCACATRn */
 217 #define ETM_EXLEVEL_NS_APP              BIT(12)
 218 #define ETM_EXLEVEL_NS_OS               BIT(13)
 219 #define ETM_EXLEVEL_NS_HYP              BIT(14)
 220 #define ETM_EXLEVEL_NS_NA               BIT(15)
 221
 222 /* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */
 223 #define ETM_EXLEVEL_LSHIFT_TRCVICTLR    8
 224
 225 /* secure / non secure masks - TRCVICTLR, IDR3 */
 226 #define ETM_EXLEVEL_S_VICTLR_MASK       GENMASK(19, 16)
 227 /* NS MON (EL3) mode never implemented */
 228 #define ETM_EXLEVEL_NS_VICTLR_MASK      GENMASK(22, 20)
 229
 230 /* Interpretation of resource numbers change at ETM v4.3 architecture */
 231 #define ETM4X_ARCH_4V3  0x43
 232
 233 enum etm_impdef_type {
 234         ETM4_IMPDEF_HISI_CORE_COMMIT,
 235         ETM4_IMPDEF_FEATURE_MAX,
 236 };
 237
 238 /**
 239  * struct etmv4_config - configuration information related to an ETMv4
 240  * @mode:       Controls various modes supported by this ETM.
 241  * @pe_sel:     Controls which PE to trace.
 242  * @cfg:        Controls the tracing options.
 243  * @eventctrl0: Controls the tracing of arbitrary events.
 244  * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
 245  * @stallctl:   If functionality that prevents trace unit buffer overflows
 246  *              is available.
 247  * @ts_ctrl:    Controls the insertion of global timestamps in the
 248  *              trace streams.
 249  * @syncfreq:   Controls how often trace synchronization requests occur.
 250  *              the TRCCCCTLR register.
 251  * @ccctlr:     Sets the threshold value for cycle counting.
 252  * @vinst_ctrl: Controls instruction trace filtering.
 253  * @viiectlr:   Set or read, the address range comparators.
 254  * @vissctlr:   Set, or read, the single address comparators that control the
 255  *              ViewInst start-stop logic.
 256  * @vipcssctlr: Set, or read, which PE comparator inputs can control the
 257  *              ViewInst start-stop logic.
 258  * @seq_idx:    Sequencor index selector.
 259  * @seq_ctrl:   Control for the sequencer state transition control register.
 260  * @seq_rst:    Moves the sequencer to state 0 when a programmed event occurs.
 261  * @seq_state:  Set, or read the sequencer state.
 262  * @cntr_idx:   Counter index seletor.
 263  * @cntrldvr:   Sets or returns the reload count value for a counter.
 264  * @cntr_ctrl:  Controls the operation of a counter.
 265  * @cntr_val:   Sets or returns the value for a counter.
 266  * @res_idx:    Resource index selector.
 267  * @res_ctrl:   Controls the selection of the resources in the trace unit.
 268  * @ss_idx:     Single-shot index selector.
 269  * @ss_ctrl:    Controls the corresponding single-shot comparator resource.
 270  * @ss_status:  The status of the corresponding single-shot comparator.
 271  * @ss_pe_cmp:  Selects the PE comparator inputs for Single-shot control.
 272  * @addr_idx:   Address comparator index selector.
 273  * @addr_val:   Value for address comparator.
 274  * @addr_acc:   Address comparator access type.
 275  * @addr_type:  Current status of the comparator register.
 276  * @ctxid_idx:  Context ID index selector.
 277  * @ctxid_pid:  Value of the context ID comparator.
 278  * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
 279  * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
 280  * @vmid_idx:   VM ID index selector.
 281  * @vmid_val:   Value of the VM ID comparator.
 282  * @vmid_mask0: VM ID comparator mask for comparator 0-3.
 283  * @vmid_mask1: VM ID comparator mask for comparator 4-7.
 284  * @ext_inp:    External input selection.
 285  * @arch:       ETM architecture version (for arch dependent config).
 286  */
 287 struct etmv4_config {
 288         u32                             mode;
 289         u32                             pe_sel;
 290         u32                             cfg;
 291         u32                             eventctrl0;
 292         u32                             eventctrl1;
 293         u32                             stall_ctrl;
 294         u32                             ts_ctrl;
 295         u32                             syncfreq;
 296         u32                             ccctlr;
 297         u32                             bb_ctrl;
 298         u32                             vinst_ctrl;
 299         u32                             viiectlr;
 300         u32                             vissctlr;
 301         u32                             vipcssctlr;
 302         u8                              seq_idx;
 303         u32                             seq_ctrl[ETM_MAX_SEQ_STATES];
 304         u32                             seq_rst;
 305         u32                             seq_state;
 306         u8                              cntr_idx;
 307         u32                             cntrldvr[ETMv4_MAX_CNTR];
 308         u32                             cntr_ctrl[ETMv4_MAX_CNTR];
 309         u32                             cntr_val[ETMv4_MAX_CNTR];
 310         u8                              res_idx;
 311         u32                             res_ctrl[ETM_MAX_RES_SEL];
 312         u8                              ss_idx;
 313         u32                             ss_ctrl[ETM_MAX_SS_CMP];
 314         u32                             ss_status[ETM_MAX_SS_CMP];
 315         u32                             ss_pe_cmp[ETM_MAX_SS_CMP];
 316         u8                              addr_idx;
 317         u64                             addr_val[ETM_MAX_SINGLE_ADDR_CMP];
 318         u64                             addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
 319         u8                              addr_type[ETM_MAX_SINGLE_ADDR_CMP];
 320         u8                              ctxid_idx;
 321         u64                             ctxid_pid[ETMv4_MAX_CTXID_CMP];
 322         u32                             ctxid_mask0;
 323         u32                             ctxid_mask1;
 324         u8                              vmid_idx;
 325         u64                             vmid_val[ETM_MAX_VMID_CMP];
 326         u32                             vmid_mask0;
 327         u32                             vmid_mask1;
 328         u32                             ext_inp;
 329         u8                              arch;
 330 };
 331
 332 /**
 333  * struct etm4_save_state - state to be preserved when ETM is without power
 334  */
 335 struct etmv4_save_state {
 336         u32     trcprgctlr;
 337         u32     trcprocselr;
 338         u32     trcconfigr;
 339         u32     trcauxctlr;
 340         u32     trceventctl0r;
 341         u32     trceventctl1r;
 342         u32     trcstallctlr;
 343         u32     trctsctlr;
 344         u32     trcsyncpr;
 345         u32     trcccctlr;
 346         u32     trcbbctlr;
 347         u32     trctraceidr;
 348         u32     trcqctlr;
 349
 350         u32     trcvictlr;
 351         u32     trcviiectlr;
 352         u32     trcvissctlr;
 353         u32     trcvipcssctlr;
 354         u32     trcvdctlr;
 355         u32     trcvdsacctlr;
 356         u32     trcvdarcctlr;
 357
 358         u32     trcseqevr[ETM_MAX_SEQ_STATES];
 359         u32     trcseqrstevr;
 360         u32     trcseqstr;
 361         u32     trcextinselr;
 362         u32     trccntrldvr[ETMv4_MAX_CNTR];
 363         u32     trccntctlr[ETMv4_MAX_CNTR];
 364         u32     trccntvr[ETMv4_MAX_CNTR];
 365
 366         u32     trcrsctlr[ETM_MAX_RES_SEL];
 367
 368         u32     trcssccr[ETM_MAX_SS_CMP];
 369         u32     trcsscsr[ETM_MAX_SS_CMP];
 370         u32     trcsspcicr[ETM_MAX_SS_CMP];
 371
 372         u64     trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
 373         u64     trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
 374         u64     trccidcvr[ETMv4_MAX_CTXID_CMP];
 375         u64     trcvmidcvr[ETM_MAX_VMID_CMP];
 376         u32     trccidcctlr0;
 377         u32     trccidcctlr1;
 378         u32     trcvmidcctlr0;
 379         u32     trcvmidcctlr1;
 380
 381         u32     trcclaimset;
 382
 383         u32     cntr_val[ETMv4_MAX_CNTR];
 384         u32     seq_state;
 385         u32     vinst_ctrl;
 386         u32     ss_status[ETM_MAX_SS_CMP];
 387
 388         u32     trcpdcr;
 389 };
 390
 391 /**
 392  * struct etm4_drvdata - specifics associated to an ETM component
 393  * @base:       Memory mapped base address for this component.
 394  * @csdev:      Component vitals needed by the framework.
 395  * @spinlock:   Only one at a time pls.
 396  * @mode:       This tracer's mode, i.e sysFS, Perf or disabled.
 397  * @cpu:        The cpu this component is affined to.
 398  * @arch:       ETM version number.
 399  * @nr_pe:      The number of processing entity available for tracing.
 400  * @nr_pe_cmp:  The number of processing entity comparator inputs that are
 401  *              available for tracing.
 402  * @nr_addr_cmp:Number of pairs of address comparators available
 403  *              as found in ETMIDR4 0-3.
 404  * @nr_cntr:    Number of counters as found in ETMIDR5 bit 28-30.
 405  * @nr_ext_inp: Number of external input.
 406  * @numcidc:    Number of contextID comparators.
 407  * @numvmidc:   Number of VMID comparators.
 408  * @nrseqstate: The number of sequencer states that are implemented.
 409  * @nr_event:   Indicates how many events the trace unit support.
 410  * @nr_resource:The number of resource selection pairs available for tracing.
 411  * @nr_ss_cmp:  Number of single-shot comparator controls that are available.
 412  * @trcid:      value of the current ID for this component.
 413  * @trcid_size: Indicates the trace ID width.
 414  * @ts_size:    Global timestamp size field.
 415  * @ctxid_size: Size of the context ID field to consider.
 416  * @vmid_size:  Size of the VM ID comparator to consider.
 417  * @ccsize:     Indicates the size of the cycle counter in bits.
 418  * @ccitmin:    minimum value that can be programmed in
 419  * @s_ex_level: In secure state, indicates whether instruction tracing is
 420  *              supported for the corresponding Exception level.
 421  * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
 422  *              supported for the corresponding Exception level.
 423  * @sticky_enable: true if ETM base configuration has been done.
 424  * @boot_enable:True if we should start tracing at boot time.
 425  * @os_unlock:  True if access to management registers is allowed.
 426  * @instrp0:    Tracing of load and store instructions
 427  *              as P0 elements is supported.
 428  * @trcbb:      Indicates if the trace unit supports branch broadcast tracing.
 429  * @trccond:    If the trace unit supports conditional
 430  *              instruction tracing.
 431  * @retstack:   Indicates if the implementation supports a return stack.
 432  * @trccci:     Indicates if the trace unit supports cycle counting
 433  *              for instruction.
 434  * @q_support:  Q element support characteristics.
 435  * @trc_error:  Whether a trace unit can trace a system
 436  *              error exception.
 437  * @syncpr:     Indicates if an implementation has a fixed
 438  *              synchronization period.
 439  * @stall_ctrl: Enables trace unit functionality that prevents trace
 440  *              unit buffer overflows.
 441  * @sysstall:   Does the system support stall control of the PE?
 442  * @nooverflow: Indicate if overflow prevention is supported.
 443  * @atbtrig:    If the implementation can support ATB triggers
 444  * @lpoverride: If the implementation can support low-power state over.
 445  * @config:     structure holding configuration parameters.
 446  * @save_state: State to be preserved across power loss
 447  * @state_needs_restore: True when there is context to restore after PM exit
 448  * @skip_power_up: Indicates if an implementation can skip powering up
 449  *                 the trace unit.
 450  * @arch_features: Bitmap of arch features of etmv4 devices.
 451  */
 452 struct etmv4_drvdata {
 453         void __iomem                    *base;
 454         struct coresight_device         *csdev;
 455         spinlock_t                      spinlock;
 456         local_t                         mode;
 457         int                             cpu;
 458         u8                              arch;
 459         u8                              nr_pe;
 460         u8                              nr_pe_cmp;
 461         u8                              nr_addr_cmp;
 462         u8                              nr_cntr;
 463         u8                              nr_ext_inp;
 464         u8                              numcidc;
 465         u8                              numvmidc;
 466         u8                              nrseqstate;
 467         u8                              nr_event;
 468         u8                              nr_resource;
 469         u8                              nr_ss_cmp;
 470         u8                              trcid;
 471         u8                              trcid_size;
 472         u8                              ts_size;
 473         u8                              ctxid_size;
 474         u8                              vmid_size;
 475         u8                              ccsize;
 476         u8                              ccitmin;
 477         u8                              s_ex_level;
 478         u8                              ns_ex_level;
 479         u8                              q_support;
 480         bool                            sticky_enable;
 481         bool                            boot_enable;
 482         bool                            os_unlock;
 483         bool                            instrp0;
 484         bool                            trcbb;
 485         bool                            trccond;
 486         bool                            retstack;
 487         bool                            trccci;
 488         bool                            trc_error;
 489         bool                            syncpr;
 490         bool                            stallctl;
 491         bool                            sysstall;
 492         bool                            nooverflow;
 493         bool                            atbtrig;
 494         bool                            lpoverride;
 495         struct etmv4_config             config;
 496         struct etmv4_save_state         *save_state;
 497         bool                            state_needs_restore;
 498         bool                            skip_power_up;
 499         DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
 500 };
 501
 502 /* Address comparator access types */
 503 enum etm_addr_acctype {
 504         ETM_INSTR_ADDR,
 505         ETM_DATA_LOAD_ADDR,
 506         ETM_DATA_STORE_ADDR,
 507         ETM_DATA_LOAD_STORE_ADDR,
 508 };
 509
 510 /* Address comparator context types */
 511 enum etm_addr_ctxtype {
 512         ETM_CTX_NONE,
 513         ETM_CTX_CTXID,
 514         ETM_CTX_VMID,
 515         ETM_CTX_CTXID_VMID,
 516 };
 517
 518 extern const struct attribute_group *coresight_etmv4_groups[];
 519 void etm4_config_trace_mode(struct etmv4_config *config);
 520 #endif