drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/property.h>
  32
  33 #include <asm/sections.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/local.h>
  36 #include <asm/virt.h>
  37
  38 #include "coresight-etm4x.h"
  39 #include "coresight-etm-perf.h"
  40
  41 static int boot_enable;
  42 module_param(boot_enable, int, 0444);
  43 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  44
  45 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  46 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  47 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  48
  49 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  50 module_param(pm_save_enable, int, 0444);
  51 MODULE_PARM_DESC(pm_save_enable,
  52         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  53
  54 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  55 static void etm4_set_default_config(struct etmv4_config *config);
  56 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  57                                   struct perf_event *event);
  58 static u64 etm4_get_access_type(struct etmv4_config *config);
  59
  60 static enum cpuhp_state hp_online;
  61
  62 struct etm4_init_arg {
  63         unsigned int            pid;
  64         struct etmv4_drvdata    *drvdata;
  65         struct csdev_access     *csa;
  66 };
  67
  68 /*
  69  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  70  *
  71  * TRCSSPCICRn is implemented only if :
  72  *      TRCSSPCICR<n> is present only if all of the following are true:
  73  *              TRCIDR4.NUMSSCC > n.
  74  *              TRCIDR4.NUMPC > 0b0000 .
  75  *              TRCSSCSR<n>.PC == 0b1
  76  */
  77 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  78 {
  79         return (n < drvdata->nr_ss_cmp) &&
  80                drvdata->nr_pe &&
  81                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  82 }
  83
  84 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  85 {
  86         u64 res = 0;
  87
  88         switch (offset) {
  89         ETM4x_READ_SYSREG_CASES(res)
  90         default :
  91                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
  92                          offset);
  93         }
  94
  95         if (!_relaxed)
  96                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
  97
  98         return res;
  99 }
 100
 101 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 102 {
 103         if (!_relaxed)
 104                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 105         if (!_64bit)
 106                 val &= GENMASK(31, 0);
 107
 108         switch (offset) {
 109         ETM4x_WRITE_SYSREG_CASES(val)
 110         default :
 111                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 112                         offset);
 113         }
 114 }
 115
 116 static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
 117 {
 118         /* Writing 0 to TRCOSLAR unlocks the trace registers */
 119         etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
 120         drvdata->os_unlock = true;
 121         isb();
 122 }
 123
 124 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 125 {
 126         if (!WARN_ON(!drvdata->csdev))
 127                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 128
 129 }
 130
 131 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 132 {
 133         if (WARN_ON(!drvdata->csdev))
 134                 return;
 135
 136         /* Writing 0x1 to TRCOSLAR locks the trace registers */
 137         etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
 138         drvdata->os_unlock = false;
 139         isb();
 140 }
 141
 142 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 143                          struct csdev_access *csa)
 144 {
 145         /* Software Lock is only accessible via memory mapped interface */
 146         if (csa->io_mem)
 147                 CS_LOCK(csa->base);
 148 }
 149
 150 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 151                            struct csdev_access *csa)
 152 {
 153         if (csa->io_mem)
 154                 CS_UNLOCK(csa->base);
 155 }
 156
 157 static int etm4_cpu_id(struct coresight_device *csdev)
 158 {
 159         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 160
 161         return drvdata->cpu;
 162 }
 163
 164 static int etm4_trace_id(struct coresight_device *csdev)
 165 {
 166         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 167
 168         return drvdata->trcid;
 169 }
 170
 171 struct etm4_enable_arg {
 172         struct etmv4_drvdata *drvdata;
 173         int rc;
 174 };
 175
 176 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 177
 178 #define HISI_HIP08_AMBA_ID              0x000b6d01
 179 #define ETM4_AMBA_MASK                  0xfffff
 180 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 181 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 182 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 183 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 184 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 185
 186 struct etm4_arch_features {
 187         void (*arch_callback)(bool enable);
 188 };
 189
 190 static bool etm4_hisi_match_pid(unsigned int id)
 191 {
 192         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 193 }
 194
 195 static void etm4_hisi_config_core_commit(bool enable)
 196 {
 197         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 198                     HISI_HIP08_CORE_COMMIT_FULL;
 199         u64 val;
 200
 201         /*
 202          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 203          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 204          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 205          * speed(minimun value). So bit 12 and 13 should be cleared together.
 206          */
 207         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 208         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 209         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 210         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 211 }
 212
 213 static struct etm4_arch_features etm4_features[] = {
 214         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 215                 .arch_callback = etm4_hisi_config_core_commit,
 216         },
 217         {},
 218 };
 219
 220 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 221 {
 222         struct etm4_arch_features *ftr;
 223         int bit;
 224
 225         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 226                 ftr = &etm4_features[bit];
 227
 228                 if (ftr->arch_callback)
 229                         ftr->arch_callback(true);
 230         }
 231 }
 232
 233 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 234 {
 235         struct etm4_arch_features *ftr;
 236         int bit;
 237
 238         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 239                 ftr = &etm4_features[bit];
 240
 241                 if (ftr->arch_callback)
 242                         ftr->arch_callback(false);
 243         }
 244 }
 245
 246 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 247                                       unsigned int id)
 248 {
 249         if (etm4_hisi_match_pid(id))
 250                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 251 }
 252 #else
 253 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 254 {
 255 }
 256
 257 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 258 {
 259 }
 260
 261 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 262                                      unsigned int id)
 263 {
 264 }
 265 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 266
 267 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 268 {
 269         int i, rc;
 270         struct etmv4_config *config = &drvdata->config;
 271         struct coresight_device *csdev = drvdata->csdev;
 272         struct device *etm_dev = &csdev->dev;
 273         struct csdev_access *csa = &csdev->access;
 274
 275
 276         etm4_cs_unlock(drvdata, csa);
 277         etm4_enable_arch_specific(drvdata);
 278
 279         etm4_os_unlock(drvdata);
 280
 281         rc = coresight_claim_device_unlocked(csdev);
 282         if (rc)
 283                 goto done;
 284
 285         /* Disable the trace unit before programming trace registers */
 286         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 287
 288         /*
 289          * If we use system instructions, we need to synchronize the
 290          * write to the TRCPRGCTLR, before accessing the TRCSTATR.
 291          * See ARM IHI0064F, section
 292          * "4.3.7 Synchronization of register updates"
 293          */
 294         if (!csa->io_mem)
 295                 isb();
 296
 297         /* wait for TRCSTATR.IDLE to go up */
 298         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 299                 dev_err(etm_dev,
 300                         "timeout while waiting for Idle Trace Status\n");
 301         if (drvdata->nr_pe)
 302                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 303         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 304         /* nothing specific implemented */
 305         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 306         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 307         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 308         etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 309         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 310         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 311         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 312         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 313         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 314         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 315         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 316         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 317         if (drvdata->nr_pe_cmp)
 318                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 319         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 320                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 321         etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 322         etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 323         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 324         for (i = 0; i < drvdata->nr_cntr; i++) {
 325                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 326                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 327                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 328         }
 329
 330         /*
 331          * Resource selector pair 0 is always implemented and reserved.  As
 332          * such start at 2.
 333          */
 334         for (i = 2; i < drvdata->nr_resource * 2; i++)
 335                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 336
 337         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 338                 /* always clear status bit on restart if using single-shot */
 339                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 340                         config->ss_status[i] &= ~BIT(31);
 341                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 342                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 343                 if (etm4x_sspcicrn_present(drvdata, i))
 344                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 345         }
 346         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 347                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 348                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 349         }
 350         for (i = 0; i < drvdata->numcidc; i++)
 351                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 352         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 353         if (drvdata->numcidc > 4)
 354                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 355
 356         for (i = 0; i < drvdata->numvmidc; i++)
 357                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 358         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 359         if (drvdata->numvmidc > 4)
 360                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 361
 362         if (!drvdata->skip_power_up) {
 363                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 364
 365                 /*
 366                  * Request to keep the trace unit powered and also
 367                  * emulation of powerdown
 368                  */
 369                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 370         }
 371
 372         /* Enable the trace unit */
 373         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 374
 375         /* Synchronize the register updates for sysreg access */
 376         if (!csa->io_mem)
 377                 isb();
 378
 379         /* wait for TRCSTATR.IDLE to go back down to '0' */
 380         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 381                 dev_err(etm_dev,
 382                         "timeout while waiting for Idle Trace Status\n");
 383
 384         /*
 385          * As recommended by section 4.3.7 ("Synchronization when using the
 386          * memory-mapped interface") of ARM IHI 0064D
 387          */
 388         dsb(sy);
 389         isb();
 390
 391 done:
 392         etm4_cs_lock(drvdata, csa);
 393
 394         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 395                 drvdata->cpu, rc);
 396         return rc;
 397 }
 398
 399 static void etm4_enable_hw_smp_call(void *info)
 400 {
 401         struct etm4_enable_arg *arg = info;
 402
 403         if (WARN_ON(!arg))
 404                 return;
 405         arg->rc = etm4_enable_hw(arg->drvdata);
 406 }
 407
 408 /*
 409  * The goal of function etm4_config_timestamp_event() is to configure a
 410  * counter that will tell the tracer to emit a timestamp packet when it
 411  * reaches zero.  This is done in order to get a more fine grained idea
 412  * of when instructions are executed so that they can be correlated
 413  * with execution on other CPUs.
 414  *
 415  * To do this the counter itself is configured to self reload and
 416  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 417  * there a resource selector is configured with the counter and the
 418  * timestamp control register to use the resource selector to trigger the
 419  * event that will insert a timestamp packet in the stream.
 420  */
 421 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 422 {
 423         int ctridx, ret = -EINVAL;
 424         int counter, rselector;
 425         u32 val = 0;
 426         struct etmv4_config *config = &drvdata->config;
 427
 428         /* No point in trying if we don't have at least one counter */
 429         if (!drvdata->nr_cntr)
 430                 goto out;
 431
 432         /* Find a counter that hasn't been initialised */
 433         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 434                 if (config->cntr_val[ctridx] == 0)
 435                         break;
 436
 437         /* All the counters have been configured already, bail out */
 438         if (ctridx == drvdata->nr_cntr) {
 439                 pr_debug("%s: no available counter found\n", __func__);
 440                 ret = -ENOSPC;
 441                 goto out;
 442         }
 443
 444         /*
 445          * Searching for an available resource selector to use, starting at
 446          * '2' since every implementation has at least 2 resource selector.
 447          * ETMIDR4 gives the number of resource selector _pairs_,
 448          * hence multiply by 2.
 449          */
 450         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 451                 if (!config->res_ctrl[rselector])
 452                         break;
 453
 454         if (rselector == drvdata->nr_resource * 2) {
 455                 pr_debug("%s: no available resource selector found\n",
 456                          __func__);
 457                 ret = -ENOSPC;
 458                 goto out;
 459         }
 460
 461         /* Remember what counter we used */
 462         counter = 1 << ctridx;
 463
 464         /*
 465          * Initialise original and reload counter value to the smallest
 466          * possible value in order to get as much precision as we can.
 467          */
 468         config->cntr_val[ctridx] = 1;
 469         config->cntrldvr[ctridx] = 1;
 470
 471         /* Set the trace counter control register */
 472         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 473                0x0 << 7         |  /* Select single resource selector */
 474                0x1;                /* Resource selector 1, i.e always true */
 475
 476         config->cntr_ctrl[ctridx] = val;
 477
 478         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 479               counter << 0;       /* Counter to use */
 480
 481         config->res_ctrl[rselector] = val;
 482
 483         val = 0x0 << 7          | /* Select single resource selector */
 484               rselector;          /* Resource selector */
 485
 486         config->ts_ctrl = val;
 487
 488         ret = 0;
 489 out:
 490         return ret;
 491 }
 492
 493 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 494                                    struct perf_event *event)
 495 {
 496         int ret = 0;
 497         struct etmv4_config *config = &drvdata->config;
 498         struct perf_event_attr *attr = &event->attr;
 499
 500         if (!attr) {
 501                 ret = -EINVAL;
 502                 goto out;
 503         }
 504
 505         /* Clear configuration from previous run */
 506         memset(config, 0, sizeof(struct etmv4_config));
 507
 508         if (attr->exclude_kernel)
 509                 config->mode = ETM_MODE_EXCL_KERN;
 510
 511         if (attr->exclude_user)
 512                 config->mode = ETM_MODE_EXCL_USER;
 513
 514         /* Always start from the default config */
 515         etm4_set_default_config(config);
 516
 517         /* Configure filters specified on the perf cmd line, if any. */
 518         ret = etm4_set_event_filters(drvdata, event);
 519         if (ret)
 520                 goto out;
 521
 522         /* Go from generic option to ETMv4 specifics */
 523         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 524                 config->cfg |= BIT(4);
 525                 /* TRM: Must program this for cycacc to work */
 526                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 527         }
 528         if (attr->config & BIT(ETM_OPT_TS)) {
 529                 /*
 530                  * Configure timestamps to be emitted at regular intervals in
 531                  * order to correlate instructions executed on different CPUs
 532                  * (CPU-wide trace scenarios).
 533                  */
 534                 ret = etm4_config_timestamp_event(drvdata);
 535
 536                 /*
 537                  * No need to go further if timestamp intervals can't
 538                  * be configured.
 539                  */
 540                 if (ret)
 541                         goto out;
 542
 543                 /* bit[11], Global timestamp tracing bit */
 544                 config->cfg |= BIT(11);
 545         }
 546
 547         if (attr->config & BIT(ETM_OPT_CTXTID))
 548                 /* bit[6], Context ID tracing bit */
 549                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 550
 551         /* return stack - enable if selected and supported */
 552         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 553                 /* bit[12], Return stack enable bit */
 554                 config->cfg |= BIT(12);
 555
 556 out:
 557         return ret;
 558 }
 559
 560 static int etm4_enable_perf(struct coresight_device *csdev,
 561                             struct perf_event *event)
 562 {
 563         int ret = 0;
 564         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 565
 566         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 567                 ret = -EINVAL;
 568                 goto out;
 569         }
 570
 571         /* Configure the tracer based on the session's specifics */
 572         ret = etm4_parse_event_config(drvdata, event);
 573         if (ret)
 574                 goto out;
 575         /* And enable it */
 576         ret = etm4_enable_hw(drvdata);
 577
 578 out:
 579         return ret;
 580 }
 581
 582 static int etm4_enable_sysfs(struct coresight_device *csdev)
 583 {
 584         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 585         struct etm4_enable_arg arg = { };
 586         int ret;
 587
 588         spin_lock(&drvdata->spinlock);
 589
 590         /*
 591          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 592          * ensures that register writes occur when cpu is powered.
 593          */
 594         arg.drvdata = drvdata;
 595         ret = smp_call_function_single(drvdata->cpu,
 596                                        etm4_enable_hw_smp_call, &arg, 1);
 597         if (!ret)
 598                 ret = arg.rc;
 599         if (!ret)
 600                 drvdata->sticky_enable = true;
 601         spin_unlock(&drvdata->spinlock);
 602
 603         if (!ret)
 604                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 605         return ret;
 606 }
 607
 608 static int etm4_enable(struct coresight_device *csdev,
 609                        struct perf_event *event, u32 mode)
 610 {
 611         int ret;
 612         u32 val;
 613         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 614
 615         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 616
 617         /* Someone is already using the tracer */
 618         if (val)
 619                 return -EBUSY;
 620
 621         switch (mode) {
 622         case CS_MODE_SYSFS:
 623                 ret = etm4_enable_sysfs(csdev);
 624                 break;
 625         case CS_MODE_PERF:
 626                 ret = etm4_enable_perf(csdev, event);
 627                 break;
 628         default:
 629                 ret = -EINVAL;
 630         }
 631
 632         /* The tracer didn't start */
 633         if (ret)
 634                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 635
 636         return ret;
 637 }
 638
 639 static void etm4_disable_hw(void *info)
 640 {
 641         u32 control;
 642         struct etmv4_drvdata *drvdata = info;
 643         struct etmv4_config *config = &drvdata->config;
 644         struct coresight_device *csdev = drvdata->csdev;
 645         struct device *etm_dev = &csdev->dev;
 646         struct csdev_access *csa = &csdev->access;
 647         int i;
 648
 649         etm4_cs_unlock(drvdata, csa);
 650         etm4_disable_arch_specific(drvdata);
 651
 652         if (!drvdata->skip_power_up) {
 653                 /* power can be removed from the trace unit now */
 654                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 655                 control &= ~TRCPDCR_PU;
 656                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 657         }
 658
 659         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 660
 661         /* EN, bit[0] Trace unit enable bit */
 662         control &= ~0x1;
 663
 664         /*
 665          * Make sure everything completes before disabling, as recommended
 666          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 667          * SSTATUS") of ARM IHI 0064D
 668          */
 669         dsb(sy);
 670         isb();
 671         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 672
 673         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 674         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 675                 dev_err(etm_dev,
 676                         "timeout while waiting for PM stable Trace Status\n");
 677
 678         /* read the status of the single shot comparators */
 679         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 680                 config->ss_status[i] =
 681                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 682         }
 683
 684         /* read back the current counter values */
 685         for (i = 0; i < drvdata->nr_cntr; i++) {
 686                 config->cntr_val[i] =
 687                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 688         }
 689
 690         coresight_disclaim_device_unlocked(csdev);
 691         etm4_cs_lock(drvdata, csa);
 692
 693         dev_dbg(&drvdata->csdev->dev,
 694                 "cpu: %d disable smp call done\n", drvdata->cpu);
 695 }
 696
 697 static int etm4_disable_perf(struct coresight_device *csdev,
 698                              struct perf_event *event)
 699 {
 700         u32 control;
 701         struct etm_filters *filters = event->hw.addr_filters;
 702         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 703
 704         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 705                 return -EINVAL;
 706
 707         etm4_disable_hw(drvdata);
 708
 709         /*
 710          * Check if the start/stop logic was active when the unit was stopped.
 711          * That way we can re-enable the start/stop logic when the process is
 712          * scheduled again.  Configuration of the start/stop logic happens in
 713          * function etm4_set_event_filters().
 714          */
 715         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 716         /* TRCVICTLR::SSSTATUS, bit[9] */
 717         filters->ssstatus = (control & BIT(9));
 718
 719         return 0;
 720 }
 721
 722 static void etm4_disable_sysfs(struct coresight_device *csdev)
 723 {
 724         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 725
 726         /*
 727          * Taking hotplug lock here protects from clocks getting disabled
 728          * with tracing being left on (crash scenario) if user disable occurs
 729          * after cpu online mask indicates the cpu is offline but before the
 730          * DYING hotplug callback is serviced by the ETM driver.
 731          */
 732         cpus_read_lock();
 733         spin_lock(&drvdata->spinlock);
 734
 735         /*
 736          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 737          * ensures that register writes occur when cpu is powered.
 738          */
 739         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 740
 741         spin_unlock(&drvdata->spinlock);
 742         cpus_read_unlock();
 743
 744         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 745 }
 746
 747 static void etm4_disable(struct coresight_device *csdev,
 748                          struct perf_event *event)
 749 {
 750         u32 mode;
 751         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 752
 753         /*
 754          * For as long as the tracer isn't disabled another entity can't
 755          * change its status.  As such we can read the status here without
 756          * fearing it will change under us.
 757          */
 758         mode = local_read(&drvdata->mode);
 759
 760         switch (mode) {
 761         case CS_MODE_DISABLED:
 762                 break;
 763         case CS_MODE_SYSFS:
 764                 etm4_disable_sysfs(csdev);
 765                 break;
 766         case CS_MODE_PERF:
 767                 etm4_disable_perf(csdev, event);
 768                 break;
 769         }
 770
 771         if (mode)
 772                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 773 }
 774
 775 static const struct coresight_ops_source etm4_source_ops = {
 776         .cpu_id         = etm4_cpu_id,
 777         .trace_id       = etm4_trace_id,
 778         .enable         = etm4_enable,
 779         .disable        = etm4_disable,
 780 };
 781
 782 static const struct coresight_ops etm4_cs_ops = {
 783         .source_ops     = &etm4_source_ops,
 784 };
 785
 786 static inline bool cpu_supports_sysreg_trace(void)
 787 {
 788         u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
 789
 790         return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
 791 }
 792
 793 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
 794                                     struct csdev_access *csa)
 795 {
 796         u32 devarch;
 797
 798         if (!cpu_supports_sysreg_trace())
 799                 return false;
 800
 801         /*
 802          * ETMs implementing sysreg access must implement TRCDEVARCH.
 803          */
 804         devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
 805         if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
 806                 return false;
 807         *csa = (struct csdev_access) {
 808                 .io_mem = false,
 809                 .read   = etm4x_sysreg_read,
 810                 .write  = etm4x_sysreg_write,
 811         };
 812
 813         drvdata->arch = etm_devarch_to_arch(devarch);
 814         return true;
 815 }
 816
 817 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
 818                                    struct csdev_access *csa)
 819 {
 820         u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
 821         u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
 822
 823         /*
 824          * All ETMs must implement TRCDEVARCH to indicate that
 825          * the component is an ETMv4. To support any broken
 826          * implementations we fall back to TRCIDR1 check, which
 827          * is not really reliable.
 828          */
 829         if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
 830                 drvdata->arch = etm_devarch_to_arch(devarch);
 831         } else {
 832                 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
 833                         smp_processor_id(), devarch);
 834
 835                 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
 836                         return false;
 837                 drvdata->arch = etm_trcidr_to_arch(idr1);
 838         }
 839
 840         *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 841         return true;
 842 }
 843
 844 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
 845                                    struct csdev_access *csa)
 846 {
 847         /*
 848          * Always choose the memory mapped io, if there is
 849          * a memory map to prevent sysreg access on broken
 850          * systems.
 851          */
 852         if (drvdata->base)
 853                 return etm4_init_iomem_access(drvdata, csa);
 854
 855         if (etm4_init_sysreg_access(drvdata, csa))
 856                 return true;
 857
 858         return false;
 859 }
 860
 861 static void etm4_init_arch_data(void *info)
 862 {
 863         u32 etmidr0;
 864         u32 etmidr2;
 865         u32 etmidr3;
 866         u32 etmidr4;
 867         u32 etmidr5;
 868         struct etm4_init_arg *init_arg = info;
 869         struct etmv4_drvdata *drvdata;
 870         struct csdev_access *csa;
 871         int i;
 872
 873         drvdata = init_arg->drvdata;
 874         csa = init_arg->csa;
 875
 876         /*
 877          * If we are unable to detect the access mechanism,
 878          * or unable to detect the trace unit type, fail
 879          * early.
 880          */
 881         if (!etm4_init_csdev_access(drvdata, csa))
 882                 return;
 883
 884         /* Make sure all registers are accessible */
 885         etm4_os_unlock_csa(drvdata, csa);
 886         etm4_cs_unlock(drvdata, csa);
 887
 888         etm4_check_arch_features(drvdata, init_arg->pid);
 889
 890         /* find all capabilities of the tracing unit */
 891         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
 892
 893         /* INSTP0, bits[2:1] P0 tracing support field */
 894         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 895                 drvdata->instrp0 = true;
 896         else
 897                 drvdata->instrp0 = false;
 898
 899         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 900         if (BMVAL(etmidr0, 5, 5))
 901                 drvdata->trcbb = true;
 902         else
 903                 drvdata->trcbb = false;
 904
 905         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 906         if (BMVAL(etmidr0, 6, 6))
 907                 drvdata->trccond = true;
 908         else
 909                 drvdata->trccond = false;
 910
 911         /* TRCCCI, bit[7] Cycle counting instruction bit */
 912         if (BMVAL(etmidr0, 7, 7))
 913                 drvdata->trccci = true;
 914         else
 915                 drvdata->trccci = false;
 916
 917         /* RETSTACK, bit[9] Return stack bit */
 918         if (BMVAL(etmidr0, 9, 9))
 919                 drvdata->retstack = true;
 920         else
 921                 drvdata->retstack = false;
 922
 923         /* NUMEVENT, bits[11:10] Number of events field */
 924         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 925         /* QSUPP, bits[16:15] Q element support field */
 926         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 927         /* TSSIZE, bits[28:24] Global timestamp size field */
 928         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 929
 930         /* maximum size of resources */
 931         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
 932         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 933         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 934         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 935         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 936         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 937         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 938
 939         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
 940         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 941         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 942         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 943         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 944         drvdata->config.s_ex_level = drvdata->s_ex_level;
 945         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 946         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 947
 948         /*
 949          * TRCERR, bit[24] whether a trace unit can trace a
 950          * system error exception.
 951          */
 952         if (BMVAL(etmidr3, 24, 24))
 953                 drvdata->trc_error = true;
 954         else
 955                 drvdata->trc_error = false;
 956
 957         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 958         if (BMVAL(etmidr3, 25, 25))
 959                 drvdata->syncpr = true;
 960         else
 961                 drvdata->syncpr = false;
 962
 963         /* STALLCTL, bit[26] is stall control implemented? */
 964         if (BMVAL(etmidr3, 26, 26))
 965                 drvdata->stallctl = true;
 966         else
 967                 drvdata->stallctl = false;
 968
 969         /* SYSSTALL, bit[27] implementation can support stall control? */
 970         if (BMVAL(etmidr3, 27, 27))
 971                 drvdata->sysstall = true;
 972         else
 973                 drvdata->sysstall = false;
 974
 975         /*
 976          * NUMPROC - the number of PEs available for tracing, 5bits
 977          *         = TRCIDR3.bits[13:12]bits[30:28]
 978          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
 979          *  bits[3:0] = TRCIDR3.bits[30:28]
 980          */
 981         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
 982
 983         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 984         if (BMVAL(etmidr3, 31, 31))
 985                 drvdata->nooverflow = true;
 986         else
 987                 drvdata->nooverflow = false;
 988
 989         /* number of resources trace unit supports */
 990         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
 991         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 992         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 993         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 994         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 995         /*
 996          * NUMRSPAIR, bits[19:16]
 997          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 998          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 999          * As such add 1 to the value of NUMRSPAIR for a better representation.
1000          *
1001          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1002          * the default TRUE and FALSE resource selectors are omitted.
1003          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1004          */
1005         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1006         if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1007                 drvdata->nr_resource += 1;
1008         /*
1009          * NUMSSCC, bits[23:20] the number of single-shot
1010          * comparator control for tracing. Read any status regs as these
1011          * also contain RO capability data.
1012          */
1013         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1014         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1015                 drvdata->config.ss_status[i] =
1016                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1017         }
1018         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1019         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1020         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1021         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1022
1023         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1024         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1025         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1026         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1027         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1028         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1029         if (BMVAL(etmidr5, 22, 22))
1030                 drvdata->atbtrig = true;
1031         else
1032                 drvdata->atbtrig = false;
1033         /*
1034          * LPOVERRIDE, bit[23] implementation supports
1035          * low-power state override
1036          */
1037         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1038                 drvdata->lpoverride = true;
1039         else
1040                 drvdata->lpoverride = false;
1041         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1042         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1043         /* NUMCNTR, bits[30:28] number of counters available for tracing */
1044         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1045         etm4_cs_lock(drvdata, csa);
1046 }
1047
1048 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1049 {
1050         return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1051 }
1052
1053 /* Set ELx trace filter access in the TRCVICTLR register */
1054 static void etm4_set_victlr_access(struct etmv4_config *config)
1055 {
1056         config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1057         config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1058 }
1059
1060 static void etm4_set_default_config(struct etmv4_config *config)
1061 {
1062         /* disable all events tracing */
1063         config->eventctrl0 = 0x0;
1064         config->eventctrl1 = 0x0;
1065
1066         /* disable stalling */
1067         config->stall_ctrl = 0x0;
1068
1069         /* enable trace synchronization every 4096 bytes, if available */
1070         config->syncfreq = 0xC;
1071
1072         /* disable timestamp event */
1073         config->ts_ctrl = 0x0;
1074
1075         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1076         config->vinst_ctrl = BIT(0);
1077
1078         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1079         etm4_set_victlr_access(config);
1080 }
1081
1082 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1083 {
1084         u64 access_type = 0;
1085
1086         /*
1087          * EXLEVEL_NS, for NonSecure Exception levels.
1088          * The mask here is a generic value and must be
1089          * shifted to the corresponding field for the registers
1090          */
1091         if (!is_kernel_in_hyp_mode()) {
1092                 /* Stay away from hypervisor mode for non-VHE */
1093                 access_type =  ETM_EXLEVEL_NS_HYP;
1094                 if (config->mode & ETM_MODE_EXCL_KERN)
1095                         access_type |= ETM_EXLEVEL_NS_OS;
1096         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1097                 access_type = ETM_EXLEVEL_NS_HYP;
1098         }
1099
1100         if (config->mode & ETM_MODE_EXCL_USER)
1101                 access_type |= ETM_EXLEVEL_NS_APP;
1102
1103         return access_type;
1104 }
1105
1106 /*
1107  * Construct the exception level masks for a given config.
1108  * This must be shifted to the corresponding register field
1109  * for usage.
1110  */
1111 static u64 etm4_get_access_type(struct etmv4_config *config)
1112 {
1113         /* All Secure exception levels are excluded from the trace */
1114         return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1115 }
1116
1117 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1118 {
1119         return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1120 }
1121
1122 static void etm4_set_comparator_filter(struct etmv4_config *config,
1123                                        u64 start, u64 stop, int comparator)
1124 {
1125         u64 access_type = etm4_get_comparator_access_type(config);
1126
1127         /* First half of default address comparator */
1128         config->addr_val[comparator] = start;
1129         config->addr_acc[comparator] = access_type;
1130         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1131
1132         /* Second half of default address comparator */
1133         config->addr_val[comparator + 1] = stop;
1134         config->addr_acc[comparator + 1] = access_type;
1135         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1136
1137         /*
1138          * Configure the ViewInst function to include this address range
1139          * comparator.
1140          *
1141          * @comparator is divided by two since it is the index in the
1142          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1143          * address range comparator _pairs_.
1144          *
1145          * Therefore:
1146          *      index 0 -> compatator pair 0
1147          *      index 2 -> comparator pair 1
1148          *      index 4 -> comparator pair 2
1149          *      ...
1150          *      index 14 -> comparator pair 7
1151          */
1152         config->viiectlr |= BIT(comparator / 2);
1153 }
1154
1155 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1156                                        u64 address, int comparator,
1157                                        enum etm_addr_type type)
1158 {
1159         int shift;
1160         u64 access_type = etm4_get_comparator_access_type(config);
1161
1162         /* Configure the comparator */
1163         config->addr_val[comparator] = address;
1164         config->addr_acc[comparator] = access_type;
1165         config->addr_type[comparator] = type;
1166
1167         /*
1168          * Configure ViewInst Start-Stop control register.
1169          * Addresses configured to start tracing go from bit 0 to n-1,
1170          * while those configured to stop tracing from 16 to 16 + n-1.
1171          */
1172         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1173         config->vissctlr |= BIT(shift + comparator);
1174 }
1175
1176 static void etm4_set_default_filter(struct etmv4_config *config)
1177 {
1178         /* Trace everything 'default' filter achieved by no filtering */
1179         config->viiectlr = 0x0;
1180
1181         /*
1182          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1183          * in the started state
1184          */
1185         config->vinst_ctrl |= BIT(9);
1186         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1187
1188         /* No start-stop filtering for ViewInst */
1189         config->vissctlr = 0x0;
1190 }
1191
1192 static void etm4_set_default(struct etmv4_config *config)
1193 {
1194         if (WARN_ON_ONCE(!config))
1195                 return;
1196
1197         /*
1198          * Make default initialisation trace everything
1199          *
1200          * This is done by a minimum default config sufficient to enable
1201          * full instruction trace - with a default filter for trace all
1202          * achieved by having no filtering.
1203          */
1204         etm4_set_default_config(config);
1205         etm4_set_default_filter(config);
1206 }
1207
1208 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1209 {
1210         int nr_comparator, index = 0;
1211         struct etmv4_config *config = &drvdata->config;
1212
1213         /*
1214          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1215          * for the total number of comparators.
1216          */
1217         nr_comparator = drvdata->nr_addr_cmp * 2;
1218
1219         /* Go through the tally of comparators looking for a free one. */
1220         while (index < nr_comparator) {
1221                 switch (type) {
1222                 case ETM_ADDR_TYPE_RANGE:
1223                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1224                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1225                                 return index;
1226
1227                         /* Address range comparators go in pairs */
1228                         index += 2;
1229                         break;
1230                 case ETM_ADDR_TYPE_START:
1231                 case ETM_ADDR_TYPE_STOP:
1232                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1233                                 return index;
1234
1235                         /* Start/stop address can have odd indexes */
1236                         index += 1;
1237                         break;
1238                 default:
1239                         return -EINVAL;
1240                 }
1241         }
1242
1243         /* If we are here all the comparators have been used. */
1244         return -ENOSPC;
1245 }
1246
1247 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1248                                   struct perf_event *event)
1249 {
1250         int i, comparator, ret = 0;
1251         u64 address;
1252         struct etmv4_config *config = &drvdata->config;
1253         struct etm_filters *filters = event->hw.addr_filters;
1254
1255         if (!filters)
1256                 goto default_filter;
1257
1258         /* Sync events with what Perf got */
1259         perf_event_addr_filters_sync(event);
1260
1261         /*
1262          * If there are no filters to deal with simply go ahead with
1263          * the default filter, i.e the entire address range.
1264          */
1265         if (!filters->nr_filters)
1266                 goto default_filter;
1267
1268         for (i = 0; i < filters->nr_filters; i++) {
1269                 struct etm_filter *filter = &filters->etm_filter[i];
1270                 enum etm_addr_type type = filter->type;
1271
1272                 /* See if a comparator is free. */
1273                 comparator = etm4_get_next_comparator(drvdata, type);
1274                 if (comparator < 0) {
1275                         ret = comparator;
1276                         goto out;
1277                 }
1278
1279                 switch (type) {
1280                 case ETM_ADDR_TYPE_RANGE:
1281                         etm4_set_comparator_filter(config,
1282                                                    filter->start_addr,
1283                                                    filter->stop_addr,
1284                                                    comparator);
1285                         /*
1286                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1287                          * in the started state
1288                          */
1289                         config->vinst_ctrl |= BIT(9);
1290
1291                         /* No start-stop filtering for ViewInst */
1292                         config->vissctlr = 0x0;
1293                         break;
1294                 case ETM_ADDR_TYPE_START:
1295                 case ETM_ADDR_TYPE_STOP:
1296                         /* Get the right start or stop address */
1297                         address = (type == ETM_ADDR_TYPE_START ?
1298                                    filter->start_addr :
1299                                    filter->stop_addr);
1300
1301                         /* Configure comparator */
1302                         etm4_set_start_stop_filter(config, address,
1303                                                    comparator, type);
1304
1305                         /*
1306                          * If filters::ssstatus == 1, trace acquisition was
1307                          * started but the process was yanked away before the
1308                          * the stop address was hit.  As such the start/stop
1309                          * logic needs to be re-started so that tracing can
1310                          * resume where it left.
1311                          *
1312                          * The start/stop logic status when a process is
1313                          * scheduled out is checked in function
1314                          * etm4_disable_perf().
1315                          */
1316                         if (filters->ssstatus)
1317                                 config->vinst_ctrl |= BIT(9);
1318
1319                         /* No include/exclude filtering for ViewInst */
1320                         config->viiectlr = 0x0;
1321                         break;
1322                 default:
1323                         ret = -EINVAL;
1324                         goto out;
1325                 }
1326         }
1327
1328         goto out;
1329
1330
1331 default_filter:
1332         etm4_set_default_filter(config);
1333
1334 out:
1335         return ret;
1336 }
1337
1338 void etm4_config_trace_mode(struct etmv4_config *config)
1339 {
1340         u32 mode;
1341
1342         mode = config->mode;
1343         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1344
1345         /* excluding kernel AND user space doesn't make sense */
1346         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1347
1348         /* nothing to do if neither flags are set */
1349         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1350                 return;
1351
1352         etm4_set_victlr_access(config);
1353 }
1354
1355 static int etm4_online_cpu(unsigned int cpu)
1356 {
1357         if (!etmdrvdata[cpu])
1358                 return 0;
1359
1360         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1361                 coresight_enable(etmdrvdata[cpu]->csdev);
1362         return 0;
1363 }
1364
1365 static int etm4_starting_cpu(unsigned int cpu)
1366 {
1367         if (!etmdrvdata[cpu])
1368                 return 0;
1369
1370         spin_lock(&etmdrvdata[cpu]->spinlock);
1371         if (!etmdrvdata[cpu]->os_unlock)
1372                 etm4_os_unlock(etmdrvdata[cpu]);
1373
1374         if (local_read(&etmdrvdata[cpu]->mode))
1375                 etm4_enable_hw(etmdrvdata[cpu]);
1376         spin_unlock(&etmdrvdata[cpu]->spinlock);
1377         return 0;
1378 }
1379
1380 static int etm4_dying_cpu(unsigned int cpu)
1381 {
1382         if (!etmdrvdata[cpu])
1383                 return 0;
1384
1385         spin_lock(&etmdrvdata[cpu]->spinlock);
1386         if (local_read(&etmdrvdata[cpu]->mode))
1387                 etm4_disable_hw(etmdrvdata[cpu]);
1388         spin_unlock(&etmdrvdata[cpu]->spinlock);
1389         return 0;
1390 }
1391
1392 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1393 {
1394         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1395 }
1396
1397 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1398 {
1399         int i, ret = 0;
1400         struct etmv4_save_state *state;
1401         struct coresight_device *csdev = drvdata->csdev;
1402         struct csdev_access *csa;
1403         struct device *etm_dev;
1404
1405         if (WARN_ON(!csdev))
1406                 return -ENODEV;
1407
1408         etm_dev = &csdev->dev;
1409         csa = &csdev->access;
1410
1411         /*
1412          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1413          * of ARM IHI 0064D
1414          */
1415         dsb(sy);
1416         isb();
1417
1418         etm4_cs_unlock(drvdata, csa);
1419         /* Lock the OS lock to disable trace and external debugger access */
1420         etm4_os_lock(drvdata);
1421
1422         /* wait for TRCSTATR.PMSTABLE to go up */
1423         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1424                 dev_err(etm_dev,
1425                         "timeout while waiting for PM Stable Status\n");
1426                 etm4_os_unlock(drvdata);
1427                 ret = -EBUSY;
1428                 goto out;
1429         }
1430
1431         state = drvdata->save_state;
1432
1433         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1434         if (drvdata->nr_pe)
1435                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1436         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1437         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1438         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1439         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1440         state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1441         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1442         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1443         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1444         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1445         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1446         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1447
1448         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1449         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1450         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1451         if (drvdata->nr_pe_cmp)
1452                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1453         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1454         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1455         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1456
1457         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1458                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1459
1460         state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1461         state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1462         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1463
1464         for (i = 0; i < drvdata->nr_cntr; i++) {
1465                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1466                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1467                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1468         }
1469
1470         for (i = 0; i < drvdata->nr_resource * 2; i++)
1471                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1472
1473         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1474                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1475                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1476                 if (etm4x_sspcicrn_present(drvdata, i))
1477                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1478         }
1479
1480         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1481                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1482                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1483         }
1484
1485         /*
1486          * Data trace stream is architecturally prohibited for A profile cores
1487          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1488          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1489          * unit") of ARM IHI 0064D.
1490          */
1491
1492         for (i = 0; i < drvdata->numcidc; i++)
1493                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1494
1495         for (i = 0; i < drvdata->numvmidc; i++)
1496                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1497
1498         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1499         if (drvdata->numcidc > 4)
1500                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1501
1502         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1503         if (drvdata->numvmidc > 4)
1504                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1505
1506         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1507
1508         if (!drvdata->skip_power_up)
1509                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1510
1511         /* wait for TRCSTATR.IDLE to go up */
1512         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1513                 dev_err(etm_dev,
1514                         "timeout while waiting for Idle Trace Status\n");
1515                 etm4_os_unlock(drvdata);
1516                 ret = -EBUSY;
1517                 goto out;
1518         }
1519
1520         drvdata->state_needs_restore = true;
1521
1522         /*
1523          * Power can be removed from the trace unit now. We do this to
1524          * potentially save power on systems that respect the TRCPDCR_PU
1525          * despite requesting software to save/restore state.
1526          */
1527         if (!drvdata->skip_power_up)
1528                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1529                                       TRCPDCR);
1530 out:
1531         etm4_cs_lock(drvdata, csa);
1532         return ret;
1533 }
1534
1535 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1536 {
1537         int i;
1538         struct etmv4_save_state *state = drvdata->save_state;
1539         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1540         struct csdev_access *csa = &tmp_csa;
1541
1542         etm4_cs_unlock(drvdata, csa);
1543         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1544
1545         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1546         if (drvdata->nr_pe)
1547                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1548         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1549         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1550         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1551         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1552         etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1553         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1554         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1555         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1556         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1557         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1558         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1559
1560         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1561         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1562         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1563         if (drvdata->nr_pe_cmp)
1564                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1565         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1566         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1567         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1568
1569         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1570                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1571
1572         etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1573         etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1574         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1575
1576         for (i = 0; i < drvdata->nr_cntr; i++) {
1577                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1578                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1579                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1580         }
1581
1582         for (i = 0; i < drvdata->nr_resource * 2; i++)
1583                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1584
1585         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1586                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1587                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1588                 if (etm4x_sspcicrn_present(drvdata, i))
1589                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1590         }
1591
1592         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1593                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1594                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1595         }
1596
1597         for (i = 0; i < drvdata->numcidc; i++)
1598                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1599
1600         for (i = 0; i < drvdata->numvmidc; i++)
1601                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1602
1603         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1604         if (drvdata->numcidc > 4)
1605                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1606
1607         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1608         if (drvdata->numvmidc > 4)
1609                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1610
1611         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1612
1613         if (!drvdata->skip_power_up)
1614                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1615
1616         drvdata->state_needs_restore = false;
1617
1618         /*
1619          * As recommended by section 4.3.7 ("Synchronization when using the
1620          * memory-mapped interface") of ARM IHI 0064D
1621          */
1622         dsb(sy);
1623         isb();
1624
1625         /* Unlock the OS lock to re-enable trace and external debug access */
1626         etm4_os_unlock(drvdata);
1627         etm4_cs_lock(drvdata, csa);
1628 }
1629
1630 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1631                               void *v)
1632 {
1633         struct etmv4_drvdata *drvdata;
1634         unsigned int cpu = smp_processor_id();
1635
1636         if (!etmdrvdata[cpu])
1637                 return NOTIFY_OK;
1638
1639         drvdata = etmdrvdata[cpu];
1640
1641         if (!drvdata->save_state)
1642                 return NOTIFY_OK;
1643
1644         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1645                 return NOTIFY_BAD;
1646
1647         switch (cmd) {
1648         case CPU_PM_ENTER:
1649                 /* save the state if self-hosted coresight is in use */
1650                 if (local_read(&drvdata->mode))
1651                         if (etm4_cpu_save(drvdata))
1652                                 return NOTIFY_BAD;
1653                 break;
1654         case CPU_PM_EXIT:
1655         case CPU_PM_ENTER_FAILED:
1656                 if (drvdata->state_needs_restore)
1657                         etm4_cpu_restore(drvdata);
1658                 break;
1659         default:
1660                 return NOTIFY_DONE;
1661         }
1662
1663         return NOTIFY_OK;
1664 }
1665
1666 static struct notifier_block etm4_cpu_pm_nb = {
1667         .notifier_call = etm4_cpu_pm_notify,
1668 };
1669
1670 /* Setup PM. Deals with error conditions and counts */
1671 static int __init etm4_pm_setup(void)
1672 {
1673         int ret;
1674
1675         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1676         if (ret)
1677                 return ret;
1678
1679         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1680                                         "arm/coresight4:starting",
1681                                         etm4_starting_cpu, etm4_dying_cpu);
1682
1683         if (ret)
1684                 goto unregister_notifier;
1685
1686         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1687                                         "arm/coresight4:online",
1688                                         etm4_online_cpu, NULL);
1689
1690         /* HP dyn state ID returned in ret on success */
1691         if (ret > 0) {
1692                 hp_online = ret;
1693                 return 0;
1694         }
1695
1696         /* failed dyn state - remove others */
1697         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1698
1699 unregister_notifier:
1700         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1701         return ret;
1702 }
1703
1704 static void etm4_pm_clear(void)
1705 {
1706         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1707         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1708         if (hp_online) {
1709                 cpuhp_remove_state_nocalls(hp_online);
1710                 hp_online = 0;
1711         }
1712 }
1713
1714 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1715 {
1716         int ret;
1717         struct coresight_platform_data *pdata = NULL;
1718         struct etmv4_drvdata *drvdata;
1719         struct coresight_desc desc = { 0 };
1720         struct etm4_init_arg init_arg = { 0 };
1721
1722         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1723         if (!drvdata)
1724                 return -ENOMEM;
1725
1726         dev_set_drvdata(dev, drvdata);
1727
1728         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1729                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1730                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1731
1732         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1733                 drvdata->save_state = devm_kmalloc(dev,
1734                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1735                 if (!drvdata->save_state)
1736                         return -ENOMEM;
1737         }
1738
1739         if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1740                 drvdata->skip_power_up = true;
1741
1742         drvdata->base = base;
1743
1744         spin_lock_init(&drvdata->spinlock);
1745
1746         drvdata->cpu = coresight_get_cpu(dev);
1747         if (drvdata->cpu < 0)
1748                 return drvdata->cpu;
1749
1750         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1751         if (!desc.name)
1752                 return -ENOMEM;
1753
1754         init_arg.drvdata = drvdata;
1755         init_arg.csa = &desc.access;
1756         init_arg.pid = etm_pid;
1757
1758         if (smp_call_function_single(drvdata->cpu,
1759                                 etm4_init_arch_data,  &init_arg, 1))
1760                 dev_err(dev, "ETM arch init failed\n");
1761
1762         if (!drvdata->arch)
1763                 return -EINVAL;
1764
1765         etm4_init_trace_id(drvdata);
1766         etm4_set_default(&drvdata->config);
1767
1768         pdata = coresight_get_platform_data(dev);
1769         if (IS_ERR(pdata))
1770                 return PTR_ERR(pdata);
1771
1772         dev->platform_data = pdata;
1773
1774         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1775         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1776         desc.ops = &etm4_cs_ops;
1777         desc.pdata = pdata;
1778         desc.dev = dev;
1779         desc.groups = coresight_etmv4_groups;
1780         drvdata->csdev = coresight_register(&desc);
1781         if (IS_ERR(drvdata->csdev))
1782                 return PTR_ERR(drvdata->csdev);
1783
1784         ret = etm_perf_symlink(drvdata->csdev, true);
1785         if (ret) {
1786                 coresight_unregister(drvdata->csdev);
1787                 return ret;
1788         }
1789
1790         etmdrvdata[drvdata->cpu] = drvdata;
1791
1792         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1793                  drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
1794                  ETM_ARCH_MINOR_VERSION(drvdata->arch));
1795
1796         if (boot_enable) {
1797                 coresight_enable(drvdata->csdev);
1798                 drvdata->boot_enable = true;
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
1805 {
1806         void __iomem *base;
1807         struct device *dev = &adev->dev;
1808         struct resource *res = &adev->res;
1809         int ret;
1810
1811         /* Validity for the resource is already checked by the AMBA core */
1812         base = devm_ioremap_resource(dev, res);
1813         if (IS_ERR(base))
1814                 return PTR_ERR(base);
1815
1816         ret = etm4_probe(dev, base, id->id);
1817         if (!ret)
1818                 pm_runtime_put(&adev->dev);
1819
1820         return ret;
1821 }
1822
1823 static struct amba_cs_uci_id uci_id_etm4[] = {
1824         {
1825                 /*  ETMv4 UCI data */
1826                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
1827                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
1828                 .devtype        = 0x00000013,
1829         }
1830 };
1831
1832 static void clear_etmdrvdata(void *info)
1833 {
1834         int cpu = *(int *)info;
1835
1836         etmdrvdata[cpu] = NULL;
1837 }
1838
1839 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
1840 {
1841         etm_perf_symlink(drvdata->csdev, false);
1842         /*
1843          * Taking hotplug lock here to avoid racing between etm4_remove_dev()
1844          * and CPU hotplug call backs.
1845          */
1846         cpus_read_lock();
1847         /*
1848          * The readers for etmdrvdata[] are CPU hotplug call backs
1849          * and PM notification call backs. Change etmdrvdata[i] on
1850          * CPU i ensures these call backs has consistent view
1851          * inside one call back function.
1852          */
1853         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1854                 etmdrvdata[drvdata->cpu] = NULL;
1855
1856         cpus_read_unlock();
1857
1858         coresight_unregister(drvdata->csdev);
1859
1860         return 0;
1861 }
1862
1863 static int __exit etm4_remove_amba(struct amba_device *adev)
1864 {
1865         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1866
1867         if (drvdata)
1868                 return etm4_remove_dev(drvdata);
1869         return 0;
1870 }
1871
1872 static const struct amba_id etm4_ids[] = {
1873         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1874         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1875         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1876         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1877         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1878         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
1879         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
1880         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1881         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1882         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1883         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1884         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1885         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1886         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1887         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1888         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1889         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1890         {},
1891 };
1892
1893 MODULE_DEVICE_TABLE(amba, etm4_ids);
1894
1895 static struct amba_driver etm4x_amba_driver = {
1896         .drv = {
1897                 .name   = "coresight-etm4x",
1898                 .owner  = THIS_MODULE,
1899                 .suppress_bind_attrs = true,
1900         },
1901         .probe          = etm4_probe_amba,
1902         .remove         = etm4_remove_amba,
1903         .id_table       = etm4_ids,
1904 };
1905
1906 static int __init etm4x_init(void)
1907 {
1908         int ret;
1909
1910         ret = etm4_pm_setup();
1911
1912         /* etm4_pm_setup() does its own cleanup - exit on error */
1913         if (ret)
1914                 return ret;
1915
1916         ret = amba_driver_register(&etm4x_amba_driver);
1917         if (ret) {
1918                 pr_err("Error registering etm4x driver\n");
1919                 etm4_pm_clear();
1920         }
1921
1922         return ret;
1923 }
1924
1925 static void __exit etm4x_exit(void)
1926 {
1927         amba_driver_unregister(&etm4x_amba_driver);
1928         etm4_pm_clear();
1929 }
1930
1931 module_init(etm4x_init);
1932 module_exit(etm4x_exit);
1933
1934 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1935 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1936 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1937 MODULE_LICENSE("GPL v2");