drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/moduleparam.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/fs.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/smp.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/stat.h>
  19 #include <linux/clk.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpu_pm.h>
  22 #include <linux/coresight.h>
  23 #include <linux/coresight-pmu.h>
  24 #include <linux/pm_wakeup.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/perf_event.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/property.h>
  31 #include <asm/sections.h>
  32 #include <asm/local.h>
  33 #include <asm/virt.h>
  34
  35 #include "coresight-etm4x.h"
  36 #include "coresight-etm-perf.h"
  37
  38 static int boot_enable;
  39 module_param(boot_enable, int, 0444);
  40 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  41
  42 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  43 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  44 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  45
  46 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  47 module_param(pm_save_enable, int, 0444);
  48 MODULE_PARM_DESC(pm_save_enable,
  49         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  50
  51 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  52 static void etm4_set_default_config(struct etmv4_config *config);
  53 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  54                                   struct perf_event *event);
  55 static u64 etm4_get_access_type(struct etmv4_config *config);
  56
  57 static enum cpuhp_state hp_online;
  58
  59 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
  60 {
  61         /* Writing 0 to TRCOSLAR unlocks the trace registers */
  62         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  63         drvdata->os_unlock = true;
  64         isb();
  65 }
  66
  67 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
  68 {
  69         /* Writing 0x1 to TRCOSLAR locks the trace registers */
  70         writel_relaxed(0x1, drvdata->base + TRCOSLAR);
  71         drvdata->os_unlock = false;
  72         isb();
  73 }
  74
  75 static bool etm4_arch_supported(u8 arch)
  76 {
  77         /* Mask out the minor version number */
  78         switch (arch & 0xf0) {
  79         case ETM_ARCH_V4:
  80                 break;
  81         default:
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 static int etm4_cpu_id(struct coresight_device *csdev)
  88 {
  89         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  90
  91         return drvdata->cpu;
  92 }
  93
  94 static int etm4_trace_id(struct coresight_device *csdev)
  95 {
  96         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  97
  98         return drvdata->trcid;
  99 }
 100
 101 struct etm4_enable_arg {
 102         struct etmv4_drvdata *drvdata;
 103         int rc;
 104 };
 105
 106 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 107 {
 108         int i, rc;
 109         struct etmv4_config *config = &drvdata->config;
 110         struct device *etm_dev = &drvdata->csdev->dev;
 111
 112         CS_UNLOCK(drvdata->base);
 113
 114         etm4_os_unlock(drvdata);
 115
 116         rc = coresight_claim_device_unlocked(drvdata->base);
 117         if (rc)
 118                 goto done;
 119
 120         /* Disable the trace unit before programming trace registers */
 121         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
 122
 123         /* wait for TRCSTATR.IDLE to go up */
 124         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 125                 dev_err(etm_dev,
 126                         "timeout while waiting for Idle Trace Status\n");
 127
 128         writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
 129         writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
 130         /* nothing specific implemented */
 131         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 132         writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 133         writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 134         writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 135         writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 136         writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 137         writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
 138         writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
 139         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 140         writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
 141         writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
 142         writel_relaxed(config->vissctlr,
 143                        drvdata->base + TRCVISSCTLR);
 144         writel_relaxed(config->vipcssctlr,
 145                        drvdata->base + TRCVIPCSSCTLR);
 146         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 147                 writel_relaxed(config->seq_ctrl[i],
 148                                drvdata->base + TRCSEQEVRn(i));
 149         writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
 150         writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
 151         writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
 152         for (i = 0; i < drvdata->nr_cntr; i++) {
 153                 writel_relaxed(config->cntrldvr[i],
 154                                drvdata->base + TRCCNTRLDVRn(i));
 155                 writel_relaxed(config->cntr_ctrl[i],
 156                                drvdata->base + TRCCNTCTLRn(i));
 157                 writel_relaxed(config->cntr_val[i],
 158                                drvdata->base + TRCCNTVRn(i));
 159         }
 160
 161         /*
 162          * Resource selector pair 0 is always implemented and reserved.  As
 163          * such start at 2.
 164          */
 165         for (i = 2; i < drvdata->nr_resource * 2; i++)
 166                 writel_relaxed(config->res_ctrl[i],
 167                                drvdata->base + TRCRSCTLRn(i));
 168
 169         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 170                 /* always clear status bit on restart if using single-shot */
 171                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 172                         config->ss_status[i] &= ~BIT(31);
 173                 writel_relaxed(config->ss_ctrl[i],
 174                                drvdata->base + TRCSSCCRn(i));
 175                 writel_relaxed(config->ss_status[i],
 176                                drvdata->base + TRCSSCSRn(i));
 177                 writel_relaxed(config->ss_pe_cmp[i],
 178                                drvdata->base + TRCSSPCICRn(i));
 179         }
 180         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 181                 writeq_relaxed(config->addr_val[i],
 182                                drvdata->base + TRCACVRn(i));
 183                 writeq_relaxed(config->addr_acc[i],
 184                                drvdata->base + TRCACATRn(i));
 185         }
 186         for (i = 0; i < drvdata->numcidc; i++)
 187                 writeq_relaxed(config->ctxid_pid[i],
 188                                drvdata->base + TRCCIDCVRn(i));
 189         writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 190         writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 191
 192         for (i = 0; i < drvdata->numvmidc; i++)
 193                 writeq_relaxed(config->vmid_val[i],
 194                                drvdata->base + TRCVMIDCVRn(i));
 195         writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 196         writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 197
 198         if (!drvdata->skip_power_up) {
 199                 /*
 200                  * Request to keep the trace unit powered and also
 201                  * emulation of powerdown
 202                  */
 203                 writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) |
 204                                TRCPDCR_PU, drvdata->base + TRCPDCR);
 205         }
 206
 207         /* Enable the trace unit */
 208         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 209
 210         /* wait for TRCSTATR.IDLE to go back down to '0' */
 211         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 212                 dev_err(etm_dev,
 213                         "timeout while waiting for Idle Trace Status\n");
 214
 215         /*
 216          * As recommended by section 4.3.7 ("Synchronization when using the
 217          * memory-mapped interface") of ARM IHI 0064D
 218          */
 219         dsb(sy);
 220         isb();
 221
 222 done:
 223         CS_LOCK(drvdata->base);
 224
 225         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 226                 drvdata->cpu, rc);
 227         return rc;
 228 }
 229
 230 static void etm4_enable_hw_smp_call(void *info)
 231 {
 232         struct etm4_enable_arg *arg = info;
 233
 234         if (WARN_ON(!arg))
 235                 return;
 236         arg->rc = etm4_enable_hw(arg->drvdata);
 237 }
 238
 239 /*
 240  * The goal of function etm4_config_timestamp_event() is to configure a
 241  * counter that will tell the tracer to emit a timestamp packet when it
 242  * reaches zero.  This is done in order to get a more fine grained idea
 243  * of when instructions are executed so that they can be correlated
 244  * with execution on other CPUs.
 245  *
 246  * To do this the counter itself is configured to self reload and
 247  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 248  * there a resource selector is configured with the counter and the
 249  * timestamp control register to use the resource selector to trigger the
 250  * event that will insert a timestamp packet in the stream.
 251  */
 252 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 253 {
 254         int ctridx, ret = -EINVAL;
 255         int counter, rselector;
 256         u32 val = 0;
 257         struct etmv4_config *config = &drvdata->config;
 258
 259         /* No point in trying if we don't have at least one counter */
 260         if (!drvdata->nr_cntr)
 261                 goto out;
 262
 263         /* Find a counter that hasn't been initialised */
 264         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 265                 if (config->cntr_val[ctridx] == 0)
 266                         break;
 267
 268         /* All the counters have been configured already, bail out */
 269         if (ctridx == drvdata->nr_cntr) {
 270                 pr_debug("%s: no available counter found\n", __func__);
 271                 ret = -ENOSPC;
 272                 goto out;
 273         }
 274
 275         /*
 276          * Searching for an available resource selector to use, starting at
 277          * '2' since every implementation has at least 2 resource selector.
 278          * ETMIDR4 gives the number of resource selector _pairs_,
 279          * hence multiply by 2.
 280          */
 281         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 282                 if (!config->res_ctrl[rselector])
 283                         break;
 284
 285         if (rselector == drvdata->nr_resource * 2) {
 286                 pr_debug("%s: no available resource selector found\n",
 287                          __func__);
 288                 ret = -ENOSPC;
 289                 goto out;
 290         }
 291
 292         /* Remember what counter we used */
 293         counter = 1 << ctridx;
 294
 295         /*
 296          * Initialise original and reload counter value to the smallest
 297          * possible value in order to get as much precision as we can.
 298          */
 299         config->cntr_val[ctridx] = 1;
 300         config->cntrldvr[ctridx] = 1;
 301
 302         /* Set the trace counter control register */
 303         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 304                0x0 << 7         |  /* Select single resource selector */
 305                0x1;                /* Resource selector 1, i.e always true */
 306
 307         config->cntr_ctrl[ctridx] = val;
 308
 309         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 310               counter << 0;       /* Counter to use */
 311
 312         config->res_ctrl[rselector] = val;
 313
 314         val = 0x0 << 7          | /* Select single resource selector */
 315               rselector;          /* Resource selector */
 316
 317         config->ts_ctrl = val;
 318
 319         ret = 0;
 320 out:
 321         return ret;
 322 }
 323
 324 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 325                                    struct perf_event *event)
 326 {
 327         int ret = 0;
 328         struct etmv4_config *config = &drvdata->config;
 329         struct perf_event_attr *attr = &event->attr;
 330
 331         if (!attr) {
 332                 ret = -EINVAL;
 333                 goto out;
 334         }
 335
 336         /* Clear configuration from previous run */
 337         memset(config, 0, sizeof(struct etmv4_config));
 338
 339         if (attr->exclude_kernel)
 340                 config->mode = ETM_MODE_EXCL_KERN;
 341
 342         if (attr->exclude_user)
 343                 config->mode = ETM_MODE_EXCL_USER;
 344
 345         /* Always start from the default config */
 346         etm4_set_default_config(config);
 347
 348         /* Configure filters specified on the perf cmd line, if any. */
 349         ret = etm4_set_event_filters(drvdata, event);
 350         if (ret)
 351                 goto out;
 352
 353         /* Go from generic option to ETMv4 specifics */
 354         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 355                 config->cfg |= BIT(4);
 356                 /* TRM: Must program this for cycacc to work */
 357                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 358         }
 359         if (attr->config & BIT(ETM_OPT_TS)) {
 360                 /*
 361                  * Configure timestamps to be emitted at regular intervals in
 362                  * order to correlate instructions executed on different CPUs
 363                  * (CPU-wide trace scenarios).
 364                  */
 365                 ret = etm4_config_timestamp_event(drvdata);
 366
 367                 /*
 368                  * No need to go further if timestamp intervals can't
 369                  * be configured.
 370                  */
 371                 if (ret)
 372                         goto out;
 373
 374                 /* bit[11], Global timestamp tracing bit */
 375                 config->cfg |= BIT(11);
 376         }
 377
 378         if (attr->config & BIT(ETM_OPT_CTXTID))
 379                 /* bit[6], Context ID tracing bit */
 380                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 381
 382         /* return stack - enable if selected and supported */
 383         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 384                 /* bit[12], Return stack enable bit */
 385                 config->cfg |= BIT(12);
 386
 387 out:
 388         return ret;
 389 }
 390
 391 static int etm4_enable_perf(struct coresight_device *csdev,
 392                             struct perf_event *event)
 393 {
 394         int ret = 0;
 395         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 396
 397         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 398                 ret = -EINVAL;
 399                 goto out;
 400         }
 401
 402         /* Configure the tracer based on the session's specifics */
 403         ret = etm4_parse_event_config(drvdata, event);
 404         if (ret)
 405                 goto out;
 406         /* And enable it */
 407         ret = etm4_enable_hw(drvdata);
 408
 409 out:
 410         return ret;
 411 }
 412
 413 static int etm4_enable_sysfs(struct coresight_device *csdev)
 414 {
 415         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 416         struct etm4_enable_arg arg = { };
 417         int ret;
 418
 419         spin_lock(&drvdata->spinlock);
 420
 421         /*
 422          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 423          * ensures that register writes occur when cpu is powered.
 424          */
 425         arg.drvdata = drvdata;
 426         ret = smp_call_function_single(drvdata->cpu,
 427                                        etm4_enable_hw_smp_call, &arg, 1);
 428         if (!ret)
 429                 ret = arg.rc;
 430         if (!ret)
 431                 drvdata->sticky_enable = true;
 432         spin_unlock(&drvdata->spinlock);
 433
 434         if (!ret)
 435                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 436         return ret;
 437 }
 438
 439 static int etm4_enable(struct coresight_device *csdev,
 440                        struct perf_event *event, u32 mode)
 441 {
 442         int ret;
 443         u32 val;
 444         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 445
 446         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 447
 448         /* Someone is already using the tracer */
 449         if (val)
 450                 return -EBUSY;
 451
 452         switch (mode) {
 453         case CS_MODE_SYSFS:
 454                 ret = etm4_enable_sysfs(csdev);
 455                 break;
 456         case CS_MODE_PERF:
 457                 ret = etm4_enable_perf(csdev, event);
 458                 break;
 459         default:
 460                 ret = -EINVAL;
 461         }
 462
 463         /* The tracer didn't start */
 464         if (ret)
 465                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 466
 467         return ret;
 468 }
 469
 470 static void etm4_disable_hw(void *info)
 471 {
 472         u32 control;
 473         struct etmv4_drvdata *drvdata = info;
 474         struct etmv4_config *config = &drvdata->config;
 475         struct device *etm_dev = &drvdata->csdev->dev;
 476         int i;
 477
 478         CS_UNLOCK(drvdata->base);
 479
 480         if (!drvdata->skip_power_up) {
 481                 /* power can be removed from the trace unit now */
 482                 control = readl_relaxed(drvdata->base + TRCPDCR);
 483                 control &= ~TRCPDCR_PU;
 484                 writel_relaxed(control, drvdata->base + TRCPDCR);
 485         }
 486
 487         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 488
 489         /* EN, bit[0] Trace unit enable bit */
 490         control &= ~0x1;
 491
 492         /*
 493          * Make sure everything completes before disabling, as recommended
 494          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 495          * SSTATUS") of ARM IHI 0064D
 496          */
 497         dsb(sy);
 498         isb();
 499         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 500
 501         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 502         if (coresight_timeout(drvdata->base, TRCSTATR,
 503                               TRCSTATR_PMSTABLE_BIT, 1))
 504                 dev_err(etm_dev,
 505                         "timeout while waiting for PM stable Trace Status\n");
 506
 507         /* read the status of the single shot comparators */
 508         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 509                 config->ss_status[i] =
 510                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 511         }
 512
 513         /* read back the current counter values */
 514         for (i = 0; i < drvdata->nr_cntr; i++) {
 515                 config->cntr_val[i] =
 516                         readl_relaxed(drvdata->base + TRCCNTVRn(i));
 517         }
 518
 519         coresight_disclaim_device_unlocked(drvdata->base);
 520
 521         CS_LOCK(drvdata->base);
 522
 523         dev_dbg(&drvdata->csdev->dev,
 524                 "cpu: %d disable smp call done\n", drvdata->cpu);
 525 }
 526
 527 static int etm4_disable_perf(struct coresight_device *csdev,
 528                              struct perf_event *event)
 529 {
 530         u32 control;
 531         struct etm_filters *filters = event->hw.addr_filters;
 532         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 533
 534         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 535                 return -EINVAL;
 536
 537         etm4_disable_hw(drvdata);
 538
 539         /*
 540          * Check if the start/stop logic was active when the unit was stopped.
 541          * That way we can re-enable the start/stop logic when the process is
 542          * scheduled again.  Configuration of the start/stop logic happens in
 543          * function etm4_set_event_filters().
 544          */
 545         control = readl_relaxed(drvdata->base + TRCVICTLR);
 546         /* TRCVICTLR::SSSTATUS, bit[9] */
 547         filters->ssstatus = (control & BIT(9));
 548
 549         return 0;
 550 }
 551
 552 static void etm4_disable_sysfs(struct coresight_device *csdev)
 553 {
 554         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 555
 556         /*
 557          * Taking hotplug lock here protects from clocks getting disabled
 558          * with tracing being left on (crash scenario) if user disable occurs
 559          * after cpu online mask indicates the cpu is offline but before the
 560          * DYING hotplug callback is serviced by the ETM driver.
 561          */
 562         cpus_read_lock();
 563         spin_lock(&drvdata->spinlock);
 564
 565         /*
 566          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 567          * ensures that register writes occur when cpu is powered.
 568          */
 569         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 570
 571         spin_unlock(&drvdata->spinlock);
 572         cpus_read_unlock();
 573
 574         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 575 }
 576
 577 static void etm4_disable(struct coresight_device *csdev,
 578                          struct perf_event *event)
 579 {
 580         u32 mode;
 581         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 582
 583         /*
 584          * For as long as the tracer isn't disabled another entity can't
 585          * change its status.  As such we can read the status here without
 586          * fearing it will change under us.
 587          */
 588         mode = local_read(&drvdata->mode);
 589
 590         switch (mode) {
 591         case CS_MODE_DISABLED:
 592                 break;
 593         case CS_MODE_SYSFS:
 594                 etm4_disable_sysfs(csdev);
 595                 break;
 596         case CS_MODE_PERF:
 597                 etm4_disable_perf(csdev, event);
 598                 break;
 599         }
 600
 601         if (mode)
 602                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 603 }
 604
 605 static const struct coresight_ops_source etm4_source_ops = {
 606         .cpu_id         = etm4_cpu_id,
 607         .trace_id       = etm4_trace_id,
 608         .enable         = etm4_enable,
 609         .disable        = etm4_disable,
 610 };
 611
 612 static const struct coresight_ops etm4_cs_ops = {
 613         .source_ops     = &etm4_source_ops,
 614 };
 615
 616 static void etm4_init_arch_data(void *info)
 617 {
 618         u32 etmidr0;
 619         u32 etmidr1;
 620         u32 etmidr2;
 621         u32 etmidr3;
 622         u32 etmidr4;
 623         u32 etmidr5;
 624         struct etmv4_drvdata *drvdata = info;
 625         int i;
 626
 627         /* Make sure all registers are accessible */
 628         etm4_os_unlock(drvdata);
 629
 630         CS_UNLOCK(drvdata->base);
 631
 632         /* find all capabilities of the tracing unit */
 633         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 634
 635         /* INSTP0, bits[2:1] P0 tracing support field */
 636         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 637                 drvdata->instrp0 = true;
 638         else
 639                 drvdata->instrp0 = false;
 640
 641         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 642         if (BMVAL(etmidr0, 5, 5))
 643                 drvdata->trcbb = true;
 644         else
 645                 drvdata->trcbb = false;
 646
 647         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 648         if (BMVAL(etmidr0, 6, 6))
 649                 drvdata->trccond = true;
 650         else
 651                 drvdata->trccond = false;
 652
 653         /* TRCCCI, bit[7] Cycle counting instruction bit */
 654         if (BMVAL(etmidr0, 7, 7))
 655                 drvdata->trccci = true;
 656         else
 657                 drvdata->trccci = false;
 658
 659         /* RETSTACK, bit[9] Return stack bit */
 660         if (BMVAL(etmidr0, 9, 9))
 661                 drvdata->retstack = true;
 662         else
 663                 drvdata->retstack = false;
 664
 665         /* NUMEVENT, bits[11:10] Number of events field */
 666         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 667         /* QSUPP, bits[16:15] Q element support field */
 668         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 669         /* TSSIZE, bits[28:24] Global timestamp size field */
 670         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 671
 672         /* base architecture of trace unit */
 673         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 674         /*
 675          * TRCARCHMIN, bits[7:4] architecture the minor version number
 676          * TRCARCHMAJ, bits[11:8] architecture major versin number
 677          */
 678         drvdata->arch = BMVAL(etmidr1, 4, 11);
 679         drvdata->config.arch = drvdata->arch;
 680
 681         /* maximum size of resources */
 682         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 683         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 684         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 685         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 686         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 687         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 688         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 689
 690         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 691         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 692         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 693         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 694         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 695         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 696         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 697
 698         /*
 699          * TRCERR, bit[24] whether a trace unit can trace a
 700          * system error exception.
 701          */
 702         if (BMVAL(etmidr3, 24, 24))
 703                 drvdata->trc_error = true;
 704         else
 705                 drvdata->trc_error = false;
 706
 707         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 708         if (BMVAL(etmidr3, 25, 25))
 709                 drvdata->syncpr = true;
 710         else
 711                 drvdata->syncpr = false;
 712
 713         /* STALLCTL, bit[26] is stall control implemented? */
 714         if (BMVAL(etmidr3, 26, 26))
 715                 drvdata->stallctl = true;
 716         else
 717                 drvdata->stallctl = false;
 718
 719         /* SYSSTALL, bit[27] implementation can support stall control? */
 720         if (BMVAL(etmidr3, 27, 27))
 721                 drvdata->sysstall = true;
 722         else
 723                 drvdata->sysstall = false;
 724
 725         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 726         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 727
 728         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 729         if (BMVAL(etmidr3, 31, 31))
 730                 drvdata->nooverflow = true;
 731         else
 732                 drvdata->nooverflow = false;
 733
 734         /* number of resources trace unit supports */
 735         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 736         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 737         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 738         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 739         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 740         /*
 741          * NUMRSPAIR, bits[19:16]
 742          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 743          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 744          * As such add 1 to the value of NUMRSPAIR for a better representation.
 745          *
 746          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
 747          * the default TRUE and FALSE resource selectors are omitted.
 748          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
 749          */
 750         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 751         if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0))
 752                 drvdata->nr_resource += 1;
 753         /*
 754          * NUMSSCC, bits[23:20] the number of single-shot
 755          * comparator control for tracing. Read any status regs as these
 756          * also contain RO capability data.
 757          */
 758         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 759         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 760                 drvdata->config.ss_status[i] =
 761                         readl_relaxed(drvdata->base + TRCSSCSRn(i));
 762         }
 763         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 764         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 765         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 766         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 767
 768         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 769         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 770         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 771         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 772         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 773         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 774         if (BMVAL(etmidr5, 22, 22))
 775                 drvdata->atbtrig = true;
 776         else
 777                 drvdata->atbtrig = false;
 778         /*
 779          * LPOVERRIDE, bit[23] implementation supports
 780          * low-power state override
 781          */
 782         if (BMVAL(etmidr5, 23, 23))
 783                 drvdata->lpoverride = true;
 784         else
 785                 drvdata->lpoverride = false;
 786         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 787         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 788         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 789         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 790         CS_LOCK(drvdata->base);
 791 }
 792
 793 /* Set ELx trace filter access in the TRCVICTLR register */
 794 static void etm4_set_victlr_access(struct etmv4_config *config)
 795 {
 796         u64 access_type;
 797
 798         config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK);
 799
 800         /*
 801          * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering
 802          * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by
 803          * etm4_get_access_type() but with a relative shift in this register.
 804          */
 805         access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR;
 806         config->vinst_ctrl |= (u32)access_type;
 807 }
 808
 809 static void etm4_set_default_config(struct etmv4_config *config)
 810 {
 811         /* disable all events tracing */
 812         config->eventctrl0 = 0x0;
 813         config->eventctrl1 = 0x0;
 814
 815         /* disable stalling */
 816         config->stall_ctrl = 0x0;
 817
 818         /* enable trace synchronization every 4096 bytes, if available */
 819         config->syncfreq = 0xC;
 820
 821         /* disable timestamp event */
 822         config->ts_ctrl = 0x0;
 823
 824         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 825         config->vinst_ctrl = BIT(0);
 826
 827         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
 828         etm4_set_victlr_access(config);
 829 }
 830
 831 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 832 {
 833         u64 access_type = 0;
 834
 835         /*
 836          * EXLEVEL_NS, bits[15:12]
 837          * The Exception levels are:
 838          *   Bit[12] Exception level 0 - Application
 839          *   Bit[13] Exception level 1 - OS
 840          *   Bit[14] Exception level 2 - Hypervisor
 841          *   Bit[15] Never implemented
 842          */
 843         if (!is_kernel_in_hyp_mode()) {
 844                 /* Stay away from hypervisor mode for non-VHE */
 845                 access_type =  ETM_EXLEVEL_NS_HYP;
 846                 if (config->mode & ETM_MODE_EXCL_KERN)
 847                         access_type |= ETM_EXLEVEL_NS_OS;
 848         } else if (config->mode & ETM_MODE_EXCL_KERN) {
 849                 access_type = ETM_EXLEVEL_NS_HYP;
 850         }
 851
 852         if (config->mode & ETM_MODE_EXCL_USER)
 853                 access_type |= ETM_EXLEVEL_NS_APP;
 854
 855         return access_type;
 856 }
 857
 858 static u64 etm4_get_access_type(struct etmv4_config *config)
 859 {
 860         u64 access_type = etm4_get_ns_access_type(config);
 861         u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
 862
 863         /*
 864          * EXLEVEL_S, bits[11:8], don't trace anything happening
 865          * in secure state.
 866          */
 867         access_type |= (ETM_EXLEVEL_S_APP       |
 868                         ETM_EXLEVEL_S_OS        |
 869                         s_hyp                   |
 870                         ETM_EXLEVEL_S_MON);
 871
 872         return access_type;
 873 }
 874
 875 static void etm4_set_comparator_filter(struct etmv4_config *config,
 876                                        u64 start, u64 stop, int comparator)
 877 {
 878         u64 access_type = etm4_get_access_type(config);
 879
 880         /* First half of default address comparator */
 881         config->addr_val[comparator] = start;
 882         config->addr_acc[comparator] = access_type;
 883         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
 884
 885         /* Second half of default address comparator */
 886         config->addr_val[comparator + 1] = stop;
 887         config->addr_acc[comparator + 1] = access_type;
 888         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
 889
 890         /*
 891          * Configure the ViewInst function to include this address range
 892          * comparator.
 893          *
 894          * @comparator is divided by two since it is the index in the
 895          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
 896          * address range comparator _pairs_.
 897          *
 898          * Therefore:
 899          *      index 0 -> compatator pair 0
 900          *      index 2 -> comparator pair 1
 901          *      index 4 -> comparator pair 2
 902          *      ...
 903          *      index 14 -> comparator pair 7
 904          */
 905         config->viiectlr |= BIT(comparator / 2);
 906 }
 907
 908 static void etm4_set_start_stop_filter(struct etmv4_config *config,
 909                                        u64 address, int comparator,
 910                                        enum etm_addr_type type)
 911 {
 912         int shift;
 913         u64 access_type = etm4_get_access_type(config);
 914
 915         /* Configure the comparator */
 916         config->addr_val[comparator] = address;
 917         config->addr_acc[comparator] = access_type;
 918         config->addr_type[comparator] = type;
 919
 920         /*
 921          * Configure ViewInst Start-Stop control register.
 922          * Addresses configured to start tracing go from bit 0 to n-1,
 923          * while those configured to stop tracing from 16 to 16 + n-1.
 924          */
 925         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
 926         config->vissctlr |= BIT(shift + comparator);
 927 }
 928
 929 static void etm4_set_default_filter(struct etmv4_config *config)
 930 {
 931         /* Trace everything 'default' filter achieved by no filtering */
 932         config->viiectlr = 0x0;
 933
 934         /*
 935          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
 936          * in the started state
 937          */
 938         config->vinst_ctrl |= BIT(9);
 939         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
 940
 941         /* No start-stop filtering for ViewInst */
 942         config->vissctlr = 0x0;
 943 }
 944
 945 static void etm4_set_default(struct etmv4_config *config)
 946 {
 947         if (WARN_ON_ONCE(!config))
 948                 return;
 949
 950         /*
 951          * Make default initialisation trace everything
 952          *
 953          * This is done by a minimum default config sufficient to enable
 954          * full instruction trace - with a default filter for trace all
 955          * achieved by having no filtering.
 956          */
 957         etm4_set_default_config(config);
 958         etm4_set_default_filter(config);
 959 }
 960
 961 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
 962 {
 963         int nr_comparator, index = 0;
 964         struct etmv4_config *config = &drvdata->config;
 965
 966         /*
 967          * nr_addr_cmp holds the number of comparator _pair_, so time 2
 968          * for the total number of comparators.
 969          */
 970         nr_comparator = drvdata->nr_addr_cmp * 2;
 971
 972         /* Go through the tally of comparators looking for a free one. */
 973         while (index < nr_comparator) {
 974                 switch (type) {
 975                 case ETM_ADDR_TYPE_RANGE:
 976                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
 977                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
 978                                 return index;
 979
 980                         /* Address range comparators go in pairs */
 981                         index += 2;
 982                         break;
 983                 case ETM_ADDR_TYPE_START:
 984                 case ETM_ADDR_TYPE_STOP:
 985                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
 986                                 return index;
 987
 988                         /* Start/stop address can have odd indexes */
 989                         index += 1;
 990                         break;
 991                 default:
 992                         return -EINVAL;
 993                 }
 994         }
 995
 996         /* If we are here all the comparators have been used. */
 997         return -ENOSPC;
 998 }
 999
1000 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1001                                   struct perf_event *event)
1002 {
1003         int i, comparator, ret = 0;
1004         u64 address;
1005         struct etmv4_config *config = &drvdata->config;
1006         struct etm_filters *filters = event->hw.addr_filters;
1007
1008         if (!filters)
1009                 goto default_filter;
1010
1011         /* Sync events with what Perf got */
1012         perf_event_addr_filters_sync(event);
1013
1014         /*
1015          * If there are no filters to deal with simply go ahead with
1016          * the default filter, i.e the entire address range.
1017          */
1018         if (!filters->nr_filters)
1019                 goto default_filter;
1020
1021         for (i = 0; i < filters->nr_filters; i++) {
1022                 struct etm_filter *filter = &filters->etm_filter[i];
1023                 enum etm_addr_type type = filter->type;
1024
1025                 /* See if a comparator is free. */
1026                 comparator = etm4_get_next_comparator(drvdata, type);
1027                 if (comparator < 0) {
1028                         ret = comparator;
1029                         goto out;
1030                 }
1031
1032                 switch (type) {
1033                 case ETM_ADDR_TYPE_RANGE:
1034                         etm4_set_comparator_filter(config,
1035                                                    filter->start_addr,
1036                                                    filter->stop_addr,
1037                                                    comparator);
1038                         /*
1039                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1040                          * in the started state
1041                          */
1042                         config->vinst_ctrl |= BIT(9);
1043
1044                         /* No start-stop filtering for ViewInst */
1045                         config->vissctlr = 0x0;
1046                         break;
1047                 case ETM_ADDR_TYPE_START:
1048                 case ETM_ADDR_TYPE_STOP:
1049                         /* Get the right start or stop address */
1050                         address = (type == ETM_ADDR_TYPE_START ?
1051                                    filter->start_addr :
1052                                    filter->stop_addr);
1053
1054                         /* Configure comparator */
1055                         etm4_set_start_stop_filter(config, address,
1056                                                    comparator, type);
1057
1058                         /*
1059                          * If filters::ssstatus == 1, trace acquisition was
1060                          * started but the process was yanked away before the
1061                          * the stop address was hit.  As such the start/stop
1062                          * logic needs to be re-started so that tracing can
1063                          * resume where it left.
1064                          *
1065                          * The start/stop logic status when a process is
1066                          * scheduled out is checked in function
1067                          * etm4_disable_perf().
1068                          */
1069                         if (filters->ssstatus)
1070                                 config->vinst_ctrl |= BIT(9);
1071
1072                         /* No include/exclude filtering for ViewInst */
1073                         config->viiectlr = 0x0;
1074                         break;
1075                 default:
1076                         ret = -EINVAL;
1077                         goto out;
1078                 }
1079         }
1080
1081         goto out;
1082
1083
1084 default_filter:
1085         etm4_set_default_filter(config);
1086
1087 out:
1088         return ret;
1089 }
1090
1091 void etm4_config_trace_mode(struct etmv4_config *config)
1092 {
1093         u32 mode;
1094
1095         mode = config->mode;
1096         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1097
1098         /* excluding kernel AND user space doesn't make sense */
1099         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1100
1101         /* nothing to do if neither flags are set */
1102         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1103                 return;
1104
1105         etm4_set_victlr_access(config);
1106 }
1107
1108 static int etm4_online_cpu(unsigned int cpu)
1109 {
1110         if (!etmdrvdata[cpu])
1111                 return 0;
1112
1113         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1114                 coresight_enable(etmdrvdata[cpu]->csdev);
1115         return 0;
1116 }
1117
1118 static int etm4_starting_cpu(unsigned int cpu)
1119 {
1120         if (!etmdrvdata[cpu])
1121                 return 0;
1122
1123         spin_lock(&etmdrvdata[cpu]->spinlock);
1124         if (!etmdrvdata[cpu]->os_unlock)
1125                 etm4_os_unlock(etmdrvdata[cpu]);
1126
1127         if (local_read(&etmdrvdata[cpu]->mode))
1128                 etm4_enable_hw(etmdrvdata[cpu]);
1129         spin_unlock(&etmdrvdata[cpu]->spinlock);
1130         return 0;
1131 }
1132
1133 static int etm4_dying_cpu(unsigned int cpu)
1134 {
1135         if (!etmdrvdata[cpu])
1136                 return 0;
1137
1138         spin_lock(&etmdrvdata[cpu]->spinlock);
1139         if (local_read(&etmdrvdata[cpu]->mode))
1140                 etm4_disable_hw(etmdrvdata[cpu]);
1141         spin_unlock(&etmdrvdata[cpu]->spinlock);
1142         return 0;
1143 }
1144
1145 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1146 {
1147         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1148 }
1149
1150 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1151 {
1152         int i, ret = 0;
1153         struct etmv4_save_state *state;
1154         struct device *etm_dev = &drvdata->csdev->dev;
1155
1156         /*
1157          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1158          * of ARM IHI 0064D
1159          */
1160         dsb(sy);
1161         isb();
1162
1163         CS_UNLOCK(drvdata->base);
1164
1165         /* Lock the OS lock to disable trace and external debugger access */
1166         etm4_os_lock(drvdata);
1167
1168         /* wait for TRCSTATR.PMSTABLE to go up */
1169         if (coresight_timeout(drvdata->base, TRCSTATR,
1170                               TRCSTATR_PMSTABLE_BIT, 1)) {
1171                 dev_err(etm_dev,
1172                         "timeout while waiting for PM Stable Status\n");
1173                 etm4_os_unlock(drvdata);
1174                 ret = -EBUSY;
1175                 goto out;
1176         }
1177
1178         state = drvdata->save_state;
1179
1180         state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR);
1181         state->trcprocselr = readl(drvdata->base + TRCPROCSELR);
1182         state->trcconfigr = readl(drvdata->base + TRCCONFIGR);
1183         state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
1184         state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
1185         state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
1186         state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
1187         state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
1188         state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
1189         state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
1190         state->trcbbctlr = readl(drvdata->base + TRCBBCTLR);
1191         state->trctraceidr = readl(drvdata->base + TRCTRACEIDR);
1192         state->trcqctlr = readl(drvdata->base + TRCQCTLR);
1193
1194         state->trcvictlr = readl(drvdata->base + TRCVICTLR);
1195         state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR);
1196         state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR);
1197         state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
1198         state->trcvdctlr = readl(drvdata->base + TRCVDCTLR);
1199         state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
1200         state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
1201
1202         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1203                 state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
1204
1205         state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
1206         state->trcseqstr = readl(drvdata->base + TRCSEQSTR);
1207         state->trcextinselr = readl(drvdata->base + TRCEXTINSELR);
1208
1209         for (i = 0; i < drvdata->nr_cntr; i++) {
1210                 state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i));
1211                 state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i));
1212                 state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i));
1213         }
1214
1215         for (i = 0; i < drvdata->nr_resource * 2; i++)
1216                 state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i));
1217
1218         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1219                 state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
1220                 state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
1221                 state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
1222         }
1223
1224         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1225                 state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i));
1226                 state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i));
1227         }
1228
1229         /*
1230          * Data trace stream is architecturally prohibited for A profile cores
1231          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1232          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1233          * unit") of ARM IHI 0064D.
1234          */
1235
1236         for (i = 0; i < drvdata->numcidc; i++)
1237                 state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i));
1238
1239         for (i = 0; i < drvdata->numvmidc; i++)
1240                 state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
1241
1242         state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
1243         state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
1244
1245         state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
1246         state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
1247
1248         state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
1249
1250         state->trcpdcr = readl(drvdata->base + TRCPDCR);
1251
1252         /* wait for TRCSTATR.IDLE to go up */
1253         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1254                 dev_err(etm_dev,
1255                         "timeout while waiting for Idle Trace Status\n");
1256                 etm4_os_unlock(drvdata);
1257                 ret = -EBUSY;
1258                 goto out;
1259         }
1260
1261         drvdata->state_needs_restore = true;
1262
1263         /*
1264          * Power can be removed from the trace unit now. We do this to
1265          * potentially save power on systems that respect the TRCPDCR_PU
1266          * despite requesting software to save/restore state.
1267          */
1268         writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
1269                         drvdata->base + TRCPDCR);
1270
1271 out:
1272         CS_LOCK(drvdata->base);
1273         return ret;
1274 }
1275
1276 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1277 {
1278         int i;
1279         struct etmv4_save_state *state = drvdata->save_state;
1280
1281         CS_UNLOCK(drvdata->base);
1282
1283         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1284
1285         writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR);
1286         writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR);
1287         writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR);
1288         writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
1289         writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
1290         writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
1291         writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
1292         writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
1293         writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
1294         writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
1295         writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR);
1296         writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR);
1297         writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR);
1298
1299         writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR);
1300         writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR);
1301         writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR);
1302         writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
1303         writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR);
1304         writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
1305         writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
1306
1307         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1308                 writel_relaxed(state->trcseqevr[i],
1309                                drvdata->base + TRCSEQEVRn(i));
1310
1311         writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR);
1312         writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR);
1313         writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR);
1314
1315         for (i = 0; i < drvdata->nr_cntr; i++) {
1316                 writel_relaxed(state->trccntrldvr[i],
1317                                drvdata->base + TRCCNTRLDVRn(i));
1318                 writel_relaxed(state->trccntctlr[i],
1319                                drvdata->base + TRCCNTCTLRn(i));
1320                 writel_relaxed(state->trccntvr[i],
1321                                drvdata->base + TRCCNTVRn(i));
1322         }
1323
1324         for (i = 0; i < drvdata->nr_resource * 2; i++)
1325                 writel_relaxed(state->trcrsctlr[i],
1326                                drvdata->base + TRCRSCTLRn(i));
1327
1328         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1329                 writel_relaxed(state->trcssccr[i],
1330                                drvdata->base + TRCSSCCRn(i));
1331                 writel_relaxed(state->trcsscsr[i],
1332                                drvdata->base + TRCSSCSRn(i));
1333                 writel_relaxed(state->trcsspcicr[i],
1334                                drvdata->base + TRCSSPCICRn(i));
1335         }
1336
1337         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1338                 writeq_relaxed(state->trcacvr[i],
1339                                drvdata->base + TRCACVRn(i));
1340                 writeq_relaxed(state->trcacatr[i],
1341                                drvdata->base + TRCACATRn(i));
1342         }
1343
1344         for (i = 0; i < drvdata->numcidc; i++)
1345                 writeq_relaxed(state->trccidcvr[i],
1346                                drvdata->base + TRCCIDCVRn(i));
1347
1348         for (i = 0; i < drvdata->numvmidc; i++)
1349                 writeq_relaxed(state->trcvmidcvr[i],
1350                                drvdata->base + TRCVMIDCVRn(i));
1351
1352         writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
1353         writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
1354
1355         writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
1356         writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
1357
1358         writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
1359
1360         writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
1361
1362         drvdata->state_needs_restore = false;
1363
1364         /*
1365          * As recommended by section 4.3.7 ("Synchronization when using the
1366          * memory-mapped interface") of ARM IHI 0064D
1367          */
1368         dsb(sy);
1369         isb();
1370
1371         /* Unlock the OS lock to re-enable trace and external debug access */
1372         etm4_os_unlock(drvdata);
1373         CS_LOCK(drvdata->base);
1374 }
1375
1376 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1377                               void *v)
1378 {
1379         struct etmv4_drvdata *drvdata;
1380         unsigned int cpu = smp_processor_id();
1381
1382         if (!etmdrvdata[cpu])
1383                 return NOTIFY_OK;
1384
1385         drvdata = etmdrvdata[cpu];
1386
1387         if (!drvdata->save_state)
1388                 return NOTIFY_OK;
1389
1390         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1391                 return NOTIFY_BAD;
1392
1393         switch (cmd) {
1394         case CPU_PM_ENTER:
1395                 /* save the state if self-hosted coresight is in use */
1396                 if (local_read(&drvdata->mode))
1397                         if (etm4_cpu_save(drvdata))
1398                                 return NOTIFY_BAD;
1399                 break;
1400         case CPU_PM_EXIT:
1401         case CPU_PM_ENTER_FAILED:
1402                 if (drvdata->state_needs_restore)
1403                         etm4_cpu_restore(drvdata);
1404                 break;
1405         default:
1406                 return NOTIFY_DONE;
1407         }
1408
1409         return NOTIFY_OK;
1410 }
1411
1412 static struct notifier_block etm4_cpu_pm_nb = {
1413         .notifier_call = etm4_cpu_pm_notify,
1414 };
1415
1416 /* Setup PM. Deals with error conditions and counts */
1417 static int __init etm4_pm_setup(void)
1418 {
1419         int ret;
1420
1421         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1422         if (ret)
1423                 return ret;
1424
1425         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1426                                         "arm/coresight4:starting",
1427                                         etm4_starting_cpu, etm4_dying_cpu);
1428
1429         if (ret)
1430                 goto unregister_notifier;
1431
1432         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1433                                         "arm/coresight4:online",
1434                                         etm4_online_cpu, NULL);
1435
1436         /* HP dyn state ID returned in ret on success */
1437         if (ret > 0) {
1438                 hp_online = ret;
1439                 return 0;
1440         }
1441
1442         /* failed dyn state - remove others */
1443         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1444
1445 unregister_notifier:
1446         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1447         return ret;
1448 }
1449
1450 static void etm4_pm_clear(void)
1451 {
1452         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1453         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1454         if (hp_online) {
1455                 cpuhp_remove_state_nocalls(hp_online);
1456                 hp_online = 0;
1457         }
1458 }
1459
1460 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1461 {
1462         int ret;
1463         void __iomem *base;
1464         struct device *dev = &adev->dev;
1465         struct coresight_platform_data *pdata = NULL;
1466         struct etmv4_drvdata *drvdata;
1467         struct resource *res = &adev->res;
1468         struct coresight_desc desc = { 0 };
1469
1470         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1471         if (!drvdata)
1472                 return -ENOMEM;
1473
1474         dev_set_drvdata(dev, drvdata);
1475
1476         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1477                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1478                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1479
1480         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1481                 drvdata->save_state = devm_kmalloc(dev,
1482                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1483                 if (!drvdata->save_state)
1484                         return -ENOMEM;
1485         }
1486
1487         if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1488                 drvdata->skip_power_up = true;
1489
1490         /* Validity for the resource is already checked by the AMBA core */
1491         base = devm_ioremap_resource(dev, res);
1492         if (IS_ERR(base))
1493                 return PTR_ERR(base);
1494
1495         drvdata->base = base;
1496
1497         spin_lock_init(&drvdata->spinlock);
1498
1499         drvdata->cpu = coresight_get_cpu(dev);
1500         if (drvdata->cpu < 0)
1501                 return drvdata->cpu;
1502
1503         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1504         if (!desc.name)
1505                 return -ENOMEM;
1506
1507         if (smp_call_function_single(drvdata->cpu,
1508                                 etm4_init_arch_data,  drvdata, 1))
1509                 dev_err(dev, "ETM arch init failed\n");
1510
1511         if (etm4_arch_supported(drvdata->arch) == false)
1512                 return -EINVAL;
1513
1514         etm4_init_trace_id(drvdata);
1515         etm4_set_default(&drvdata->config);
1516
1517         pdata = coresight_get_platform_data(dev);
1518         if (IS_ERR(pdata))
1519                 return PTR_ERR(pdata);
1520
1521         adev->dev.platform_data = pdata;
1522
1523         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1524         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1525         desc.ops = &etm4_cs_ops;
1526         desc.pdata = pdata;
1527         desc.dev = dev;
1528         desc.groups = coresight_etmv4_groups;
1529         drvdata->csdev = coresight_register(&desc);
1530         if (IS_ERR(drvdata->csdev))
1531                 return PTR_ERR(drvdata->csdev);
1532
1533         ret = etm_perf_symlink(drvdata->csdev, true);
1534         if (ret) {
1535                 coresight_unregister(drvdata->csdev);
1536                 return ret;
1537         }
1538
1539         etmdrvdata[drvdata->cpu] = drvdata;
1540
1541         pm_runtime_put(&adev->dev);
1542         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1543                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1544
1545         if (boot_enable) {
1546                 coresight_enable(drvdata->csdev);
1547                 drvdata->boot_enable = true;
1548         }
1549
1550         return 0;
1551 }
1552
1553 static struct amba_cs_uci_id uci_id_etm4[] = {
1554         {
1555                 /*  ETMv4 UCI data */
1556                 .devarch        = 0x47704a13,
1557                 .devarch_mask   = 0xfff0ffff,
1558                 .devtype        = 0x00000013,
1559         }
1560 };
1561
1562 static void __exit clear_etmdrvdata(void *info)
1563 {
1564         int cpu = *(int *)info;
1565
1566         etmdrvdata[cpu] = NULL;
1567 }
1568
1569 static int __exit etm4_remove(struct amba_device *adev)
1570 {
1571         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1572
1573         etm_perf_symlink(drvdata->csdev, false);
1574
1575         /*
1576          * Taking hotplug lock here to avoid racing between etm4_remove and
1577          * CPU hotplug call backs.
1578          */
1579         cpus_read_lock();
1580         /*
1581          * The readers for etmdrvdata[] are CPU hotplug call backs
1582          * and PM notification call backs. Change etmdrvdata[i] on
1583          * CPU i ensures these call backs has consistent view
1584          * inside one call back function.
1585          */
1586         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1587                 etmdrvdata[drvdata->cpu] = NULL;
1588
1589         cpus_read_unlock();
1590
1591         coresight_unregister(drvdata->csdev);
1592
1593         return 0;
1594 }
1595
1596 static const struct amba_id etm4_ids[] = {
1597         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1598         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1599         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1600         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1601         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1602         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1603         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1604         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1605         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1606         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1607         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1608         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1609         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1610         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1611         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1612         {},
1613 };
1614
1615 MODULE_DEVICE_TABLE(amba, etm4_ids);
1616
1617 static struct amba_driver etm4x_driver = {
1618         .drv = {
1619                 .name   = "coresight-etm4x",
1620                 .owner  = THIS_MODULE,
1621                 .suppress_bind_attrs = true,
1622         },
1623         .probe          = etm4_probe,
1624         .remove         = etm4_remove,
1625         .id_table       = etm4_ids,
1626 };
1627
1628 static int __init etm4x_init(void)
1629 {
1630         int ret;
1631
1632         ret = etm4_pm_setup();
1633
1634         /* etm4_pm_setup() does its own cleanup - exit on error */
1635         if (ret)
1636                 return ret;
1637
1638         ret = amba_driver_register(&etm4x_driver);
1639         if (ret) {
1640                 pr_err("Error registering etm4x driver\n");
1641                 etm4_pm_clear();
1642         }
1643
1644         return ret;
1645 }
1646
1647 static void __exit etm4x_exit(void)
1648 {
1649         amba_driver_unregister(&etm4x_driver);
1650         etm4_pm_clear();
1651 }
1652
1653 module_init(etm4x_init);
1654 module_exit(etm4x_exit);
1655
1656 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1657 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1658 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1659 MODULE_LICENSE("GPL v2");