1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
8 #include <linux/host1x.h>
9 #include <linux/iommu.h>
10 #include <linux/slab.h>
12 #include <trace/events/host1x.h>
14 #include "../channel.h"
19 #define TRACE_MAX_LENGTH 128U
21 static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
22 u32 offset, u32 words)
24 struct device *dev = cdma_to_channel(cdma)->dev;
27 if (host1x_debug_trace_cmdbuf)
28 mem = host1x_bo_mmap(bo);
33 * Write in batches of 128 as there seems to be a limit
34 * of how much you can output to ftrace at once.
36 for (i = 0; i < words; i += TRACE_MAX_LENGTH) {
37 u32 num_words = min(words - i, TRACE_MAX_LENGTH);
39 offset += i * sizeof(u32);
41 trace_host1x_cdma_push_gather(dev_name(dev), bo,
46 host1x_bo_munmap(bo, mem);
50 static void submit_gathers(struct host1x_job *job)
52 struct host1x_cdma *cdma = &job->channel->cdma;
54 struct device *dev = job->channel->dev;
58 for (i = 0; i < job->num_gathers; i++) {
59 struct host1x_job_gather *g = &job->gathers[i];
60 dma_addr_t addr = g->base + g->offset;
63 op2 = lower_32_bits(addr);
64 op3 = upper_32_bits(addr);
66 trace_write_gather(cdma, g->bo, g->offset, g->words);
70 u32 op1 = host1x_opcode_gather_wide(g->words);
71 u32 op4 = HOST1X_OPCODE_NOP;
73 host1x_cdma_push_wide(cdma, op1, op2, op3, op4);
75 dev_err(dev, "invalid gather for push buffer %pad\n",
80 u32 op1 = host1x_opcode_gather(g->words);
82 host1x_cdma_push(cdma, op1, op2);
87 static inline void synchronize_syncpt_base(struct host1x_job *job)
89 struct host1x_syncpt *sp = job->syncpt;
93 value = host1x_syncpt_read_max(sp);
96 host1x_cdma_push(&job->channel->cdma,
97 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
98 HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1),
99 HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(id) |
100 HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value));
103 static void host1x_channel_set_streamid(struct host1x_channel *channel)
107 #ifdef CONFIG_IOMMU_API
108 struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
110 sid = spec->ids[0] & 0xffff;
113 host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
117 static int channel_submit(struct host1x_job *job)
119 struct host1x_channel *ch = job->channel;
120 struct host1x_syncpt *sp = job->syncpt;
121 u32 user_syncpt_incrs = job->syncpt_incrs;
125 struct host1x_waitlist *completed_waiter = NULL;
126 struct host1x *host = dev_get_drvdata(ch->dev->parent);
128 trace_host1x_channel_submit(dev_name(ch->dev),
129 job->num_gathers, job->num_relocs,
130 job->syncpt->id, job->syncpt_incrs);
132 /* before error checks, return current max */
133 prev_max = job->syncpt_end = host1x_syncpt_read_max(sp);
135 /* get submit lock */
136 err = mutex_lock_interruptible(&ch->submitlock);
140 completed_waiter = kzalloc(sizeof(*completed_waiter), GFP_KERNEL);
141 if (!completed_waiter) {
142 mutex_unlock(&ch->submitlock);
147 host1x_channel_set_streamid(ch);
149 /* begin a CDMA submit */
150 err = host1x_cdma_begin(&ch->cdma, job);
152 mutex_unlock(&ch->submitlock);
156 if (job->serialize) {
158 * Force serialization by inserting a host wait for the
159 * previous job to finish before this one can commence.
161 host1x_cdma_push(&ch->cdma,
162 host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
163 host1x_uclass_wait_syncpt_r(), 1),
164 host1x_class_host_wait_syncpt(job->syncpt->id,
165 host1x_syncpt_read_max(sp)));
168 /* Synchronize base register to allow using it for relative waiting */
170 synchronize_syncpt_base(job);
172 syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
174 host1x_hw_syncpt_assign_to_channel(host, sp, ch);
176 job->syncpt_end = syncval;
178 /* add a setclass for modules that require it */
180 host1x_cdma_push(&ch->cdma,
181 host1x_opcode_setclass(job->class, 0, 0),
186 /* end CDMA submit & stash pinned hMems into sync queue */
187 host1x_cdma_end(&ch->cdma, job);
189 trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, syncval);
191 /* schedule a submit complete interrupt */
192 err = host1x_intr_add_action(host, sp, syncval,
193 HOST1X_INTR_ACTION_SUBMIT_COMPLETE, ch,
194 completed_waiter, NULL);
195 completed_waiter = NULL;
196 WARN(err, "Failed to set submit complete interrupt");
198 mutex_unlock(&ch->submitlock);
203 kfree(completed_waiter);
207 static void enable_gather_filter(struct host1x *host,
208 struct host1x_channel *ch)
216 val = host1x_hypervisor_readl(
217 host, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
218 val |= BIT(ch->id % 32);
219 host1x_hypervisor_writel(
220 host, val, HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(ch->id / 32));
223 HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(1),
224 HOST1X_CHANNEL_CHANNELCTRL);
228 static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
232 ch->regs = dev->regs + index * 0x4000;
234 ch->regs = dev->regs + index * 0x100;
236 enable_gather_filter(dev, ch);
240 static const struct host1x_channel_ops host1x_channel_ops = {
241 .init = host1x_channel_init,
242 .submit = channel_submit,