1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022 Intel Corporation
6 #ifndef _XE_PT_TYPES_H_
7 #define _XE_PT_TYPES_H_
9 #include <linux/types.h>
11 #include "xe_pt_walk.h"
20 __XE_CACHE_LEVEL_COUNT,
23 #define XE_VM_MAX_LEVEL 4
29 unsigned int num_live;
32 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)
33 /** addr: Virtual address start address of the PT. */
39 u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,
40 enum xe_cache_level cache, u32 pt_level);
41 u64 (*pte_encode_vma)(u64 pte, struct xe_vma *vma,
42 enum xe_cache_level cache, u32 pt_level);
43 u64 (*pte_encode_addr)(u64 addr, enum xe_cache_level cache,
44 u32 pt_level, bool devmem, u64 flags);
45 u64 (*pde_encode_bo)(struct xe_bo *bo, u64 bo_offset,
46 const enum xe_cache_level cache);
54 struct xe_vm_pgtable_update {
55 /** @bo: page table bo to write to */
58 /** @ofs: offset inside this PTE to begin writing to (in qwords) */
61 /** @qwords: number of PTE's to write */
64 /** @pt: opaque pointer useful for the caller of xe_migrate_update_pgtables */
67 /** @pt_entries: Newly added pagetable entries */
68 struct xe_pt_entry *pt_entries;
70 /** @flags: Target flags */