drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <linux/clk.h>
  39 #include <linux/component.h>
  40 #include <linux/i2c.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/rational.h>
  46 #include <linux/reset.h>
  47 #include <sound/dmaengine_pcm.h>
  48 #include <sound/pcm_drm_eld.h>
  49 #include <sound/pcm_params.h>
  50 #include <sound/soc.h>
  51 #include "media/cec.h"
  52 #include "vc4_drv.h"
  53 #include "vc4_hdmi.h"
  54 #include "vc4_hdmi_regs.h"
  55 #include "vc4_regs.h"
  56
  57 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  58 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  59 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  60 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  61 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  62 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  63
  64 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  65 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  66 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  67 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  68
  69 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  70 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  71 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  72 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  73 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  74 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  75
  76 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  77 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  78
  79 # define VC4_HD_M_SW_RST                        BIT(2)
  80 # define VC4_HD_M_ENABLE                        BIT(0)
  81
  82 #define CEC_CLOCK_FREQ 40000
  83 #define VC4_HSM_MID_CLOCK 149985000
  84
  85 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
  86 {
  87         struct drm_info_node *node = (struct drm_info_node *)m->private;
  88         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
  89         struct drm_printer p = drm_seq_file_printer(m);
  90
  91         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
  92         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
  93
  94         return 0;
  95 }
  96
  97 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
  98 {
  99         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 100         udelay(1);
 101         HDMI_WRITE(HDMI_M_CTL, 0);
 102
 103         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 104
 105         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 106                    VC4_HDMI_SW_RESET_HDMI |
 107                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 108
 109         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 110 }
 111
 112 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 113 {
 114         reset_control_reset(vc4_hdmi->reset);
 115
 116         HDMI_WRITE(HDMI_DVP_CTL, 0);
 117
 118         HDMI_WRITE(HDMI_CLOCK_STOP,
 119                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 120 }
 121
 122 static enum drm_connector_status
 123 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 124 {
 125         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 126
 127         if (vc4_hdmi->hpd_gpio) {
 128                 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
 129                     vc4_hdmi->hpd_active_low)
 130                         return connector_status_connected;
 131                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 132                 return connector_status_disconnected;
 133         }
 134
 135         if (drm_probe_ddc(vc4_hdmi->ddc))
 136                 return connector_status_connected;
 137
 138         if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 139                 return connector_status_connected;
 140         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 141         return connector_status_disconnected;
 142 }
 143
 144 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 145 {
 146         drm_connector_unregister(connector);
 147         drm_connector_cleanup(connector);
 148 }
 149
 150 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 151 {
 152         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 153         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 154         int ret = 0;
 155         struct edid *edid;
 156
 157         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 158         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 159         if (!edid)
 160                 return -ENODEV;
 161
 162         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 163
 164         drm_connector_update_edid_property(connector, edid);
 165         ret = drm_add_edid_modes(connector, edid);
 166         kfree(edid);
 167
 168         return ret;
 169 }
 170
 171 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 172 {
 173         struct vc4_hdmi_connector_state *old_state =
 174                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 175         struct vc4_hdmi_connector_state *new_state =
 176                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 177
 178         if (connector->state)
 179                 __drm_atomic_helper_connector_destroy_state(connector->state);
 180
 181         kfree(old_state);
 182         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 183
 184         if (!new_state)
 185                 return;
 186
 187         drm_atomic_helper_connector_tv_reset(connector);
 188 }
 189
 190 static struct drm_connector_state *
 191 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 192 {
 193         struct drm_connector_state *conn_state = connector->state;
 194         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 195         struct vc4_hdmi_connector_state *new_state;
 196
 197         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 198         if (!new_state)
 199                 return NULL;
 200
 201         new_state->pixel_rate = vc4_state->pixel_rate;
 202         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 203
 204         return &new_state->base;
 205 }
 206
 207 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 208         .detect = vc4_hdmi_connector_detect,
 209         .fill_modes = drm_helper_probe_single_connector_modes,
 210         .destroy = vc4_hdmi_connector_destroy,
 211         .reset = vc4_hdmi_connector_reset,
 212         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 213         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 214 };
 215
 216 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 217         .get_modes = vc4_hdmi_connector_get_modes,
 218 };
 219
 220 static int vc4_hdmi_connector_init(struct drm_device *dev,
 221                                    struct vc4_hdmi *vc4_hdmi)
 222 {
 223         struct drm_connector *connector = &vc4_hdmi->connector;
 224         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 225         int ret;
 226
 227         drm_connector_init_with_ddc(dev, connector,
 228                                     &vc4_hdmi_connector_funcs,
 229                                     DRM_MODE_CONNECTOR_HDMIA,
 230                                     vc4_hdmi->ddc);
 231         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 232
 233         /* Create and attach TV margin props to this connector. */
 234         ret = drm_mode_create_tv_margin_properties(dev);
 235         if (ret)
 236                 return ret;
 237
 238         drm_connector_attach_tv_margin_properties(connector);
 239
 240         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 241                              DRM_CONNECTOR_POLL_DISCONNECT);
 242
 243         connector->interlace_allowed = 1;
 244         connector->doublescan_allowed = 0;
 245
 246         drm_connector_attach_encoder(connector, encoder);
 247
 248         return 0;
 249 }
 250
 251 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 252                                 enum hdmi_infoframe_type type,
 253                                 bool poll)
 254 {
 255         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 256         u32 packet_id = type - 0x80;
 257
 258         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 259                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 260
 261         if (!poll)
 262                 return 0;
 263
 264         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 265                           BIT(packet_id)), 100);
 266 }
 267
 268 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 269                                      union hdmi_infoframe *frame)
 270 {
 271         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 272         u32 packet_id = frame->any.type - 0x80;
 273         const struct vc4_hdmi_register *ram_packet_start =
 274                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 275         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 276         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 277                                                        ram_packet_start->reg);
 278         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 279         ssize_t len, i;
 280         int ret;
 281
 282         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 283                     VC4_HDMI_RAM_PACKET_ENABLE),
 284                   "Packet RAM has to be on to store the packet.");
 285
 286         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 287         if (len < 0)
 288                 return;
 289
 290         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 291         if (ret) {
 292                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 293                 return;
 294         }
 295
 296         for (i = 0; i < len; i += 7) {
 297                 writel(buffer[i + 0] << 0 |
 298                        buffer[i + 1] << 8 |
 299                        buffer[i + 2] << 16,
 300                        base + packet_reg);
 301                 packet_reg += 4;
 302
 303                 writel(buffer[i + 3] << 0 |
 304                        buffer[i + 4] << 8 |
 305                        buffer[i + 5] << 16 |
 306                        buffer[i + 6] << 24,
 307                        base + packet_reg);
 308                 packet_reg += 4;
 309         }
 310
 311         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 312                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 313         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 314                         BIT(packet_id)), 100);
 315         if (ret)
 316                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 317 }
 318
 319 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 320 {
 321         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 322         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 323         struct drm_connector *connector = &vc4_hdmi->connector;
 324         struct drm_connector_state *cstate = connector->state;
 325         struct drm_crtc *crtc = encoder->crtc;
 326         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 327         union hdmi_infoframe frame;
 328         int ret;
 329
 330         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 331                                                        connector, mode);
 332         if (ret < 0) {
 333                 DRM_ERROR("couldn't fill AVI infoframe\n");
 334                 return;
 335         }
 336
 337         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 338                                            connector, mode,
 339                                            vc4_encoder->limited_rgb_range ?
 340                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 341                                            HDMI_QUANTIZATION_RANGE_FULL);
 342
 343         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 344
 345         vc4_hdmi_write_infoframe(encoder, &frame);
 346 }
 347
 348 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 349 {
 350         union hdmi_infoframe frame;
 351         int ret;
 352
 353         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 354         if (ret < 0) {
 355                 DRM_ERROR("couldn't fill SPD infoframe\n");
 356                 return;
 357         }
 358
 359         frame.spd.sdi = HDMI_SPD_SDI_PC;
 360
 361         vc4_hdmi_write_infoframe(encoder, &frame);
 362 }
 363
 364 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 365 {
 366         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 367         union hdmi_infoframe frame;
 368
 369         hdmi_audio_infoframe_init(&frame.audio);
 370
 371         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 372         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 373         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 374         frame.audio.channels = vc4_hdmi->audio.channels;
 375
 376         vc4_hdmi_write_infoframe(encoder, &frame);
 377 }
 378
 379 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 380 {
 381         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 382
 383         vc4_hdmi_set_avi_infoframe(encoder);
 384         vc4_hdmi_set_spd_infoframe(encoder);
 385         /*
 386          * If audio was streaming, then we need to reenabled the audio
 387          * infoframe here during encoder_enable.
 388          */
 389         if (vc4_hdmi->audio.streaming)
 390                 vc4_hdmi_set_audio_infoframe(encoder);
 391 }
 392
 393 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 394                                                struct drm_atomic_state *state)
 395 {
 396         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 397
 398         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 399
 400         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
 401                    VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
 402
 403         HDMI_WRITE(HDMI_VID_CTL,
 404                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 405 }
 406
 407 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 408                                                  struct drm_atomic_state *state)
 409 {
 410         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 411         int ret;
 412
 413         if (vc4_hdmi->variant->phy_disable)
 414                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 415
 416         HDMI_WRITE(HDMI_VID_CTL,
 417                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 418
 419         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 420         clk_disable_unprepare(vc4_hdmi->hsm_clock);
 421         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 422
 423         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 424         if (ret < 0)
 425                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 426 }
 427
 428 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 429 {
 430 }
 431
 432 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 433 {
 434         u32 csc_ctl;
 435
 436         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 437                                 VC4_HD_CSC_CTL_ORDER);
 438
 439         if (enable) {
 440                 /* CEA VICs other than #1 requre limited range RGB
 441                  * output unless overridden by an AVI infoframe.
 442                  * Apply a colorspace conversion to squash 0-255 down
 443                  * to 16-235.  The matrix here is:
 444                  *
 445                  * [ 0      0      0.8594 16]
 446                  * [ 0      0.8594 0      16]
 447                  * [ 0.8594 0      0      16]
 448                  * [ 0      0      0       1]
 449                  */
 450                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 451                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 452                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 453                                          VC4_HD_CSC_CTL_MODE);
 454
 455                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 456                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 457                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 458                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 459                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 460                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 461         }
 462
 463         /* The RGB order applies even when CSC is disabled. */
 464         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 465 }
 466
 467 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 468 {
 469         u32 csc_ctl;
 470
 471         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 472
 473         if (enable) {
 474                 /* CEA VICs other than #1 requre limited range RGB
 475                  * output unless overridden by an AVI infoframe.
 476                  * Apply a colorspace conversion to squash 0-255 down
 477                  * to 16-235.  The matrix here is:
 478                  *
 479                  * [ 0.8594 0      0      16]
 480                  * [ 0      0.8594 0      16]
 481                  * [ 0      0      0.8594 16]
 482                  * [ 0      0      0       1]
 483                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 484                  */
 485                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 486                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 487                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 488                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 489                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 490                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 491         } else {
 492                 /* Still use the matrix for full range, but make it unity.
 493                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 494                  */
 495                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 496                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 497                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 498                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 499                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 500                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 501         }
 502
 503         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 504 }
 505
 506 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 507                                  struct drm_display_mode *mode)
 508 {
 509         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 510         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 511         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 512         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 513         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 514                                    VC4_HDMI_VERTA_VSP) |
 515                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 516                                    VC4_HDMI_VERTA_VFP) |
 517                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 518         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 519                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 520                                    VC4_HDMI_VERTB_VBP));
 521         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 522                           VC4_SET_FIELD(mode->crtc_vtotal -
 523                                         mode->crtc_vsync_end -
 524                                         interlaced,
 525                                         VC4_HDMI_VERTB_VBP));
 526
 527         HDMI_WRITE(HDMI_HORZA,
 528                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 529                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 530                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 531                                  VC4_HDMI_HORZA_HAP));
 532
 533         HDMI_WRITE(HDMI_HORZB,
 534                    VC4_SET_FIELD((mode->htotal -
 535                                   mode->hsync_end) * pixel_rep,
 536                                  VC4_HDMI_HORZB_HBP) |
 537                    VC4_SET_FIELD((mode->hsync_end -
 538                                   mode->hsync_start) * pixel_rep,
 539                                  VC4_HDMI_HORZB_HSP) |
 540                    VC4_SET_FIELD((mode->hsync_start -
 541                                   mode->hdisplay) * pixel_rep,
 542                                  VC4_HDMI_HORZB_HFP));
 543
 544         HDMI_WRITE(HDMI_VERTA0, verta);
 545         HDMI_WRITE(HDMI_VERTA1, verta);
 546
 547         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 548         HDMI_WRITE(HDMI_VERTB1, vertb);
 549 }
 550 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 551                                  struct drm_display_mode *mode)
 552 {
 553         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 554         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 555         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 556         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 557         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 558                                    VC5_HDMI_VERTA_VSP) |
 559                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 560                                    VC5_HDMI_VERTA_VFP) |
 561                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 562         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 563                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 564                                    VC4_HDMI_VERTB_VBP));
 565         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 566                           VC4_SET_FIELD(mode->crtc_vtotal -
 567                                         mode->crtc_vsync_end -
 568                                         interlaced,
 569                                         VC4_HDMI_VERTB_VBP));
 570
 571         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 572         HDMI_WRITE(HDMI_HORZA,
 573                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 574                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 575                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 576                                  VC5_HDMI_HORZA_HAP) |
 577                    VC4_SET_FIELD((mode->hsync_start -
 578                                   mode->hdisplay) * pixel_rep,
 579                                  VC5_HDMI_HORZA_HFP));
 580
 581         HDMI_WRITE(HDMI_HORZB,
 582                    VC4_SET_FIELD((mode->htotal -
 583                                   mode->hsync_end) * pixel_rep,
 584                                  VC5_HDMI_HORZB_HBP) |
 585                    VC4_SET_FIELD((mode->hsync_end -
 586                                   mode->hsync_start) * pixel_rep,
 587                                  VC5_HDMI_HORZB_HSP));
 588
 589         HDMI_WRITE(HDMI_VERTA0, verta);
 590         HDMI_WRITE(HDMI_VERTA1, verta);
 591
 592         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 593         HDMI_WRITE(HDMI_VERTB1, vertb);
 594
 595         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 596 }
 597
 598 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 599 {
 600         u32 drift;
 601         int ret;
 602
 603         drift = HDMI_READ(HDMI_FIFO_CTL);
 604         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 605
 606         HDMI_WRITE(HDMI_FIFO_CTL,
 607                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 608         HDMI_WRITE(HDMI_FIFO_CTL,
 609                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 610         usleep_range(1000, 1100);
 611         HDMI_WRITE(HDMI_FIFO_CTL,
 612                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 613         HDMI_WRITE(HDMI_FIFO_CTL,
 614                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 615
 616         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 617                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 618         WARN_ONCE(ret, "Timeout waiting for "
 619                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 620 }
 621
 622 static struct drm_connector_state *
 623 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 624                                      struct drm_atomic_state *state)
 625 {
 626         struct drm_connector_state *conn_state;
 627         struct drm_connector *connector;
 628         unsigned int i;
 629
 630         for_each_new_connector_in_state(state, connector, conn_state, i) {
 631                 if (conn_state->best_encoder == encoder)
 632                         return conn_state;
 633         }
 634
 635         return NULL;
 636 }
 637
 638 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 639                                                 struct drm_atomic_state *state)
 640 {
 641         struct drm_connector_state *conn_state =
 642                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 643         struct vc4_hdmi_connector_state *vc4_conn_state =
 644                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 645         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 646         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 647         unsigned long pixel_rate, hsm_rate;
 648         int ret;
 649
 650         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
 651         if (ret < 0) {
 652                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 653                 return;
 654         }
 655
 656         pixel_rate = vc4_conn_state->pixel_rate;
 657         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 658         if (ret) {
 659                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 660                 return;
 661         }
 662
 663         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 664         if (ret) {
 665                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 666                 return;
 667         }
 668
 669         /*
 670          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 671          * be faster than pixel clock, infinitesimally faster, tested in
 672          * simulation. Otherwise, exact value is unimportant for HDMI
 673          * operation." This conflicts with bcm2835's vc4 documentation, which
 674          * states HSM's clock has to be at least 108% of the pixel clock.
 675          *
 676          * Real life tests reveal that vc4's firmware statement holds up, and
 677          * users are able to use pixel clocks closer to HSM's, namely for
 678          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 679          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 680          * 162MHz.
 681          *
 682          * Additionally, the AXI clock needs to be at least 25% of
 683          * pixel clock, but HSM ends up being the limiting factor.
 684          */
 685         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 686         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 687         if (ret) {
 688                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 689                 return;
 690         }
 691
 692         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
 693         if (ret) {
 694                 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
 695                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 696                 return;
 697         }
 698
 699         /*
 700          * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
 701          * at 300MHz.
 702          */
 703         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
 704                                (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
 705         if (ret) {
 706                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 707                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 708                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 709                 return;
 710         }
 711
 712         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 713         if (ret) {
 714                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 715                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 716                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 717                 return;
 718         }
 719
 720         if (vc4_hdmi->variant->reset)
 721                 vc4_hdmi->variant->reset(vc4_hdmi);
 722
 723         if (vc4_hdmi->variant->phy_init)
 724                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 725
 726         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 727                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 728                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 729                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 730
 731         if (vc4_hdmi->variant->set_timings)
 732                 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
 733 }
 734
 735 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 736                                              struct drm_atomic_state *state)
 737 {
 738         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 739         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 740         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 741
 742         if (vc4_encoder->hdmi_monitor &&
 743             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 744                 if (vc4_hdmi->variant->csc_setup)
 745                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 746
 747                 vc4_encoder->limited_rgb_range = true;
 748         } else {
 749                 if (vc4_hdmi->variant->csc_setup)
 750                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 751
 752                 vc4_encoder->limited_rgb_range = false;
 753         }
 754
 755         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 756 }
 757
 758 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
 759                                               struct drm_atomic_state *state)
 760 {
 761         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 762         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 763         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 764         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 765         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 766         int ret;
 767
 768         HDMI_WRITE(HDMI_VID_CTL,
 769                    VC4_HD_VID_CTL_ENABLE |
 770                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 771                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
 772                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 773                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 774
 775         HDMI_WRITE(HDMI_VID_CTL,
 776                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
 777
 778         if (vc4_encoder->hdmi_monitor) {
 779                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 780                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 781                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 782
 783                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 784                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 785                 WARN_ONCE(ret, "Timeout waiting for "
 786                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 787         } else {
 788                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 789                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 790                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 791                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 792                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 793                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 794
 795                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 796                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 797                 WARN_ONCE(ret, "Timeout waiting for "
 798                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 799         }
 800
 801         if (vc4_encoder->hdmi_monitor) {
 802                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 803                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 804                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 805                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 806                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 807
 808                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 809                            VC4_HDMI_RAM_PACKET_ENABLE);
 810
 811                 vc4_hdmi_set_infoframes(encoder);
 812         }
 813
 814         vc4_hdmi_recenter_fifo(vc4_hdmi);
 815 }
 816
 817 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 818 {
 819 }
 820
 821 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
 822 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
 823
 824 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 825                                          struct drm_crtc_state *crtc_state,
 826                                          struct drm_connector_state *conn_state)
 827 {
 828         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 829         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 830         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 831         unsigned long long pixel_rate = mode->clock * 1000;
 832         unsigned long long tmds_rate;
 833
 834         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 835             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 836              (mode->hsync_end % 2) || (mode->htotal % 2)))
 837                 return -EINVAL;
 838
 839         /*
 840          * The 1440p@60 pixel rate is in the same range than the first
 841          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
 842          * bandwidth). Slightly lower the frequency to bring it out of
 843          * the WiFi range.
 844          */
 845         tmds_rate = pixel_rate * 10;
 846         if (vc4_hdmi->disable_wifi_frequencies &&
 847             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
 848              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
 849                 mode->clock = 238560;
 850                 pixel_rate = mode->clock * 1000;
 851         }
 852
 853         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 854                 pixel_rate = pixel_rate * 2;
 855
 856         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
 857                 return -EINVAL;
 858
 859         vc4_state->pixel_rate = pixel_rate;
 860
 861         return 0;
 862 }
 863
 864 static enum drm_mode_status
 865 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 866                             const struct drm_display_mode *mode)
 867 {
 868         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 869
 870         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 871             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 872              (mode->hsync_end % 2) || (mode->htotal % 2)))
 873                 return MODE_H_ILLEGAL;
 874
 875         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 876                 return MODE_CLOCK_HIGH;
 877
 878         return MODE_OK;
 879 }
 880
 881 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 882         .atomic_check = vc4_hdmi_encoder_atomic_check,
 883         .mode_valid = vc4_hdmi_encoder_mode_valid,
 884         .disable = vc4_hdmi_encoder_disable,
 885         .enable = vc4_hdmi_encoder_enable,
 886 };
 887
 888 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 889 {
 890         int i;
 891         u32 channel_map = 0;
 892
 893         for (i = 0; i < 8; i++) {
 894                 if (channel_mask & BIT(i))
 895                         channel_map |= i << (3 * i);
 896         }
 897         return channel_map;
 898 }
 899
 900 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 901 {
 902         int i;
 903         u32 channel_map = 0;
 904
 905         for (i = 0; i < 8; i++) {
 906                 if (channel_mask & BIT(i))
 907                         channel_map |= i << (4 * i);
 908         }
 909         return channel_map;
 910 }
 911
 912 /* HDMI audio codec callbacks */
 913 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
 914 {
 915         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
 916         unsigned long n, m;
 917
 918         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
 919                                     VC4_HD_MAI_SMP_N_MASK >>
 920                                     VC4_HD_MAI_SMP_N_SHIFT,
 921                                     (VC4_HD_MAI_SMP_M_MASK >>
 922                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 923                                     &n, &m);
 924
 925         HDMI_WRITE(HDMI_MAI_SMP,
 926                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 927                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 928 }
 929
 930 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
 931 {
 932         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 933         struct drm_crtc *crtc = encoder->crtc;
 934         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 935         u32 samplerate = vc4_hdmi->audio.samplerate;
 936         u32 n, cts;
 937         u64 tmp;
 938
 939         n = 128 * samplerate / 1000;
 940         tmp = (u64)(mode->clock * 1000) * n;
 941         do_div(tmp, 128 * samplerate);
 942         cts = tmp;
 943
 944         HDMI_WRITE(HDMI_CRP_CFG,
 945                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 946                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 947
 948         /*
 949          * We could get slightly more accurate clocks in some cases by
 950          * providing a CTS_1 value.  The two CTS values are alternated
 951          * between based on the period fields
 952          */
 953         HDMI_WRITE(HDMI_CTS_0, cts);
 954         HDMI_WRITE(HDMI_CTS_1, cts);
 955 }
 956
 957 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 958 {
 959         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 960
 961         return snd_soc_card_get_drvdata(card);
 962 }
 963
 964 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 965                                   struct snd_soc_dai *dai)
 966 {
 967         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 968         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 969         struct drm_connector *connector = &vc4_hdmi->connector;
 970         int ret;
 971
 972         if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
 973                 return -EINVAL;
 974
 975         vc4_hdmi->audio.substream = substream;
 976
 977         /*
 978          * If the HDMI encoder hasn't probed, or the encoder is
 979          * currently in DVI mode, treat the codec dai as missing.
 980          */
 981         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 982                                 VC4_HDMI_RAM_PACKET_ENABLE))
 983                 return -ENODEV;
 984
 985         ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
 986         if (ret)
 987                 return ret;
 988
 989         return 0;
 990 }
 991
 992 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 993 {
 994         return 0;
 995 }
 996
 997 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
 998 {
 999         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1000         struct device *dev = &vc4_hdmi->pdev->dev;
1001         int ret;
1002
1003         vc4_hdmi->audio.streaming = false;
1004         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1005         if (ret)
1006                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1007
1008         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1009         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1010         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1011 }
1012
1013 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1014                                     struct snd_soc_dai *dai)
1015 {
1016         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1017
1018         if (substream != vc4_hdmi->audio.substream)
1019                 return;
1020
1021         vc4_hdmi_audio_reset(vc4_hdmi);
1022
1023         vc4_hdmi->audio.substream = NULL;
1024 }
1025
1026 /* HDMI audio codec callbacks */
1027 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1028                                     struct snd_pcm_hw_params *params,
1029                                     struct snd_soc_dai *dai)
1030 {
1031         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1032         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1033         struct device *dev = &vc4_hdmi->pdev->dev;
1034         u32 audio_packet_config, channel_mask;
1035         u32 channel_map;
1036
1037         if (substream != vc4_hdmi->audio.substream)
1038                 return -EINVAL;
1039
1040         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1041                 params_rate(params), params_width(params),
1042                 params_channels(params));
1043
1044         vc4_hdmi->audio.channels = params_channels(params);
1045         vc4_hdmi->audio.samplerate = params_rate(params);
1046
1047         HDMI_WRITE(HDMI_MAI_CTL,
1048                    VC4_HD_MAI_CTL_RESET |
1049                    VC4_HD_MAI_CTL_FLUSH |
1050                    VC4_HD_MAI_CTL_DLATE |
1051                    VC4_HD_MAI_CTL_ERRORE |
1052                    VC4_HD_MAI_CTL_ERRORF);
1053
1054         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1055
1056         /* The B frame identifier should match the value used by alsa-lib (8) */
1057         audio_packet_config =
1058                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1059                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1060                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1061
1062         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1063         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1064                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1065
1066         /* Set the MAI threshold.  This logic mimics the firmware's. */
1067         if (vc4_hdmi->audio.samplerate > 96000) {
1068                 HDMI_WRITE(HDMI_MAI_THR,
1069                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1070                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1071         } else if (vc4_hdmi->audio.samplerate > 48000) {
1072                 HDMI_WRITE(HDMI_MAI_THR,
1073                            VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1074                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1075         } else {
1076                 HDMI_WRITE(HDMI_MAI_THR,
1077                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1078                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1079                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1080                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1081         }
1082
1083         HDMI_WRITE(HDMI_MAI_CONFIG,
1084                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1085                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1086
1087         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1088         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1089         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1090         vc4_hdmi_set_n_cts(vc4_hdmi);
1091
1092         vc4_hdmi_set_audio_infoframe(encoder);
1093
1094         return 0;
1095 }
1096
1097 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1098                                   struct snd_soc_dai *dai)
1099 {
1100         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1101
1102         switch (cmd) {
1103         case SNDRV_PCM_TRIGGER_START:
1104                 vc4_hdmi->audio.streaming = true;
1105
1106                 if (vc4_hdmi->variant->phy_rng_enable)
1107                         vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1108
1109                 HDMI_WRITE(HDMI_MAI_CTL,
1110                            VC4_SET_FIELD(vc4_hdmi->audio.channels,
1111                                          VC4_HD_MAI_CTL_CHNUM) |
1112                            VC4_HD_MAI_CTL_ENABLE);
1113                 break;
1114         case SNDRV_PCM_TRIGGER_STOP:
1115                 HDMI_WRITE(HDMI_MAI_CTL,
1116                            VC4_HD_MAI_CTL_DLATE |
1117                            VC4_HD_MAI_CTL_ERRORE |
1118                            VC4_HD_MAI_CTL_ERRORF);
1119
1120                 if (vc4_hdmi->variant->phy_rng_disable)
1121                         vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1122
1123                 vc4_hdmi->audio.streaming = false;
1124
1125                 break;
1126         default:
1127                 break;
1128         }
1129
1130         return 0;
1131 }
1132
1133 static inline struct vc4_hdmi *
1134 snd_component_to_hdmi(struct snd_soc_component *component)
1135 {
1136         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1137
1138         return snd_soc_card_get_drvdata(card);
1139 }
1140
1141 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1142                                        struct snd_ctl_elem_info *uinfo)
1143 {
1144         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1145         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1146         struct drm_connector *connector = &vc4_hdmi->connector;
1147
1148         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1149         uinfo->count = sizeof(connector->eld);
1150
1151         return 0;
1152 }
1153
1154 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1155                                       struct snd_ctl_elem_value *ucontrol)
1156 {
1157         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1158         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1159         struct drm_connector *connector = &vc4_hdmi->connector;
1160
1161         memcpy(ucontrol->value.bytes.data, connector->eld,
1162                sizeof(connector->eld));
1163
1164         return 0;
1165 }
1166
1167 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1168         {
1169                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1170                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1171                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1172                 .name = "ELD",
1173                 .info = vc4_hdmi_audio_eld_ctl_info,
1174                 .get = vc4_hdmi_audio_eld_ctl_get,
1175         },
1176 };
1177
1178 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1179         SND_SOC_DAPM_OUTPUT("TX"),
1180 };
1181
1182 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1183         { "TX", NULL, "Playback" },
1184 };
1185
1186 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1187         .name                   = "vc4-hdmi-codec-dai-component",
1188         .controls               = vc4_hdmi_audio_controls,
1189         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1190         .dapm_widgets           = vc4_hdmi_audio_widgets,
1191         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1192         .dapm_routes            = vc4_hdmi_audio_routes,
1193         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1194         .idle_bias_on           = 1,
1195         .use_pmdown_time        = 1,
1196         .endianness             = 1,
1197         .non_legacy_dai_naming  = 1,
1198 };
1199
1200 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1201         .startup = vc4_hdmi_audio_startup,
1202         .shutdown = vc4_hdmi_audio_shutdown,
1203         .hw_params = vc4_hdmi_audio_hw_params,
1204         .set_fmt = vc4_hdmi_audio_set_fmt,
1205         .trigger = vc4_hdmi_audio_trigger,
1206 };
1207
1208 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1209         .name = "vc4-hdmi-hifi",
1210         .playback = {
1211                 .stream_name = "Playback",
1212                 .channels_min = 2,
1213                 .channels_max = 8,
1214                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1215                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1216                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1217                          SNDRV_PCM_RATE_192000,
1218                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1219         },
1220 };
1221
1222 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1223         .name = "vc4-hdmi-cpu-dai-component",
1224 };
1225
1226 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1227 {
1228         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1229
1230         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1231
1232         return 0;
1233 }
1234
1235 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1236         .name = "vc4-hdmi-cpu-dai",
1237         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1238         .playback = {
1239                 .stream_name = "Playback",
1240                 .channels_min = 1,
1241                 .channels_max = 8,
1242                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1243                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1244                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1245                          SNDRV_PCM_RATE_192000,
1246                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1247         },
1248         .ops = &vc4_hdmi_audio_dai_ops,
1249 };
1250
1251 static const struct snd_dmaengine_pcm_config pcm_conf = {
1252         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1253         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1254 };
1255
1256 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1257 {
1258         const struct vc4_hdmi_register *mai_data =
1259                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1260         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1261         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1262         struct device *dev = &vc4_hdmi->pdev->dev;
1263         const __be32 *addr;
1264         int index;
1265         int ret;
1266
1267         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1268                 dev_warn(dev,
1269                          "'dmas' DT property is missing, no HDMI audio\n");
1270                 return 0;
1271         }
1272
1273         if (mai_data->reg != VC4_HD) {
1274                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1275                 return -EINVAL;
1276         }
1277
1278         /*
1279          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1280          * the bus address specified in the DT, because the physical address
1281          * (the one returned by platform_get_resource()) is not appropriate
1282          * for DMA transfers.
1283          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1284          */
1285         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1286         /* Before BCM2711, we don't have a named register range */
1287         if (index < 0)
1288                 index = 1;
1289
1290         addr = of_get_address(dev->of_node, index, NULL, NULL);
1291
1292         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1293         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1294         vc4_hdmi->audio.dma_data.maxburst = 2;
1295
1296         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1297         if (ret) {
1298                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1299                 return ret;
1300         }
1301
1302         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1303                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1304         if (ret) {
1305                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1306                 return ret;
1307         }
1308
1309         /* register component and codec dai */
1310         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1311                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1312         if (ret) {
1313                 dev_err(dev, "Could not register component: %d\n", ret);
1314                 return ret;
1315         }
1316
1317         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1318         dai_link->codecs        = &vc4_hdmi->audio.codec;
1319         dai_link->platforms     = &vc4_hdmi->audio.platform;
1320
1321         dai_link->num_cpus      = 1;
1322         dai_link->num_codecs    = 1;
1323         dai_link->num_platforms = 1;
1324
1325         dai_link->name = "MAI";
1326         dai_link->stream_name = "MAI PCM";
1327         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1328         dai_link->cpus->dai_name = dev_name(dev);
1329         dai_link->codecs->name = dev_name(dev);
1330         dai_link->platforms->name = dev_name(dev);
1331
1332         card->dai_link = dai_link;
1333         card->num_links = 1;
1334         card->name = vc4_hdmi->variant->card_name;
1335         card->dev = dev;
1336         card->owner = THIS_MODULE;
1337
1338         /*
1339          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1340          * stores a pointer to the snd card object in dev->driver_data. This
1341          * means we cannot use it for something else. The hdmi back-pointer is
1342          * now stored in card->drvdata and should be retrieved with
1343          * snd_soc_card_get_drvdata() if needed.
1344          */
1345         snd_soc_card_set_drvdata(card, vc4_hdmi);
1346         ret = devm_snd_soc_register_card(dev, card);
1347         if (ret)
1348                 dev_err(dev, "Could not register sound card: %d\n", ret);
1349
1350         return ret;
1351
1352 }
1353
1354 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1355 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1356 {
1357         struct vc4_hdmi *vc4_hdmi = priv;
1358
1359         if (vc4_hdmi->cec_irq_was_rx) {
1360                 if (vc4_hdmi->cec_rx_msg.len)
1361                         cec_received_msg(vc4_hdmi->cec_adap,
1362                                          &vc4_hdmi->cec_rx_msg);
1363         } else if (vc4_hdmi->cec_tx_ok) {
1364                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1365                                   0, 0, 0, 0);
1366         } else {
1367                 /*
1368                  * This CEC implementation makes 1 retry, so if we
1369                  * get a NACK, then that means it made 2 attempts.
1370                  */
1371                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1372                                   0, 2, 0, 0);
1373         }
1374         return IRQ_HANDLED;
1375 }
1376
1377 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1378 {
1379         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1380         unsigned int i;
1381
1382         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1383                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1384         for (i = 0; i < msg->len; i += 4) {
1385                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i);
1386
1387                 msg->msg[i] = val & 0xff;
1388                 msg->msg[i + 1] = (val >> 8) & 0xff;
1389                 msg->msg[i + 2] = (val >> 16) & 0xff;
1390                 msg->msg[i + 3] = (val >> 24) & 0xff;
1391         }
1392 }
1393
1394 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1395 {
1396         struct vc4_hdmi *vc4_hdmi = priv;
1397         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1398         u32 cntrl1, cntrl5;
1399
1400         if (!(stat & VC4_HDMI_CPU_CEC))
1401                 return IRQ_NONE;
1402         vc4_hdmi->cec_rx_msg.len = 0;
1403         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1404         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1405         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1406         if (vc4_hdmi->cec_irq_was_rx) {
1407                 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1408                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1409                 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1410                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1411         } else {
1412                 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1413                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1414         }
1415         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1416         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1417
1418         return IRQ_WAKE_THREAD;
1419 }
1420
1421 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1422 {
1423         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1424         /* clock period in microseconds */
1425         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1426         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1427
1428         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1429                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1430                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1431         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1432                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1433
1434         if (enable) {
1435                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1436                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1437                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1438                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1439                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1440                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1441                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1442                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1443                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1444                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1445                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1446                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1447                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1448                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1449                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1450                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1451                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1452                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1453                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1454
1455                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1456         } else {
1457                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1458                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1459                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1460         }
1461         return 0;
1462 }
1463
1464 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1465 {
1466         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1467
1468         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1469                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1470                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1471         return 0;
1472 }
1473
1474 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1475                                       u32 signal_free_time, struct cec_msg *msg)
1476 {
1477         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1478         u32 val;
1479         unsigned int i;
1480
1481         for (i = 0; i < msg->len; i += 4)
1482                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i,
1483                            (msg->msg[i]) |
1484                            (msg->msg[i + 1] << 8) |
1485                            (msg->msg[i + 2] << 16) |
1486                            (msg->msg[i + 3] << 24));
1487
1488         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1489         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1490         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1491         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1492         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1493         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1494
1495         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1496         return 0;
1497 }
1498
1499 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1500         .adap_enable = vc4_hdmi_cec_adap_enable,
1501         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1502         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1503 };
1504
1505 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1506 {
1507         struct cec_connector_info conn_info;
1508         struct platform_device *pdev = vc4_hdmi->pdev;
1509         u32 value;
1510         int ret;
1511
1512         if (!vc4_hdmi->variant->cec_available)
1513                 return 0;
1514
1515         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1516                                                   vc4_hdmi, "vc4",
1517                                                   CEC_CAP_DEFAULTS |
1518                                                   CEC_CAP_CONNECTOR_INFO, 1);
1519         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1520         if (ret < 0)
1521                 return ret;
1522
1523         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1524         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1525
1526         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1527         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1528         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1529         /*
1530          * Set the logical address to Unregistered and set the clock
1531          * divider: the hsm_clock rate and this divider setting will
1532          * give a 40 kHz CEC clock.
1533          */
1534         value |= VC4_HDMI_CEC_ADDR_MASK |
1535                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1536         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1537         ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1538                                         vc4_cec_irq_handler,
1539                                         vc4_cec_irq_handler_thread, 0,
1540                                         "vc4 hdmi cec", vc4_hdmi);
1541         if (ret)
1542                 goto err_delete_cec_adap;
1543
1544         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1545         if (ret < 0)
1546                 goto err_delete_cec_adap;
1547
1548         return 0;
1549
1550 err_delete_cec_adap:
1551         cec_delete_adapter(vc4_hdmi->cec_adap);
1552
1553         return ret;
1554 }
1555
1556 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1557 {
1558         cec_unregister_adapter(vc4_hdmi->cec_adap);
1559 }
1560 #else
1561 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1562 {
1563         return 0;
1564 }
1565
1566 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1567
1568 #endif
1569
1570 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1571                                  struct debugfs_regset32 *regset,
1572                                  enum vc4_hdmi_regs reg)
1573 {
1574         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1575         struct debugfs_reg32 *regs, *new_regs;
1576         unsigned int count = 0;
1577         unsigned int i;
1578
1579         regs = kcalloc(variant->num_registers, sizeof(*regs),
1580                        GFP_KERNEL);
1581         if (!regs)
1582                 return -ENOMEM;
1583
1584         for (i = 0; i < variant->num_registers; i++) {
1585                 const struct vc4_hdmi_register *field = &variant->registers[i];
1586
1587                 if (field->reg != reg)
1588                         continue;
1589
1590                 regs[count].name = field->name;
1591                 regs[count].offset = field->offset;
1592                 count++;
1593         }
1594
1595         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1596         if (!new_regs)
1597                 return -ENOMEM;
1598
1599         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1600         regset->regs = new_regs;
1601         regset->nregs = count;
1602
1603         return 0;
1604 }
1605
1606 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1607 {
1608         struct platform_device *pdev = vc4_hdmi->pdev;
1609         struct device *dev = &pdev->dev;
1610         int ret;
1611
1612         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1613         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1614                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1615
1616         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1617         if (IS_ERR(vc4_hdmi->hd_regs))
1618                 return PTR_ERR(vc4_hdmi->hd_regs);
1619
1620         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1621         if (ret)
1622                 return ret;
1623
1624         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1625         if (ret)
1626                 return ret;
1627
1628         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1629         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1630                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1631                 if (ret != -EPROBE_DEFER)
1632                         DRM_ERROR("Failed to get pixel clock\n");
1633                 return ret;
1634         }
1635
1636         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1637         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1638                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1639                 return PTR_ERR(vc4_hdmi->hsm_clock);
1640         }
1641         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1642
1643         return 0;
1644 }
1645
1646 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1647 {
1648         struct platform_device *pdev = vc4_hdmi->pdev;
1649         struct device *dev = &pdev->dev;
1650         struct resource *res;
1651
1652         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1653         if (!res)
1654                 return -ENODEV;
1655
1656         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1657                                                resource_size(res));
1658         if (!vc4_hdmi->hdmicore_regs)
1659                 return -ENOMEM;
1660
1661         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1662         if (!res)
1663                 return -ENODEV;
1664
1665         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1666         if (!vc4_hdmi->hd_regs)
1667                 return -ENOMEM;
1668
1669         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1670         if (!res)
1671                 return -ENODEV;
1672
1673         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1674         if (!vc4_hdmi->cec_regs)
1675                 return -ENOMEM;
1676
1677         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1678         if (!res)
1679                 return -ENODEV;
1680
1681         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1682         if (!vc4_hdmi->csc_regs)
1683                 return -ENOMEM;
1684
1685         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1686         if (!res)
1687                 return -ENODEV;
1688
1689         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1690         if (!vc4_hdmi->dvp_regs)
1691                 return -ENOMEM;
1692
1693         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1694         if (!res)
1695                 return -ENODEV;
1696
1697         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1698         if (!vc4_hdmi->phy_regs)
1699                 return -ENOMEM;
1700
1701         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1702         if (!res)
1703                 return -ENODEV;
1704
1705         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1706         if (!vc4_hdmi->ram_regs)
1707                 return -ENOMEM;
1708
1709         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1710         if (!res)
1711                 return -ENODEV;
1712
1713         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1714         if (!vc4_hdmi->rm_regs)
1715                 return -ENOMEM;
1716
1717         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1718         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1719                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1720                 return PTR_ERR(vc4_hdmi->hsm_clock);
1721         }
1722
1723         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1724         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1725                 DRM_ERROR("Failed to get pixel bvb clock\n");
1726                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1727         }
1728
1729         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1730         if (IS_ERR(vc4_hdmi->audio_clock)) {
1731                 DRM_ERROR("Failed to get audio clock\n");
1732                 return PTR_ERR(vc4_hdmi->audio_clock);
1733         }
1734
1735         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1736         if (IS_ERR(vc4_hdmi->reset)) {
1737                 DRM_ERROR("Failed to get HDMI reset line\n");
1738                 return PTR_ERR(vc4_hdmi->reset);
1739         }
1740
1741         return 0;
1742 }
1743
1744 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1745 {
1746         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1747         struct platform_device *pdev = to_platform_device(dev);
1748         struct drm_device *drm = dev_get_drvdata(master);
1749         struct vc4_hdmi *vc4_hdmi;
1750         struct drm_encoder *encoder;
1751         struct device_node *ddc_node;
1752         u32 value;
1753         int ret;
1754
1755         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1756         if (!vc4_hdmi)
1757                 return -ENOMEM;
1758
1759         dev_set_drvdata(dev, vc4_hdmi);
1760         encoder = &vc4_hdmi->encoder.base.base;
1761         vc4_hdmi->encoder.base.type = variant->encoder_type;
1762         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1763         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1764         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1765         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1766         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1767         vc4_hdmi->pdev = pdev;
1768         vc4_hdmi->variant = variant;
1769
1770         ret = variant->init_resources(vc4_hdmi);
1771         if (ret)
1772                 return ret;
1773
1774         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1775         if (!ddc_node) {
1776                 DRM_ERROR("Failed to find ddc node in device tree\n");
1777                 return -ENODEV;
1778         }
1779
1780         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1781         of_node_put(ddc_node);
1782         if (!vc4_hdmi->ddc) {
1783                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1784                 return -EPROBE_DEFER;
1785         }
1786
1787         /* Only use the GPIO HPD pin if present in the DT, otherwise
1788          * we'll use the HDMI core's register.
1789          */
1790         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1791                 enum of_gpio_flags hpd_gpio_flags;
1792
1793                 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1794                                                              "hpd-gpios", 0,
1795                                                              &hpd_gpio_flags);
1796                 if (vc4_hdmi->hpd_gpio < 0) {
1797                         ret = vc4_hdmi->hpd_gpio;
1798                         goto err_unprepare_hsm;
1799                 }
1800
1801                 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1802         }
1803
1804         vc4_hdmi->disable_wifi_frequencies =
1805                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
1806
1807         pm_runtime_enable(dev);
1808
1809         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1810         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1811
1812         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1813         if (ret)
1814                 goto err_destroy_encoder;
1815
1816         ret = vc4_hdmi_cec_init(vc4_hdmi);
1817         if (ret)
1818                 goto err_destroy_conn;
1819
1820         ret = vc4_hdmi_audio_init(vc4_hdmi);
1821         if (ret)
1822                 goto err_free_cec;
1823
1824         vc4_debugfs_add_file(drm, variant->debugfs_name,
1825                              vc4_hdmi_debugfs_regs,
1826                              vc4_hdmi);
1827
1828         return 0;
1829
1830 err_free_cec:
1831         vc4_hdmi_cec_exit(vc4_hdmi);
1832 err_destroy_conn:
1833         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1834 err_destroy_encoder:
1835         drm_encoder_cleanup(encoder);
1836 err_unprepare_hsm:
1837         pm_runtime_disable(dev);
1838         put_device(&vc4_hdmi->ddc->dev);
1839
1840         return ret;
1841 }
1842
1843 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1844                             void *data)
1845 {
1846         struct vc4_hdmi *vc4_hdmi;
1847
1848         /*
1849          * ASoC makes it a bit hard to retrieve a pointer to the
1850          * vc4_hdmi structure. Registering the card will overwrite our
1851          * device drvdata with a pointer to the snd_soc_card structure,
1852          * which can then be used to retrieve whatever drvdata we want
1853          * to associate.
1854          *
1855          * However, that doesn't fly in the case where we wouldn't
1856          * register an ASoC card (because of an old DT that is missing
1857          * the dmas properties for example), then the card isn't
1858          * registered and the device drvdata wouldn't be set.
1859          *
1860          * We can deal with both cases by making sure a snd_soc_card
1861          * pointer and a vc4_hdmi structure are pointing to the same
1862          * memory address, so we can treat them indistinctly without any
1863          * issue.
1864          */
1865         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
1866         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
1867         vc4_hdmi = dev_get_drvdata(dev);
1868
1869         kfree(vc4_hdmi->hdmi_regset.regs);
1870         kfree(vc4_hdmi->hd_regset.regs);
1871
1872         vc4_hdmi_cec_exit(vc4_hdmi);
1873         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1874         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
1875
1876         pm_runtime_disable(dev);
1877
1878         put_device(&vc4_hdmi->ddc->dev);
1879 }
1880
1881 static const struct component_ops vc4_hdmi_ops = {
1882         .bind   = vc4_hdmi_bind,
1883         .unbind = vc4_hdmi_unbind,
1884 };
1885
1886 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1887 {
1888         return component_add(&pdev->dev, &vc4_hdmi_ops);
1889 }
1890
1891 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1892 {
1893         component_del(&pdev->dev, &vc4_hdmi_ops);
1894         return 0;
1895 }
1896
1897 static const struct vc4_hdmi_variant bcm2835_variant = {
1898         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
1899         .debugfs_name           = "hdmi_regs",
1900         .card_name              = "vc4-hdmi",
1901         .max_pixel_clock        = 162000000,
1902         .cec_available          = true,
1903         .registers              = vc4_hdmi_fields,
1904         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
1905
1906         .init_resources         = vc4_hdmi_init_resources,
1907         .csc_setup              = vc4_hdmi_csc_setup,
1908         .reset                  = vc4_hdmi_reset,
1909         .set_timings            = vc4_hdmi_set_timings,
1910         .phy_init               = vc4_hdmi_phy_init,
1911         .phy_disable            = vc4_hdmi_phy_disable,
1912         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
1913         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
1914         .channel_map            = vc4_hdmi_channel_map,
1915 };
1916
1917 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1918         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
1919         .debugfs_name           = "hdmi0_regs",
1920         .card_name              = "vc4-hdmi-0",
1921         .max_pixel_clock        = 297000000,
1922         .registers              = vc5_hdmi_hdmi0_fields,
1923         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1924         .phy_lane_mapping       = {
1925                 PHY_LANE_0,
1926                 PHY_LANE_1,
1927                 PHY_LANE_2,
1928                 PHY_LANE_CK,
1929         },
1930         .unsupported_odd_h_timings      = true,
1931
1932         .init_resources         = vc5_hdmi_init_resources,
1933         .csc_setup              = vc5_hdmi_csc_setup,
1934         .reset                  = vc5_hdmi_reset,
1935         .set_timings            = vc5_hdmi_set_timings,
1936         .phy_init               = vc5_hdmi_phy_init,
1937         .phy_disable            = vc5_hdmi_phy_disable,
1938         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1939         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1940         .channel_map            = vc5_hdmi_channel_map,
1941 };
1942
1943 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1944         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
1945         .debugfs_name           = "hdmi1_regs",
1946         .card_name              = "vc4-hdmi-1",
1947         .max_pixel_clock        = 297000000,
1948         .registers              = vc5_hdmi_hdmi1_fields,
1949         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1950         .phy_lane_mapping       = {
1951                 PHY_LANE_1,
1952                 PHY_LANE_0,
1953                 PHY_LANE_CK,
1954                 PHY_LANE_2,
1955         },
1956         .unsupported_odd_h_timings      = true,
1957
1958         .init_resources         = vc5_hdmi_init_resources,
1959         .csc_setup              = vc5_hdmi_csc_setup,
1960         .reset                  = vc5_hdmi_reset,
1961         .set_timings            = vc5_hdmi_set_timings,
1962         .phy_init               = vc5_hdmi_phy_init,
1963         .phy_disable            = vc5_hdmi_phy_disable,
1964         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1965         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1966         .channel_map            = vc5_hdmi_channel_map,
1967 };
1968
1969 static const struct of_device_id vc4_hdmi_dt_match[] = {
1970         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
1971         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
1972         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
1973         {}
1974 };
1975
1976 struct platform_driver vc4_hdmi_driver = {
1977         .probe = vc4_hdmi_dev_probe,
1978         .remove = vc4_hdmi_dev_remove,
1979         .driver = {
1980                 .name = "vc4_hdmi",
1981                 .of_match_table = vc4_hdmi_dt_match,
1982         },
1983 };