drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define CEC_CLOCK_FREQ 40000
  98
  99 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 100
 101 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 102 {
 103         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 104 }
 105
 106 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 107 {
 108         struct drm_info_node *node = (struct drm_info_node *)m->private;
 109         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 110         struct drm_printer p = drm_seq_file_printer(m);
 111
 112         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 113         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 114
 115         return 0;
 116 }
 117
 118 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 119 {
 120         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 121         udelay(1);
 122         HDMI_WRITE(HDMI_M_CTL, 0);
 123
 124         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 125
 126         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 127                    VC4_HDMI_SW_RESET_HDMI |
 128                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 129
 130         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 131 }
 132
 133 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 134 {
 135         reset_control_reset(vc4_hdmi->reset);
 136
 137         HDMI_WRITE(HDMI_DVP_CTL, 0);
 138
 139         HDMI_WRITE(HDMI_CLOCK_STOP,
 140                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 141 }
 142
 143 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 144 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 145 {
 146         u16 clk_cnt;
 147         u32 value;
 148
 149         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 150         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 151
 152         /*
 153          * Set the clock divider: the hsm_clock rate and this divider
 154          * setting will give a 40 kHz CEC clock.
 155          */
 156         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 157         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 158         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 159 }
 160 #else
 161 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 162 #endif
 163
 164 static enum drm_connector_status
 165 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 166 {
 167         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 168         bool connected = false;
 169
 170         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 171
 172         if (vc4_hdmi->hpd_gpio &&
 173             gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
 174                 connected = true;
 175         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 176                 connected = true;
 177         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 178                 connected = true;
 179         }
 180
 181         if (connected) {
 182                 if (connector->status != connector_status_connected) {
 183                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 184
 185                         if (edid) {
 186                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 187                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 188                                 kfree(edid);
 189                         }
 190                 }
 191
 192                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 193                 return connector_status_connected;
 194         }
 195
 196         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 197         pm_runtime_put(&vc4_hdmi->pdev->dev);
 198         return connector_status_disconnected;
 199 }
 200
 201 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 202 {
 203         drm_connector_unregister(connector);
 204         drm_connector_cleanup(connector);
 205 }
 206
 207 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 208 {
 209         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 210         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 211         int ret = 0;
 212         struct edid *edid;
 213
 214         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 215         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 216         if (!edid)
 217                 return -ENODEV;
 218
 219         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 220
 221         drm_connector_update_edid_property(connector, edid);
 222         ret = drm_add_edid_modes(connector, edid);
 223         kfree(edid);
 224
 225         if (vc4_hdmi->disable_4kp60) {
 226                 struct drm_device *drm = connector->dev;
 227                 struct drm_display_mode *mode;
 228
 229                 list_for_each_entry(mode, &connector->probed_modes, head) {
 230                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 231                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 232                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 233                         }
 234                 }
 235         }
 236
 237         return ret;
 238 }
 239
 240 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 241                                            struct drm_atomic_state *state)
 242 {
 243         struct drm_connector_state *old_state =
 244                 drm_atomic_get_old_connector_state(state, connector);
 245         struct drm_connector_state *new_state =
 246                 drm_atomic_get_new_connector_state(state, connector);
 247         struct drm_crtc *crtc = new_state->crtc;
 248
 249         if (!crtc)
 250                 return 0;
 251
 252         if (old_state->colorspace != new_state->colorspace ||
 253             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 254                 struct drm_crtc_state *crtc_state;
 255
 256                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 257                 if (IS_ERR(crtc_state))
 258                         return PTR_ERR(crtc_state);
 259
 260                 crtc_state->mode_changed = true;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 267 {
 268         struct vc4_hdmi_connector_state *old_state =
 269                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 270         struct vc4_hdmi_connector_state *new_state =
 271                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 272
 273         if (connector->state)
 274                 __drm_atomic_helper_connector_destroy_state(connector->state);
 275
 276         kfree(old_state);
 277         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 278
 279         if (!new_state)
 280                 return;
 281
 282         new_state->base.max_bpc = 8;
 283         new_state->base.max_requested_bpc = 8;
 284         drm_atomic_helper_connector_tv_reset(connector);
 285 }
 286
 287 static struct drm_connector_state *
 288 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 289 {
 290         struct drm_connector_state *conn_state = connector->state;
 291         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 292         struct vc4_hdmi_connector_state *new_state;
 293
 294         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 295         if (!new_state)
 296                 return NULL;
 297
 298         new_state->pixel_rate = vc4_state->pixel_rate;
 299         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 300
 301         return &new_state->base;
 302 }
 303
 304 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 305         .detect = vc4_hdmi_connector_detect,
 306         .fill_modes = drm_helper_probe_single_connector_modes,
 307         .destroy = vc4_hdmi_connector_destroy,
 308         .reset = vc4_hdmi_connector_reset,
 309         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 310         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 311 };
 312
 313 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 314         .get_modes = vc4_hdmi_connector_get_modes,
 315         .atomic_check = vc4_hdmi_connector_atomic_check,
 316 };
 317
 318 static int vc4_hdmi_connector_init(struct drm_device *dev,
 319                                    struct vc4_hdmi *vc4_hdmi)
 320 {
 321         struct drm_connector *connector = &vc4_hdmi->connector;
 322         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 323         int ret;
 324
 325         drm_connector_init_with_ddc(dev, connector,
 326                                     &vc4_hdmi_connector_funcs,
 327                                     DRM_MODE_CONNECTOR_HDMIA,
 328                                     vc4_hdmi->ddc);
 329         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 330
 331         /*
 332          * Some of the properties below require access to state, like bpc.
 333          * Allocate some default initial connector state with our reset helper.
 334          */
 335         if (connector->funcs->reset)
 336                 connector->funcs->reset(connector);
 337
 338         /* Create and attach TV margin props to this connector. */
 339         ret = drm_mode_create_tv_margin_properties(dev);
 340         if (ret)
 341                 return ret;
 342
 343         ret = drm_mode_create_hdmi_colorspace_property(connector);
 344         if (ret)
 345                 return ret;
 346
 347         drm_connector_attach_colorspace_property(connector);
 348         drm_connector_attach_tv_margin_properties(connector);
 349         drm_connector_attach_max_bpc_property(connector, 8, 12);
 350
 351         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 352                              DRM_CONNECTOR_POLL_DISCONNECT);
 353
 354         connector->interlace_allowed = 1;
 355         connector->doublescan_allowed = 0;
 356
 357         if (vc4_hdmi->variant->supports_hdr)
 358                 drm_connector_attach_hdr_output_metadata_property(connector);
 359
 360         drm_connector_attach_encoder(connector, encoder);
 361
 362         return 0;
 363 }
 364
 365 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 366                                 enum hdmi_infoframe_type type,
 367                                 bool poll)
 368 {
 369         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 370         u32 packet_id = type - 0x80;
 371
 372         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 373                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 374
 375         if (!poll)
 376                 return 0;
 377
 378         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 379                           BIT(packet_id)), 100);
 380 }
 381
 382 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 383                                      union hdmi_infoframe *frame)
 384 {
 385         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 386         u32 packet_id = frame->any.type - 0x80;
 387         const struct vc4_hdmi_register *ram_packet_start =
 388                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 389         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 390         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 391                                                        ram_packet_start->reg);
 392         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 393         ssize_t len, i;
 394         int ret;
 395
 396         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 397                     VC4_HDMI_RAM_PACKET_ENABLE),
 398                   "Packet RAM has to be on to store the packet.");
 399
 400         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 401         if (len < 0)
 402                 return;
 403
 404         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 405         if (ret) {
 406                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 407                 return;
 408         }
 409
 410         for (i = 0; i < len; i += 7) {
 411                 writel(buffer[i + 0] << 0 |
 412                        buffer[i + 1] << 8 |
 413                        buffer[i + 2] << 16,
 414                        base + packet_reg);
 415                 packet_reg += 4;
 416
 417                 writel(buffer[i + 3] << 0 |
 418                        buffer[i + 4] << 8 |
 419                        buffer[i + 5] << 16 |
 420                        buffer[i + 6] << 24,
 421                        base + packet_reg);
 422                 packet_reg += 4;
 423         }
 424
 425         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 426                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 427         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 428                         BIT(packet_id)), 100);
 429         if (ret)
 430                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 431 }
 432
 433 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 434 {
 435         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 436         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 437         struct drm_connector *connector = &vc4_hdmi->connector;
 438         struct drm_connector_state *cstate = connector->state;
 439         struct drm_crtc *crtc = cstate->crtc;
 440         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 441         union hdmi_infoframe frame;
 442         int ret;
 443
 444         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 445                                                        connector, mode);
 446         if (ret < 0) {
 447                 DRM_ERROR("couldn't fill AVI infoframe\n");
 448                 return;
 449         }
 450
 451         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 452                                            connector, mode,
 453                                            vc4_encoder->limited_rgb_range ?
 454                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 455                                            HDMI_QUANTIZATION_RANGE_FULL);
 456         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 457         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 458
 459         vc4_hdmi_write_infoframe(encoder, &frame);
 460 }
 461
 462 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 463 {
 464         union hdmi_infoframe frame;
 465         int ret;
 466
 467         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 468         if (ret < 0) {
 469                 DRM_ERROR("couldn't fill SPD infoframe\n");
 470                 return;
 471         }
 472
 473         frame.spd.sdi = HDMI_SPD_SDI_PC;
 474
 475         vc4_hdmi_write_infoframe(encoder, &frame);
 476 }
 477
 478 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 479 {
 480         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 481         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 482         union hdmi_infoframe frame;
 483
 484         memcpy(&frame.audio, audio, sizeof(*audio));
 485         vc4_hdmi_write_infoframe(encoder, &frame);
 486 }
 487
 488 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 489 {
 490         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 491         struct drm_connector *connector = &vc4_hdmi->connector;
 492         struct drm_connector_state *conn_state = connector->state;
 493         union hdmi_infoframe frame;
 494
 495         if (!vc4_hdmi->variant->supports_hdr)
 496                 return;
 497
 498         if (!conn_state->hdr_output_metadata)
 499                 return;
 500
 501         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 502                 return;
 503
 504         vc4_hdmi_write_infoframe(encoder, &frame);
 505 }
 506
 507 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 508 {
 509         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 510
 511         vc4_hdmi_set_avi_infoframe(encoder);
 512         vc4_hdmi_set_spd_infoframe(encoder);
 513         /*
 514          * If audio was streaming, then we need to reenabled the audio
 515          * infoframe here during encoder_enable.
 516          */
 517         if (vc4_hdmi->audio.streaming)
 518                 vc4_hdmi_set_audio_infoframe(encoder);
 519
 520         vc4_hdmi_set_hdr_infoframe(encoder);
 521 }
 522
 523 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 524                                          struct drm_display_mode *mode)
 525 {
 526         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 527         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 528         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 529
 530         if (!vc4_encoder->hdmi_monitor)
 531                 return false;
 532
 533         if (!display->hdmi.scdc.supported ||
 534             !display->hdmi.scdc.scrambling.supported)
 535                 return false;
 536
 537         return true;
 538 }
 539
 540 #define SCRAMBLING_POLLING_DELAY_MS     1000
 541
 542 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 543 {
 544         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 545         struct drm_connector *connector = &vc4_hdmi->connector;
 546         struct drm_connector_state *cstate = connector->state;
 547         struct drm_crtc *crtc = cstate->crtc;
 548         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 549
 550         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 551                 return;
 552
 553         if (!vc4_hdmi_mode_needs_scrambling(mode))
 554                 return;
 555
 556         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 557         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 558
 559         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 560                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 561
 562         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 563                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 564 }
 565
 566 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 567 {
 568         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 569         struct drm_connector *connector = &vc4_hdmi->connector;
 570         struct drm_connector_state *cstate = connector->state;
 571
 572         /*
 573          * At boot, connector->state will be NULL. Since we don't know the
 574          * state of the scrambler and in order to avoid any
 575          * inconsistency, let's disable it all the time.
 576          */
 577         if (cstate && !vc4_hdmi_supports_scrambling(encoder, &cstate->crtc->mode))
 578                 return;
 579
 580         if (cstate && !vc4_hdmi_mode_needs_scrambling(&cstate->crtc->mode))
 581                 return;
 582
 583         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 584                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 585
 586         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 587                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 588
 589         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 590         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 591 }
 592
 593 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 594 {
 595         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 596                                                  struct vc4_hdmi,
 597                                                  scrambling_work);
 598
 599         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 600                 return;
 601
 602         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 603         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 604
 605         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 606                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 607 }
 608
 609 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 610                                                struct drm_atomic_state *state)
 611 {
 612         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 613
 614         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 615
 616         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 617
 618         mdelay(1);
 619
 620         HDMI_WRITE(HDMI_VID_CTL,
 621                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 622         vc4_hdmi_disable_scrambling(encoder);
 623 }
 624
 625 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 626                                                  struct drm_atomic_state *state)
 627 {
 628         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 629         int ret;
 630
 631         HDMI_WRITE(HDMI_VID_CTL,
 632                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 633
 634         if (vc4_hdmi->variant->phy_disable)
 635                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 636
 637         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 638         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 639
 640         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 641         if (ret < 0)
 642                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 643 }
 644
 645 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 646 {
 647 }
 648
 649 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 650 {
 651         u32 csc_ctl;
 652
 653         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 654                                 VC4_HD_CSC_CTL_ORDER);
 655
 656         if (enable) {
 657                 /* CEA VICs other than #1 requre limited range RGB
 658                  * output unless overridden by an AVI infoframe.
 659                  * Apply a colorspace conversion to squash 0-255 down
 660                  * to 16-235.  The matrix here is:
 661                  *
 662                  * [ 0      0      0.8594 16]
 663                  * [ 0      0.8594 0      16]
 664                  * [ 0.8594 0      0      16]
 665                  * [ 0      0      0       1]
 666                  */
 667                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 668                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 669                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 670                                          VC4_HD_CSC_CTL_MODE);
 671
 672                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 673                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 674                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 675                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 676                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 677                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 678         }
 679
 680         /* The RGB order applies even when CSC is disabled. */
 681         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 682 }
 683
 684 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 685 {
 686         u32 csc_ctl;
 687
 688         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 689
 690         if (enable) {
 691                 /* CEA VICs other than #1 requre limited range RGB
 692                  * output unless overridden by an AVI infoframe.
 693                  * Apply a colorspace conversion to squash 0-255 down
 694                  * to 16-235.  The matrix here is:
 695                  *
 696                  * [ 0.8594 0      0      16]
 697                  * [ 0      0.8594 0      16]
 698                  * [ 0      0      0.8594 16]
 699                  * [ 0      0      0       1]
 700                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 701                  */
 702                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 703                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 704                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 705                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 706                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 707                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 708         } else {
 709                 /* Still use the matrix for full range, but make it unity.
 710                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 711                  */
 712                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 713                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 714                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 715                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 716                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 717                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 718         }
 719
 720         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 721 }
 722
 723 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 724                                  struct drm_connector_state *state,
 725                                  struct drm_display_mode *mode)
 726 {
 727         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 728         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 729         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 730         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 731         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 732                                    VC4_HDMI_VERTA_VSP) |
 733                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 734                                    VC4_HDMI_VERTA_VFP) |
 735                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 736         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 737                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 738                                    VC4_HDMI_VERTB_VBP));
 739         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 740                           VC4_SET_FIELD(mode->crtc_vtotal -
 741                                         mode->crtc_vsync_end -
 742                                         interlaced,
 743                                         VC4_HDMI_VERTB_VBP));
 744
 745         HDMI_WRITE(HDMI_HORZA,
 746                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 747                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 748                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 749                                  VC4_HDMI_HORZA_HAP));
 750
 751         HDMI_WRITE(HDMI_HORZB,
 752                    VC4_SET_FIELD((mode->htotal -
 753                                   mode->hsync_end) * pixel_rep,
 754                                  VC4_HDMI_HORZB_HBP) |
 755                    VC4_SET_FIELD((mode->hsync_end -
 756                                   mode->hsync_start) * pixel_rep,
 757                                  VC4_HDMI_HORZB_HSP) |
 758                    VC4_SET_FIELD((mode->hsync_start -
 759                                   mode->hdisplay) * pixel_rep,
 760                                  VC4_HDMI_HORZB_HFP));
 761
 762         HDMI_WRITE(HDMI_VERTA0, verta);
 763         HDMI_WRITE(HDMI_VERTA1, verta);
 764
 765         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 766         HDMI_WRITE(HDMI_VERTB1, vertb);
 767 }
 768
 769 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 770                                  struct drm_connector_state *state,
 771                                  struct drm_display_mode *mode)
 772 {
 773         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 774         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 775         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 776         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 777         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 778                                    VC5_HDMI_VERTA_VSP) |
 779                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 780                                    VC5_HDMI_VERTA_VFP) |
 781                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 782         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 783                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 784                                    VC4_HDMI_VERTB_VBP));
 785         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 786                           VC4_SET_FIELD(mode->crtc_vtotal -
 787                                         mode->crtc_vsync_end -
 788                                         interlaced,
 789                                         VC4_HDMI_VERTB_VBP));
 790         unsigned char gcp;
 791         bool gcp_en;
 792         u32 reg;
 793
 794         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 795         HDMI_WRITE(HDMI_HORZA,
 796                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 797                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 798                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 799                                  VC5_HDMI_HORZA_HAP) |
 800                    VC4_SET_FIELD((mode->hsync_start -
 801                                   mode->hdisplay) * pixel_rep,
 802                                  VC5_HDMI_HORZA_HFP));
 803
 804         HDMI_WRITE(HDMI_HORZB,
 805                    VC4_SET_FIELD((mode->htotal -
 806                                   mode->hsync_end) * pixel_rep,
 807                                  VC5_HDMI_HORZB_HBP) |
 808                    VC4_SET_FIELD((mode->hsync_end -
 809                                   mode->hsync_start) * pixel_rep,
 810                                  VC5_HDMI_HORZB_HSP));
 811
 812         HDMI_WRITE(HDMI_VERTA0, verta);
 813         HDMI_WRITE(HDMI_VERTA1, verta);
 814
 815         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 816         HDMI_WRITE(HDMI_VERTB1, vertb);
 817
 818         switch (state->max_bpc) {
 819         case 12:
 820                 gcp = 6;
 821                 gcp_en = true;
 822                 break;
 823         case 10:
 824                 gcp = 5;
 825                 gcp_en = true;
 826                 break;
 827         case 8:
 828         default:
 829                 gcp = 4;
 830                 gcp_en = false;
 831                 break;
 832         }
 833
 834         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 835         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 836                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 837         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 838                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 839         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 840
 841         reg = HDMI_READ(HDMI_GCP_WORD_1);
 842         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 843         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 844         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 845
 846         reg = HDMI_READ(HDMI_GCP_CONFIG);
 847         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 848         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 849         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 850
 851         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 852 }
 853
 854 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 855 {
 856         u32 drift;
 857         int ret;
 858
 859         drift = HDMI_READ(HDMI_FIFO_CTL);
 860         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 861
 862         HDMI_WRITE(HDMI_FIFO_CTL,
 863                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 864         HDMI_WRITE(HDMI_FIFO_CTL,
 865                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 866         usleep_range(1000, 1100);
 867         HDMI_WRITE(HDMI_FIFO_CTL,
 868                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 869         HDMI_WRITE(HDMI_FIFO_CTL,
 870                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 871
 872         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 873                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 874         WARN_ONCE(ret, "Timeout waiting for "
 875                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 876 }
 877
 878 static struct drm_connector_state *
 879 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 880                                      struct drm_atomic_state *state)
 881 {
 882         struct drm_connector_state *conn_state;
 883         struct drm_connector *connector;
 884         unsigned int i;
 885
 886         for_each_new_connector_in_state(state, connector, conn_state, i) {
 887                 if (conn_state->best_encoder == encoder)
 888                         return conn_state;
 889         }
 890
 891         return NULL;
 892 }
 893
 894 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 895                                                 struct drm_atomic_state *state)
 896 {
 897         struct drm_connector_state *conn_state =
 898                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 899         struct vc4_hdmi_connector_state *vc4_conn_state =
 900                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 901         struct drm_crtc_state *crtc_state =
 902                 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
 903         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 904         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 905         unsigned long bvb_rate, pixel_rate, hsm_rate;
 906         int ret;
 907
 908         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 909         if (ret < 0) {
 910                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 911                 return;
 912         }
 913
 914         pixel_rate = vc4_conn_state->pixel_rate;
 915         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 916         if (ret) {
 917                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 918                 return;
 919         }
 920
 921         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 922         if (ret) {
 923                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 924                 return;
 925         }
 926
 927         /*
 928          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 929          * be faster than pixel clock, infinitesimally faster, tested in
 930          * simulation. Otherwise, exact value is unimportant for HDMI
 931          * operation." This conflicts with bcm2835's vc4 documentation, which
 932          * states HSM's clock has to be at least 108% of the pixel clock.
 933          *
 934          * Real life tests reveal that vc4's firmware statement holds up, and
 935          * users are able to use pixel clocks closer to HSM's, namely for
 936          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 937          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 938          * 162MHz.
 939          *
 940          * Additionally, the AXI clock needs to be at least 25% of
 941          * pixel clock, but HSM ends up being the limiting factor.
 942          */
 943         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 944         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 945         if (ret) {
 946                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 947                 return;
 948         }
 949
 950         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 951
 952         if (pixel_rate > 297000000)
 953                 bvb_rate = 300000000;
 954         else if (pixel_rate > 148500000)
 955                 bvb_rate = 150000000;
 956         else
 957                 bvb_rate = 75000000;
 958
 959         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 960         if (ret) {
 961                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 962                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 963                 return;
 964         }
 965
 966         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 967         if (ret) {
 968                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 969                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 970                 return;
 971         }
 972
 973         if (vc4_hdmi->variant->phy_init)
 974                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 975
 976         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 977                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 978                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 979                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 980
 981         if (vc4_hdmi->variant->set_timings)
 982                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 983 }
 984
 985 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 986                                              struct drm_atomic_state *state)
 987 {
 988         struct drm_connector_state *conn_state =
 989                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 990         struct drm_crtc_state *crtc_state =
 991                 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
 992         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 993         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 994         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 995
 996         if (vc4_encoder->hdmi_monitor &&
 997             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 998                 if (vc4_hdmi->variant->csc_setup)
 999                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1000
1001                 vc4_encoder->limited_rgb_range = true;
1002         } else {
1003                 if (vc4_hdmi->variant->csc_setup)
1004                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1005
1006                 vc4_encoder->limited_rgb_range = false;
1007         }
1008
1009         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1010 }
1011
1012 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1013                                               struct drm_atomic_state *state)
1014 {
1015         struct drm_connector_state *conn_state =
1016                 vc4_hdmi_encoder_get_connector_state(encoder, state);
1017         struct drm_crtc_state *crtc_state =
1018                 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1019         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1020         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1021         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1022         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1023         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1024         int ret;
1025
1026         HDMI_WRITE(HDMI_VID_CTL,
1027                    VC4_HD_VID_CTL_ENABLE |
1028                    VC4_HD_VID_CTL_CLRRGB |
1029                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1030                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1031                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1032                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1033
1034         HDMI_WRITE(HDMI_VID_CTL,
1035                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1036
1037         if (vc4_encoder->hdmi_monitor) {
1038                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1039                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1040                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1041
1042                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1043                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1044                 WARN_ONCE(ret, "Timeout waiting for "
1045                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1046         } else {
1047                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1048                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1049                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1050                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1051                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1052                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1053
1054                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1055                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1056                 WARN_ONCE(ret, "Timeout waiting for "
1057                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1058         }
1059
1060         if (vc4_encoder->hdmi_monitor) {
1061                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1062                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1063                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1064                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1065                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1066
1067                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1068                            VC4_HDMI_RAM_PACKET_ENABLE);
1069
1070                 vc4_hdmi_set_infoframes(encoder);
1071         }
1072
1073         vc4_hdmi_recenter_fifo(vc4_hdmi);
1074         vc4_hdmi_enable_scrambling(encoder);
1075 }
1076
1077 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1078 {
1079 }
1080
1081 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1082 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1083
1084 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1085                                          struct drm_crtc_state *crtc_state,
1086                                          struct drm_connector_state *conn_state)
1087 {
1088         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1089         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1090         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1091         unsigned long long pixel_rate = mode->clock * 1000;
1092         unsigned long long tmds_rate;
1093
1094         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1095             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1096              (mode->hsync_end % 2) || (mode->htotal % 2)))
1097                 return -EINVAL;
1098
1099         /*
1100          * The 1440p@60 pixel rate is in the same range than the first
1101          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1102          * bandwidth). Slightly lower the frequency to bring it out of
1103          * the WiFi range.
1104          */
1105         tmds_rate = pixel_rate * 10;
1106         if (vc4_hdmi->disable_wifi_frequencies &&
1107             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1108              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1109                 mode->clock = 238560;
1110                 pixel_rate = mode->clock * 1000;
1111         }
1112
1113         if (conn_state->max_bpc == 12) {
1114                 pixel_rate = pixel_rate * 150;
1115                 do_div(pixel_rate, 100);
1116         } else if (conn_state->max_bpc == 10) {
1117                 pixel_rate = pixel_rate * 125;
1118                 do_div(pixel_rate, 100);
1119         }
1120
1121         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1122                 pixel_rate = pixel_rate * 2;
1123
1124         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1125                 return -EINVAL;
1126
1127         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1128                 return -EINVAL;
1129
1130         vc4_state->pixel_rate = pixel_rate;
1131
1132         return 0;
1133 }
1134
1135 static enum drm_mode_status
1136 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1137                             const struct drm_display_mode *mode)
1138 {
1139         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1140
1141         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1142             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1143              (mode->hsync_end % 2) || (mode->htotal % 2)))
1144                 return MODE_H_ILLEGAL;
1145
1146         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1147                 return MODE_CLOCK_HIGH;
1148
1149         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1150                 return MODE_CLOCK_HIGH;
1151
1152         return MODE_OK;
1153 }
1154
1155 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1156         .atomic_check = vc4_hdmi_encoder_atomic_check,
1157         .mode_valid = vc4_hdmi_encoder_mode_valid,
1158         .disable = vc4_hdmi_encoder_disable,
1159         .enable = vc4_hdmi_encoder_enable,
1160 };
1161
1162 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1163 {
1164         int i;
1165         u32 channel_map = 0;
1166
1167         for (i = 0; i < 8; i++) {
1168                 if (channel_mask & BIT(i))
1169                         channel_map |= i << (3 * i);
1170         }
1171         return channel_map;
1172 }
1173
1174 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1175 {
1176         int i;
1177         u32 channel_map = 0;
1178
1179         for (i = 0; i < 8; i++) {
1180                 if (channel_mask & BIT(i))
1181                         channel_map |= i << (4 * i);
1182         }
1183         return channel_map;
1184 }
1185
1186 /* HDMI audio codec callbacks */
1187 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1188 {
1189         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1190         unsigned long n, m;
1191
1192         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1193                                     VC4_HD_MAI_SMP_N_MASK >>
1194                                     VC4_HD_MAI_SMP_N_SHIFT,
1195                                     (VC4_HD_MAI_SMP_M_MASK >>
1196                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1197                                     &n, &m);
1198
1199         HDMI_WRITE(HDMI_MAI_SMP,
1200                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1201                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1202 }
1203
1204 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1205 {
1206         struct drm_connector *connector = &vc4_hdmi->connector;
1207         struct drm_crtc *crtc = connector->state->crtc;
1208         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1209         u32 samplerate = vc4_hdmi->audio.samplerate;
1210         u32 n, cts;
1211         u64 tmp;
1212
1213         n = 128 * samplerate / 1000;
1214         tmp = (u64)(mode->clock * 1000) * n;
1215         do_div(tmp, 128 * samplerate);
1216         cts = tmp;
1217
1218         HDMI_WRITE(HDMI_CRP_CFG,
1219                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1220                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1221
1222         /*
1223          * We could get slightly more accurate clocks in some cases by
1224          * providing a CTS_1 value.  The two CTS values are alternated
1225          * between based on the period fields
1226          */
1227         HDMI_WRITE(HDMI_CTS_0, cts);
1228         HDMI_WRITE(HDMI_CTS_1, cts);
1229 }
1230
1231 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1232 {
1233         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1234
1235         return snd_soc_card_get_drvdata(card);
1236 }
1237
1238 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1239 {
1240         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1241         struct drm_connector *connector = &vc4_hdmi->connector;
1242
1243         /*
1244          * If the HDMI encoder hasn't probed, or the encoder is
1245          * currently in DVI mode, treat the codec dai as missing.
1246          */
1247         if (!connector->state || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1248                                 VC4_HDMI_RAM_PACKET_ENABLE))
1249                 return -ENODEV;
1250
1251         vc4_hdmi->audio.streaming = true;
1252
1253         HDMI_WRITE(HDMI_MAI_CTL,
1254                    VC4_HD_MAI_CTL_RESET |
1255                    VC4_HD_MAI_CTL_FLUSH |
1256                    VC4_HD_MAI_CTL_DLATE |
1257                    VC4_HD_MAI_CTL_ERRORE |
1258                    VC4_HD_MAI_CTL_ERRORF);
1259
1260         if (vc4_hdmi->variant->phy_rng_enable)
1261                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1262
1263         return 0;
1264 }
1265
1266 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1267 {
1268         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1269         struct device *dev = &vc4_hdmi->pdev->dev;
1270         int ret;
1271
1272         vc4_hdmi->audio.streaming = false;
1273         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1274         if (ret)
1275                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1276
1277         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1278         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1279         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1280 }
1281
1282 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1283 {
1284         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1285
1286         HDMI_WRITE(HDMI_MAI_CTL,
1287                    VC4_HD_MAI_CTL_DLATE |
1288                    VC4_HD_MAI_CTL_ERRORE |
1289                    VC4_HD_MAI_CTL_ERRORF);
1290
1291         if (vc4_hdmi->variant->phy_rng_disable)
1292                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1293
1294         vc4_hdmi->audio.streaming = false;
1295         vc4_hdmi_audio_reset(vc4_hdmi);
1296 }
1297
1298 static int sample_rate_to_mai_fmt(int samplerate)
1299 {
1300         switch (samplerate) {
1301         case 8000:
1302                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1303         case 11025:
1304                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1305         case 12000:
1306                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1307         case 16000:
1308                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1309         case 22050:
1310                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1311         case 24000:
1312                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1313         case 32000:
1314                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1315         case 44100:
1316                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1317         case 48000:
1318                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1319         case 64000:
1320                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1321         case 88200:
1322                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1323         case 96000:
1324                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1325         case 128000:
1326                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1327         case 176400:
1328                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1329         case 192000:
1330                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1331         default:
1332                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1333         }
1334 }
1335
1336 /* HDMI audio codec callbacks */
1337 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1338                                   struct hdmi_codec_daifmt *daifmt,
1339                                   struct hdmi_codec_params *params)
1340 {
1341         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1342         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1343         u32 audio_packet_config, channel_mask;
1344         u32 channel_map;
1345         u32 mai_audio_format;
1346         u32 mai_sample_rate;
1347
1348         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1349                 params->sample_rate, params->sample_width,
1350                 params->channels);
1351
1352         vc4_hdmi->audio.channels = params->channels;
1353         vc4_hdmi->audio.samplerate = params->sample_rate;
1354
1355         HDMI_WRITE(HDMI_MAI_CTL,
1356                    VC4_SET_FIELD(params->channels, VC4_HD_MAI_CTL_CHNUM) |
1357                    VC4_HD_MAI_CTL_WHOLSMP |
1358                    VC4_HD_MAI_CTL_CHALIGN |
1359                    VC4_HD_MAI_CTL_ENABLE);
1360
1361         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1362
1363         mai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);
1364         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1365             params->channels == 8)
1366                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1367         else
1368                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1369         HDMI_WRITE(HDMI_MAI_FMT,
1370                    VC4_SET_FIELD(mai_sample_rate,
1371                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1372                    VC4_SET_FIELD(mai_audio_format,
1373                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1374
1375         /* The B frame identifier should match the value used by alsa-lib (8) */
1376         audio_packet_config =
1377                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1378                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1379                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1380
1381         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1382         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1383                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1384
1385         /* Set the MAI threshold */
1386         HDMI_WRITE(HDMI_MAI_THR,
1387                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1388                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1389                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1390                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1391
1392         HDMI_WRITE(HDMI_MAI_CONFIG,
1393                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1394                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1395                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1396
1397         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1398         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1399         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1400         vc4_hdmi_set_n_cts(vc4_hdmi);
1401
1402         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1403         vc4_hdmi_set_audio_infoframe(encoder);
1404
1405         return 0;
1406 }
1407
1408 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1409         SND_SOC_DAPM_OUTPUT("TX"),
1410 };
1411
1412 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1413         { "TX", NULL, "Playback" },
1414 };
1415
1416 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1417         .name                   = "vc4-hdmi-codec-dai-component",
1418         .dapm_widgets           = vc4_hdmi_audio_widgets,
1419         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1420         .dapm_routes            = vc4_hdmi_audio_routes,
1421         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1422         .idle_bias_on           = 1,
1423         .use_pmdown_time        = 1,
1424         .endianness             = 1,
1425         .non_legacy_dai_naming  = 1,
1426 };
1427
1428 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1429         .name = "vc4-hdmi-cpu-dai-component",
1430 };
1431
1432 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1433 {
1434         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1435
1436         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1437
1438         return 0;
1439 }
1440
1441 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1442         .name = "vc4-hdmi-cpu-dai",
1443         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1444         .playback = {
1445                 .stream_name = "Playback",
1446                 .channels_min = 1,
1447                 .channels_max = 8,
1448                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1449                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1450                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1451                          SNDRV_PCM_RATE_192000,
1452                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1453         },
1454 };
1455
1456 static const struct snd_dmaengine_pcm_config pcm_conf = {
1457         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1458         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1459 };
1460
1461 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1462                                   uint8_t *buf, size_t len)
1463 {
1464         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1465         struct drm_connector *connector = &vc4_hdmi->connector;
1466
1467         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1468
1469         return 0;
1470 }
1471
1472 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1473         .get_eld = vc4_hdmi_audio_get_eld,
1474         .prepare = vc4_hdmi_audio_prepare,
1475         .audio_shutdown = vc4_hdmi_audio_shutdown,
1476         .audio_startup = vc4_hdmi_audio_startup,
1477 };
1478
1479 struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1480         .ops = &vc4_hdmi_codec_ops,
1481         .max_i2s_channels = 8,
1482         .i2s = 1,
1483 };
1484
1485 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1486 {
1487         const struct vc4_hdmi_register *mai_data =
1488                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1489         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1490         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1491         struct device *dev = &vc4_hdmi->pdev->dev;
1492         struct platform_device *codec_pdev;
1493         const __be32 *addr;
1494         int index;
1495         int ret;
1496
1497         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1498                 dev_warn(dev,
1499                          "'dmas' DT property is missing, no HDMI audio\n");
1500                 return 0;
1501         }
1502
1503         if (mai_data->reg != VC4_HD) {
1504                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1505                 return -EINVAL;
1506         }
1507
1508         /*
1509          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1510          * the bus address specified in the DT, because the physical address
1511          * (the one returned by platform_get_resource()) is not appropriate
1512          * for DMA transfers.
1513          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1514          */
1515         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1516         /* Before BCM2711, we don't have a named register range */
1517         if (index < 0)
1518                 index = 1;
1519
1520         addr = of_get_address(dev->of_node, index, NULL, NULL);
1521
1522         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1523         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1524         vc4_hdmi->audio.dma_data.maxburst = 2;
1525
1526         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1527         if (ret) {
1528                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1529                 return ret;
1530         }
1531
1532         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1533                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1534         if (ret) {
1535                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1536                 return ret;
1537         }
1538
1539         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1540                                                    PLATFORM_DEVID_AUTO,
1541                                                    &vc4_hdmi_codec_pdata,
1542                                                    sizeof(vc4_hdmi_codec_pdata));
1543         if (IS_ERR(codec_pdev)) {
1544                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1545                 return PTR_ERR(codec_pdev);
1546         }
1547
1548         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1549         dai_link->codecs        = &vc4_hdmi->audio.codec;
1550         dai_link->platforms     = &vc4_hdmi->audio.platform;
1551
1552         dai_link->num_cpus      = 1;
1553         dai_link->num_codecs    = 1;
1554         dai_link->num_platforms = 1;
1555
1556         dai_link->name = "MAI";
1557         dai_link->stream_name = "MAI PCM";
1558         dai_link->codecs->dai_name = "i2s-hifi";
1559         dai_link->cpus->dai_name = dev_name(dev);
1560         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1561         dai_link->platforms->name = dev_name(dev);
1562
1563         card->dai_link = dai_link;
1564         card->num_links = 1;
1565         card->name = vc4_hdmi->variant->card_name;
1566         card->driver_name = "vc4-hdmi";
1567         card->dev = dev;
1568         card->owner = THIS_MODULE;
1569
1570         /*
1571          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1572          * stores a pointer to the snd card object in dev->driver_data. This
1573          * means we cannot use it for something else. The hdmi back-pointer is
1574          * now stored in card->drvdata and should be retrieved with
1575          * snd_soc_card_get_drvdata() if needed.
1576          */
1577         snd_soc_card_set_drvdata(card, vc4_hdmi);
1578         ret = devm_snd_soc_register_card(dev, card);
1579         if (ret)
1580                 dev_err_probe(dev, ret, "Could not register sound card\n");
1581
1582         return ret;
1583
1584 }
1585
1586 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1587 {
1588         struct vc4_hdmi *vc4_hdmi = priv;
1589         struct drm_device *dev = vc4_hdmi->connector.dev;
1590
1591         if (dev && dev->registered)
1592                 drm_kms_helper_hotplug_event(dev);
1593
1594         return IRQ_HANDLED;
1595 }
1596
1597 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1598 {
1599         struct drm_connector *connector = &vc4_hdmi->connector;
1600         struct platform_device *pdev = vc4_hdmi->pdev;
1601         int ret;
1602
1603         if (vc4_hdmi->variant->external_irq_controller) {
1604                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1605                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1606
1607                 ret = request_threaded_irq(hpd_con,
1608                                            NULL,
1609                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1610                                            "vc4 hdmi hpd connected", vc4_hdmi);
1611                 if (ret)
1612                         return ret;
1613
1614                 ret = request_threaded_irq(hpd_rm,
1615                                            NULL,
1616                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1617                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1618                 if (ret) {
1619                         free_irq(hpd_con, vc4_hdmi);
1620                         return ret;
1621                 }
1622
1623                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1624         }
1625
1626         return 0;
1627 }
1628
1629 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1630 {
1631         struct platform_device *pdev = vc4_hdmi->pdev;
1632
1633         if (vc4_hdmi->variant->external_irq_controller) {
1634                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1635                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1636         }
1637 }
1638
1639 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1640 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1641 {
1642         struct vc4_hdmi *vc4_hdmi = priv;
1643
1644         if (vc4_hdmi->cec_rx_msg.len)
1645                 cec_received_msg(vc4_hdmi->cec_adap,
1646                                  &vc4_hdmi->cec_rx_msg);
1647
1648         return IRQ_HANDLED;
1649 }
1650
1651 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1652 {
1653         struct vc4_hdmi *vc4_hdmi = priv;
1654
1655         if (vc4_hdmi->cec_tx_ok) {
1656                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1657                                   0, 0, 0, 0);
1658         } else {
1659                 /*
1660                  * This CEC implementation makes 1 retry, so if we
1661                  * get a NACK, then that means it made 2 attempts.
1662                  */
1663                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1664                                   0, 2, 0, 0);
1665         }
1666         return IRQ_HANDLED;
1667 }
1668
1669 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1670 {
1671         struct vc4_hdmi *vc4_hdmi = priv;
1672         irqreturn_t ret;
1673
1674         if (vc4_hdmi->cec_irq_was_rx)
1675                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1676         else
1677                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1678
1679         return ret;
1680 }
1681
1682 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1683 {
1684         struct drm_device *dev = vc4_hdmi->connector.dev;
1685         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1686         unsigned int i;
1687
1688         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1689                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1690
1691         if (msg->len > 16) {
1692                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1693                 return;
1694         }
1695
1696         for (i = 0; i < msg->len; i += 4) {
1697                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1698
1699                 msg->msg[i] = val & 0xff;
1700                 msg->msg[i + 1] = (val >> 8) & 0xff;
1701                 msg->msg[i + 2] = (val >> 16) & 0xff;
1702                 msg->msg[i + 3] = (val >> 24) & 0xff;
1703         }
1704 }
1705
1706 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1707 {
1708         struct vc4_hdmi *vc4_hdmi = priv;
1709         u32 cntrl1;
1710
1711         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1712         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1713         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1714         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1715
1716         return IRQ_WAKE_THREAD;
1717 }
1718
1719 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1720 {
1721         struct vc4_hdmi *vc4_hdmi = priv;
1722         u32 cntrl1;
1723
1724         vc4_hdmi->cec_rx_msg.len = 0;
1725         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1726         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1727         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1728         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1729         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1730
1731         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1732
1733         return IRQ_WAKE_THREAD;
1734 }
1735
1736 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1737 {
1738         struct vc4_hdmi *vc4_hdmi = priv;
1739         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1740         irqreturn_t ret;
1741         u32 cntrl5;
1742
1743         if (!(stat & VC4_HDMI_CPU_CEC))
1744                 return IRQ_NONE;
1745
1746         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1747         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1748         if (vc4_hdmi->cec_irq_was_rx)
1749                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1750         else
1751                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1752
1753         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1754         return ret;
1755 }
1756
1757 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1758 {
1759         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1760         /* clock period in microseconds */
1761         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1762         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1763
1764         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1765                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1766                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1767         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1768                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1769
1770         if (enable) {
1771                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1772                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1773                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1774                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1775                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1776                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1777                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1778                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1779                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1780                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1781                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1782                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1783                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1784                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1785                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1786                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1787                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1788                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1789                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1790
1791                 if (!vc4_hdmi->variant->external_irq_controller)
1792                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1793         } else {
1794                 if (!vc4_hdmi->variant->external_irq_controller)
1795                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1796                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1797                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1798         }
1799         return 0;
1800 }
1801
1802 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1803 {
1804         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1805
1806         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1807                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1808                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1809         return 0;
1810 }
1811
1812 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1813                                       u32 signal_free_time, struct cec_msg *msg)
1814 {
1815         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1816         struct drm_device *dev = vc4_hdmi->connector.dev;
1817         u32 val;
1818         unsigned int i;
1819
1820         if (msg->len > 16) {
1821                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1822                 return -ENOMEM;
1823         }
1824
1825         for (i = 0; i < msg->len; i += 4)
1826                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1827                            (msg->msg[i]) |
1828                            (msg->msg[i + 1] << 8) |
1829                            (msg->msg[i + 2] << 16) |
1830                            (msg->msg[i + 3] << 24));
1831
1832         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1833         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1834         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1835         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1836         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1837         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1838
1839         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1840         return 0;
1841 }
1842
1843 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1844         .adap_enable = vc4_hdmi_cec_adap_enable,
1845         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1846         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1847 };
1848
1849 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1850 {
1851         struct cec_connector_info conn_info;
1852         struct platform_device *pdev = vc4_hdmi->pdev;
1853         struct device *dev = &pdev->dev;
1854         u32 value;
1855         int ret;
1856
1857         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1858                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1859                 return 0;
1860         }
1861
1862         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1863                                                   vc4_hdmi, "vc4",
1864                                                   CEC_CAP_DEFAULTS |
1865                                                   CEC_CAP_CONNECTOR_INFO, 1);
1866         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1867         if (ret < 0)
1868                 return ret;
1869
1870         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1871         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1872
1873         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1874         /* Set the logical address to Unregistered */
1875         value |= VC4_HDMI_CEC_ADDR_MASK;
1876         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1877
1878         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1879
1880         if (vc4_hdmi->variant->external_irq_controller) {
1881                 ret = devm_request_threaded_irq(&pdev->dev,
1882                                                 platform_get_irq_byname(pdev, "cec-rx"),
1883                                                 vc4_cec_irq_handler_rx_bare,
1884                                                 vc4_cec_irq_handler_rx_thread, 0,
1885                                                 "vc4 hdmi cec rx", vc4_hdmi);
1886                 if (ret)
1887                         goto err_delete_cec_adap;
1888
1889                 ret = devm_request_threaded_irq(&pdev->dev,
1890                                                 platform_get_irq_byname(pdev, "cec-tx"),
1891                                                 vc4_cec_irq_handler_tx_bare,
1892                                                 vc4_cec_irq_handler_tx_thread, 0,
1893                                                 "vc4 hdmi cec tx", vc4_hdmi);
1894                 if (ret)
1895                         goto err_delete_cec_adap;
1896         } else {
1897                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1898
1899                 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1900                                                 vc4_cec_irq_handler,
1901                                                 vc4_cec_irq_handler_thread, 0,
1902                                                 "vc4 hdmi cec", vc4_hdmi);
1903                 if (ret)
1904                         goto err_delete_cec_adap;
1905         }
1906
1907         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1908         if (ret < 0)
1909                 goto err_delete_cec_adap;
1910
1911         return 0;
1912
1913 err_delete_cec_adap:
1914         cec_delete_adapter(vc4_hdmi->cec_adap);
1915
1916         return ret;
1917 }
1918
1919 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1920 {
1921         cec_unregister_adapter(vc4_hdmi->cec_adap);
1922 }
1923 #else
1924 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1925 {
1926         return 0;
1927 }
1928
1929 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1930
1931 #endif
1932
1933 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1934                                  struct debugfs_regset32 *regset,
1935                                  enum vc4_hdmi_regs reg)
1936 {
1937         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1938         struct debugfs_reg32 *regs, *new_regs;
1939         unsigned int count = 0;
1940         unsigned int i;
1941
1942         regs = kcalloc(variant->num_registers, sizeof(*regs),
1943                        GFP_KERNEL);
1944         if (!regs)
1945                 return -ENOMEM;
1946
1947         for (i = 0; i < variant->num_registers; i++) {
1948                 const struct vc4_hdmi_register *field = &variant->registers[i];
1949
1950                 if (field->reg != reg)
1951                         continue;
1952
1953                 regs[count].name = field->name;
1954                 regs[count].offset = field->offset;
1955                 count++;
1956         }
1957
1958         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1959         if (!new_regs)
1960                 return -ENOMEM;
1961
1962         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1963         regset->regs = new_regs;
1964         regset->nregs = count;
1965
1966         return 0;
1967 }
1968
1969 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1970 {
1971         struct platform_device *pdev = vc4_hdmi->pdev;
1972         struct device *dev = &pdev->dev;
1973         int ret;
1974
1975         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1976         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1977                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1978
1979         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1980         if (IS_ERR(vc4_hdmi->hd_regs))
1981                 return PTR_ERR(vc4_hdmi->hd_regs);
1982
1983         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1984         if (ret)
1985                 return ret;
1986
1987         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1988         if (ret)
1989                 return ret;
1990
1991         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1992         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1993                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1994                 if (ret != -EPROBE_DEFER)
1995                         DRM_ERROR("Failed to get pixel clock\n");
1996                 return ret;
1997         }
1998
1999         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2000         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2001                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2002                 return PTR_ERR(vc4_hdmi->hsm_clock);
2003         }
2004         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2005         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2006
2007         return 0;
2008 }
2009
2010 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2011 {
2012         struct platform_device *pdev = vc4_hdmi->pdev;
2013         struct device *dev = &pdev->dev;
2014         struct resource *res;
2015
2016         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2017         if (!res)
2018                 return -ENODEV;
2019
2020         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2021                                                resource_size(res));
2022         if (!vc4_hdmi->hdmicore_regs)
2023                 return -ENOMEM;
2024
2025         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2026         if (!res)
2027                 return -ENODEV;
2028
2029         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2030         if (!vc4_hdmi->hd_regs)
2031                 return -ENOMEM;
2032
2033         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2034         if (!res)
2035                 return -ENODEV;
2036
2037         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2038         if (!vc4_hdmi->cec_regs)
2039                 return -ENOMEM;
2040
2041         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2042         if (!res)
2043                 return -ENODEV;
2044
2045         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2046         if (!vc4_hdmi->csc_regs)
2047                 return -ENOMEM;
2048
2049         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2050         if (!res)
2051                 return -ENODEV;
2052
2053         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2054         if (!vc4_hdmi->dvp_regs)
2055                 return -ENOMEM;
2056
2057         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2058         if (!res)
2059                 return -ENODEV;
2060
2061         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2062         if (!vc4_hdmi->phy_regs)
2063                 return -ENOMEM;
2064
2065         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2066         if (!res)
2067                 return -ENODEV;
2068
2069         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2070         if (!vc4_hdmi->ram_regs)
2071                 return -ENOMEM;
2072
2073         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2074         if (!res)
2075                 return -ENODEV;
2076
2077         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2078         if (!vc4_hdmi->rm_regs)
2079                 return -ENOMEM;
2080
2081         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2082         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2083                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2084                 return PTR_ERR(vc4_hdmi->hsm_clock);
2085         }
2086
2087         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2088         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2089                 DRM_ERROR("Failed to get pixel bvb clock\n");
2090                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2091         }
2092
2093         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2094         if (IS_ERR(vc4_hdmi->audio_clock)) {
2095                 DRM_ERROR("Failed to get audio clock\n");
2096                 return PTR_ERR(vc4_hdmi->audio_clock);
2097         }
2098
2099         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2100         if (IS_ERR(vc4_hdmi->cec_clock)) {
2101                 DRM_ERROR("Failed to get CEC clock\n");
2102                 return PTR_ERR(vc4_hdmi->cec_clock);
2103         }
2104
2105         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2106         if (IS_ERR(vc4_hdmi->reset)) {
2107                 DRM_ERROR("Failed to get HDMI reset line\n");
2108                 return PTR_ERR(vc4_hdmi->reset);
2109         }
2110
2111         return 0;
2112 }
2113
2114 #ifdef CONFIG_PM
2115 static int vc4_hdmi_runtime_suspend(struct device *dev)
2116 {
2117         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2118
2119         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2120
2121         return 0;
2122 }
2123
2124 static int vc4_hdmi_runtime_resume(struct device *dev)
2125 {
2126         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2127         int ret;
2128
2129         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2130         if (ret)
2131                 return ret;
2132
2133         return 0;
2134 }
2135 #endif
2136
2137 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2138 {
2139         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2140         struct platform_device *pdev = to_platform_device(dev);
2141         struct drm_device *drm = dev_get_drvdata(master);
2142         struct vc4_hdmi *vc4_hdmi;
2143         struct drm_encoder *encoder;
2144         struct device_node *ddc_node;
2145         int ret;
2146
2147         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2148         if (!vc4_hdmi)
2149                 return -ENOMEM;
2150         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2151
2152         dev_set_drvdata(dev, vc4_hdmi);
2153         encoder = &vc4_hdmi->encoder.base.base;
2154         vc4_hdmi->encoder.base.type = variant->encoder_type;
2155         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2156         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2157         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2158         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2159         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2160         vc4_hdmi->pdev = pdev;
2161         vc4_hdmi->variant = variant;
2162
2163         ret = variant->init_resources(vc4_hdmi);
2164         if (ret)
2165                 return ret;
2166
2167         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2168         if (!ddc_node) {
2169                 DRM_ERROR("Failed to find ddc node in device tree\n");
2170                 return -ENODEV;
2171         }
2172
2173         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2174         of_node_put(ddc_node);
2175         if (!vc4_hdmi->ddc) {
2176                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2177                 return -EPROBE_DEFER;
2178         }
2179
2180         /* Only use the GPIO HPD pin if present in the DT, otherwise
2181          * we'll use the HDMI core's register.
2182          */
2183         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2184         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2185                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2186                 goto err_put_ddc;
2187         }
2188
2189         vc4_hdmi->disable_wifi_frequencies =
2190                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2191
2192         if (variant->max_pixel_clock == 600000000) {
2193                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2194                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2195
2196                 if (max_rate < 550000000)
2197                         vc4_hdmi->disable_4kp60 = true;
2198         }
2199
2200         if (vc4_hdmi->variant->reset)
2201                 vc4_hdmi->variant->reset(vc4_hdmi);
2202
2203         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2204              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2205             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2206                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2207                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2208                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2209         }
2210
2211         pm_runtime_enable(dev);
2212
2213         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2214         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2215
2216         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2217         if (ret)
2218                 goto err_destroy_encoder;
2219
2220         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2221         if (ret)
2222                 goto err_destroy_conn;
2223
2224         ret = vc4_hdmi_cec_init(vc4_hdmi);
2225         if (ret)
2226                 goto err_free_hotplug;
2227
2228         ret = vc4_hdmi_audio_init(vc4_hdmi);
2229         if (ret)
2230                 goto err_free_cec;
2231
2232         vc4_debugfs_add_file(drm, variant->debugfs_name,
2233                              vc4_hdmi_debugfs_regs,
2234                              vc4_hdmi);
2235
2236         return 0;
2237
2238 err_free_cec:
2239         vc4_hdmi_cec_exit(vc4_hdmi);
2240 err_free_hotplug:
2241         vc4_hdmi_hotplug_exit(vc4_hdmi);
2242 err_destroy_conn:
2243         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2244 err_destroy_encoder:
2245         drm_encoder_cleanup(encoder);
2246         pm_runtime_disable(dev);
2247 err_put_ddc:
2248         put_device(&vc4_hdmi->ddc->dev);
2249
2250         return ret;
2251 }
2252
2253 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2254                             void *data)
2255 {
2256         struct vc4_hdmi *vc4_hdmi;
2257
2258         /*
2259          * ASoC makes it a bit hard to retrieve a pointer to the
2260          * vc4_hdmi structure. Registering the card will overwrite our
2261          * device drvdata with a pointer to the snd_soc_card structure,
2262          * which can then be used to retrieve whatever drvdata we want
2263          * to associate.
2264          *
2265          * However, that doesn't fly in the case where we wouldn't
2266          * register an ASoC card (because of an old DT that is missing
2267          * the dmas properties for example), then the card isn't
2268          * registered and the device drvdata wouldn't be set.
2269          *
2270          * We can deal with both cases by making sure a snd_soc_card
2271          * pointer and a vc4_hdmi structure are pointing to the same
2272          * memory address, so we can treat them indistinctly without any
2273          * issue.
2274          */
2275         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2276         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2277         vc4_hdmi = dev_get_drvdata(dev);
2278
2279         kfree(vc4_hdmi->hdmi_regset.regs);
2280         kfree(vc4_hdmi->hd_regset.regs);
2281
2282         vc4_hdmi_cec_exit(vc4_hdmi);
2283         vc4_hdmi_hotplug_exit(vc4_hdmi);
2284         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2285         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2286
2287         pm_runtime_disable(dev);
2288
2289         put_device(&vc4_hdmi->ddc->dev);
2290 }
2291
2292 static const struct component_ops vc4_hdmi_ops = {
2293         .bind   = vc4_hdmi_bind,
2294         .unbind = vc4_hdmi_unbind,
2295 };
2296
2297 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2298 {
2299         return component_add(&pdev->dev, &vc4_hdmi_ops);
2300 }
2301
2302 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2303 {
2304         component_del(&pdev->dev, &vc4_hdmi_ops);
2305         return 0;
2306 }
2307
2308 static const struct vc4_hdmi_variant bcm2835_variant = {
2309         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2310         .debugfs_name           = "hdmi_regs",
2311         .card_name              = "vc4-hdmi",
2312         .max_pixel_clock        = 162000000,
2313         .registers              = vc4_hdmi_fields,
2314         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2315
2316         .init_resources         = vc4_hdmi_init_resources,
2317         .csc_setup              = vc4_hdmi_csc_setup,
2318         .reset                  = vc4_hdmi_reset,
2319         .set_timings            = vc4_hdmi_set_timings,
2320         .phy_init               = vc4_hdmi_phy_init,
2321         .phy_disable            = vc4_hdmi_phy_disable,
2322         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2323         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2324         .channel_map            = vc4_hdmi_channel_map,
2325         .supports_hdr           = false,
2326 };
2327
2328 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2329         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2330         .debugfs_name           = "hdmi0_regs",
2331         .card_name              = "vc4-hdmi-0",
2332         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2333         .registers              = vc5_hdmi_hdmi0_fields,
2334         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2335         .phy_lane_mapping       = {
2336                 PHY_LANE_0,
2337                 PHY_LANE_1,
2338                 PHY_LANE_2,
2339                 PHY_LANE_CK,
2340         },
2341         .unsupported_odd_h_timings      = true,
2342         .external_irq_controller        = true,
2343
2344         .init_resources         = vc5_hdmi_init_resources,
2345         .csc_setup              = vc5_hdmi_csc_setup,
2346         .reset                  = vc5_hdmi_reset,
2347         .set_timings            = vc5_hdmi_set_timings,
2348         .phy_init               = vc5_hdmi_phy_init,
2349         .phy_disable            = vc5_hdmi_phy_disable,
2350         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2351         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2352         .channel_map            = vc5_hdmi_channel_map,
2353         .supports_hdr           = true,
2354 };
2355
2356 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2357         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2358         .debugfs_name           = "hdmi1_regs",
2359         .card_name              = "vc4-hdmi-1",
2360         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2361         .registers              = vc5_hdmi_hdmi1_fields,
2362         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2363         .phy_lane_mapping       = {
2364                 PHY_LANE_1,
2365                 PHY_LANE_0,
2366                 PHY_LANE_CK,
2367                 PHY_LANE_2,
2368         },
2369         .unsupported_odd_h_timings      = true,
2370         .external_irq_controller        = true,
2371
2372         .init_resources         = vc5_hdmi_init_resources,
2373         .csc_setup              = vc5_hdmi_csc_setup,
2374         .reset                  = vc5_hdmi_reset,
2375         .set_timings            = vc5_hdmi_set_timings,
2376         .phy_init               = vc5_hdmi_phy_init,
2377         .phy_disable            = vc5_hdmi_phy_disable,
2378         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2379         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2380         .channel_map            = vc5_hdmi_channel_map,
2381         .supports_hdr           = true,
2382 };
2383
2384 static const struct of_device_id vc4_hdmi_dt_match[] = {
2385         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2386         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2387         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2388         {}
2389 };
2390
2391 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2392         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2393                            vc4_hdmi_runtime_resume,
2394                            NULL)
2395 };
2396
2397 struct platform_driver vc4_hdmi_driver = {
2398         .probe = vc4_hdmi_dev_probe,
2399         .remove = vc4_hdmi_dev_remove,
2400         .driver = {
2401                 .name = "vc4_hdmi",
2402                 .of_match_table = vc4_hdmi_dt_match,
2403                 .pm = &vc4_hdmi_pm_ops,
2404         },
2405 };