drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 103 {
 104         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 105 }
 106
 107 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 108                                        const struct drm_display_mode *mode)
 109 {
 110         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 111
 112         return !vc4_encoder->hdmi_monitor ||
 113                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 114 }
 115
 116 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 117 {
 118         struct drm_info_node *node = (struct drm_info_node *)m->private;
 119         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 120         struct drm_printer p = drm_seq_file_printer(m);
 121
 122         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 123         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 124
 125         return 0;
 126 }
 127
 128 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 133
 134         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 135         udelay(1);
 136         HDMI_WRITE(HDMI_M_CTL, 0);
 137
 138         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 139
 140         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 141                    VC4_HDMI_SW_RESET_HDMI |
 142                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 143
 144         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 145
 146         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 147 }
 148
 149 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 150 {
 151         unsigned long flags;
 152
 153         reset_control_reset(vc4_hdmi->reset);
 154
 155         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 156
 157         HDMI_WRITE(HDMI_DVP_CTL, 0);
 158
 159         HDMI_WRITE(HDMI_CLOCK_STOP,
 160                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 161
 162         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 163 }
 164
 165 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 167 {
 168         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 169         unsigned long flags;
 170         u16 clk_cnt;
 171         u32 value;
 172
 173         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 174
 175         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 176         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 177
 178         /*
 179          * Set the clock divider: the hsm_clock rate and this divider
 180          * setting will give a 40 kHz CEC clock.
 181          */
 182         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 183         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 184         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 185
 186         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 187 }
 188 #else
 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 190 #endif
 191
 192 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 193
 194 static enum drm_connector_status
 195 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 196 {
 197         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 198         bool connected = false;
 199
 200         mutex_lock(&vc4_hdmi->mutex);
 201
 202         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 203
 204         if (vc4_hdmi->hpd_gpio) {
 205                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 206                         connected = true;
 207         } else {
 208                 if (vc4_hdmi->variant->hp_detect &&
 209                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 210                         connected = true;
 211         }
 212
 213         if (connected) {
 214                 if (connector->status != connector_status_connected) {
 215                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 216
 217                         if (edid) {
 218                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 219                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 220                                 kfree(edid);
 221                         }
 222                 }
 223
 224                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 225                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 226                 mutex_unlock(&vc4_hdmi->mutex);
 227                 return connector_status_connected;
 228         }
 229
 230         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 231         pm_runtime_put(&vc4_hdmi->pdev->dev);
 232         mutex_unlock(&vc4_hdmi->mutex);
 233         return connector_status_disconnected;
 234 }
 235
 236 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 237 {
 238         drm_connector_unregister(connector);
 239         drm_connector_cleanup(connector);
 240 }
 241
 242 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 243 {
 244         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 245         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 246         int ret = 0;
 247         struct edid *edid;
 248
 249         mutex_lock(&vc4_hdmi->mutex);
 250
 251         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 252         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 253         if (!edid) {
 254                 ret = -ENODEV;
 255                 goto out;
 256         }
 257
 258         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 259
 260         drm_connector_update_edid_property(connector, edid);
 261         ret = drm_add_edid_modes(connector, edid);
 262         kfree(edid);
 263
 264         if (vc4_hdmi->disable_4kp60) {
 265                 struct drm_device *drm = connector->dev;
 266                 struct drm_display_mode *mode;
 267
 268                 list_for_each_entry(mode, &connector->probed_modes, head) {
 269                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 270                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 271                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 272                         }
 273                 }
 274         }
 275
 276 out:
 277         mutex_unlock(&vc4_hdmi->mutex);
 278
 279         return ret;
 280 }
 281
 282 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 283                                            struct drm_atomic_state *state)
 284 {
 285         struct drm_connector_state *old_state =
 286                 drm_atomic_get_old_connector_state(state, connector);
 287         struct drm_connector_state *new_state =
 288                 drm_atomic_get_new_connector_state(state, connector);
 289         struct drm_crtc *crtc = new_state->crtc;
 290
 291         if (!crtc)
 292                 return 0;
 293
 294         if (old_state->colorspace != new_state->colorspace ||
 295             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 296                 struct drm_crtc_state *crtc_state;
 297
 298                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 299                 if (IS_ERR(crtc_state))
 300                         return PTR_ERR(crtc_state);
 301
 302                 crtc_state->mode_changed = true;
 303         }
 304
 305         return 0;
 306 }
 307
 308 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 309 {
 310         struct vc4_hdmi_connector_state *old_state =
 311                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 312         struct vc4_hdmi_connector_state *new_state =
 313                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 314
 315         if (connector->state)
 316                 __drm_atomic_helper_connector_destroy_state(connector->state);
 317
 318         kfree(old_state);
 319         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 320
 321         if (!new_state)
 322                 return;
 323
 324         new_state->base.max_bpc = 8;
 325         new_state->base.max_requested_bpc = 8;
 326         drm_atomic_helper_connector_tv_reset(connector);
 327 }
 328
 329 static struct drm_connector_state *
 330 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 331 {
 332         struct drm_connector_state *conn_state = connector->state;
 333         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 334         struct vc4_hdmi_connector_state *new_state;
 335
 336         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 337         if (!new_state)
 338                 return NULL;
 339
 340         new_state->pixel_rate = vc4_state->pixel_rate;
 341         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 342
 343         return &new_state->base;
 344 }
 345
 346 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 347         .detect = vc4_hdmi_connector_detect,
 348         .fill_modes = drm_helper_probe_single_connector_modes,
 349         .destroy = vc4_hdmi_connector_destroy,
 350         .reset = vc4_hdmi_connector_reset,
 351         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 352         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 353 };
 354
 355 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 356         .get_modes = vc4_hdmi_connector_get_modes,
 357         .atomic_check = vc4_hdmi_connector_atomic_check,
 358 };
 359
 360 static int vc4_hdmi_connector_init(struct drm_device *dev,
 361                                    struct vc4_hdmi *vc4_hdmi)
 362 {
 363         struct drm_connector *connector = &vc4_hdmi->connector;
 364         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 365         int ret;
 366
 367         drm_connector_init_with_ddc(dev, connector,
 368                                     &vc4_hdmi_connector_funcs,
 369                                     DRM_MODE_CONNECTOR_HDMIA,
 370                                     vc4_hdmi->ddc);
 371         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 372
 373         /*
 374          * Some of the properties below require access to state, like bpc.
 375          * Allocate some default initial connector state with our reset helper.
 376          */
 377         if (connector->funcs->reset)
 378                 connector->funcs->reset(connector);
 379
 380         /* Create and attach TV margin props to this connector. */
 381         ret = drm_mode_create_tv_margin_properties(dev);
 382         if (ret)
 383                 return ret;
 384
 385         ret = drm_mode_create_hdmi_colorspace_property(connector);
 386         if (ret)
 387                 return ret;
 388
 389         drm_connector_attach_colorspace_property(connector);
 390         drm_connector_attach_tv_margin_properties(connector);
 391         drm_connector_attach_max_bpc_property(connector, 8, 12);
 392
 393         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 394                              DRM_CONNECTOR_POLL_DISCONNECT);
 395
 396         connector->interlace_allowed = 1;
 397         connector->doublescan_allowed = 0;
 398
 399         if (vc4_hdmi->variant->supports_hdr)
 400                 drm_connector_attach_hdr_output_metadata_property(connector);
 401
 402         drm_connector_attach_encoder(connector, encoder);
 403
 404         return 0;
 405 }
 406
 407 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 408                                 enum hdmi_infoframe_type type,
 409                                 bool poll)
 410 {
 411         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 412         u32 packet_id = type - 0x80;
 413         unsigned long flags;
 414
 415         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 416         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 417                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 418         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 419
 420         if (!poll)
 421                 return 0;
 422
 423         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 424                           BIT(packet_id)), 100);
 425 }
 426
 427 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 428                                      union hdmi_infoframe *frame)
 429 {
 430         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 431         u32 packet_id = frame->any.type - 0x80;
 432         const struct vc4_hdmi_register *ram_packet_start =
 433                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 434         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 435         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 436                                                        ram_packet_start->reg);
 437         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 438         unsigned long flags;
 439         ssize_t len, i;
 440         int ret;
 441
 442         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 443                     VC4_HDMI_RAM_PACKET_ENABLE),
 444                   "Packet RAM has to be on to store the packet.");
 445
 446         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 447         if (len < 0)
 448                 return;
 449
 450         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 451         if (ret) {
 452                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 453                 return;
 454         }
 455
 456         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 457
 458         for (i = 0; i < len; i += 7) {
 459                 writel(buffer[i + 0] << 0 |
 460                        buffer[i + 1] << 8 |
 461                        buffer[i + 2] << 16,
 462                        base + packet_reg);
 463                 packet_reg += 4;
 464
 465                 writel(buffer[i + 3] << 0 |
 466                        buffer[i + 4] << 8 |
 467                        buffer[i + 5] << 16 |
 468                        buffer[i + 6] << 24,
 469                        base + packet_reg);
 470                 packet_reg += 4;
 471         }
 472
 473         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 474                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 475
 476         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 477
 478         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 479                         BIT(packet_id)), 100);
 480         if (ret)
 481                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 482 }
 483
 484 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 485 {
 486         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 487         struct drm_connector *connector = &vc4_hdmi->connector;
 488         struct drm_connector_state *cstate = connector->state;
 489         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 490         union hdmi_infoframe frame;
 491         int ret;
 492
 493         lockdep_assert_held(&vc4_hdmi->mutex);
 494
 495         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 496                                                        connector, mode);
 497         if (ret < 0) {
 498                 DRM_ERROR("couldn't fill AVI infoframe\n");
 499                 return;
 500         }
 501
 502         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 503                                            connector, mode,
 504                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 505                                            HDMI_QUANTIZATION_RANGE_FULL :
 506                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 507         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 508         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 509
 510         vc4_hdmi_write_infoframe(encoder, &frame);
 511 }
 512
 513 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 514 {
 515         union hdmi_infoframe frame;
 516         int ret;
 517
 518         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 519         if (ret < 0) {
 520                 DRM_ERROR("couldn't fill SPD infoframe\n");
 521                 return;
 522         }
 523
 524         frame.spd.sdi = HDMI_SPD_SDI_PC;
 525
 526         vc4_hdmi_write_infoframe(encoder, &frame);
 527 }
 528
 529 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 530 {
 531         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 532         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 533         union hdmi_infoframe frame;
 534
 535         memcpy(&frame.audio, audio, sizeof(*audio));
 536         vc4_hdmi_write_infoframe(encoder, &frame);
 537 }
 538
 539 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 540 {
 541         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 542         struct drm_connector *connector = &vc4_hdmi->connector;
 543         struct drm_connector_state *conn_state = connector->state;
 544         union hdmi_infoframe frame;
 545
 546         lockdep_assert_held(&vc4_hdmi->mutex);
 547
 548         if (!vc4_hdmi->variant->supports_hdr)
 549                 return;
 550
 551         if (!conn_state->hdr_output_metadata)
 552                 return;
 553
 554         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 555                 return;
 556
 557         vc4_hdmi_write_infoframe(encoder, &frame);
 558 }
 559
 560 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 561 {
 562         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 563
 564         lockdep_assert_held(&vc4_hdmi->mutex);
 565
 566         vc4_hdmi_set_avi_infoframe(encoder);
 567         vc4_hdmi_set_spd_infoframe(encoder);
 568         /*
 569          * If audio was streaming, then we need to reenabled the audio
 570          * infoframe here during encoder_enable.
 571          */
 572         if (vc4_hdmi->audio.streaming)
 573                 vc4_hdmi_set_audio_infoframe(encoder);
 574
 575         vc4_hdmi_set_hdr_infoframe(encoder);
 576 }
 577
 578 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 579                                          struct drm_display_mode *mode)
 580 {
 581         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 582         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 583         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 584
 585         lockdep_assert_held(&vc4_hdmi->mutex);
 586
 587         if (!vc4_encoder->hdmi_monitor)
 588                 return false;
 589
 590         if (!display->hdmi.scdc.supported ||
 591             !display->hdmi.scdc.scrambling.supported)
 592                 return false;
 593
 594         return true;
 595 }
 596
 597 #define SCRAMBLING_POLLING_DELAY_MS     1000
 598
 599 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 600 {
 601         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 602         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 603         unsigned long flags;
 604
 605         lockdep_assert_held(&vc4_hdmi->mutex);
 606
 607         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 608                 return;
 609
 610         if (!vc4_hdmi_mode_needs_scrambling(mode))
 611                 return;
 612
 613         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 614         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 615
 616         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 617         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 618                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 619         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 620
 621         vc4_hdmi->scdc_enabled = true;
 622
 623         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 624                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 625 }
 626
 627 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 628 {
 629         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 630         unsigned long flags;
 631
 632         lockdep_assert_held(&vc4_hdmi->mutex);
 633
 634         if (!vc4_hdmi->scdc_enabled)
 635                 return;
 636
 637         vc4_hdmi->scdc_enabled = false;
 638
 639         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 640                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 641
 642         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 643         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 644                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 645         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 646
 647         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 648         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 649 }
 650
 651 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 652 {
 653         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 654                                                  struct vc4_hdmi,
 655                                                  scrambling_work);
 656
 657         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 658                 return;
 659
 660         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 661         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 662
 663         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 664                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 665 }
 666
 667 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 668                                                struct drm_atomic_state *state)
 669 {
 670         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 671         unsigned long flags;
 672
 673         mutex_lock(&vc4_hdmi->mutex);
 674
 675         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 676
 677         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 678
 679         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 680
 681         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 682
 683         mdelay(1);
 684
 685         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 686         HDMI_WRITE(HDMI_VID_CTL,
 687                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 688         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 689
 690         vc4_hdmi_disable_scrambling(encoder);
 691
 692         mutex_unlock(&vc4_hdmi->mutex);
 693 }
 694
 695 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 696                                                  struct drm_atomic_state *state)
 697 {
 698         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 699         unsigned long flags;
 700         int ret;
 701
 702         mutex_lock(&vc4_hdmi->mutex);
 703
 704         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 705         HDMI_WRITE(HDMI_VID_CTL,
 706                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 707         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 708
 709         if (vc4_hdmi->variant->phy_disable)
 710                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 711
 712         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 713         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 714
 715         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 716         if (ret < 0)
 717                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 718
 719         mutex_unlock(&vc4_hdmi->mutex);
 720 }
 721
 722 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 723 {
 724         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 725
 726         mutex_lock(&vc4_hdmi->mutex);
 727         vc4_hdmi->output_enabled = false;
 728         mutex_unlock(&vc4_hdmi->mutex);
 729 }
 730
 731 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 732                                struct drm_connector_state *state,
 733                                const struct drm_display_mode *mode)
 734 {
 735         unsigned long flags;
 736         u32 csc_ctl;
 737
 738         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 739
 740         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 741                                 VC4_HD_CSC_CTL_ORDER);
 742
 743         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 744                 /* CEA VICs other than #1 requre limited range RGB
 745                  * output unless overridden by an AVI infoframe.
 746                  * Apply a colorspace conversion to squash 0-255 down
 747                  * to 16-235.  The matrix here is:
 748                  *
 749                  * [ 0      0      0.8594 16]
 750                  * [ 0      0.8594 0      16]
 751                  * [ 0.8594 0      0      16]
 752                  * [ 0      0      0       1]
 753                  */
 754                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 755                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 756                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 757                                          VC4_HD_CSC_CTL_MODE);
 758
 759                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 760                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 761                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 762                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 763                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 764                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 765         }
 766
 767         /* The RGB order applies even when CSC is disabled. */
 768         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 769
 770         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 771 }
 772
 773 /*
 774  * If we need to output Full Range RGB, then use the unity matrix
 775  *
 776  * [ 1      0      0      0]
 777  * [ 0      1      0      0]
 778  * [ 0      0      1      0]
 779  *
 780  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 781  */
 782 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 783         { 0x2000, 0x0000, 0x0000, 0x0000 },
 784         { 0x0000, 0x2000, 0x0000, 0x0000 },
 785         { 0x0000, 0x0000, 0x2000, 0x0000 },
 786 };
 787
 788 /*
 789  * CEA VICs other than #1 require limited range RGB output unless
 790  * overridden by an AVI infoframe. Apply a colorspace conversion to
 791  * squash 0-255 down to 16-235. The matrix here is:
 792  *
 793  * [ 0.8594 0      0      16]
 794  * [ 0      0.8594 0      16]
 795  * [ 0      0      0.8594 16]
 796  *
 797  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 798  */
 799 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 800         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 801         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 802         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 803 };
 804
 805 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
 806                                     const u16 coeffs[3][4])
 807 {
 808         lockdep_assert_held(&vc4_hdmi->hw_lock);
 809
 810         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
 811         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
 812         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
 813         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
 814         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
 815         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
 816 }
 817
 818 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 819                                struct drm_connector_state *state,
 820                                const struct drm_display_mode *mode)
 821 {
 822         unsigned long flags;
 823         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 824                                                                VC5_MT_CP_CSC_CTL_MODE);
 825
 826         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 827
 828         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 829
 830         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
 831                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
 832         else
 833                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
 834
 835         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 836
 837         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 838 }
 839
 840 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 841                                  struct drm_connector_state *state,
 842                                  struct drm_display_mode *mode)
 843 {
 844         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 845         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 846         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 847         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 848         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 849                                    VC4_HDMI_VERTA_VSP) |
 850                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 851                                    VC4_HDMI_VERTA_VFP) |
 852                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 853         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 854                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 855                                    VC4_HDMI_VERTB_VBP));
 856         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 857                           VC4_SET_FIELD(mode->crtc_vtotal -
 858                                         mode->crtc_vsync_end -
 859                                         interlaced,
 860                                         VC4_HDMI_VERTB_VBP));
 861         unsigned long flags;
 862
 863         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 864
 865         HDMI_WRITE(HDMI_HORZA,
 866                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 867                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 868                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 869                                  VC4_HDMI_HORZA_HAP));
 870
 871         HDMI_WRITE(HDMI_HORZB,
 872                    VC4_SET_FIELD((mode->htotal -
 873                                   mode->hsync_end) * pixel_rep,
 874                                  VC4_HDMI_HORZB_HBP) |
 875                    VC4_SET_FIELD((mode->hsync_end -
 876                                   mode->hsync_start) * pixel_rep,
 877                                  VC4_HDMI_HORZB_HSP) |
 878                    VC4_SET_FIELD((mode->hsync_start -
 879                                   mode->hdisplay) * pixel_rep,
 880                                  VC4_HDMI_HORZB_HFP));
 881
 882         HDMI_WRITE(HDMI_VERTA0, verta);
 883         HDMI_WRITE(HDMI_VERTA1, verta);
 884
 885         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 886         HDMI_WRITE(HDMI_VERTB1, vertb);
 887
 888         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 889 }
 890
 891 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 892                                  struct drm_connector_state *state,
 893                                  struct drm_display_mode *mode)
 894 {
 895         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 896         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 897         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 898         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 899         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 900                                    VC5_HDMI_VERTA_VSP) |
 901                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 902                                    VC5_HDMI_VERTA_VFP) |
 903                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 904         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 905                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 906                                    VC4_HDMI_VERTB_VBP));
 907         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 908                           VC4_SET_FIELD(mode->crtc_vtotal -
 909                                         mode->crtc_vsync_end -
 910                                         interlaced,
 911                                         VC4_HDMI_VERTB_VBP));
 912         unsigned long flags;
 913         unsigned char gcp;
 914         bool gcp_en;
 915         u32 reg;
 916
 917         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 918
 919         HDMI_WRITE(HDMI_HORZA,
 920                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 921                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 922                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 923                                  VC5_HDMI_HORZA_HAP) |
 924                    VC4_SET_FIELD((mode->hsync_start -
 925                                   mode->hdisplay) * pixel_rep,
 926                                  VC5_HDMI_HORZA_HFP));
 927
 928         HDMI_WRITE(HDMI_HORZB,
 929                    VC4_SET_FIELD((mode->htotal -
 930                                   mode->hsync_end) * pixel_rep,
 931                                  VC5_HDMI_HORZB_HBP) |
 932                    VC4_SET_FIELD((mode->hsync_end -
 933                                   mode->hsync_start) * pixel_rep,
 934                                  VC5_HDMI_HORZB_HSP));
 935
 936         HDMI_WRITE(HDMI_VERTA0, verta);
 937         HDMI_WRITE(HDMI_VERTA1, verta);
 938
 939         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 940         HDMI_WRITE(HDMI_VERTB1, vertb);
 941
 942         switch (state->max_bpc) {
 943         case 12:
 944                 gcp = 6;
 945                 gcp_en = true;
 946                 break;
 947         case 10:
 948                 gcp = 5;
 949                 gcp_en = true;
 950                 break;
 951         case 8:
 952         default:
 953                 gcp = 4;
 954                 gcp_en = false;
 955                 break;
 956         }
 957
 958         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 959         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 960                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 961         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 962                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 963         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 964
 965         reg = HDMI_READ(HDMI_GCP_WORD_1);
 966         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 967         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 968         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 969
 970         reg = HDMI_READ(HDMI_GCP_CONFIG);
 971         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 972         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 973         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 974
 975         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 976
 977         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 978 }
 979
 980 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 981 {
 982         unsigned long flags;
 983         u32 drift;
 984         int ret;
 985
 986         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 987
 988         drift = HDMI_READ(HDMI_FIFO_CTL);
 989         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 990
 991         HDMI_WRITE(HDMI_FIFO_CTL,
 992                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 993         HDMI_WRITE(HDMI_FIFO_CTL,
 994                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 995
 996         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 997
 998         usleep_range(1000, 1100);
 999
1000         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1001
1002         HDMI_WRITE(HDMI_FIFO_CTL,
1003                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1004         HDMI_WRITE(HDMI_FIFO_CTL,
1005                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1006
1007         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1008
1009         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1010                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1011         WARN_ONCE(ret, "Timeout waiting for "
1012                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1013 }
1014
1015 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1016                                                 struct drm_atomic_state *state)
1017 {
1018         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1019         struct drm_connector *connector = &vc4_hdmi->connector;
1020         struct drm_connector_state *conn_state =
1021                 drm_atomic_get_new_connector_state(state, connector);
1022         struct vc4_hdmi_connector_state *vc4_conn_state =
1023                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1024         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1025         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1026         unsigned long bvb_rate, hsm_rate;
1027         unsigned long flags;
1028         int ret;
1029
1030         mutex_lock(&vc4_hdmi->mutex);
1031
1032         /*
1033          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1034          * be faster than pixel clock, infinitesimally faster, tested in
1035          * simulation. Otherwise, exact value is unimportant for HDMI
1036          * operation." This conflicts with bcm2835's vc4 documentation, which
1037          * states HSM's clock has to be at least 108% of the pixel clock.
1038          *
1039          * Real life tests reveal that vc4's firmware statement holds up, and
1040          * users are able to use pixel clocks closer to HSM's, namely for
1041          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1042          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1043          * 162MHz.
1044          *
1045          * Additionally, the AXI clock needs to be at least 25% of
1046          * pixel clock, but HSM ends up being the limiting factor.
1047          */
1048         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1049         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1050         if (ret) {
1051                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1052                 goto out;
1053         }
1054
1055         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1056         if (ret < 0) {
1057                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1058                 goto out;
1059         }
1060
1061         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1062         if (ret) {
1063                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1064                 goto err_put_runtime_pm;
1065         }
1066
1067         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1068         if (ret) {
1069                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1070                 goto err_put_runtime_pm;
1071         }
1072
1073
1074         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1075
1076         if (pixel_rate > 297000000)
1077                 bvb_rate = 300000000;
1078         else if (pixel_rate > 148500000)
1079                 bvb_rate = 150000000;
1080         else
1081                 bvb_rate = 75000000;
1082
1083         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1084         if (ret) {
1085                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1086                 goto err_disable_pixel_clock;
1087         }
1088
1089         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1090         if (ret) {
1091                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1092                 goto err_disable_pixel_clock;
1093         }
1094
1095         if (vc4_hdmi->variant->phy_init)
1096                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1097
1098         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1099
1100         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1101                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1102                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1103                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1104
1105         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1106
1107         if (vc4_hdmi->variant->set_timings)
1108                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1109
1110         mutex_unlock(&vc4_hdmi->mutex);
1111
1112         return;
1113
1114 err_disable_pixel_clock:
1115         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1116 err_put_runtime_pm:
1117         pm_runtime_put(&vc4_hdmi->pdev->dev);
1118 out:
1119         mutex_unlock(&vc4_hdmi->mutex);
1120         return;
1121 }
1122
1123 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1124                                              struct drm_atomic_state *state)
1125 {
1126         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1127         struct drm_connector *connector = &vc4_hdmi->connector;
1128         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1129         struct drm_connector_state *conn_state =
1130                 drm_atomic_get_new_connector_state(state, connector);
1131         unsigned long flags;
1132
1133         mutex_lock(&vc4_hdmi->mutex);
1134
1135         if (vc4_hdmi->variant->csc_setup)
1136                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1137
1138         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1139         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1140         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1141
1142         mutex_unlock(&vc4_hdmi->mutex);
1143 }
1144
1145 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1146                                               struct drm_atomic_state *state)
1147 {
1148         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1149         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1150         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1151         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1152         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1153         unsigned long flags;
1154         int ret;
1155
1156         mutex_lock(&vc4_hdmi->mutex);
1157
1158         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1159
1160         HDMI_WRITE(HDMI_VID_CTL,
1161                    VC4_HD_VID_CTL_ENABLE |
1162                    VC4_HD_VID_CTL_CLRRGB |
1163                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1164                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1165                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1166                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1167
1168         HDMI_WRITE(HDMI_VID_CTL,
1169                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1170
1171         if (vc4_encoder->hdmi_monitor) {
1172                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1173                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1174                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1175
1176                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1177
1178                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1179                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1180                 WARN_ONCE(ret, "Timeout waiting for "
1181                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1182         } else {
1183                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1184                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1185                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1186                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1187                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1188                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1189
1190                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1191
1192                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1193                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1194                 WARN_ONCE(ret, "Timeout waiting for "
1195                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1196         }
1197
1198         if (vc4_encoder->hdmi_monitor) {
1199                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1200
1201                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1202                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1203                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1204                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1205                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1206
1207                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1208                            VC4_HDMI_RAM_PACKET_ENABLE);
1209
1210                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1211
1212                 vc4_hdmi_set_infoframes(encoder);
1213         }
1214
1215         vc4_hdmi_recenter_fifo(vc4_hdmi);
1216         vc4_hdmi_enable_scrambling(encoder);
1217
1218         mutex_unlock(&vc4_hdmi->mutex);
1219 }
1220
1221 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1222 {
1223         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1224
1225         mutex_lock(&vc4_hdmi->mutex);
1226         vc4_hdmi->output_enabled = true;
1227         mutex_unlock(&vc4_hdmi->mutex);
1228 }
1229
1230 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1231                                              struct drm_crtc_state *crtc_state,
1232                                              struct drm_connector_state *conn_state)
1233 {
1234         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1235
1236         mutex_lock(&vc4_hdmi->mutex);
1237         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1238                       &crtc_state->adjusted_mode);
1239         mutex_unlock(&vc4_hdmi->mutex);
1240 }
1241
1242 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1243 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1244
1245 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1246                                          struct drm_crtc_state *crtc_state,
1247                                          struct drm_connector_state *conn_state)
1248 {
1249         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1250         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1251         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1252         unsigned long long pixel_rate = mode->clock * 1000;
1253         unsigned long long tmds_rate;
1254
1255         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1256             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1257             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1258              (mode->hsync_end % 2) || (mode->htotal % 2)))
1259                 return -EINVAL;
1260
1261         /*
1262          * The 1440p@60 pixel rate is in the same range than the first
1263          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1264          * bandwidth). Slightly lower the frequency to bring it out of
1265          * the WiFi range.
1266          */
1267         tmds_rate = pixel_rate * 10;
1268         if (vc4_hdmi->disable_wifi_frequencies &&
1269             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1270              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1271                 mode->clock = 238560;
1272                 pixel_rate = mode->clock * 1000;
1273         }
1274
1275         if (conn_state->max_bpc == 12) {
1276                 pixel_rate = pixel_rate * 150;
1277                 do_div(pixel_rate, 100);
1278         } else if (conn_state->max_bpc == 10) {
1279                 pixel_rate = pixel_rate * 125;
1280                 do_div(pixel_rate, 100);
1281         }
1282
1283         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1284                 pixel_rate = pixel_rate * 2;
1285
1286         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1287                 return -EINVAL;
1288
1289         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1290                 return -EINVAL;
1291
1292         vc4_state->pixel_rate = pixel_rate;
1293
1294         return 0;
1295 }
1296
1297 static enum drm_mode_status
1298 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1299                             const struct drm_display_mode *mode)
1300 {
1301         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1302
1303         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1304             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1305             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1306              (mode->hsync_end % 2) || (mode->htotal % 2)))
1307                 return MODE_H_ILLEGAL;
1308
1309         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1310                 return MODE_CLOCK_HIGH;
1311
1312         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1313                 return MODE_CLOCK_HIGH;
1314
1315         return MODE_OK;
1316 }
1317
1318 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1319         .atomic_check = vc4_hdmi_encoder_atomic_check,
1320         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1321         .mode_valid = vc4_hdmi_encoder_mode_valid,
1322         .disable = vc4_hdmi_encoder_disable,
1323         .enable = vc4_hdmi_encoder_enable,
1324 };
1325
1326 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1327 {
1328         int i;
1329         u32 channel_map = 0;
1330
1331         for (i = 0; i < 8; i++) {
1332                 if (channel_mask & BIT(i))
1333                         channel_map |= i << (3 * i);
1334         }
1335         return channel_map;
1336 }
1337
1338 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1339 {
1340         int i;
1341         u32 channel_map = 0;
1342
1343         for (i = 0; i < 8; i++) {
1344                 if (channel_mask & BIT(i))
1345                         channel_map |= i << (4 * i);
1346         }
1347         return channel_map;
1348 }
1349
1350 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1351 {
1352         unsigned long flags;
1353         u32 hotplug;
1354
1355         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1356         hotplug = HDMI_READ(HDMI_HOTPLUG);
1357         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1358
1359         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1360 }
1361
1362 /* HDMI audio codec callbacks */
1363 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1364                                          unsigned int samplerate)
1365 {
1366         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1367         unsigned long flags;
1368         unsigned long n, m;
1369
1370         rational_best_approximation(hsm_clock, samplerate,
1371                                     VC4_HD_MAI_SMP_N_MASK >>
1372                                     VC4_HD_MAI_SMP_N_SHIFT,
1373                                     (VC4_HD_MAI_SMP_M_MASK >>
1374                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1375                                     &n, &m);
1376
1377         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1378         HDMI_WRITE(HDMI_MAI_SMP,
1379                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1380                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1381         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382 }
1383
1384 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1385 {
1386         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1387         u32 n, cts;
1388         u64 tmp;
1389
1390         lockdep_assert_held(&vc4_hdmi->mutex);
1391         lockdep_assert_held(&vc4_hdmi->hw_lock);
1392
1393         n = 128 * samplerate / 1000;
1394         tmp = (u64)(mode->clock * 1000) * n;
1395         do_div(tmp, 128 * samplerate);
1396         cts = tmp;
1397
1398         HDMI_WRITE(HDMI_CRP_CFG,
1399                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1400                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1401
1402         /*
1403          * We could get slightly more accurate clocks in some cases by
1404          * providing a CTS_1 value.  The two CTS values are alternated
1405          * between based on the period fields
1406          */
1407         HDMI_WRITE(HDMI_CTS_0, cts);
1408         HDMI_WRITE(HDMI_CTS_1, cts);
1409 }
1410
1411 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1412 {
1413         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1414
1415         return snd_soc_card_get_drvdata(card);
1416 }
1417
1418 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1419 {
1420         lockdep_assert_held(&vc4_hdmi->mutex);
1421
1422         /*
1423          * If the controller is disabled, prevent any ALSA output.
1424          */
1425         if (!vc4_hdmi->output_enabled)
1426                 return false;
1427
1428         /*
1429          * If the encoder is currently in DVI mode, treat the codec DAI
1430          * as missing.
1431          */
1432         if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE))
1433                 return false;
1434
1435         return true;
1436 }
1437
1438 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1439 {
1440         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1441         unsigned long flags;
1442
1443         mutex_lock(&vc4_hdmi->mutex);
1444
1445         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1446                 mutex_unlock(&vc4_hdmi->mutex);
1447                 return -ENODEV;
1448         }
1449
1450         vc4_hdmi->audio.streaming = true;
1451
1452         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1453         HDMI_WRITE(HDMI_MAI_CTL,
1454                    VC4_HD_MAI_CTL_RESET |
1455                    VC4_HD_MAI_CTL_FLUSH |
1456                    VC4_HD_MAI_CTL_DLATE |
1457                    VC4_HD_MAI_CTL_ERRORE |
1458                    VC4_HD_MAI_CTL_ERRORF);
1459         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1460
1461         if (vc4_hdmi->variant->phy_rng_enable)
1462                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1463
1464         mutex_unlock(&vc4_hdmi->mutex);
1465
1466         return 0;
1467 }
1468
1469 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1470 {
1471         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1472         struct device *dev = &vc4_hdmi->pdev->dev;
1473         unsigned long flags;
1474         int ret;
1475
1476         lockdep_assert_held(&vc4_hdmi->mutex);
1477
1478         vc4_hdmi->audio.streaming = false;
1479         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1480         if (ret)
1481                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1482
1483         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1484
1485         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1486         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1487         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1488
1489         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1490 }
1491
1492 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1493 {
1494         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1495         unsigned long flags;
1496
1497         mutex_lock(&vc4_hdmi->mutex);
1498
1499         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1500
1501         HDMI_WRITE(HDMI_MAI_CTL,
1502                    VC4_HD_MAI_CTL_DLATE |
1503                    VC4_HD_MAI_CTL_ERRORE |
1504                    VC4_HD_MAI_CTL_ERRORF);
1505
1506         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1507
1508         if (vc4_hdmi->variant->phy_rng_disable)
1509                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1510
1511         vc4_hdmi->audio.streaming = false;
1512         vc4_hdmi_audio_reset(vc4_hdmi);
1513
1514         mutex_unlock(&vc4_hdmi->mutex);
1515 }
1516
1517 static int sample_rate_to_mai_fmt(int samplerate)
1518 {
1519         switch (samplerate) {
1520         case 8000:
1521                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1522         case 11025:
1523                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1524         case 12000:
1525                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1526         case 16000:
1527                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1528         case 22050:
1529                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1530         case 24000:
1531                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1532         case 32000:
1533                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1534         case 44100:
1535                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1536         case 48000:
1537                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1538         case 64000:
1539                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1540         case 88200:
1541                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1542         case 96000:
1543                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1544         case 128000:
1545                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1546         case 176400:
1547                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1548         case 192000:
1549                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1550         default:
1551                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1552         }
1553 }
1554
1555 /* HDMI audio codec callbacks */
1556 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1557                                   struct hdmi_codec_daifmt *daifmt,
1558                                   struct hdmi_codec_params *params)
1559 {
1560         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1561         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1562         unsigned int sample_rate = params->sample_rate;
1563         unsigned int channels = params->channels;
1564         unsigned long flags;
1565         u32 audio_packet_config, channel_mask;
1566         u32 channel_map;
1567         u32 mai_audio_format;
1568         u32 mai_sample_rate;
1569
1570         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1571                 sample_rate, params->sample_width, channels);
1572
1573         mutex_lock(&vc4_hdmi->mutex);
1574
1575         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1576                 mutex_unlock(&vc4_hdmi->mutex);
1577                 return -EINVAL;
1578         }
1579
1580         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1581
1582         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1583         HDMI_WRITE(HDMI_MAI_CTL,
1584                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1585                    VC4_HD_MAI_CTL_WHOLSMP |
1586                    VC4_HD_MAI_CTL_CHALIGN |
1587                    VC4_HD_MAI_CTL_ENABLE);
1588
1589         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1590         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1591             params->channels == 8)
1592                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1593         else
1594                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1595         HDMI_WRITE(HDMI_MAI_FMT,
1596                    VC4_SET_FIELD(mai_sample_rate,
1597                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1598                    VC4_SET_FIELD(mai_audio_format,
1599                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1600
1601         /* The B frame identifier should match the value used by alsa-lib (8) */
1602         audio_packet_config =
1603                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1604                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1605                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1606
1607         channel_mask = GENMASK(channels - 1, 0);
1608         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1609                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1610
1611         /* Set the MAI threshold */
1612         HDMI_WRITE(HDMI_MAI_THR,
1613                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1614                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1615                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1616                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1617
1618         HDMI_WRITE(HDMI_MAI_CONFIG,
1619                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1620                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1621                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1622
1623         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1624         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1625         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1626
1627         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1628
1629         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1630
1631         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1632         vc4_hdmi_set_audio_infoframe(encoder);
1633
1634         mutex_unlock(&vc4_hdmi->mutex);
1635
1636         return 0;
1637 }
1638
1639 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1640         .name = "vc4-hdmi-cpu-dai-component",
1641 };
1642
1643 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1644 {
1645         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1646
1647         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1648
1649         return 0;
1650 }
1651
1652 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1653         .name = "vc4-hdmi-cpu-dai",
1654         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1655         .playback = {
1656                 .stream_name = "Playback",
1657                 .channels_min = 1,
1658                 .channels_max = 8,
1659                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1660                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1661                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1662                          SNDRV_PCM_RATE_192000,
1663                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1664         },
1665 };
1666
1667 static const struct snd_dmaengine_pcm_config pcm_conf = {
1668         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1669         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1670 };
1671
1672 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1673                                   uint8_t *buf, size_t len)
1674 {
1675         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1676         struct drm_connector *connector = &vc4_hdmi->connector;
1677
1678         mutex_lock(&vc4_hdmi->mutex);
1679         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1680         mutex_unlock(&vc4_hdmi->mutex);
1681
1682         return 0;
1683 }
1684
1685 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1686         .get_eld = vc4_hdmi_audio_get_eld,
1687         .prepare = vc4_hdmi_audio_prepare,
1688         .audio_shutdown = vc4_hdmi_audio_shutdown,
1689         .audio_startup = vc4_hdmi_audio_startup,
1690 };
1691
1692 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1693         .ops = &vc4_hdmi_codec_ops,
1694         .max_i2s_channels = 8,
1695         .i2s = 1,
1696 };
1697
1698 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1699 {
1700         const struct vc4_hdmi_register *mai_data =
1701                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1702         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1703         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1704         struct device *dev = &vc4_hdmi->pdev->dev;
1705         struct platform_device *codec_pdev;
1706         const __be32 *addr;
1707         int index;
1708         int ret;
1709
1710         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1711                 dev_warn(dev,
1712                          "'dmas' DT property is missing, no HDMI audio\n");
1713                 return 0;
1714         }
1715
1716         if (mai_data->reg != VC4_HD) {
1717                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1718                 return -EINVAL;
1719         }
1720
1721         /*
1722          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1723          * the bus address specified in the DT, because the physical address
1724          * (the one returned by platform_get_resource()) is not appropriate
1725          * for DMA transfers.
1726          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1727          */
1728         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1729         /* Before BCM2711, we don't have a named register range */
1730         if (index < 0)
1731                 index = 1;
1732
1733         addr = of_get_address(dev->of_node, index, NULL, NULL);
1734
1735         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1736         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1737         vc4_hdmi->audio.dma_data.maxburst = 2;
1738
1739         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1740         if (ret) {
1741                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1742                 return ret;
1743         }
1744
1745         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1746                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1747         if (ret) {
1748                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1749                 return ret;
1750         }
1751
1752         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1753                                                    PLATFORM_DEVID_AUTO,
1754                                                    &vc4_hdmi_codec_pdata,
1755                                                    sizeof(vc4_hdmi_codec_pdata));
1756         if (IS_ERR(codec_pdev)) {
1757                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1758                 return PTR_ERR(codec_pdev);
1759         }
1760         vc4_hdmi->audio.codec_pdev = codec_pdev;
1761
1762         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1763         dai_link->codecs        = &vc4_hdmi->audio.codec;
1764         dai_link->platforms     = &vc4_hdmi->audio.platform;
1765
1766         dai_link->num_cpus      = 1;
1767         dai_link->num_codecs    = 1;
1768         dai_link->num_platforms = 1;
1769
1770         dai_link->name = "MAI";
1771         dai_link->stream_name = "MAI PCM";
1772         dai_link->codecs->dai_name = "i2s-hifi";
1773         dai_link->cpus->dai_name = dev_name(dev);
1774         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1775         dai_link->platforms->name = dev_name(dev);
1776
1777         card->dai_link = dai_link;
1778         card->num_links = 1;
1779         card->name = vc4_hdmi->variant->card_name;
1780         card->driver_name = "vc4-hdmi";
1781         card->dev = dev;
1782         card->owner = THIS_MODULE;
1783
1784         /*
1785          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1786          * stores a pointer to the snd card object in dev->driver_data. This
1787          * means we cannot use it for something else. The hdmi back-pointer is
1788          * now stored in card->drvdata and should be retrieved with
1789          * snd_soc_card_get_drvdata() if needed.
1790          */
1791         snd_soc_card_set_drvdata(card, vc4_hdmi);
1792         ret = devm_snd_soc_register_card(dev, card);
1793         if (ret)
1794                 dev_err_probe(dev, ret, "Could not register sound card\n");
1795
1796         return ret;
1797
1798 }
1799
1800 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1801 {
1802         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1803         vc4_hdmi->audio.codec_pdev = NULL;
1804 }
1805
1806 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1807 {
1808         struct vc4_hdmi *vc4_hdmi = priv;
1809         struct drm_connector *connector = &vc4_hdmi->connector;
1810         struct drm_device *dev = connector->dev;
1811
1812         if (dev && dev->registered)
1813                 drm_connector_helper_hpd_irq_event(connector);
1814
1815         return IRQ_HANDLED;
1816 }
1817
1818 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1819 {
1820         struct drm_connector *connector = &vc4_hdmi->connector;
1821         struct platform_device *pdev = vc4_hdmi->pdev;
1822         int ret;
1823
1824         if (vc4_hdmi->variant->external_irq_controller) {
1825                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1826                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1827
1828                 ret = request_threaded_irq(hpd_con,
1829                                            NULL,
1830                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1831                                            "vc4 hdmi hpd connected", vc4_hdmi);
1832                 if (ret)
1833                         return ret;
1834
1835                 ret = request_threaded_irq(hpd_rm,
1836                                            NULL,
1837                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1838                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1839                 if (ret) {
1840                         free_irq(hpd_con, vc4_hdmi);
1841                         return ret;
1842                 }
1843
1844                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1845         }
1846
1847         return 0;
1848 }
1849
1850 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1851 {
1852         struct platform_device *pdev = vc4_hdmi->pdev;
1853
1854         if (vc4_hdmi->variant->external_irq_controller) {
1855                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1856                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1857         }
1858 }
1859
1860 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1861 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1862 {
1863         struct vc4_hdmi *vc4_hdmi = priv;
1864
1865         if (vc4_hdmi->cec_rx_msg.len)
1866                 cec_received_msg(vc4_hdmi->cec_adap,
1867                                  &vc4_hdmi->cec_rx_msg);
1868
1869         return IRQ_HANDLED;
1870 }
1871
1872 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1873 {
1874         struct vc4_hdmi *vc4_hdmi = priv;
1875
1876         if (vc4_hdmi->cec_tx_ok) {
1877                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1878                                   0, 0, 0, 0);
1879         } else {
1880                 /*
1881                  * This CEC implementation makes 1 retry, so if we
1882                  * get a NACK, then that means it made 2 attempts.
1883                  */
1884                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1885                                   0, 2, 0, 0);
1886         }
1887         return IRQ_HANDLED;
1888 }
1889
1890 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1891 {
1892         struct vc4_hdmi *vc4_hdmi = priv;
1893         irqreturn_t ret;
1894
1895         if (vc4_hdmi->cec_irq_was_rx)
1896                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1897         else
1898                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1899
1900         return ret;
1901 }
1902
1903 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1904 {
1905         struct drm_device *dev = vc4_hdmi->connector.dev;
1906         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1907         unsigned int i;
1908
1909         lockdep_assert_held(&vc4_hdmi->hw_lock);
1910
1911         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1912                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1913
1914         if (msg->len > 16) {
1915                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1916                 return;
1917         }
1918
1919         for (i = 0; i < msg->len; i += 4) {
1920                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1921
1922                 msg->msg[i] = val & 0xff;
1923                 msg->msg[i + 1] = (val >> 8) & 0xff;
1924                 msg->msg[i + 2] = (val >> 16) & 0xff;
1925                 msg->msg[i + 3] = (val >> 24) & 0xff;
1926         }
1927 }
1928
1929 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1930 {
1931         u32 cntrl1;
1932
1933         lockdep_assert_held(&vc4_hdmi->hw_lock);
1934
1935         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1936         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1937         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1938         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1939
1940         return IRQ_WAKE_THREAD;
1941 }
1942
1943 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1944 {
1945         struct vc4_hdmi *vc4_hdmi = priv;
1946         irqreturn_t ret;
1947
1948         spin_lock(&vc4_hdmi->hw_lock);
1949         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1950         spin_unlock(&vc4_hdmi->hw_lock);
1951
1952         return ret;
1953 }
1954
1955 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1956 {
1957         u32 cntrl1;
1958
1959         lockdep_assert_held(&vc4_hdmi->hw_lock);
1960
1961         vc4_hdmi->cec_rx_msg.len = 0;
1962         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1963         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1964         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1965         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1966         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1967
1968         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1969
1970         return IRQ_WAKE_THREAD;
1971 }
1972
1973 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1974 {
1975         struct vc4_hdmi *vc4_hdmi = priv;
1976         irqreturn_t ret;
1977
1978         spin_lock(&vc4_hdmi->hw_lock);
1979         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1980         spin_unlock(&vc4_hdmi->hw_lock);
1981
1982         return ret;
1983 }
1984
1985 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1986 {
1987         struct vc4_hdmi *vc4_hdmi = priv;
1988         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1989         irqreturn_t ret;
1990         u32 cntrl5;
1991
1992         if (!(stat & VC4_HDMI_CPU_CEC))
1993                 return IRQ_NONE;
1994
1995         spin_lock(&vc4_hdmi->hw_lock);
1996         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1997         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1998         if (vc4_hdmi->cec_irq_was_rx)
1999                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2000         else
2001                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2002
2003         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2004         spin_unlock(&vc4_hdmi->hw_lock);
2005
2006         return ret;
2007 }
2008
2009 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2010 {
2011         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2012         /* clock period in microseconds */
2013         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2014         unsigned long flags;
2015         u32 val;
2016         int ret;
2017
2018         /*
2019          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2020          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2021          * .detect or .get_modes might call .adap_enable, which leads to this
2022          * function being called with that mutex held.
2023          *
2024          * Concurrency is not an issue for the moment since we don't share any
2025          * state with KMS, so we can ignore the lock for now, but we need to
2026          * keep it in mind if we were to change that assumption.
2027          */
2028
2029         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2030         if (ret)
2031                 return ret;
2032
2033         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2034
2035         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2036         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2037                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2038                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2039         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2040                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2041
2042         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2043                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2044         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2045         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2046                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2047                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2048                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2049                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2050                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2051         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2052                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2053                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2054                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2055                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2056         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2057                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2058                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2059                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2060                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2061
2062         if (!vc4_hdmi->variant->external_irq_controller)
2063                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2064
2065         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2066
2067         return 0;
2068 }
2069
2070 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2071 {
2072         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2073         unsigned long flags;
2074
2075         /*
2076          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2077          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2078          * .detect or .get_modes might call .adap_enable, which leads to this
2079          * function being called with that mutex held.
2080          *
2081          * Concurrency is not an issue for the moment since we don't share any
2082          * state with KMS, so we can ignore the lock for now, but we need to
2083          * keep it in mind if we were to change that assumption.
2084          */
2085
2086         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2087
2088         if (!vc4_hdmi->variant->external_irq_controller)
2089                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2090
2091         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2092                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2093
2094         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2095
2096         pm_runtime_put(&vc4_hdmi->pdev->dev);
2097
2098         return 0;
2099 }
2100
2101 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2102 {
2103         if (enable)
2104                 return vc4_hdmi_cec_enable(adap);
2105         else
2106                 return vc4_hdmi_cec_disable(adap);
2107 }
2108
2109 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2110 {
2111         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2112         unsigned long flags;
2113
2114         /*
2115          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2116          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2117          * .detect or .get_modes might call .adap_enable, which leads to this
2118          * function being called with that mutex held.
2119          *
2120          * Concurrency is not an issue for the moment since we don't share any
2121          * state with KMS, so we can ignore the lock for now, but we need to
2122          * keep it in mind if we were to change that assumption.
2123          */
2124
2125         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2126         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2127                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2128                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2129         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2130
2131         return 0;
2132 }
2133
2134 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2135                                       u32 signal_free_time, struct cec_msg *msg)
2136 {
2137         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2138         struct drm_device *dev = vc4_hdmi->connector.dev;
2139         unsigned long flags;
2140         u32 val;
2141         unsigned int i;
2142
2143         /*
2144          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2145          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2146          * .detect or .get_modes might call .adap_enable, which leads to this
2147          * function being called with that mutex held.
2148          *
2149          * Concurrency is not an issue for the moment since we don't share any
2150          * state with KMS, so we can ignore the lock for now, but we need to
2151          * keep it in mind if we were to change that assumption.
2152          */
2153
2154         if (msg->len > 16) {
2155                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2156                 return -ENOMEM;
2157         }
2158
2159         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2160
2161         for (i = 0; i < msg->len; i += 4)
2162                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2163                            (msg->msg[i]) |
2164                            (msg->msg[i + 1] << 8) |
2165                            (msg->msg[i + 2] << 16) |
2166                            (msg->msg[i + 3] << 24));
2167
2168         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2169         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2170         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2171         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2172         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2173         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2174
2175         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2176
2177         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2178
2179         return 0;
2180 }
2181
2182 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2183         .adap_enable = vc4_hdmi_cec_adap_enable,
2184         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2185         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2186 };
2187
2188 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2189 {
2190         struct cec_connector_info conn_info;
2191         struct platform_device *pdev = vc4_hdmi->pdev;
2192         struct device *dev = &pdev->dev;
2193         unsigned long flags;
2194         u32 value;
2195         int ret;
2196
2197         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2198                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2199                 return 0;
2200         }
2201
2202         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2203                                                   vc4_hdmi, "vc4",
2204                                                   CEC_CAP_DEFAULTS |
2205                                                   CEC_CAP_CONNECTOR_INFO, 1);
2206         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2207         if (ret < 0)
2208                 return ret;
2209
2210         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2211         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2212
2213         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2214         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2215         /* Set the logical address to Unregistered */
2216         value |= VC4_HDMI_CEC_ADDR_MASK;
2217         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2218         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2219
2220         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2221
2222         if (vc4_hdmi->variant->external_irq_controller) {
2223                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2224                                            vc4_cec_irq_handler_rx_bare,
2225                                            vc4_cec_irq_handler_rx_thread, 0,
2226                                            "vc4 hdmi cec rx", vc4_hdmi);
2227                 if (ret)
2228                         goto err_delete_cec_adap;
2229
2230                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2231                                            vc4_cec_irq_handler_tx_bare,
2232                                            vc4_cec_irq_handler_tx_thread, 0,
2233                                            "vc4 hdmi cec tx", vc4_hdmi);
2234                 if (ret)
2235                         goto err_remove_cec_rx_handler;
2236         } else {
2237                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2238                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2239                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2240
2241                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2242                                            vc4_cec_irq_handler,
2243                                            vc4_cec_irq_handler_thread, 0,
2244                                            "vc4 hdmi cec", vc4_hdmi);
2245                 if (ret)
2246                         goto err_delete_cec_adap;
2247         }
2248
2249         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2250         if (ret < 0)
2251                 goto err_remove_handlers;
2252
2253         return 0;
2254
2255 err_remove_handlers:
2256         if (vc4_hdmi->variant->external_irq_controller)
2257                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2258         else
2259                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2260
2261 err_remove_cec_rx_handler:
2262         if (vc4_hdmi->variant->external_irq_controller)
2263                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2264
2265 err_delete_cec_adap:
2266         cec_delete_adapter(vc4_hdmi->cec_adap);
2267
2268         return ret;
2269 }
2270
2271 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2272 {
2273         struct platform_device *pdev = vc4_hdmi->pdev;
2274
2275         if (vc4_hdmi->variant->external_irq_controller) {
2276                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2277                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2278         } else {
2279                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2280         }
2281
2282         cec_unregister_adapter(vc4_hdmi->cec_adap);
2283 }
2284 #else
2285 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2286 {
2287         return 0;
2288 }
2289
2290 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2291
2292 #endif
2293
2294 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2295                                  struct debugfs_regset32 *regset,
2296                                  enum vc4_hdmi_regs reg)
2297 {
2298         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2299         struct debugfs_reg32 *regs, *new_regs;
2300         unsigned int count = 0;
2301         unsigned int i;
2302
2303         regs = kcalloc(variant->num_registers, sizeof(*regs),
2304                        GFP_KERNEL);
2305         if (!regs)
2306                 return -ENOMEM;
2307
2308         for (i = 0; i < variant->num_registers; i++) {
2309                 const struct vc4_hdmi_register *field = &variant->registers[i];
2310
2311                 if (field->reg != reg)
2312                         continue;
2313
2314                 regs[count].name = field->name;
2315                 regs[count].offset = field->offset;
2316                 count++;
2317         }
2318
2319         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2320         if (!new_regs)
2321                 return -ENOMEM;
2322
2323         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2324         regset->regs = new_regs;
2325         regset->nregs = count;
2326
2327         return 0;
2328 }
2329
2330 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2331 {
2332         struct platform_device *pdev = vc4_hdmi->pdev;
2333         struct device *dev = &pdev->dev;
2334         int ret;
2335
2336         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2337         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2338                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2339
2340         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2341         if (IS_ERR(vc4_hdmi->hd_regs))
2342                 return PTR_ERR(vc4_hdmi->hd_regs);
2343
2344         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2345         if (ret)
2346                 return ret;
2347
2348         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2349         if (ret)
2350                 return ret;
2351
2352         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2353         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2354                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2355                 if (ret != -EPROBE_DEFER)
2356                         DRM_ERROR("Failed to get pixel clock\n");
2357                 return ret;
2358         }
2359
2360         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2361         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2362                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2363                 return PTR_ERR(vc4_hdmi->hsm_clock);
2364         }
2365         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2366         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2367
2368         return 0;
2369 }
2370
2371 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2372 {
2373         struct platform_device *pdev = vc4_hdmi->pdev;
2374         struct device *dev = &pdev->dev;
2375         struct resource *res;
2376
2377         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2378         if (!res)
2379                 return -ENODEV;
2380
2381         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2382                                                resource_size(res));
2383         if (!vc4_hdmi->hdmicore_regs)
2384                 return -ENOMEM;
2385
2386         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2387         if (!res)
2388                 return -ENODEV;
2389
2390         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2391         if (!vc4_hdmi->hd_regs)
2392                 return -ENOMEM;
2393
2394         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2395         if (!res)
2396                 return -ENODEV;
2397
2398         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2399         if (!vc4_hdmi->cec_regs)
2400                 return -ENOMEM;
2401
2402         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2403         if (!res)
2404                 return -ENODEV;
2405
2406         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2407         if (!vc4_hdmi->csc_regs)
2408                 return -ENOMEM;
2409
2410         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2411         if (!res)
2412                 return -ENODEV;
2413
2414         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2415         if (!vc4_hdmi->dvp_regs)
2416                 return -ENOMEM;
2417
2418         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2419         if (!res)
2420                 return -ENODEV;
2421
2422         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2423         if (!vc4_hdmi->phy_regs)
2424                 return -ENOMEM;
2425
2426         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2427         if (!res)
2428                 return -ENODEV;
2429
2430         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2431         if (!vc4_hdmi->ram_regs)
2432                 return -ENOMEM;
2433
2434         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2435         if (!res)
2436                 return -ENODEV;
2437
2438         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2439         if (!vc4_hdmi->rm_regs)
2440                 return -ENOMEM;
2441
2442         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2443         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2444                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2445                 return PTR_ERR(vc4_hdmi->hsm_clock);
2446         }
2447
2448         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2449         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2450                 DRM_ERROR("Failed to get pixel bvb clock\n");
2451                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2452         }
2453
2454         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2455         if (IS_ERR(vc4_hdmi->audio_clock)) {
2456                 DRM_ERROR("Failed to get audio clock\n");
2457                 return PTR_ERR(vc4_hdmi->audio_clock);
2458         }
2459
2460         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2461         if (IS_ERR(vc4_hdmi->cec_clock)) {
2462                 DRM_ERROR("Failed to get CEC clock\n");
2463                 return PTR_ERR(vc4_hdmi->cec_clock);
2464         }
2465
2466         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2467         if (IS_ERR(vc4_hdmi->reset)) {
2468                 DRM_ERROR("Failed to get HDMI reset line\n");
2469                 return PTR_ERR(vc4_hdmi->reset);
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2476 {
2477         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2478
2479         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2480
2481         return 0;
2482 }
2483
2484 static int vc4_hdmi_runtime_resume(struct device *dev)
2485 {
2486         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2487         int ret;
2488
2489         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2490         if (ret)
2491                 return ret;
2492
2493         return 0;
2494 }
2495
2496 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2497 {
2498         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2499         struct platform_device *pdev = to_platform_device(dev);
2500         struct drm_device *drm = dev_get_drvdata(master);
2501         struct vc4_hdmi *vc4_hdmi;
2502         struct drm_encoder *encoder;
2503         struct device_node *ddc_node;
2504         int ret;
2505
2506         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2507         if (!vc4_hdmi)
2508                 return -ENOMEM;
2509         mutex_init(&vc4_hdmi->mutex);
2510         spin_lock_init(&vc4_hdmi->hw_lock);
2511         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2512
2513         dev_set_drvdata(dev, vc4_hdmi);
2514         encoder = &vc4_hdmi->encoder.base.base;
2515         vc4_hdmi->encoder.base.type = variant->encoder_type;
2516         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2517         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2518         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2519         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2520         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2521         vc4_hdmi->pdev = pdev;
2522         vc4_hdmi->variant = variant;
2523
2524         /*
2525          * Since we don't know the state of the controller and its
2526          * display (if any), let's assume it's always enabled.
2527          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2528          * sure it's disabled, and avoid any inconsistency.
2529          */
2530         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2531                 vc4_hdmi->scdc_enabled = true;
2532
2533         ret = variant->init_resources(vc4_hdmi);
2534         if (ret)
2535                 return ret;
2536
2537         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2538         if (!ddc_node) {
2539                 DRM_ERROR("Failed to find ddc node in device tree\n");
2540                 return -ENODEV;
2541         }
2542
2543         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2544         of_node_put(ddc_node);
2545         if (!vc4_hdmi->ddc) {
2546                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2547                 return -EPROBE_DEFER;
2548         }
2549
2550         /* Only use the GPIO HPD pin if present in the DT, otherwise
2551          * we'll use the HDMI core's register.
2552          */
2553         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2554         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2555                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2556                 goto err_put_ddc;
2557         }
2558
2559         vc4_hdmi->disable_wifi_frequencies =
2560                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2561
2562         if (variant->max_pixel_clock == 600000000) {
2563                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2564                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2565
2566                 if (max_rate < 550000000)
2567                         vc4_hdmi->disable_4kp60 = true;
2568         }
2569
2570         /*
2571          * If we boot without any cable connected to the HDMI connector,
2572          * the firmware will skip the HSM initialization and leave it
2573          * with a rate of 0, resulting in a bus lockup when we're
2574          * accessing the registers even if it's enabled.
2575          *
2576          * Let's put a sensible default at runtime_resume so that we
2577          * don't end up in this situation.
2578          */
2579         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2580         if (ret)
2581                 goto err_put_ddc;
2582
2583         /*
2584          * We need to have the device powered up at this point to call
2585          * our reset hook and for the CEC init.
2586          */
2587         ret = vc4_hdmi_runtime_resume(dev);
2588         if (ret)
2589                 goto err_put_ddc;
2590
2591         pm_runtime_get_noresume(dev);
2592         pm_runtime_set_active(dev);
2593         pm_runtime_enable(dev);
2594
2595         if (vc4_hdmi->variant->reset)
2596                 vc4_hdmi->variant->reset(vc4_hdmi);
2597
2598         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2599              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2600             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2601                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2602                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2603                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2604         }
2605
2606         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2607         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2608
2609         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2610         if (ret)
2611                 goto err_destroy_encoder;
2612
2613         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2614         if (ret)
2615                 goto err_destroy_conn;
2616
2617         ret = vc4_hdmi_cec_init(vc4_hdmi);
2618         if (ret)
2619                 goto err_free_hotplug;
2620
2621         ret = vc4_hdmi_audio_init(vc4_hdmi);
2622         if (ret)
2623                 goto err_free_cec;
2624
2625         vc4_debugfs_add_file(drm, variant->debugfs_name,
2626                              vc4_hdmi_debugfs_regs,
2627                              vc4_hdmi);
2628
2629         pm_runtime_put_sync(dev);
2630
2631         return 0;
2632
2633 err_free_cec:
2634         vc4_hdmi_cec_exit(vc4_hdmi);
2635 err_free_hotplug:
2636         vc4_hdmi_hotplug_exit(vc4_hdmi);
2637 err_destroy_conn:
2638         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2639 err_destroy_encoder:
2640         drm_encoder_cleanup(encoder);
2641         pm_runtime_put_sync(dev);
2642         pm_runtime_disable(dev);
2643 err_put_ddc:
2644         put_device(&vc4_hdmi->ddc->dev);
2645
2646         return ret;
2647 }
2648
2649 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2650                             void *data)
2651 {
2652         struct vc4_hdmi *vc4_hdmi;
2653
2654         /*
2655          * ASoC makes it a bit hard to retrieve a pointer to the
2656          * vc4_hdmi structure. Registering the card will overwrite our
2657          * device drvdata with a pointer to the snd_soc_card structure,
2658          * which can then be used to retrieve whatever drvdata we want
2659          * to associate.
2660          *
2661          * However, that doesn't fly in the case where we wouldn't
2662          * register an ASoC card (because of an old DT that is missing
2663          * the dmas properties for example), then the card isn't
2664          * registered and the device drvdata wouldn't be set.
2665          *
2666          * We can deal with both cases by making sure a snd_soc_card
2667          * pointer and a vc4_hdmi structure are pointing to the same
2668          * memory address, so we can treat them indistinctly without any
2669          * issue.
2670          */
2671         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2672         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2673         vc4_hdmi = dev_get_drvdata(dev);
2674
2675         kfree(vc4_hdmi->hdmi_regset.regs);
2676         kfree(vc4_hdmi->hd_regset.regs);
2677
2678         vc4_hdmi_audio_exit(vc4_hdmi);
2679         vc4_hdmi_cec_exit(vc4_hdmi);
2680         vc4_hdmi_hotplug_exit(vc4_hdmi);
2681         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2682         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2683
2684         pm_runtime_disable(dev);
2685
2686         put_device(&vc4_hdmi->ddc->dev);
2687 }
2688
2689 static const struct component_ops vc4_hdmi_ops = {
2690         .bind   = vc4_hdmi_bind,
2691         .unbind = vc4_hdmi_unbind,
2692 };
2693
2694 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2695 {
2696         return component_add(&pdev->dev, &vc4_hdmi_ops);
2697 }
2698
2699 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2700 {
2701         component_del(&pdev->dev, &vc4_hdmi_ops);
2702         return 0;
2703 }
2704
2705 static const struct vc4_hdmi_variant bcm2835_variant = {
2706         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2707         .debugfs_name           = "hdmi_regs",
2708         .card_name              = "vc4-hdmi",
2709         .max_pixel_clock        = 162000000,
2710         .registers              = vc4_hdmi_fields,
2711         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2712
2713         .init_resources         = vc4_hdmi_init_resources,
2714         .csc_setup              = vc4_hdmi_csc_setup,
2715         .reset                  = vc4_hdmi_reset,
2716         .set_timings            = vc4_hdmi_set_timings,
2717         .phy_init               = vc4_hdmi_phy_init,
2718         .phy_disable            = vc4_hdmi_phy_disable,
2719         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2720         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2721         .channel_map            = vc4_hdmi_channel_map,
2722         .supports_hdr           = false,
2723 };
2724
2725 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2726         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2727         .debugfs_name           = "hdmi0_regs",
2728         .card_name              = "vc4-hdmi-0",
2729         .max_pixel_clock        = 600000000,
2730         .registers              = vc5_hdmi_hdmi0_fields,
2731         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2732         .phy_lane_mapping       = {
2733                 PHY_LANE_0,
2734                 PHY_LANE_1,
2735                 PHY_LANE_2,
2736                 PHY_LANE_CK,
2737         },
2738         .unsupported_odd_h_timings      = true,
2739         .external_irq_controller        = true,
2740
2741         .init_resources         = vc5_hdmi_init_resources,
2742         .csc_setup              = vc5_hdmi_csc_setup,
2743         .reset                  = vc5_hdmi_reset,
2744         .set_timings            = vc5_hdmi_set_timings,
2745         .phy_init               = vc5_hdmi_phy_init,
2746         .phy_disable            = vc5_hdmi_phy_disable,
2747         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2748         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2749         .channel_map            = vc5_hdmi_channel_map,
2750         .supports_hdr           = true,
2751         .hp_detect              = vc5_hdmi_hp_detect,
2752 };
2753
2754 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2755         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2756         .debugfs_name           = "hdmi1_regs",
2757         .card_name              = "vc4-hdmi-1",
2758         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2759         .registers              = vc5_hdmi_hdmi1_fields,
2760         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2761         .phy_lane_mapping       = {
2762                 PHY_LANE_1,
2763                 PHY_LANE_0,
2764                 PHY_LANE_CK,
2765                 PHY_LANE_2,
2766         },
2767         .unsupported_odd_h_timings      = true,
2768         .external_irq_controller        = true,
2769
2770         .init_resources         = vc5_hdmi_init_resources,
2771         .csc_setup              = vc5_hdmi_csc_setup,
2772         .reset                  = vc5_hdmi_reset,
2773         .set_timings            = vc5_hdmi_set_timings,
2774         .phy_init               = vc5_hdmi_phy_init,
2775         .phy_disable            = vc5_hdmi_phy_disable,
2776         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2777         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2778         .channel_map            = vc5_hdmi_channel_map,
2779         .supports_hdr           = true,
2780         .hp_detect              = vc5_hdmi_hp_detect,
2781 };
2782
2783 static const struct of_device_id vc4_hdmi_dt_match[] = {
2784         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2785         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2786         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2787         {}
2788 };
2789
2790 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2791         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2792                            vc4_hdmi_runtime_resume,
2793                            NULL)
2794 };
2795
2796 struct platform_driver vc4_hdmi_driver = {
2797         .probe = vc4_hdmi_dev_probe,
2798         .remove = vc4_hdmi_dev_remove,
2799         .driver = {
2800                 .name = "vc4_hdmi",
2801                 .of_match_table = vc4_hdmi_dt_match,
2802                 .pm = &vc4_hdmi_pm_ops,
2803         },
2804 };