1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/bitops.h>
8 #include <linux/host1x.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_aperture.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_debugfs.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_ioctl.h>
21 #include <drm/drm_prime.h>
22 #include <drm/drm_vblank.h>
28 #define DRIVER_NAME "tegra"
29 #define DRIVER_DESC "NVIDIA Tegra graphics"
30 #define DRIVER_DATE "20120330"
31 #define DRIVER_MAJOR 0
32 #define DRIVER_MINOR 0
33 #define DRIVER_PATCHLEVEL 0
35 #define CARVEOUT_SZ SZ_64M
36 #define CDMA_GATHER_FETCHES_MAX_NB 16383
38 static int tegra_atomic_check(struct drm_device *drm,
39 struct drm_atomic_state *state)
43 err = drm_atomic_helper_check(drm, state);
47 return tegra_display_hub_atomic_check(drm, state);
50 static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
51 .fb_create = tegra_fb_create,
52 #ifdef CONFIG_DRM_FBDEV_EMULATION
53 .output_poll_changed = drm_fb_helper_output_poll_changed,
55 .atomic_check = tegra_atomic_check,
56 .atomic_commit = drm_atomic_helper_commit,
59 static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
61 struct drm_device *drm = old_state->dev;
62 struct tegra_drm *tegra = drm->dev_private;
65 bool fence_cookie = dma_fence_begin_signalling();
67 drm_atomic_helper_commit_modeset_disables(drm, old_state);
68 tegra_display_hub_atomic_commit(drm, old_state);
69 drm_atomic_helper_commit_planes(drm, old_state, 0);
70 drm_atomic_helper_commit_modeset_enables(drm, old_state);
71 drm_atomic_helper_commit_hw_done(old_state);
72 dma_fence_end_signalling(fence_cookie);
73 drm_atomic_helper_wait_for_vblanks(drm, old_state);
74 drm_atomic_helper_cleanup_planes(drm, old_state);
76 drm_atomic_helper_commit_tail_rpm(old_state);
80 static const struct drm_mode_config_helper_funcs
81 tegra_drm_mode_config_helpers = {
82 .atomic_commit_tail = tegra_atomic_commit_tail,
85 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
87 struct tegra_drm_file *fpriv;
89 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
93 idr_init_base(&fpriv->legacy_contexts, 1);
94 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
95 xa_init(&fpriv->syncpoints);
96 mutex_init(&fpriv->lock);
97 filp->driver_priv = fpriv;
102 static void tegra_drm_context_free(struct tegra_drm_context *context)
104 context->client->ops->close_channel(context);
108 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
109 struct drm_tegra_reloc __user *src,
110 struct drm_device *drm,
111 struct drm_file *file)
116 err = get_user(cmdbuf, &src->cmdbuf.handle);
120 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
124 err = get_user(target, &src->target.handle);
128 err = get_user(dest->target.offset, &src->target.offset);
132 err = get_user(dest->shift, &src->shift);
136 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
138 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
139 if (!dest->cmdbuf.bo)
142 dest->target.bo = tegra_gem_lookup(file, target);
143 if (!dest->target.bo)
149 int tegra_drm_submit(struct tegra_drm_context *context,
150 struct drm_tegra_submit *args, struct drm_device *drm,
151 struct drm_file *file)
153 struct host1x_client *client = &context->client->base;
154 unsigned int num_cmdbufs = args->num_cmdbufs;
155 unsigned int num_relocs = args->num_relocs;
156 struct drm_tegra_cmdbuf __user *user_cmdbufs;
157 struct drm_tegra_reloc __user *user_relocs;
158 struct drm_tegra_syncpt __user *user_syncpt;
159 struct drm_tegra_syncpt syncpt;
160 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
161 struct drm_gem_object **refs;
162 struct host1x_syncpt *sp = NULL;
163 struct host1x_job *job;
164 unsigned int num_refs;
167 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
168 user_relocs = u64_to_user_ptr(args->relocs);
169 user_syncpt = u64_to_user_ptr(args->syncpts);
171 /* We don't yet support other than one syncpt_incr struct per submit */
172 if (args->num_syncpts != 1)
175 /* We don't yet support waitchks */
176 if (args->num_waitchks != 0)
179 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
180 args->num_relocs, false);
184 job->num_relocs = args->num_relocs;
185 job->client = client;
186 job->class = client->class;
187 job->serialize = true;
188 job->syncpt_recovery = true;
191 * Track referenced BOs so that they can be unreferenced after the
192 * submission is complete.
194 num_refs = num_cmdbufs + num_relocs * 2;
196 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
202 /* reuse as an iterator later */
205 while (num_cmdbufs) {
206 struct drm_tegra_cmdbuf cmdbuf;
207 struct host1x_bo *bo;
208 struct tegra_bo *obj;
211 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
217 * The maximum number of CDMA gather fetches is 16383, a higher
218 * value means the words count is malformed.
220 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
225 bo = tegra_gem_lookup(file, cmdbuf.handle);
231 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
232 obj = host1x_to_tegra_bo(bo);
233 refs[num_refs++] = &obj->gem;
236 * Gather buffer base address must be 4-bytes aligned,
237 * unaligned offset is malformed and cause commands stream
238 * corruption on the buffer address relocation.
240 if (offset & 3 || offset > obj->gem.size) {
245 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
250 /* copy and resolve relocations from submit */
251 while (num_relocs--) {
252 struct host1x_reloc *reloc;
253 struct tegra_bo *obj;
255 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
256 &user_relocs[num_relocs], drm,
261 reloc = &job->relocs[num_relocs];
262 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
263 refs[num_refs++] = &obj->gem;
266 * The unaligned cmdbuf offset will cause an unaligned write
267 * during of the relocations patching, corrupting the commands
270 if (reloc->cmdbuf.offset & 3 ||
271 reloc->cmdbuf.offset >= obj->gem.size) {
276 obj = host1x_to_tegra_bo(reloc->target.bo);
277 refs[num_refs++] = &obj->gem;
279 if (reloc->target.offset >= obj->gem.size) {
285 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
290 /* Syncpoint ref will be dropped on job release. */
291 sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
297 job->is_addr_reg = context->client->ops->is_addr_reg;
298 job->is_valid_class = context->client->ops->is_valid_class;
299 job->syncpt_incrs = syncpt.incrs;
301 job->timeout = 10000;
303 if (args->timeout && args->timeout < 10000)
304 job->timeout = args->timeout;
306 err = host1x_job_pin(job, context->client->base.dev);
310 err = host1x_job_submit(job);
312 host1x_job_unpin(job);
316 args->fence = job->syncpt_end;
320 drm_gem_object_put(refs[num_refs]);
330 #ifdef CONFIG_DRM_TEGRA_STAGING
331 static int tegra_gem_create(struct drm_device *drm, void *data,
332 struct drm_file *file)
334 struct drm_tegra_gem_create *args = data;
337 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
345 static int tegra_gem_mmap(struct drm_device *drm, void *data,
346 struct drm_file *file)
348 struct drm_tegra_gem_mmap *args = data;
349 struct drm_gem_object *gem;
352 gem = drm_gem_object_lookup(file, args->handle);
356 bo = to_tegra_bo(gem);
358 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
360 drm_gem_object_put(gem);
365 static int tegra_syncpt_read(struct drm_device *drm, void *data,
366 struct drm_file *file)
368 struct host1x *host = dev_get_drvdata(drm->dev->parent);
369 struct drm_tegra_syncpt_read *args = data;
370 struct host1x_syncpt *sp;
372 sp = host1x_syncpt_get_by_id_noref(host, args->id);
376 args->value = host1x_syncpt_read_min(sp);
380 static int tegra_syncpt_incr(struct drm_device *drm, void *data,
381 struct drm_file *file)
383 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
384 struct drm_tegra_syncpt_incr *args = data;
385 struct host1x_syncpt *sp;
387 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
391 return host1x_syncpt_incr(sp);
394 static int tegra_syncpt_wait(struct drm_device *drm, void *data,
395 struct drm_file *file)
397 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
398 struct drm_tegra_syncpt_wait *args = data;
399 struct host1x_syncpt *sp;
401 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
405 return host1x_syncpt_wait(sp, args->thresh,
406 msecs_to_jiffies(args->timeout),
410 static int tegra_client_open(struct tegra_drm_file *fpriv,
411 struct tegra_drm_client *client,
412 struct tegra_drm_context *context)
416 err = client->ops->open_channel(client, context);
420 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
422 client->ops->close_channel(context);
426 context->client = client;
432 static int tegra_open_channel(struct drm_device *drm, void *data,
433 struct drm_file *file)
435 struct tegra_drm_file *fpriv = file->driver_priv;
436 struct tegra_drm *tegra = drm->dev_private;
437 struct drm_tegra_open_channel *args = data;
438 struct tegra_drm_context *context;
439 struct tegra_drm_client *client;
442 context = kzalloc(sizeof(*context), GFP_KERNEL);
446 mutex_lock(&fpriv->lock);
448 list_for_each_entry(client, &tegra->clients, list)
449 if (client->base.class == args->client) {
450 err = tegra_client_open(fpriv, client, context);
454 args->context = context->id;
461 mutex_unlock(&fpriv->lock);
465 static int tegra_close_channel(struct drm_device *drm, void *data,
466 struct drm_file *file)
468 struct tegra_drm_file *fpriv = file->driver_priv;
469 struct drm_tegra_close_channel *args = data;
470 struct tegra_drm_context *context;
473 mutex_lock(&fpriv->lock);
475 context = idr_find(&fpriv->legacy_contexts, args->context);
481 idr_remove(&fpriv->legacy_contexts, context->id);
482 tegra_drm_context_free(context);
485 mutex_unlock(&fpriv->lock);
489 static int tegra_get_syncpt(struct drm_device *drm, void *data,
490 struct drm_file *file)
492 struct tegra_drm_file *fpriv = file->driver_priv;
493 struct drm_tegra_get_syncpt *args = data;
494 struct tegra_drm_context *context;
495 struct host1x_syncpt *syncpt;
498 mutex_lock(&fpriv->lock);
500 context = idr_find(&fpriv->legacy_contexts, args->context);
506 if (args->index >= context->client->base.num_syncpts) {
511 syncpt = context->client->base.syncpts[args->index];
512 args->id = host1x_syncpt_id(syncpt);
515 mutex_unlock(&fpriv->lock);
519 static int tegra_submit(struct drm_device *drm, void *data,
520 struct drm_file *file)
522 struct tegra_drm_file *fpriv = file->driver_priv;
523 struct drm_tegra_submit *args = data;
524 struct tegra_drm_context *context;
527 mutex_lock(&fpriv->lock);
529 context = idr_find(&fpriv->legacy_contexts, args->context);
535 err = context->client->ops->submit(context, args, drm, file);
538 mutex_unlock(&fpriv->lock);
542 static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
543 struct drm_file *file)
545 struct tegra_drm_file *fpriv = file->driver_priv;
546 struct drm_tegra_get_syncpt_base *args = data;
547 struct tegra_drm_context *context;
548 struct host1x_syncpt_base *base;
549 struct host1x_syncpt *syncpt;
552 mutex_lock(&fpriv->lock);
554 context = idr_find(&fpriv->legacy_contexts, args->context);
560 if (args->syncpt >= context->client->base.num_syncpts) {
565 syncpt = context->client->base.syncpts[args->syncpt];
567 base = host1x_syncpt_get_base(syncpt);
573 args->id = host1x_syncpt_base_id(base);
576 mutex_unlock(&fpriv->lock);
580 static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
581 struct drm_file *file)
583 struct drm_tegra_gem_set_tiling *args = data;
584 enum tegra_bo_tiling_mode mode;
585 struct drm_gem_object *gem;
586 unsigned long value = 0;
589 switch (args->mode) {
590 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
591 mode = TEGRA_BO_TILING_MODE_PITCH;
593 if (args->value != 0)
598 case DRM_TEGRA_GEM_TILING_MODE_TILED:
599 mode = TEGRA_BO_TILING_MODE_TILED;
601 if (args->value != 0)
606 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
607 mode = TEGRA_BO_TILING_MODE_BLOCK;
619 gem = drm_gem_object_lookup(file, args->handle);
623 bo = to_tegra_bo(gem);
625 bo->tiling.mode = mode;
626 bo->tiling.value = value;
628 drm_gem_object_put(gem);
633 static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
634 struct drm_file *file)
636 struct drm_tegra_gem_get_tiling *args = data;
637 struct drm_gem_object *gem;
641 gem = drm_gem_object_lookup(file, args->handle);
645 bo = to_tegra_bo(gem);
647 switch (bo->tiling.mode) {
648 case TEGRA_BO_TILING_MODE_PITCH:
649 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
653 case TEGRA_BO_TILING_MODE_TILED:
654 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
658 case TEGRA_BO_TILING_MODE_BLOCK:
659 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
660 args->value = bo->tiling.value;
668 drm_gem_object_put(gem);
673 static int tegra_gem_set_flags(struct drm_device *drm, void *data,
674 struct drm_file *file)
676 struct drm_tegra_gem_set_flags *args = data;
677 struct drm_gem_object *gem;
680 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
683 gem = drm_gem_object_lookup(file, args->handle);
687 bo = to_tegra_bo(gem);
690 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
691 bo->flags |= TEGRA_BO_BOTTOM_UP;
693 drm_gem_object_put(gem);
698 static int tegra_gem_get_flags(struct drm_device *drm, void *data,
699 struct drm_file *file)
701 struct drm_tegra_gem_get_flags *args = data;
702 struct drm_gem_object *gem;
705 gem = drm_gem_object_lookup(file, args->handle);
709 bo = to_tegra_bo(gem);
712 if (bo->flags & TEGRA_BO_BOTTOM_UP)
713 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
715 drm_gem_object_put(gem);
721 static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
722 #ifdef CONFIG_DRM_TEGRA_STAGING
723 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open,
725 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close,
727 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map,
729 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
731 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate,
733 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free,
736 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW),
737 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW),
738 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
740 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
742 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
744 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
746 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
748 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
750 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
752 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
754 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
756 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
758 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
760 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
765 static const struct file_operations tegra_drm_fops = {
766 .owner = THIS_MODULE,
768 .release = drm_release,
769 .unlocked_ioctl = drm_ioctl,
770 .mmap = tegra_drm_mmap,
773 .compat_ioctl = drm_compat_ioctl,
774 .llseek = noop_llseek,
777 static int tegra_drm_context_cleanup(int id, void *p, void *data)
779 struct tegra_drm_context *context = p;
781 tegra_drm_context_free(context);
786 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
788 struct tegra_drm_file *fpriv = file->driver_priv;
790 mutex_lock(&fpriv->lock);
791 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
792 tegra_drm_uapi_close_file(fpriv);
793 mutex_unlock(&fpriv->lock);
795 idr_destroy(&fpriv->legacy_contexts);
796 mutex_destroy(&fpriv->lock);
800 #ifdef CONFIG_DEBUG_FS
801 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
803 struct drm_info_node *node = (struct drm_info_node *)s->private;
804 struct drm_device *drm = node->minor->dev;
805 struct drm_framebuffer *fb;
807 mutex_lock(&drm->mode_config.fb_lock);
809 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
810 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
811 fb->base.id, fb->width, fb->height,
813 fb->format->cpp[0] * 8,
814 drm_framebuffer_read_refcount(fb));
817 mutex_unlock(&drm->mode_config.fb_lock);
822 static int tegra_debugfs_iova(struct seq_file *s, void *data)
824 struct drm_info_node *node = (struct drm_info_node *)s->private;
825 struct drm_device *drm = node->minor->dev;
826 struct tegra_drm *tegra = drm->dev_private;
827 struct drm_printer p = drm_seq_file_printer(s);
830 mutex_lock(&tegra->mm_lock);
831 drm_mm_print(&tegra->mm, &p);
832 mutex_unlock(&tegra->mm_lock);
838 static struct drm_info_list tegra_debugfs_list[] = {
839 { "framebuffers", tegra_debugfs_framebuffers, 0 },
840 { "iova", tegra_debugfs_iova, 0 },
843 static void tegra_debugfs_init(struct drm_minor *minor)
845 drm_debugfs_create_files(tegra_debugfs_list,
846 ARRAY_SIZE(tegra_debugfs_list),
847 minor->debugfs_root, minor);
851 static const struct drm_driver tegra_drm_driver = {
852 .driver_features = DRIVER_MODESET | DRIVER_GEM |
853 DRIVER_ATOMIC | DRIVER_RENDER,
854 .open = tegra_drm_open,
855 .postclose = tegra_drm_postclose,
856 .lastclose = drm_fb_helper_lastclose,
858 #if defined(CONFIG_DEBUG_FS)
859 .debugfs_init = tegra_debugfs_init,
862 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
863 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
864 .gem_prime_import = tegra_gem_prime_import,
866 .dumb_create = tegra_bo_dumb_create,
868 .ioctls = tegra_drm_ioctls,
869 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
870 .fops = &tegra_drm_fops,
875 .major = DRIVER_MAJOR,
876 .minor = DRIVER_MINOR,
877 .patchlevel = DRIVER_PATCHLEVEL,
880 int tegra_drm_register_client(struct tegra_drm *tegra,
881 struct tegra_drm_client *client)
884 * When MLOCKs are implemented, change to allocate a shared channel
885 * only when MLOCKs are disabled.
887 client->shared_channel = host1x_channel_request(&client->base);
888 if (!client->shared_channel)
891 mutex_lock(&tegra->clients_lock);
892 list_add_tail(&client->list, &tegra->clients);
894 mutex_unlock(&tegra->clients_lock);
899 int tegra_drm_unregister_client(struct tegra_drm *tegra,
900 struct tegra_drm_client *client)
902 mutex_lock(&tegra->clients_lock);
903 list_del_init(&client->list);
905 mutex_unlock(&tegra->clients_lock);
907 if (client->shared_channel)
908 host1x_channel_put(client->shared_channel);
913 int host1x_client_iommu_attach(struct host1x_client *client)
915 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
916 struct drm_device *drm = dev_get_drvdata(client->host);
917 struct tegra_drm *tegra = drm->dev_private;
918 struct iommu_group *group = NULL;
922 * If the host1x client is already attached to an IOMMU domain that is
923 * not the shared IOMMU domain, don't try to attach it to a different
924 * domain. This allows using the IOMMU-backed DMA API.
926 if (domain && domain != tegra->domain)
930 group = iommu_group_get(client->dev);
934 if (domain != tegra->domain) {
935 err = iommu_attach_group(tegra->domain, group);
937 iommu_group_put(group);
942 tegra->use_explicit_iommu = true;
945 client->group = group;
950 void host1x_client_iommu_detach(struct host1x_client *client)
952 struct drm_device *drm = dev_get_drvdata(client->host);
953 struct tegra_drm *tegra = drm->dev_private;
954 struct iommu_domain *domain;
958 * Devices that are part of the same group may no longer be
959 * attached to a domain at this point because their group may
960 * have been detached by an earlier client.
962 domain = iommu_get_domain_for_dev(client->dev);
964 iommu_detach_group(tegra->domain, client->group);
966 iommu_group_put(client->group);
967 client->group = NULL;
971 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
979 size = iova_align(&tegra->carveout.domain, size);
981 size = PAGE_ALIGN(size);
983 gfp = GFP_KERNEL | __GFP_ZERO;
984 if (!tegra->domain) {
986 * Many units only support 32-bit addresses, even on 64-bit
987 * SoCs. If there is no IOMMU to translate into a 32-bit IO
988 * virtual address space, force allocations to be in the
989 * lower 32-bit range.
994 virt = (void *)__get_free_pages(gfp, get_order(size));
996 return ERR_PTR(-ENOMEM);
998 if (!tegra->domain) {
1000 * If IOMMU is disabled, devices address physical memory
1003 *dma = virt_to_phys(virt);
1007 alloc = alloc_iova(&tegra->carveout.domain,
1008 size >> tegra->carveout.shift,
1009 tegra->carveout.limit, true);
1015 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1016 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1017 size, IOMMU_READ | IOMMU_WRITE);
1024 __free_iova(&tegra->carveout.domain, alloc);
1026 free_pages((unsigned long)virt, get_order(size));
1028 return ERR_PTR(err);
1031 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1035 size = iova_align(&tegra->carveout.domain, size);
1037 size = PAGE_ALIGN(size);
1039 if (tegra->domain) {
1040 iommu_unmap(tegra->domain, dma, size);
1041 free_iova(&tegra->carveout.domain,
1042 iova_pfn(&tegra->carveout.domain, dma));
1045 free_pages((unsigned long)virt, get_order(size));
1048 static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1050 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1051 struct iommu_domain *domain;
1054 * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1055 * likely to be allocated beyond the 32-bit boundary if sufficient
1056 * system memory is available. This is problematic on earlier Tegra
1057 * generations where host1x supports a maximum of 32 address bits in
1058 * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1059 * as well it won't be able to process buffers allocated beyond the
1062 * The DMA API will use bounce buffers in this case, so that could
1063 * perhaps still be made to work, even if less efficient, but there
1064 * is another catch: in order to perform cache maintenance on pages
1065 * allocated for discontiguous buffers we need to map and unmap the
1066 * SG table representing these buffers. This is fine for something
1067 * small like a push buffer, but it exhausts the bounce buffer pool
1068 * (typically on the order of a few MiB) for framebuffers (many MiB
1069 * for any modern resolution).
1071 * Work around this by making sure that Tegra DRM clients only use
1072 * an IOMMU if the parent host1x also uses an IOMMU.
1074 * Note that there's still a small gap here that we don't cover: if
1075 * the DMA API is backed by an IOMMU there's no way to control which
1076 * device is attached to an IOMMU and which isn't, except via wiring
1077 * up the device tree appropriately. This is considered an problem
1078 * of integration, so care must be taken for the DT to be consistent.
1080 domain = iommu_get_domain_for_dev(dev->dev.parent);
1083 * Tegra20 and Tegra30 don't support addressing memory beyond the
1084 * 32-bit boundary, so the regular GATHER opcodes will always be
1085 * sufficient and whether or not the host1x is attached to an IOMMU
1088 if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1091 return domain != NULL;
1094 static int host1x_drm_probe(struct host1x_device *dev)
1096 struct tegra_drm *tegra;
1097 struct drm_device *drm;
1100 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1102 return PTR_ERR(drm);
1104 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
1110 if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1111 tegra->domain = iommu_domain_alloc(&platform_bus_type);
1112 if (!tegra->domain) {
1117 err = iova_cache_get();
1122 mutex_init(&tegra->clients_lock);
1123 INIT_LIST_HEAD(&tegra->clients);
1125 dev_set_drvdata(&dev->dev, drm);
1126 drm->dev_private = tegra;
1129 drm_mode_config_init(drm);
1131 drm->mode_config.min_width = 0;
1132 drm->mode_config.min_height = 0;
1133 drm->mode_config.max_width = 0;
1134 drm->mode_config.max_height = 0;
1136 drm->mode_config.normalize_zpos = true;
1138 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1139 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1141 err = tegra_drm_fb_prepare(drm);
1145 drm_kms_helper_poll_init(drm);
1147 err = host1x_device_init(dev);
1152 * Now that all display controller have been initialized, the maximum
1153 * supported resolution is known and the bitmask for horizontal and
1154 * vertical bitfields can be computed.
1156 tegra->hmask = drm->mode_config.max_width - 1;
1157 tegra->vmask = drm->mode_config.max_height - 1;
1159 if (tegra->use_explicit_iommu) {
1160 u64 carveout_start, carveout_end, gem_start, gem_end;
1161 u64 dma_mask = dma_get_mask(&dev->dev);
1162 dma_addr_t start, end;
1163 unsigned long order;
1165 start = tegra->domain->geometry.aperture_start & dma_mask;
1166 end = tegra->domain->geometry.aperture_end & dma_mask;
1169 gem_end = end - CARVEOUT_SZ;
1170 carveout_start = gem_end + 1;
1173 order = __ffs(tegra->domain->pgsize_bitmap);
1174 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1175 carveout_start >> order);
1177 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1178 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1180 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1181 mutex_init(&tegra->mm_lock);
1183 DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1184 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1185 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1187 } else if (tegra->domain) {
1188 iommu_domain_free(tegra->domain);
1189 tegra->domain = NULL;
1194 err = tegra_display_hub_prepare(tegra->hub);
1200 * We don't use the drm_irq_install() helpers provided by the DRM
1201 * core, so we need to set this manually in order to allow the
1202 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
1204 drm->irq_enabled = true;
1206 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1207 drm->max_vblank_count = 0xffffffff;
1209 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1213 drm_mode_config_reset(drm);
1215 err = drm_aperture_remove_framebuffers(false, "tegradrmfb");
1219 err = tegra_drm_fb_init(drm);
1223 err = drm_dev_register(drm, 0);
1230 tegra_drm_fb_exit(drm);
1233 tegra_display_hub_cleanup(tegra->hub);
1235 if (tegra->domain) {
1236 mutex_destroy(&tegra->mm_lock);
1237 drm_mm_takedown(&tegra->mm);
1238 put_iova_domain(&tegra->carveout.domain);
1242 host1x_device_exit(dev);
1244 drm_kms_helper_poll_fini(drm);
1245 tegra_drm_fb_free(drm);
1247 drm_mode_config_cleanup(drm);
1250 iommu_domain_free(tegra->domain);
1258 static int host1x_drm_remove(struct host1x_device *dev)
1260 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1261 struct tegra_drm *tegra = drm->dev_private;
1264 drm_dev_unregister(drm);
1266 drm_kms_helper_poll_fini(drm);
1267 tegra_drm_fb_exit(drm);
1268 drm_atomic_helper_shutdown(drm);
1269 drm_mode_config_cleanup(drm);
1272 tegra_display_hub_cleanup(tegra->hub);
1274 err = host1x_device_exit(dev);
1276 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1278 if (tegra->domain) {
1279 mutex_destroy(&tegra->mm_lock);
1280 drm_mm_takedown(&tegra->mm);
1281 put_iova_domain(&tegra->carveout.domain);
1283 iommu_domain_free(tegra->domain);
1292 #ifdef CONFIG_PM_SLEEP
1293 static int host1x_drm_suspend(struct device *dev)
1295 struct drm_device *drm = dev_get_drvdata(dev);
1297 return drm_mode_config_helper_suspend(drm);
1300 static int host1x_drm_resume(struct device *dev)
1302 struct drm_device *drm = dev_get_drvdata(dev);
1304 return drm_mode_config_helper_resume(drm);
1308 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1311 static const struct of_device_id host1x_drm_subdevs[] = {
1312 { .compatible = "nvidia,tegra20-dc", },
1313 { .compatible = "nvidia,tegra20-hdmi", },
1314 { .compatible = "nvidia,tegra20-gr2d", },
1315 { .compatible = "nvidia,tegra20-gr3d", },
1316 { .compatible = "nvidia,tegra30-dc", },
1317 { .compatible = "nvidia,tegra30-hdmi", },
1318 { .compatible = "nvidia,tegra30-gr2d", },
1319 { .compatible = "nvidia,tegra30-gr3d", },
1320 { .compatible = "nvidia,tegra114-dc", },
1321 { .compatible = "nvidia,tegra114-dsi", },
1322 { .compatible = "nvidia,tegra114-hdmi", },
1323 { .compatible = "nvidia,tegra114-gr2d", },
1324 { .compatible = "nvidia,tegra114-gr3d", },
1325 { .compatible = "nvidia,tegra124-dc", },
1326 { .compatible = "nvidia,tegra124-sor", },
1327 { .compatible = "nvidia,tegra124-hdmi", },
1328 { .compatible = "nvidia,tegra124-dsi", },
1329 { .compatible = "nvidia,tegra124-vic", },
1330 { .compatible = "nvidia,tegra132-dsi", },
1331 { .compatible = "nvidia,tegra210-dc", },
1332 { .compatible = "nvidia,tegra210-dsi", },
1333 { .compatible = "nvidia,tegra210-sor", },
1334 { .compatible = "nvidia,tegra210-sor1", },
1335 { .compatible = "nvidia,tegra210-vic", },
1336 { .compatible = "nvidia,tegra186-display", },
1337 { .compatible = "nvidia,tegra186-dc", },
1338 { .compatible = "nvidia,tegra186-sor", },
1339 { .compatible = "nvidia,tegra186-sor1", },
1340 { .compatible = "nvidia,tegra186-vic", },
1341 { .compatible = "nvidia,tegra194-display", },
1342 { .compatible = "nvidia,tegra194-dc", },
1343 { .compatible = "nvidia,tegra194-sor", },
1344 { .compatible = "nvidia,tegra194-vic", },
1348 static struct host1x_driver host1x_drm_driver = {
1351 .pm = &host1x_drm_pm_ops,
1353 .probe = host1x_drm_probe,
1354 .remove = host1x_drm_remove,
1355 .subdevs = host1x_drm_subdevs,
1358 static struct platform_driver * const drivers[] = {
1359 &tegra_display_hub_driver,
1363 &tegra_dpaux_driver,
1370 static int __init host1x_drm_init(void)
1374 err = host1x_driver_register(&host1x_drm_driver);
1378 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1380 goto unregister_host1x;
1385 host1x_driver_unregister(&host1x_drm_driver);
1388 module_init(host1x_drm_init);
1390 static void __exit host1x_drm_exit(void)
1392 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1393 host1x_driver_unregister(&host1x_drm_driver);
1395 module_exit(host1x_drm_exit);
1397 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1398 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1399 MODULE_LICENSE("GPL v2");