1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/bitops.h>
8 #include <linux/host1x.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_aperture.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_debugfs.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_ioctl.h>
21 #include <drm/drm_prime.h>
22 #include <drm/drm_vblank.h>
27 #define DRIVER_NAME "tegra"
28 #define DRIVER_DESC "NVIDIA Tegra graphics"
29 #define DRIVER_DATE "20120330"
30 #define DRIVER_MAJOR 0
31 #define DRIVER_MINOR 0
32 #define DRIVER_PATCHLEVEL 0
34 #define CARVEOUT_SZ SZ_64M
35 #define CDMA_GATHER_FETCHES_MAX_NB 16383
37 struct tegra_drm_file {
42 static int tegra_atomic_check(struct drm_device *drm,
43 struct drm_atomic_state *state)
47 err = drm_atomic_helper_check(drm, state);
51 return tegra_display_hub_atomic_check(drm, state);
54 static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
55 .fb_create = tegra_fb_create,
56 #ifdef CONFIG_DRM_FBDEV_EMULATION
57 .output_poll_changed = drm_fb_helper_output_poll_changed,
59 .atomic_check = tegra_atomic_check,
60 .atomic_commit = drm_atomic_helper_commit,
63 static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
65 struct drm_device *drm = old_state->dev;
66 struct tegra_drm *tegra = drm->dev_private;
69 bool fence_cookie = dma_fence_begin_signalling();
71 drm_atomic_helper_commit_modeset_disables(drm, old_state);
72 tegra_display_hub_atomic_commit(drm, old_state);
73 drm_atomic_helper_commit_planes(drm, old_state, 0);
74 drm_atomic_helper_commit_modeset_enables(drm, old_state);
75 drm_atomic_helper_commit_hw_done(old_state);
76 dma_fence_end_signalling(fence_cookie);
77 drm_atomic_helper_wait_for_vblanks(drm, old_state);
78 drm_atomic_helper_cleanup_planes(drm, old_state);
80 drm_atomic_helper_commit_tail_rpm(old_state);
84 static const struct drm_mode_config_helper_funcs
85 tegra_drm_mode_config_helpers = {
86 .atomic_commit_tail = tegra_atomic_commit_tail,
89 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
91 struct tegra_drm_file *fpriv;
93 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
97 idr_init_base(&fpriv->contexts, 1);
98 mutex_init(&fpriv->lock);
99 filp->driver_priv = fpriv;
104 static void tegra_drm_context_free(struct tegra_drm_context *context)
106 context->client->ops->close_channel(context);
110 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
111 struct drm_tegra_reloc __user *src,
112 struct drm_device *drm,
113 struct drm_file *file)
118 err = get_user(cmdbuf, &src->cmdbuf.handle);
122 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
126 err = get_user(target, &src->target.handle);
130 err = get_user(dest->target.offset, &src->target.offset);
134 err = get_user(dest->shift, &src->shift);
138 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
140 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
141 if (!dest->cmdbuf.bo)
144 dest->target.bo = tegra_gem_lookup(file, target);
145 if (!dest->target.bo)
151 int tegra_drm_submit(struct tegra_drm_context *context,
152 struct drm_tegra_submit *args, struct drm_device *drm,
153 struct drm_file *file)
155 struct host1x_client *client = &context->client->base;
156 unsigned int num_cmdbufs = args->num_cmdbufs;
157 unsigned int num_relocs = args->num_relocs;
158 struct drm_tegra_cmdbuf __user *user_cmdbufs;
159 struct drm_tegra_reloc __user *user_relocs;
160 struct drm_tegra_syncpt __user *user_syncpt;
161 struct drm_tegra_syncpt syncpt;
162 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
163 struct drm_gem_object **refs;
164 struct host1x_syncpt *sp = NULL;
165 struct host1x_job *job;
166 unsigned int num_refs;
169 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
170 user_relocs = u64_to_user_ptr(args->relocs);
171 user_syncpt = u64_to_user_ptr(args->syncpts);
173 /* We don't yet support other than one syncpt_incr struct per submit */
174 if (args->num_syncpts != 1)
177 /* We don't yet support waitchks */
178 if (args->num_waitchks != 0)
181 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
182 args->num_relocs, false);
186 job->num_relocs = args->num_relocs;
187 job->client = client;
188 job->class = client->class;
189 job->serialize = true;
190 job->syncpt_recovery = true;
193 * Track referenced BOs so that they can be unreferenced after the
194 * submission is complete.
196 num_refs = num_cmdbufs + num_relocs * 2;
198 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
204 /* reuse as an iterator later */
207 while (num_cmdbufs) {
208 struct drm_tegra_cmdbuf cmdbuf;
209 struct host1x_bo *bo;
210 struct tegra_bo *obj;
213 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
219 * The maximum number of CDMA gather fetches is 16383, a higher
220 * value means the words count is malformed.
222 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
227 bo = tegra_gem_lookup(file, cmdbuf.handle);
233 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
234 obj = host1x_to_tegra_bo(bo);
235 refs[num_refs++] = &obj->gem;
238 * Gather buffer base address must be 4-bytes aligned,
239 * unaligned offset is malformed and cause commands stream
240 * corruption on the buffer address relocation.
242 if (offset & 3 || offset > obj->gem.size) {
247 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
252 /* copy and resolve relocations from submit */
253 while (num_relocs--) {
254 struct host1x_reloc *reloc;
255 struct tegra_bo *obj;
257 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
258 &user_relocs[num_relocs], drm,
263 reloc = &job->relocs[num_relocs];
264 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
265 refs[num_refs++] = &obj->gem;
268 * The unaligned cmdbuf offset will cause an unaligned write
269 * during of the relocations patching, corrupting the commands
272 if (reloc->cmdbuf.offset & 3 ||
273 reloc->cmdbuf.offset >= obj->gem.size) {
278 obj = host1x_to_tegra_bo(reloc->target.bo);
279 refs[num_refs++] = &obj->gem;
281 if (reloc->target.offset >= obj->gem.size) {
287 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
292 /* Syncpoint ref will be dropped on job release. */
293 sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
299 job->is_addr_reg = context->client->ops->is_addr_reg;
300 job->is_valid_class = context->client->ops->is_valid_class;
301 job->syncpt_incrs = syncpt.incrs;
303 job->timeout = 10000;
305 if (args->timeout && args->timeout < 10000)
306 job->timeout = args->timeout;
308 err = host1x_job_pin(job, context->client->base.dev);
312 err = host1x_job_submit(job);
314 host1x_job_unpin(job);
318 args->fence = job->syncpt_end;
322 drm_gem_object_put(refs[num_refs]);
332 #ifdef CONFIG_DRM_TEGRA_STAGING
333 static int tegra_gem_create(struct drm_device *drm, void *data,
334 struct drm_file *file)
336 struct drm_tegra_gem_create *args = data;
339 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
347 static int tegra_gem_mmap(struct drm_device *drm, void *data,
348 struct drm_file *file)
350 struct drm_tegra_gem_mmap *args = data;
351 struct drm_gem_object *gem;
354 gem = drm_gem_object_lookup(file, args->handle);
358 bo = to_tegra_bo(gem);
360 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
362 drm_gem_object_put(gem);
367 static int tegra_syncpt_read(struct drm_device *drm, void *data,
368 struct drm_file *file)
370 struct host1x *host = dev_get_drvdata(drm->dev->parent);
371 struct drm_tegra_syncpt_read *args = data;
372 struct host1x_syncpt *sp;
374 sp = host1x_syncpt_get_by_id_noref(host, args->id);
378 args->value = host1x_syncpt_read_min(sp);
382 static int tegra_syncpt_incr(struct drm_device *drm, void *data,
383 struct drm_file *file)
385 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
386 struct drm_tegra_syncpt_incr *args = data;
387 struct host1x_syncpt *sp;
389 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
393 return host1x_syncpt_incr(sp);
396 static int tegra_syncpt_wait(struct drm_device *drm, void *data,
397 struct drm_file *file)
399 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
400 struct drm_tegra_syncpt_wait *args = data;
401 struct host1x_syncpt *sp;
403 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
407 return host1x_syncpt_wait(sp, args->thresh,
408 msecs_to_jiffies(args->timeout),
412 static int tegra_client_open(struct tegra_drm_file *fpriv,
413 struct tegra_drm_client *client,
414 struct tegra_drm_context *context)
418 err = client->ops->open_channel(client, context);
422 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
424 client->ops->close_channel(context);
428 context->client = client;
434 static int tegra_open_channel(struct drm_device *drm, void *data,
435 struct drm_file *file)
437 struct tegra_drm_file *fpriv = file->driver_priv;
438 struct tegra_drm *tegra = drm->dev_private;
439 struct drm_tegra_open_channel *args = data;
440 struct tegra_drm_context *context;
441 struct tegra_drm_client *client;
444 context = kzalloc(sizeof(*context), GFP_KERNEL);
448 mutex_lock(&fpriv->lock);
450 list_for_each_entry(client, &tegra->clients, list)
451 if (client->base.class == args->client) {
452 err = tegra_client_open(fpriv, client, context);
456 args->context = context->id;
463 mutex_unlock(&fpriv->lock);
467 static int tegra_close_channel(struct drm_device *drm, void *data,
468 struct drm_file *file)
470 struct tegra_drm_file *fpriv = file->driver_priv;
471 struct drm_tegra_close_channel *args = data;
472 struct tegra_drm_context *context;
475 mutex_lock(&fpriv->lock);
477 context = idr_find(&fpriv->contexts, args->context);
483 idr_remove(&fpriv->contexts, context->id);
484 tegra_drm_context_free(context);
487 mutex_unlock(&fpriv->lock);
491 static int tegra_get_syncpt(struct drm_device *drm, void *data,
492 struct drm_file *file)
494 struct tegra_drm_file *fpriv = file->driver_priv;
495 struct drm_tegra_get_syncpt *args = data;
496 struct tegra_drm_context *context;
497 struct host1x_syncpt *syncpt;
500 mutex_lock(&fpriv->lock);
502 context = idr_find(&fpriv->contexts, args->context);
508 if (args->index >= context->client->base.num_syncpts) {
513 syncpt = context->client->base.syncpts[args->index];
514 args->id = host1x_syncpt_id(syncpt);
517 mutex_unlock(&fpriv->lock);
521 static int tegra_submit(struct drm_device *drm, void *data,
522 struct drm_file *file)
524 struct tegra_drm_file *fpriv = file->driver_priv;
525 struct drm_tegra_submit *args = data;
526 struct tegra_drm_context *context;
529 mutex_lock(&fpriv->lock);
531 context = idr_find(&fpriv->contexts, args->context);
537 err = context->client->ops->submit(context, args, drm, file);
540 mutex_unlock(&fpriv->lock);
544 static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
545 struct drm_file *file)
547 struct tegra_drm_file *fpriv = file->driver_priv;
548 struct drm_tegra_get_syncpt_base *args = data;
549 struct tegra_drm_context *context;
550 struct host1x_syncpt_base *base;
551 struct host1x_syncpt *syncpt;
554 mutex_lock(&fpriv->lock);
556 context = idr_find(&fpriv->contexts, args->context);
562 if (args->syncpt >= context->client->base.num_syncpts) {
567 syncpt = context->client->base.syncpts[args->syncpt];
569 base = host1x_syncpt_get_base(syncpt);
575 args->id = host1x_syncpt_base_id(base);
578 mutex_unlock(&fpriv->lock);
582 static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
583 struct drm_file *file)
585 struct drm_tegra_gem_set_tiling *args = data;
586 enum tegra_bo_tiling_mode mode;
587 struct drm_gem_object *gem;
588 unsigned long value = 0;
591 switch (args->mode) {
592 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
593 mode = TEGRA_BO_TILING_MODE_PITCH;
595 if (args->value != 0)
600 case DRM_TEGRA_GEM_TILING_MODE_TILED:
601 mode = TEGRA_BO_TILING_MODE_TILED;
603 if (args->value != 0)
608 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
609 mode = TEGRA_BO_TILING_MODE_BLOCK;
621 gem = drm_gem_object_lookup(file, args->handle);
625 bo = to_tegra_bo(gem);
627 bo->tiling.mode = mode;
628 bo->tiling.value = value;
630 drm_gem_object_put(gem);
635 static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
636 struct drm_file *file)
638 struct drm_tegra_gem_get_tiling *args = data;
639 struct drm_gem_object *gem;
643 gem = drm_gem_object_lookup(file, args->handle);
647 bo = to_tegra_bo(gem);
649 switch (bo->tiling.mode) {
650 case TEGRA_BO_TILING_MODE_PITCH:
651 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
655 case TEGRA_BO_TILING_MODE_TILED:
656 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
660 case TEGRA_BO_TILING_MODE_BLOCK:
661 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
662 args->value = bo->tiling.value;
670 drm_gem_object_put(gem);
675 static int tegra_gem_set_flags(struct drm_device *drm, void *data,
676 struct drm_file *file)
678 struct drm_tegra_gem_set_flags *args = data;
679 struct drm_gem_object *gem;
682 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
685 gem = drm_gem_object_lookup(file, args->handle);
689 bo = to_tegra_bo(gem);
692 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
693 bo->flags |= TEGRA_BO_BOTTOM_UP;
695 drm_gem_object_put(gem);
700 static int tegra_gem_get_flags(struct drm_device *drm, void *data,
701 struct drm_file *file)
703 struct drm_tegra_gem_get_flags *args = data;
704 struct drm_gem_object *gem;
707 gem = drm_gem_object_lookup(file, args->handle);
711 bo = to_tegra_bo(gem);
714 if (bo->flags & TEGRA_BO_BOTTOM_UP)
715 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
717 drm_gem_object_put(gem);
723 static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
724 #ifdef CONFIG_DRM_TEGRA_STAGING
725 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
727 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
729 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
731 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
733 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
735 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
737 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
739 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
741 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
743 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
745 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
747 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
749 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
751 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
756 static const struct file_operations tegra_drm_fops = {
757 .owner = THIS_MODULE,
759 .release = drm_release,
760 .unlocked_ioctl = drm_ioctl,
761 .mmap = tegra_drm_mmap,
764 .compat_ioctl = drm_compat_ioctl,
765 .llseek = noop_llseek,
768 static int tegra_drm_context_cleanup(int id, void *p, void *data)
770 struct tegra_drm_context *context = p;
772 tegra_drm_context_free(context);
777 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
779 struct tegra_drm_file *fpriv = file->driver_priv;
781 mutex_lock(&fpriv->lock);
782 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
783 mutex_unlock(&fpriv->lock);
785 idr_destroy(&fpriv->contexts);
786 mutex_destroy(&fpriv->lock);
790 #ifdef CONFIG_DEBUG_FS
791 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
793 struct drm_info_node *node = (struct drm_info_node *)s->private;
794 struct drm_device *drm = node->minor->dev;
795 struct drm_framebuffer *fb;
797 mutex_lock(&drm->mode_config.fb_lock);
799 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
800 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
801 fb->base.id, fb->width, fb->height,
803 fb->format->cpp[0] * 8,
804 drm_framebuffer_read_refcount(fb));
807 mutex_unlock(&drm->mode_config.fb_lock);
812 static int tegra_debugfs_iova(struct seq_file *s, void *data)
814 struct drm_info_node *node = (struct drm_info_node *)s->private;
815 struct drm_device *drm = node->minor->dev;
816 struct tegra_drm *tegra = drm->dev_private;
817 struct drm_printer p = drm_seq_file_printer(s);
820 mutex_lock(&tegra->mm_lock);
821 drm_mm_print(&tegra->mm, &p);
822 mutex_unlock(&tegra->mm_lock);
828 static struct drm_info_list tegra_debugfs_list[] = {
829 { "framebuffers", tegra_debugfs_framebuffers, 0 },
830 { "iova", tegra_debugfs_iova, 0 },
833 static void tegra_debugfs_init(struct drm_minor *minor)
835 drm_debugfs_create_files(tegra_debugfs_list,
836 ARRAY_SIZE(tegra_debugfs_list),
837 minor->debugfs_root, minor);
841 static const struct drm_driver tegra_drm_driver = {
842 .driver_features = DRIVER_MODESET | DRIVER_GEM |
843 DRIVER_ATOMIC | DRIVER_RENDER,
844 .open = tegra_drm_open,
845 .postclose = tegra_drm_postclose,
846 .lastclose = drm_fb_helper_lastclose,
848 #if defined(CONFIG_DEBUG_FS)
849 .debugfs_init = tegra_debugfs_init,
852 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
853 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
854 .gem_prime_import = tegra_gem_prime_import,
856 .dumb_create = tegra_bo_dumb_create,
858 .ioctls = tegra_drm_ioctls,
859 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
860 .fops = &tegra_drm_fops,
865 .major = DRIVER_MAJOR,
866 .minor = DRIVER_MINOR,
867 .patchlevel = DRIVER_PATCHLEVEL,
870 int tegra_drm_register_client(struct tegra_drm *tegra,
871 struct tegra_drm_client *client)
874 * When MLOCKs are implemented, change to allocate a shared channel
875 * only when MLOCKs are disabled.
877 client->shared_channel = host1x_channel_request(&client->base);
878 if (!client->shared_channel)
881 mutex_lock(&tegra->clients_lock);
882 list_add_tail(&client->list, &tegra->clients);
884 mutex_unlock(&tegra->clients_lock);
889 int tegra_drm_unregister_client(struct tegra_drm *tegra,
890 struct tegra_drm_client *client)
892 mutex_lock(&tegra->clients_lock);
893 list_del_init(&client->list);
895 mutex_unlock(&tegra->clients_lock);
897 if (client->shared_channel)
898 host1x_channel_put(client->shared_channel);
903 int host1x_client_iommu_attach(struct host1x_client *client)
905 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
906 struct drm_device *drm = dev_get_drvdata(client->host);
907 struct tegra_drm *tegra = drm->dev_private;
908 struct iommu_group *group = NULL;
912 * If the host1x client is already attached to an IOMMU domain that is
913 * not the shared IOMMU domain, don't try to attach it to a different
914 * domain. This allows using the IOMMU-backed DMA API.
916 if (domain && domain != tegra->domain)
920 group = iommu_group_get(client->dev);
924 if (domain != tegra->domain) {
925 err = iommu_attach_group(tegra->domain, group);
927 iommu_group_put(group);
932 tegra->use_explicit_iommu = true;
935 client->group = group;
940 void host1x_client_iommu_detach(struct host1x_client *client)
942 struct drm_device *drm = dev_get_drvdata(client->host);
943 struct tegra_drm *tegra = drm->dev_private;
944 struct iommu_domain *domain;
948 * Devices that are part of the same group may no longer be
949 * attached to a domain at this point because their group may
950 * have been detached by an earlier client.
952 domain = iommu_get_domain_for_dev(client->dev);
954 iommu_detach_group(tegra->domain, client->group);
956 iommu_group_put(client->group);
957 client->group = NULL;
961 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
969 size = iova_align(&tegra->carveout.domain, size);
971 size = PAGE_ALIGN(size);
973 gfp = GFP_KERNEL | __GFP_ZERO;
974 if (!tegra->domain) {
976 * Many units only support 32-bit addresses, even on 64-bit
977 * SoCs. If there is no IOMMU to translate into a 32-bit IO
978 * virtual address space, force allocations to be in the
979 * lower 32-bit range.
984 virt = (void *)__get_free_pages(gfp, get_order(size));
986 return ERR_PTR(-ENOMEM);
988 if (!tegra->domain) {
990 * If IOMMU is disabled, devices address physical memory
993 *dma = virt_to_phys(virt);
997 alloc = alloc_iova(&tegra->carveout.domain,
998 size >> tegra->carveout.shift,
999 tegra->carveout.limit, true);
1005 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1006 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1007 size, IOMMU_READ | IOMMU_WRITE);
1014 __free_iova(&tegra->carveout.domain, alloc);
1016 free_pages((unsigned long)virt, get_order(size));
1018 return ERR_PTR(err);
1021 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1025 size = iova_align(&tegra->carveout.domain, size);
1027 size = PAGE_ALIGN(size);
1029 if (tegra->domain) {
1030 iommu_unmap(tegra->domain, dma, size);
1031 free_iova(&tegra->carveout.domain,
1032 iova_pfn(&tegra->carveout.domain, dma));
1035 free_pages((unsigned long)virt, get_order(size));
1038 static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1040 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1041 struct iommu_domain *domain;
1044 * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1045 * likely to be allocated beyond the 32-bit boundary if sufficient
1046 * system memory is available. This is problematic on earlier Tegra
1047 * generations where host1x supports a maximum of 32 address bits in
1048 * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1049 * as well it won't be able to process buffers allocated beyond the
1052 * The DMA API will use bounce buffers in this case, so that could
1053 * perhaps still be made to work, even if less efficient, but there
1054 * is another catch: in order to perform cache maintenance on pages
1055 * allocated for discontiguous buffers we need to map and unmap the
1056 * SG table representing these buffers. This is fine for something
1057 * small like a push buffer, but it exhausts the bounce buffer pool
1058 * (typically on the order of a few MiB) for framebuffers (many MiB
1059 * for any modern resolution).
1061 * Work around this by making sure that Tegra DRM clients only use
1062 * an IOMMU if the parent host1x also uses an IOMMU.
1064 * Note that there's still a small gap here that we don't cover: if
1065 * the DMA API is backed by an IOMMU there's no way to control which
1066 * device is attached to an IOMMU and which isn't, except via wiring
1067 * up the device tree appropriately. This is considered an problem
1068 * of integration, so care must be taken for the DT to be consistent.
1070 domain = iommu_get_domain_for_dev(dev->dev.parent);
1073 * Tegra20 and Tegra30 don't support addressing memory beyond the
1074 * 32-bit boundary, so the regular GATHER opcodes will always be
1075 * sufficient and whether or not the host1x is attached to an IOMMU
1078 if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1081 return domain != NULL;
1084 static int host1x_drm_probe(struct host1x_device *dev)
1086 struct tegra_drm *tegra;
1087 struct drm_device *drm;
1090 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1092 return PTR_ERR(drm);
1094 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
1100 if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1101 tegra->domain = iommu_domain_alloc(&platform_bus_type);
1102 if (!tegra->domain) {
1107 err = iova_cache_get();
1112 mutex_init(&tegra->clients_lock);
1113 INIT_LIST_HEAD(&tegra->clients);
1115 dev_set_drvdata(&dev->dev, drm);
1116 drm->dev_private = tegra;
1119 drm_mode_config_init(drm);
1121 drm->mode_config.min_width = 0;
1122 drm->mode_config.min_height = 0;
1123 drm->mode_config.max_width = 0;
1124 drm->mode_config.max_height = 0;
1126 drm->mode_config.normalize_zpos = true;
1128 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1129 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1131 err = tegra_drm_fb_prepare(drm);
1135 drm_kms_helper_poll_init(drm);
1137 err = host1x_device_init(dev);
1142 * Now that all display controller have been initialized, the maximum
1143 * supported resolution is known and the bitmask for horizontal and
1144 * vertical bitfields can be computed.
1146 tegra->hmask = drm->mode_config.max_width - 1;
1147 tegra->vmask = drm->mode_config.max_height - 1;
1149 if (tegra->use_explicit_iommu) {
1150 u64 carveout_start, carveout_end, gem_start, gem_end;
1151 u64 dma_mask = dma_get_mask(&dev->dev);
1152 dma_addr_t start, end;
1153 unsigned long order;
1155 start = tegra->domain->geometry.aperture_start & dma_mask;
1156 end = tegra->domain->geometry.aperture_end & dma_mask;
1159 gem_end = end - CARVEOUT_SZ;
1160 carveout_start = gem_end + 1;
1163 order = __ffs(tegra->domain->pgsize_bitmap);
1164 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1165 carveout_start >> order);
1167 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1168 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1170 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1171 mutex_init(&tegra->mm_lock);
1173 DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1174 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1175 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1177 } else if (tegra->domain) {
1178 iommu_domain_free(tegra->domain);
1179 tegra->domain = NULL;
1184 err = tegra_display_hub_prepare(tegra->hub);
1190 * We don't use the drm_irq_install() helpers provided by the DRM
1191 * core, so we need to set this manually in order to allow the
1192 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
1194 drm->irq_enabled = true;
1196 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1197 drm->max_vblank_count = 0xffffffff;
1199 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1203 drm_mode_config_reset(drm);
1205 err = drm_aperture_remove_framebuffers(false, "tegradrmfb");
1209 err = tegra_drm_fb_init(drm);
1213 err = drm_dev_register(drm, 0);
1220 tegra_drm_fb_exit(drm);
1223 tegra_display_hub_cleanup(tegra->hub);
1225 if (tegra->domain) {
1226 mutex_destroy(&tegra->mm_lock);
1227 drm_mm_takedown(&tegra->mm);
1228 put_iova_domain(&tegra->carveout.domain);
1232 host1x_device_exit(dev);
1234 drm_kms_helper_poll_fini(drm);
1235 tegra_drm_fb_free(drm);
1237 drm_mode_config_cleanup(drm);
1240 iommu_domain_free(tegra->domain);
1248 static int host1x_drm_remove(struct host1x_device *dev)
1250 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1251 struct tegra_drm *tegra = drm->dev_private;
1254 drm_dev_unregister(drm);
1256 drm_kms_helper_poll_fini(drm);
1257 tegra_drm_fb_exit(drm);
1258 drm_atomic_helper_shutdown(drm);
1259 drm_mode_config_cleanup(drm);
1262 tegra_display_hub_cleanup(tegra->hub);
1264 err = host1x_device_exit(dev);
1266 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1268 if (tegra->domain) {
1269 mutex_destroy(&tegra->mm_lock);
1270 drm_mm_takedown(&tegra->mm);
1271 put_iova_domain(&tegra->carveout.domain);
1273 iommu_domain_free(tegra->domain);
1282 #ifdef CONFIG_PM_SLEEP
1283 static int host1x_drm_suspend(struct device *dev)
1285 struct drm_device *drm = dev_get_drvdata(dev);
1287 return drm_mode_config_helper_suspend(drm);
1290 static int host1x_drm_resume(struct device *dev)
1292 struct drm_device *drm = dev_get_drvdata(dev);
1294 return drm_mode_config_helper_resume(drm);
1298 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1301 static const struct of_device_id host1x_drm_subdevs[] = {
1302 { .compatible = "nvidia,tegra20-dc", },
1303 { .compatible = "nvidia,tegra20-hdmi", },
1304 { .compatible = "nvidia,tegra20-gr2d", },
1305 { .compatible = "nvidia,tegra20-gr3d", },
1306 { .compatible = "nvidia,tegra30-dc", },
1307 { .compatible = "nvidia,tegra30-hdmi", },
1308 { .compatible = "nvidia,tegra30-gr2d", },
1309 { .compatible = "nvidia,tegra30-gr3d", },
1310 { .compatible = "nvidia,tegra114-dc", },
1311 { .compatible = "nvidia,tegra114-dsi", },
1312 { .compatible = "nvidia,tegra114-hdmi", },
1313 { .compatible = "nvidia,tegra114-gr2d", },
1314 { .compatible = "nvidia,tegra114-gr3d", },
1315 { .compatible = "nvidia,tegra124-dc", },
1316 { .compatible = "nvidia,tegra124-sor", },
1317 { .compatible = "nvidia,tegra124-hdmi", },
1318 { .compatible = "nvidia,tegra124-dsi", },
1319 { .compatible = "nvidia,tegra124-vic", },
1320 { .compatible = "nvidia,tegra132-dsi", },
1321 { .compatible = "nvidia,tegra210-dc", },
1322 { .compatible = "nvidia,tegra210-dsi", },
1323 { .compatible = "nvidia,tegra210-sor", },
1324 { .compatible = "nvidia,tegra210-sor1", },
1325 { .compatible = "nvidia,tegra210-vic", },
1326 { .compatible = "nvidia,tegra186-display", },
1327 { .compatible = "nvidia,tegra186-dc", },
1328 { .compatible = "nvidia,tegra186-sor", },
1329 { .compatible = "nvidia,tegra186-sor1", },
1330 { .compatible = "nvidia,tegra186-vic", },
1331 { .compatible = "nvidia,tegra194-display", },
1332 { .compatible = "nvidia,tegra194-dc", },
1333 { .compatible = "nvidia,tegra194-sor", },
1334 { .compatible = "nvidia,tegra194-vic", },
1338 static struct host1x_driver host1x_drm_driver = {
1341 .pm = &host1x_drm_pm_ops,
1343 .probe = host1x_drm_probe,
1344 .remove = host1x_drm_remove,
1345 .subdevs = host1x_drm_subdevs,
1348 static struct platform_driver * const drivers[] = {
1349 &tegra_display_hub_driver,
1353 &tegra_dpaux_driver,
1360 static int __init host1x_drm_init(void)
1364 err = host1x_driver_register(&host1x_drm_driver);
1368 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1370 goto unregister_host1x;
1375 host1x_driver_unregister(&host1x_drm_driver);
1378 module_init(host1x_drm_init);
1380 static void __exit host1x_drm_exit(void)
1382 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1383 host1x_driver_unregister(&host1x_drm_driver);
1385 module_exit(host1x_drm_exit);
1387 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1388 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1389 MODULE_LICENSE("GPL v2");