drivers/gpu/drm/tegra/dc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/iommu.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/reset.h>
  15
  16 #include <soc/tegra/pmc.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_debugfs.h>
  21 #include <drm/drm_fourcc.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include "dc.h"
  26 #include "drm.h"
  27 #include "gem.h"
  28 #include "hub.h"
  29 #include "plane.h"
  30
  31 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
  32                                             struct drm_crtc_state *state);
  33
  34 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  35 {
  36         stats->frames = 0;
  37         stats->vblank = 0;
  38         stats->underflow = 0;
  39         stats->overflow = 0;
  40 }
  41
  42 /* Reads the active copy of a register. */
  43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  44 {
  45         u32 value;
  46
  47         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  48         value = tegra_dc_readl(dc, offset);
  49         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  50
  51         return value;
  52 }
  53
  54 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  55                                               unsigned int offset)
  56 {
  57         if (offset >= 0x500 && offset <= 0x638) {
  58                 offset = 0x000 + (offset - 0x500);
  59                 return plane->offset + offset;
  60         }
  61
  62         if (offset >= 0x700 && offset <= 0x719) {
  63                 offset = 0x180 + (offset - 0x700);
  64                 return plane->offset + offset;
  65         }
  66
  67         if (offset >= 0x800 && offset <= 0x839) {
  68                 offset = 0x1c0 + (offset - 0x800);
  69                 return plane->offset + offset;
  70         }
  71
  72         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  73
  74         return plane->offset + offset;
  75 }
  76
  77 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  78                                     unsigned int offset)
  79 {
  80         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  81 }
  82
  83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  84                                       unsigned int offset)
  85 {
  86         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  87 }
  88
  89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  90 {
  91         struct device_node *np = dc->dev->of_node;
  92         struct of_phandle_iterator it;
  93         int err;
  94
  95         of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
  96                 if (it.node == dev->of_node)
  97                         return true;
  98
  99         return false;
 100 }
 101
 102 /*
 103  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 104  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 105  * Latching happens mmediately if the display controller is in STOP mode or
 106  * on the next frame boundary otherwise.
 107  *
 108  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 109  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 110  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 111  * into the ACTIVE copy, either immediately if the display controller is in
 112  * STOP mode, or at the next frame boundary otherwise.
 113  */
 114 void tegra_dc_commit(struct tegra_dc *dc)
 115 {
 116         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 117         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 118 }
 119
 120 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 121                                   unsigned int bpp)
 122 {
 123         fixed20_12 outf = dfixed_init(out);
 124         fixed20_12 inf = dfixed_init(in);
 125         u32 dda_inc;
 126         int max;
 127
 128         if (v)
 129                 max = 15;
 130         else {
 131                 switch (bpp) {
 132                 case 2:
 133                         max = 8;
 134                         break;
 135
 136                 default:
 137                         WARN_ON_ONCE(1);
 138                         fallthrough;
 139                 case 4:
 140                         max = 4;
 141                         break;
 142                 }
 143         }
 144
 145         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 146         inf.full -= dfixed_const(1);
 147
 148         dda_inc = dfixed_div(inf, outf);
 149         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 150
 151         return dda_inc;
 152 }
 153
 154 static inline u32 compute_initial_dda(unsigned int in)
 155 {
 156         fixed20_12 inf = dfixed_init(in);
 157         return dfixed_frac(inf);
 158 }
 159
 160 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 161 {
 162         u32 background[3] = {
 163                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 164                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 165                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 166         };
 167         u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 168                          BLEND_COLOR_KEY_NONE;
 169         u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 170         struct tegra_plane_state *state;
 171         u32 blending[2];
 172         unsigned int i;
 173
 174         /* disable blending for non-overlapping case */
 175         tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 176         tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 177
 178         state = to_tegra_plane_state(plane->base.state);
 179
 180         if (state->opaque) {
 181                 /*
 182                  * Since custom fix-weight blending isn't utilized and weight
 183                  * of top window is set to max, we can enforce dependent
 184                  * blending which in this case results in transparent bottom
 185                  * window if top window is opaque and if top window enables
 186                  * alpha blending, then bottom window is getting alpha value
 187                  * of 1 minus the sum of alpha components of the overlapping
 188                  * plane.
 189                  */
 190                 background[0] |= BLEND_CONTROL_DEPENDENT;
 191                 background[1] |= BLEND_CONTROL_DEPENDENT;
 192
 193                 /*
 194                  * The region where three windows overlap is the intersection
 195                  * of the two regions where two windows overlap. It contributes
 196                  * to the area if all of the windows on top of it have an alpha
 197                  * component.
 198                  */
 199                 switch (state->base.normalized_zpos) {
 200                 case 0:
 201                         if (state->blending[0].alpha &&
 202                             state->blending[1].alpha)
 203                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 204                         break;
 205
 206                 case 1:
 207                         background[2] |= BLEND_CONTROL_DEPENDENT;
 208                         break;
 209                 }
 210         } else {
 211                 /*
 212                  * Enable alpha blending if pixel format has an alpha
 213                  * component.
 214                  */
 215                 foreground |= BLEND_CONTROL_ALPHA;
 216
 217                 /*
 218                  * If any of the windows on top of this window is opaque, it
 219                  * will completely conceal this window within that area. If
 220                  * top window has an alpha component, it is blended over the
 221                  * bottom window.
 222                  */
 223                 for (i = 0; i < 2; i++) {
 224                         if (state->blending[i].alpha &&
 225                             state->blending[i].top)
 226                                 background[i] |= BLEND_CONTROL_DEPENDENT;
 227                 }
 228
 229                 switch (state->base.normalized_zpos) {
 230                 case 0:
 231                         if (state->blending[0].alpha &&
 232                             state->blending[1].alpha)
 233                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 234                         break;
 235
 236                 case 1:
 237                         /*
 238                          * When both middle and topmost windows have an alpha,
 239                          * these windows a mixed together and then the result
 240                          * is blended over the bottom window.
 241                          */
 242                         if (state->blending[0].alpha &&
 243                             state->blending[0].top)
 244                                 background[2] |= BLEND_CONTROL_ALPHA;
 245
 246                         if (state->blending[1].alpha &&
 247                             state->blending[1].top)
 248                                 background[2] |= BLEND_CONTROL_ALPHA;
 249                         break;
 250                 }
 251         }
 252
 253         switch (state->base.normalized_zpos) {
 254         case 0:
 255                 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 256                 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 257                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 258                 break;
 259
 260         case 1:
 261                 /*
 262                  * If window B / C is topmost, then X / Y registers are
 263                  * matching the order of blending[...] state indices,
 264                  * otherwise a swap is required.
 265                  */
 266                 if (!state->blending[0].top && state->blending[1].top) {
 267                         blending[0] = foreground;
 268                         blending[1] = background[1];
 269                 } else {
 270                         blending[0] = background[0];
 271                         blending[1] = foreground;
 272                 }
 273
 274                 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 275                 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 276                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 277                 break;
 278
 279         case 2:
 280                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 281                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 282                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 283                 break;
 284         }
 285 }
 286
 287 static void tegra_plane_setup_blending(struct tegra_plane *plane,
 288                                        const struct tegra_dc_window *window)
 289 {
 290         u32 value;
 291
 292         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 293                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 294                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 295         tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 296
 297         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 298                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 299                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 300         tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 301
 302         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 303         tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 304 }
 305
 306 static bool
 307 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 308                                      const struct tegra_dc_window *window)
 309 {
 310         struct tegra_dc *dc = plane->dc;
 311
 312         if (window->src.w == window->dst.w)
 313                 return false;
 314
 315         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 316                 return false;
 317
 318         return true;
 319 }
 320
 321 static bool
 322 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 323                                    const struct tegra_dc_window *window)
 324 {
 325         struct tegra_dc *dc = plane->dc;
 326
 327         if (window->src.h == window->dst.h)
 328                 return false;
 329
 330         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 331                 return false;
 332
 333         if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 334                 return false;
 335
 336         return true;
 337 }
 338
 339 static void tegra_dc_setup_window(struct tegra_plane *plane,
 340                                   const struct tegra_dc_window *window)
 341 {
 342         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 343         struct tegra_dc *dc = plane->dc;
 344         bool yuv, planar;
 345         u32 value;
 346
 347         /*
 348          * For YUV planar modes, the number of bytes per pixel takes into
 349          * account only the luma component and therefore is 1.
 350          */
 351         yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL);
 352         if (!yuv)
 353                 bpp = window->bits_per_pixel / 8;
 354         else
 355                 bpp = planar ? 1 : 2;
 356
 357         tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 358         tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 359
 360         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 361         tegra_plane_writel(plane, value, DC_WIN_POSITION);
 362
 363         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 364         tegra_plane_writel(plane, value, DC_WIN_SIZE);
 365
 366         h_offset = window->src.x * bpp;
 367         v_offset = window->src.y;
 368         h_size = window->src.w * bpp;
 369         v_size = window->src.h;
 370
 371         if (window->reflect_x)
 372                 h_offset += (window->src.w - 1) * bpp;
 373
 374         if (window->reflect_y)
 375                 v_offset += window->src.h - 1;
 376
 377         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 378         tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 379
 380         /*
 381          * For DDA computations the number of bytes per pixel for YUV planar
 382          * modes needs to take into account all Y, U and V components.
 383          */
 384         if (yuv && planar)
 385                 bpp = 2;
 386
 387         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 388         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 389
 390         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 391         tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 392
 393         h_dda = compute_initial_dda(window->src.x);
 394         v_dda = compute_initial_dda(window->src.y);
 395
 396         tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 397         tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 398
 399         tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 400         tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 401
 402         tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 403
 404         if (yuv && planar) {
 405                 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 406                 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 407                 value = window->stride[1] << 16 | window->stride[0];
 408                 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 409         } else {
 410                 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 411         }
 412
 413         tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 414         tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 415
 416         if (dc->soc->supports_block_linear) {
 417                 unsigned long height = window->tiling.value;
 418
 419                 switch (window->tiling.mode) {
 420                 case TEGRA_BO_TILING_MODE_PITCH:
 421                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 422                         break;
 423
 424                 case TEGRA_BO_TILING_MODE_TILED:
 425                         value = DC_WINBUF_SURFACE_KIND_TILED;
 426                         break;
 427
 428                 case TEGRA_BO_TILING_MODE_BLOCK:
 429                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 430                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 431                         break;
 432                 }
 433
 434                 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 435         } else {
 436                 switch (window->tiling.mode) {
 437                 case TEGRA_BO_TILING_MODE_PITCH:
 438                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 439                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 440                         break;
 441
 442                 case TEGRA_BO_TILING_MODE_TILED:
 443                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 444                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 445                         break;
 446
 447                 case TEGRA_BO_TILING_MODE_BLOCK:
 448                         /*
 449                          * No need to handle this here because ->atomic_check
 450                          * will already have filtered it out.
 451                          */
 452                         break;
 453                 }
 454
 455                 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 456         }
 457
 458         value = WIN_ENABLE;
 459
 460         if (yuv) {
 461                 /* setup default colorspace conversion coefficients */
 462                 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 463                 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 464                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 465                 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 466                 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 467                 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 468                 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 469                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 470
 471                 value |= CSC_ENABLE;
 472         } else if (window->bits_per_pixel < 24) {
 473                 value |= COLOR_EXPAND;
 474         }
 475
 476         if (window->reflect_x)
 477                 value |= H_DIRECTION;
 478
 479         if (window->reflect_y)
 480                 value |= V_DIRECTION;
 481
 482         if (tegra_plane_use_horizontal_filtering(plane, window)) {
 483                 /*
 484                  * Enable horizontal 6-tap filter and set filtering
 485                  * coefficients to the default values defined in TRM.
 486                  */
 487                 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 488                 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 489                 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 490                 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 491                 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 492                 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 493                 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 494                 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 495                 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 496                 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 497                 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 498                 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 499                 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 500                 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 501                 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 502                 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 503
 504                 value |= H_FILTER;
 505         }
 506
 507         if (tegra_plane_use_vertical_filtering(plane, window)) {
 508                 unsigned int i, k;
 509
 510                 /*
 511                  * Enable vertical 2-tap filter and set filtering
 512                  * coefficients to the default values defined in TRM.
 513                  */
 514                 for (i = 0, k = 128; i < 16; i++, k -= 8)
 515                         tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 516
 517                 value |= V_FILTER;
 518         }
 519
 520         tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 521
 522         if (dc->soc->has_legacy_blending)
 523                 tegra_plane_setup_blending_legacy(plane);
 524         else
 525                 tegra_plane_setup_blending(plane, window);
 526 }
 527
 528 static const u32 tegra20_primary_formats[] = {
 529         DRM_FORMAT_ARGB4444,
 530         DRM_FORMAT_ARGB1555,
 531         DRM_FORMAT_RGB565,
 532         DRM_FORMAT_RGBA5551,
 533         DRM_FORMAT_ABGR8888,
 534         DRM_FORMAT_ARGB8888,
 535         /* non-native formats */
 536         DRM_FORMAT_XRGB1555,
 537         DRM_FORMAT_RGBX5551,
 538         DRM_FORMAT_XBGR8888,
 539         DRM_FORMAT_XRGB8888,
 540 };
 541
 542 static const u64 tegra20_modifiers[] = {
 543         DRM_FORMAT_MOD_LINEAR,
 544         DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 545         DRM_FORMAT_MOD_INVALID
 546 };
 547
 548 static const u32 tegra114_primary_formats[] = {
 549         DRM_FORMAT_ARGB4444,
 550         DRM_FORMAT_ARGB1555,
 551         DRM_FORMAT_RGB565,
 552         DRM_FORMAT_RGBA5551,
 553         DRM_FORMAT_ABGR8888,
 554         DRM_FORMAT_ARGB8888,
 555         /* new on Tegra114 */
 556         DRM_FORMAT_ABGR4444,
 557         DRM_FORMAT_ABGR1555,
 558         DRM_FORMAT_BGRA5551,
 559         DRM_FORMAT_XRGB1555,
 560         DRM_FORMAT_RGBX5551,
 561         DRM_FORMAT_XBGR1555,
 562         DRM_FORMAT_BGRX5551,
 563         DRM_FORMAT_BGR565,
 564         DRM_FORMAT_BGRA8888,
 565         DRM_FORMAT_RGBA8888,
 566         DRM_FORMAT_XRGB8888,
 567         DRM_FORMAT_XBGR8888,
 568 };
 569
 570 static const u32 tegra124_primary_formats[] = {
 571         DRM_FORMAT_ARGB4444,
 572         DRM_FORMAT_ARGB1555,
 573         DRM_FORMAT_RGB565,
 574         DRM_FORMAT_RGBA5551,
 575         DRM_FORMAT_ABGR8888,
 576         DRM_FORMAT_ARGB8888,
 577         /* new on Tegra114 */
 578         DRM_FORMAT_ABGR4444,
 579         DRM_FORMAT_ABGR1555,
 580         DRM_FORMAT_BGRA5551,
 581         DRM_FORMAT_XRGB1555,
 582         DRM_FORMAT_RGBX5551,
 583         DRM_FORMAT_XBGR1555,
 584         DRM_FORMAT_BGRX5551,
 585         DRM_FORMAT_BGR565,
 586         DRM_FORMAT_BGRA8888,
 587         DRM_FORMAT_RGBA8888,
 588         DRM_FORMAT_XRGB8888,
 589         DRM_FORMAT_XBGR8888,
 590         /* new on Tegra124 */
 591         DRM_FORMAT_RGBX8888,
 592         DRM_FORMAT_BGRX8888,
 593 };
 594
 595 static const u64 tegra124_modifiers[] = {
 596         DRM_FORMAT_MOD_LINEAR,
 597         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 598         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 599         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 600         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 601         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 602         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 603         DRM_FORMAT_MOD_INVALID
 604 };
 605
 606 static int tegra_plane_atomic_check(struct drm_plane *plane,
 607                                     struct drm_atomic_state *state)
 608 {
 609         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 610                                                                                  plane);
 611         struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
 612         unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
 613                                           DRM_MODE_REFLECT_X |
 614                                           DRM_MODE_REFLECT_Y;
 615         unsigned int rotation = new_plane_state->rotation;
 616         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 617         struct tegra_plane *tegra = to_tegra_plane(plane);
 618         struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
 619         int err;
 620
 621         /* no need for further checks if the plane is being disabled */
 622         if (!new_plane_state->crtc)
 623                 return 0;
 624
 625         err = tegra_plane_format(new_plane_state->fb->format->format,
 626                                  &plane_state->format,
 627                                  &plane_state->swap);
 628         if (err < 0)
 629                 return err;
 630
 631         /*
 632          * Tegra20 and Tegra30 are special cases here because they support
 633          * only variants of specific formats with an alpha component, but not
 634          * the corresponding opaque formats. However, the opaque formats can
 635          * be emulated by disabling alpha blending for the plane.
 636          */
 637         if (dc->soc->has_legacy_blending) {
 638                 err = tegra_plane_setup_legacy_state(tegra, plane_state);
 639                 if (err < 0)
 640                         return err;
 641         }
 642
 643         err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
 644         if (err < 0)
 645                 return err;
 646
 647         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 648             !dc->soc->supports_block_linear) {
 649                 DRM_ERROR("hardware doesn't support block linear mode\n");
 650                 return -EINVAL;
 651         }
 652
 653         /*
 654          * Older userspace used custom BO flag in order to specify the Y
 655          * reflection, while modern userspace uses the generic DRM rotation
 656          * property in order to achieve the same result.  The legacy BO flag
 657          * duplicates the DRM rotation property when both are set.
 658          */
 659         if (tegra_fb_is_bottom_up(new_plane_state->fb))
 660                 rotation |= DRM_MODE_REFLECT_Y;
 661
 662         rotation = drm_rotation_simplify(rotation, supported_rotation);
 663
 664         if (rotation & DRM_MODE_REFLECT_X)
 665                 plane_state->reflect_x = true;
 666         else
 667                 plane_state->reflect_x = false;
 668
 669         if (rotation & DRM_MODE_REFLECT_Y)
 670                 plane_state->reflect_y = true;
 671         else
 672                 plane_state->reflect_y = false;
 673
 674         /*
 675          * Tegra doesn't support different strides for U and V planes so we
 676          * error out if the user tries to display a framebuffer with such a
 677          * configuration.
 678          */
 679         if (new_plane_state->fb->format->num_planes > 2) {
 680                 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
 681                         DRM_ERROR("unsupported UV-plane configuration\n");
 682                         return -EINVAL;
 683                 }
 684         }
 685
 686         err = tegra_plane_state_add(tegra, new_plane_state);
 687         if (err < 0)
 688                 return err;
 689
 690         return 0;
 691 }
 692
 693 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 694                                        struct drm_atomic_state *state)
 695 {
 696         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 697                                                                            plane);
 698         struct tegra_plane *p = to_tegra_plane(plane);
 699         u32 value;
 700
 701         /* rien ne va plus */
 702         if (!old_state || !old_state->crtc)
 703                 return;
 704
 705         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 706         value &= ~WIN_ENABLE;
 707         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 708 }
 709
 710 static void tegra_plane_atomic_update(struct drm_plane *plane,
 711                                       struct drm_atomic_state *state)
 712 {
 713         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 714                                                                            plane);
 715         struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 716         struct drm_framebuffer *fb = new_state->fb;
 717         struct tegra_plane *p = to_tegra_plane(plane);
 718         struct tegra_dc_window window;
 719         unsigned int i;
 720
 721         /* rien ne va plus */
 722         if (!new_state->crtc || !new_state->fb)
 723                 return;
 724
 725         if (!new_state->visible)
 726                 return tegra_plane_atomic_disable(plane, state);
 727
 728         memset(&window, 0, sizeof(window));
 729         window.src.x = new_state->src.x1 >> 16;
 730         window.src.y = new_state->src.y1 >> 16;
 731         window.src.w = drm_rect_width(&new_state->src) >> 16;
 732         window.src.h = drm_rect_height(&new_state->src) >> 16;
 733         window.dst.x = new_state->dst.x1;
 734         window.dst.y = new_state->dst.y1;
 735         window.dst.w = drm_rect_width(&new_state->dst);
 736         window.dst.h = drm_rect_height(&new_state->dst);
 737         window.bits_per_pixel = fb->format->cpp[0] * 8;
 738         window.reflect_x = tegra_plane_state->reflect_x;
 739         window.reflect_y = tegra_plane_state->reflect_y;
 740
 741         /* copy from state */
 742         window.zpos = new_state->normalized_zpos;
 743         window.tiling = tegra_plane_state->tiling;
 744         window.format = tegra_plane_state->format;
 745         window.swap = tegra_plane_state->swap;
 746
 747         for (i = 0; i < fb->format->num_planes; i++) {
 748                 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
 749
 750                 /*
 751                  * Tegra uses a shared stride for UV planes. Framebuffers are
 752                  * already checked for this in the tegra_plane_atomic_check()
 753                  * function, so it's safe to ignore the V-plane pitch here.
 754                  */
 755                 if (i < 2)
 756                         window.stride[i] = fb->pitches[i];
 757         }
 758
 759         tegra_dc_setup_window(p, &window);
 760 }
 761
 762 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 763         .prepare_fb = tegra_plane_prepare_fb,
 764         .cleanup_fb = tegra_plane_cleanup_fb,
 765         .atomic_check = tegra_plane_atomic_check,
 766         .atomic_disable = tegra_plane_atomic_disable,
 767         .atomic_update = tegra_plane_atomic_update,
 768 };
 769
 770 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 771 {
 772         /*
 773          * Ideally this would use drm_crtc_mask(), but that would require the
 774          * CRTC to already be in the mode_config's list of CRTCs. However, it
 775          * will only be added to that list in the drm_crtc_init_with_planes()
 776          * (in tegra_dc_init()), which in turn requires registration of these
 777          * planes. So we have ourselves a nice little chicken and egg problem
 778          * here.
 779          *
 780          * We work around this by manually creating the mask from the number
 781          * of CRTCs that have been registered, and should therefore always be
 782          * the same as drm_crtc_index() after registration.
 783          */
 784         return 1 << drm->mode_config.num_crtc;
 785 }
 786
 787 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 788                                                     struct tegra_dc *dc)
 789 {
 790         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 791         enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 792         struct tegra_plane *plane;
 793         unsigned int num_formats;
 794         const u64 *modifiers;
 795         const u32 *formats;
 796         int err;
 797
 798         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 799         if (!plane)
 800                 return ERR_PTR(-ENOMEM);
 801
 802         /* Always use window A as primary window */
 803         plane->offset = 0xa00;
 804         plane->index = 0;
 805         plane->dc = dc;
 806
 807         num_formats = dc->soc->num_primary_formats;
 808         formats = dc->soc->primary_formats;
 809         modifiers = dc->soc->modifiers;
 810
 811         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 812                                        &tegra_plane_funcs, formats,
 813                                        num_formats, modifiers, type, NULL);
 814         if (err < 0) {
 815                 kfree(plane);
 816                 return ERR_PTR(err);
 817         }
 818
 819         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 820         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 821
 822         err = drm_plane_create_rotation_property(&plane->base,
 823                                                  DRM_MODE_ROTATE_0,
 824                                                  DRM_MODE_ROTATE_0 |
 825                                                  DRM_MODE_ROTATE_180 |
 826                                                  DRM_MODE_REFLECT_X |
 827                                                  DRM_MODE_REFLECT_Y);
 828         if (err < 0)
 829                 dev_err(dc->dev, "failed to create rotation property: %d\n",
 830                         err);
 831
 832         return &plane->base;
 833 }
 834
 835 static const u32 tegra_legacy_cursor_plane_formats[] = {
 836         DRM_FORMAT_RGBA8888,
 837 };
 838
 839 static const u32 tegra_cursor_plane_formats[] = {
 840         DRM_FORMAT_ARGB8888,
 841 };
 842
 843 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 844                                      struct drm_atomic_state *state)
 845 {
 846         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 847                                                                                  plane);
 848         struct tegra_plane *tegra = to_tegra_plane(plane);
 849         int err;
 850
 851         /* no need for further checks if the plane is being disabled */
 852         if (!new_plane_state->crtc)
 853                 return 0;
 854
 855         /* scaling not supported for cursor */
 856         if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
 857             (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
 858                 return -EINVAL;
 859
 860         /* only square cursors supported */
 861         if (new_plane_state->src_w != new_plane_state->src_h)
 862                 return -EINVAL;
 863
 864         if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
 865             new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
 866                 return -EINVAL;
 867
 868         err = tegra_plane_state_add(tegra, new_plane_state);
 869         if (err < 0)
 870                 return err;
 871
 872         return 0;
 873 }
 874
 875 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 876                                        struct drm_atomic_state *state)
 877 {
 878         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 879                                                                            plane);
 880         struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
 881         struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
 882         struct tegra_drm *tegra = plane->dev->dev_private;
 883 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 884         u64 dma_mask = *dc->dev->dma_mask;
 885 #endif
 886         unsigned int x, y;
 887         u32 value = 0;
 888
 889         /* rien ne va plus */
 890         if (!new_state->crtc || !new_state->fb)
 891                 return;
 892
 893         /*
 894          * Legacy display supports hardware clipping of the cursor, but
 895          * nvdisplay relies on software to clip the cursor to the screen.
 896          */
 897         if (!dc->soc->has_nvdisplay)
 898                 value |= CURSOR_CLIP_DISPLAY;
 899
 900         switch (new_state->crtc_w) {
 901         case 32:
 902                 value |= CURSOR_SIZE_32x32;
 903                 break;
 904
 905         case 64:
 906                 value |= CURSOR_SIZE_64x64;
 907                 break;
 908
 909         case 128:
 910                 value |= CURSOR_SIZE_128x128;
 911                 break;
 912
 913         case 256:
 914                 value |= CURSOR_SIZE_256x256;
 915                 break;
 916
 917         default:
 918                 WARN(1, "cursor size %ux%u not supported\n",
 919                      new_state->crtc_w, new_state->crtc_h);
 920                 return;
 921         }
 922
 923         value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
 924         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 925
 926 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 927         value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
 928         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 929 #endif
 930
 931         /* enable cursor and set blend mode */
 932         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 933         value |= CURSOR_ENABLE;
 934         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 935
 936         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 937         value &= ~CURSOR_DST_BLEND_MASK;
 938         value &= ~CURSOR_SRC_BLEND_MASK;
 939
 940         if (dc->soc->has_nvdisplay)
 941                 value &= ~CURSOR_COMPOSITION_MODE_XOR;
 942         else
 943                 value |= CURSOR_MODE_NORMAL;
 944
 945         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 946         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 947         value |= CURSOR_ALPHA;
 948         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 949
 950         /* nvdisplay relies on software for clipping */
 951         if (dc->soc->has_nvdisplay) {
 952                 struct drm_rect src;
 953
 954                 x = new_state->dst.x1;
 955                 y = new_state->dst.y1;
 956
 957                 drm_rect_fp_to_int(&src, &new_state->src);
 958
 959                 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
 960                 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
 961
 962                 value = (drm_rect_height(&src) & tegra->vmask) << 16 |
 963                         (drm_rect_width(&src) & tegra->hmask);
 964                 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
 965         } else {
 966                 x = new_state->crtc_x;
 967                 y = new_state->crtc_y;
 968         }
 969
 970         /* position the cursor */
 971         value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
 972         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 973 }
 974
 975 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 976                                         struct drm_atomic_state *state)
 977 {
 978         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 979                                                                            plane);
 980         struct tegra_dc *dc;
 981         u32 value;
 982
 983         /* rien ne va plus */
 984         if (!old_state || !old_state->crtc)
 985                 return;
 986
 987         dc = to_tegra_dc(old_state->crtc);
 988
 989         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 990         value &= ~CURSOR_ENABLE;
 991         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 992 }
 993
 994 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 995         .prepare_fb = tegra_plane_prepare_fb,
 996         .cleanup_fb = tegra_plane_cleanup_fb,
 997         .atomic_check = tegra_cursor_atomic_check,
 998         .atomic_update = tegra_cursor_atomic_update,
 999         .atomic_disable = tegra_cursor_atomic_disable,
1000 };
1001
1002 static const uint64_t linear_modifiers[] = {
1003         DRM_FORMAT_MOD_LINEAR,
1004         DRM_FORMAT_MOD_INVALID
1005 };
1006
1007 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1008                                                       struct tegra_dc *dc)
1009 {
1010         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1011         struct tegra_plane *plane;
1012         unsigned int num_formats;
1013         const u32 *formats;
1014         int err;
1015
1016         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1017         if (!plane)
1018                 return ERR_PTR(-ENOMEM);
1019
1020         /*
1021          * This index is kind of fake. The cursor isn't a regular plane, but
1022          * its update and activation request bits in DC_CMD_STATE_CONTROL do
1023          * use the same programming. Setting this fake index here allows the
1024          * code in tegra_add_plane_state() to do the right thing without the
1025          * need to special-casing the cursor plane.
1026          */
1027         plane->index = 6;
1028         plane->dc = dc;
1029
1030         if (!dc->soc->has_nvdisplay) {
1031                 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1032                 formats = tegra_legacy_cursor_plane_formats;
1033         } else {
1034                 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1035                 formats = tegra_cursor_plane_formats;
1036         }
1037
1038         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1039                                        &tegra_plane_funcs, formats,
1040                                        num_formats, linear_modifiers,
1041                                        DRM_PLANE_TYPE_CURSOR, NULL);
1042         if (err < 0) {
1043                 kfree(plane);
1044                 return ERR_PTR(err);
1045         }
1046
1047         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1048         drm_plane_create_zpos_immutable_property(&plane->base, 255);
1049
1050         return &plane->base;
1051 }
1052
1053 static const u32 tegra20_overlay_formats[] = {
1054         DRM_FORMAT_ARGB4444,
1055         DRM_FORMAT_ARGB1555,
1056         DRM_FORMAT_RGB565,
1057         DRM_FORMAT_RGBA5551,
1058         DRM_FORMAT_ABGR8888,
1059         DRM_FORMAT_ARGB8888,
1060         /* non-native formats */
1061         DRM_FORMAT_XRGB1555,
1062         DRM_FORMAT_RGBX5551,
1063         DRM_FORMAT_XBGR8888,
1064         DRM_FORMAT_XRGB8888,
1065         /* planar formats */
1066         DRM_FORMAT_UYVY,
1067         DRM_FORMAT_YUYV,
1068         DRM_FORMAT_YUV420,
1069         DRM_FORMAT_YUV422,
1070 };
1071
1072 static const u32 tegra114_overlay_formats[] = {
1073         DRM_FORMAT_ARGB4444,
1074         DRM_FORMAT_ARGB1555,
1075         DRM_FORMAT_RGB565,
1076         DRM_FORMAT_RGBA5551,
1077         DRM_FORMAT_ABGR8888,
1078         DRM_FORMAT_ARGB8888,
1079         /* new on Tegra114 */
1080         DRM_FORMAT_ABGR4444,
1081         DRM_FORMAT_ABGR1555,
1082         DRM_FORMAT_BGRA5551,
1083         DRM_FORMAT_XRGB1555,
1084         DRM_FORMAT_RGBX5551,
1085         DRM_FORMAT_XBGR1555,
1086         DRM_FORMAT_BGRX5551,
1087         DRM_FORMAT_BGR565,
1088         DRM_FORMAT_BGRA8888,
1089         DRM_FORMAT_RGBA8888,
1090         DRM_FORMAT_XRGB8888,
1091         DRM_FORMAT_XBGR8888,
1092         /* planar formats */
1093         DRM_FORMAT_UYVY,
1094         DRM_FORMAT_YUYV,
1095         DRM_FORMAT_YUV420,
1096         DRM_FORMAT_YUV422,
1097 };
1098
1099 static const u32 tegra124_overlay_formats[] = {
1100         DRM_FORMAT_ARGB4444,
1101         DRM_FORMAT_ARGB1555,
1102         DRM_FORMAT_RGB565,
1103         DRM_FORMAT_RGBA5551,
1104         DRM_FORMAT_ABGR8888,
1105         DRM_FORMAT_ARGB8888,
1106         /* new on Tegra114 */
1107         DRM_FORMAT_ABGR4444,
1108         DRM_FORMAT_ABGR1555,
1109         DRM_FORMAT_BGRA5551,
1110         DRM_FORMAT_XRGB1555,
1111         DRM_FORMAT_RGBX5551,
1112         DRM_FORMAT_XBGR1555,
1113         DRM_FORMAT_BGRX5551,
1114         DRM_FORMAT_BGR565,
1115         DRM_FORMAT_BGRA8888,
1116         DRM_FORMAT_RGBA8888,
1117         DRM_FORMAT_XRGB8888,
1118         DRM_FORMAT_XBGR8888,
1119         /* new on Tegra124 */
1120         DRM_FORMAT_RGBX8888,
1121         DRM_FORMAT_BGRX8888,
1122         /* planar formats */
1123         DRM_FORMAT_UYVY,
1124         DRM_FORMAT_YUYV,
1125         DRM_FORMAT_YUV420,
1126         DRM_FORMAT_YUV422,
1127 };
1128
1129 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1130                                                        struct tegra_dc *dc,
1131                                                        unsigned int index,
1132                                                        bool cursor)
1133 {
1134         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1135         struct tegra_plane *plane;
1136         unsigned int num_formats;
1137         enum drm_plane_type type;
1138         const u32 *formats;
1139         int err;
1140
1141         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1142         if (!plane)
1143                 return ERR_PTR(-ENOMEM);
1144
1145         plane->offset = 0xa00 + 0x200 * index;
1146         plane->index = index;
1147         plane->dc = dc;
1148
1149         num_formats = dc->soc->num_overlay_formats;
1150         formats = dc->soc->overlay_formats;
1151
1152         if (!cursor)
1153                 type = DRM_PLANE_TYPE_OVERLAY;
1154         else
1155                 type = DRM_PLANE_TYPE_CURSOR;
1156
1157         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1158                                        &tegra_plane_funcs, formats,
1159                                        num_formats, linear_modifiers,
1160                                        type, NULL);
1161         if (err < 0) {
1162                 kfree(plane);
1163                 return ERR_PTR(err);
1164         }
1165
1166         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1167         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1168
1169         err = drm_plane_create_rotation_property(&plane->base,
1170                                                  DRM_MODE_ROTATE_0,
1171                                                  DRM_MODE_ROTATE_0 |
1172                                                  DRM_MODE_ROTATE_180 |
1173                                                  DRM_MODE_REFLECT_X |
1174                                                  DRM_MODE_REFLECT_Y);
1175         if (err < 0)
1176                 dev_err(dc->dev, "failed to create rotation property: %d\n",
1177                         err);
1178
1179         return &plane->base;
1180 }
1181
1182 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1183                                                     struct tegra_dc *dc)
1184 {
1185         struct drm_plane *plane, *primary = NULL;
1186         unsigned int i, j;
1187
1188         for (i = 0; i < dc->soc->num_wgrps; i++) {
1189                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1190
1191                 if (wgrp->dc == dc->pipe) {
1192                         for (j = 0; j < wgrp->num_windows; j++) {
1193                                 unsigned int index = wgrp->windows[j];
1194
1195                                 plane = tegra_shared_plane_create(drm, dc,
1196                                                                   wgrp->index,
1197                                                                   index);
1198                                 if (IS_ERR(plane))
1199                                         return plane;
1200
1201                                 /*
1202                                  * Choose the first shared plane owned by this
1203                                  * head as the primary plane.
1204                                  */
1205                                 if (!primary) {
1206                                         plane->type = DRM_PLANE_TYPE_PRIMARY;
1207                                         primary = plane;
1208                                 }
1209                         }
1210                 }
1211         }
1212
1213         return primary;
1214 }
1215
1216 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1217                                              struct tegra_dc *dc)
1218 {
1219         struct drm_plane *planes[2], *primary;
1220         unsigned int planes_num;
1221         unsigned int i;
1222         int err;
1223
1224         primary = tegra_primary_plane_create(drm, dc);
1225         if (IS_ERR(primary))
1226                 return primary;
1227
1228         if (dc->soc->supports_cursor)
1229                 planes_num = 2;
1230         else
1231                 planes_num = 1;
1232
1233         for (i = 0; i < planes_num; i++) {
1234                 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1235                                                           false);
1236                 if (IS_ERR(planes[i])) {
1237                         err = PTR_ERR(planes[i]);
1238
1239                         while (i--)
1240                                 tegra_plane_funcs.destroy(planes[i]);
1241
1242                         tegra_plane_funcs.destroy(primary);
1243                         return ERR_PTR(err);
1244                 }
1245         }
1246
1247         return primary;
1248 }
1249
1250 static void tegra_dc_destroy(struct drm_crtc *crtc)
1251 {
1252         drm_crtc_cleanup(crtc);
1253 }
1254
1255 static void tegra_crtc_reset(struct drm_crtc *crtc)
1256 {
1257         struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1258
1259         if (crtc->state)
1260                 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1261
1262         __drm_atomic_helper_crtc_reset(crtc, &state->base);
1263 }
1264
1265 static struct drm_crtc_state *
1266 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1267 {
1268         struct tegra_dc_state *state = to_dc_state(crtc->state);
1269         struct tegra_dc_state *copy;
1270
1271         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1272         if (!copy)
1273                 return NULL;
1274
1275         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1276         copy->clk = state->clk;
1277         copy->pclk = state->pclk;
1278         copy->div = state->div;
1279         copy->planes = state->planes;
1280
1281         return &copy->base;
1282 }
1283
1284 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1285                                             struct drm_crtc_state *state)
1286 {
1287         __drm_atomic_helper_crtc_destroy_state(state);
1288         kfree(state);
1289 }
1290
1291 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1292
1293 static const struct debugfs_reg32 tegra_dc_regs[] = {
1294         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1295         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1296         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1297         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1298         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1299         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1300         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1301         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1302         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1303         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1304         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1305         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1306         DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1307         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1308         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1309         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1310         DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1311         DEBUGFS_REG32(DC_CMD_INT_STATUS),
1312         DEBUGFS_REG32(DC_CMD_INT_MASK),
1313         DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1314         DEBUGFS_REG32(DC_CMD_INT_TYPE),
1315         DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1316         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1317         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1318         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1319         DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1320         DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1321         DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1322         DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1323         DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1324         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1325         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1326         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1327         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1328         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1329         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1330         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1331         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1332         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1333         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1334         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1335         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1336         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1337         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1338         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1339         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1340         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1341         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1342         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1343         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1344         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1345         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1346         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1347         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1348         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1349         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1350         DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1351         DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1352         DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1353         DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1354         DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1355         DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1356         DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1357         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1358         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1359         DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1360         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1361         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1362         DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1363         DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1364         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1365         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1366         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1367         DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1368         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1369         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1370         DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1371         DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1372         DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1373         DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1374         DEBUGFS_REG32(DC_DISP_ACTIVE),
1375         DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1376         DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1377         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1378         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1379         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1380         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1381         DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1382         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1383         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1384         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1385         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1386         DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1387         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1388         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1389         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1390         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1391         DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1392         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1393         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1394         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1395         DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1396         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1397         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1398         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1399         DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1400         DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1401         DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1402         DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1403         DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1404         DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1405         DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1406         DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1407         DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1408         DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1409         DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1410         DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1411         DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1412         DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1413         DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1414         DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1415         DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1416         DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1417         DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1418         DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1419         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1420         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1421         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1422         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1423         DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1424         DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1425         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1426         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1427         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1428         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1429         DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1430         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1431         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1432         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1433         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1434         DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1435         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1436         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1437         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1438         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1439         DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1440         DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1441         DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1442         DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1443         DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1444         DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1445         DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1446         DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1447         DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1448         DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1449         DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1450         DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1451         DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1452         DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1453         DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1454         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1455         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1456         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1457         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1458         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1459         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1460         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1461         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1462         DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1463         DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1464         DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1465         DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1466         DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1467         DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1468         DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1469         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1470         DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1471         DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1472         DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1473         DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1474         DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1475         DEBUGFS_REG32(DC_WIN_POSITION),
1476         DEBUGFS_REG32(DC_WIN_SIZE),
1477         DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1478         DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1479         DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1480         DEBUGFS_REG32(DC_WIN_DDA_INC),
1481         DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1482         DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1483         DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1484         DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1485         DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1486         DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1487         DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1488         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1489         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1490         DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1491         DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1492         DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1493         DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1494         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1495         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1496         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1497         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1498         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1499         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1500         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1501         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1502         DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1503         DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1504         DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1505         DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1506 };
1507
1508 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1509 {
1510         struct drm_info_node *node = s->private;
1511         struct tegra_dc *dc = node->info_ent->data;
1512         unsigned int i;
1513         int err = 0;
1514
1515         drm_modeset_lock(&dc->base.mutex, NULL);
1516
1517         if (!dc->base.state->active) {
1518                 err = -EBUSY;
1519                 goto unlock;
1520         }
1521
1522         for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1523                 unsigned int offset = tegra_dc_regs[i].offset;
1524
1525                 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1526                            offset, tegra_dc_readl(dc, offset));
1527         }
1528
1529 unlock:
1530         drm_modeset_unlock(&dc->base.mutex);
1531         return err;
1532 }
1533
1534 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1535 {
1536         struct drm_info_node *node = s->private;
1537         struct tegra_dc *dc = node->info_ent->data;
1538         int err = 0;
1539         u32 value;
1540
1541         drm_modeset_lock(&dc->base.mutex, NULL);
1542
1543         if (!dc->base.state->active) {
1544                 err = -EBUSY;
1545                 goto unlock;
1546         }
1547
1548         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1549         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1550         tegra_dc_commit(dc);
1551
1552         drm_crtc_wait_one_vblank(&dc->base);
1553         drm_crtc_wait_one_vblank(&dc->base);
1554
1555         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1556         seq_printf(s, "%08x\n", value);
1557
1558         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1559
1560 unlock:
1561         drm_modeset_unlock(&dc->base.mutex);
1562         return err;
1563 }
1564
1565 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1566 {
1567         struct drm_info_node *node = s->private;
1568         struct tegra_dc *dc = node->info_ent->data;
1569
1570         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1571         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1572         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1573         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1574
1575         return 0;
1576 }
1577
1578 static struct drm_info_list debugfs_files[] = {
1579         { "regs", tegra_dc_show_regs, 0, NULL },
1580         { "crc", tegra_dc_show_crc, 0, NULL },
1581         { "stats", tegra_dc_show_stats, 0, NULL },
1582 };
1583
1584 static int tegra_dc_late_register(struct drm_crtc *crtc)
1585 {
1586         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1587         struct drm_minor *minor = crtc->dev->primary;
1588         struct dentry *root;
1589         struct tegra_dc *dc = to_tegra_dc(crtc);
1590
1591 #ifdef CONFIG_DEBUG_FS
1592         root = crtc->debugfs_entry;
1593 #else
1594         root = NULL;
1595 #endif
1596
1597         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1598                                     GFP_KERNEL);
1599         if (!dc->debugfs_files)
1600                 return -ENOMEM;
1601
1602         for (i = 0; i < count; i++)
1603                 dc->debugfs_files[i].data = dc;
1604
1605         drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1606
1607         return 0;
1608 }
1609
1610 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1611 {
1612         unsigned int count = ARRAY_SIZE(debugfs_files);
1613         struct drm_minor *minor = crtc->dev->primary;
1614         struct tegra_dc *dc = to_tegra_dc(crtc);
1615
1616         drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1617         kfree(dc->debugfs_files);
1618         dc->debugfs_files = NULL;
1619 }
1620
1621 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1622 {
1623         struct tegra_dc *dc = to_tegra_dc(crtc);
1624
1625         /* XXX vblank syncpoints don't work with nvdisplay yet */
1626         if (dc->syncpt && !dc->soc->has_nvdisplay)
1627                 return host1x_syncpt_read(dc->syncpt);
1628
1629         /* fallback to software emulated VBLANK counter */
1630         return (u32)drm_crtc_vblank_count(&dc->base);
1631 }
1632
1633 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1634 {
1635         struct tegra_dc *dc = to_tegra_dc(crtc);
1636         u32 value;
1637
1638         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1639         value |= VBLANK_INT;
1640         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1641
1642         return 0;
1643 }
1644
1645 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1646 {
1647         struct tegra_dc *dc = to_tegra_dc(crtc);
1648         u32 value;
1649
1650         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1651         value &= ~VBLANK_INT;
1652         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1653 }
1654
1655 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1656         .page_flip = drm_atomic_helper_page_flip,
1657         .set_config = drm_atomic_helper_set_config,
1658         .destroy = tegra_dc_destroy,
1659         .reset = tegra_crtc_reset,
1660         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1661         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1662         .late_register = tegra_dc_late_register,
1663         .early_unregister = tegra_dc_early_unregister,
1664         .get_vblank_counter = tegra_dc_get_vblank_counter,
1665         .enable_vblank = tegra_dc_enable_vblank,
1666         .disable_vblank = tegra_dc_disable_vblank,
1667 };
1668
1669 static int tegra_dc_set_timings(struct tegra_dc *dc,
1670                                 struct drm_display_mode *mode)
1671 {
1672         unsigned int h_ref_to_sync = 1;
1673         unsigned int v_ref_to_sync = 1;
1674         unsigned long value;
1675
1676         if (!dc->soc->has_nvdisplay) {
1677                 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1678
1679                 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1680                 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1681         }
1682
1683         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1684                 ((mode->hsync_end - mode->hsync_start) <<  0);
1685         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1686
1687         value = ((mode->vtotal - mode->vsync_end) << 16) |
1688                 ((mode->htotal - mode->hsync_end) <<  0);
1689         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1690
1691         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1692                 ((mode->hsync_start - mode->hdisplay) <<  0);
1693         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1694
1695         value = (mode->vdisplay << 16) | mode->hdisplay;
1696         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1697
1698         return 0;
1699 }
1700
1701 /**
1702  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1703  *     state
1704  * @dc: display controller
1705  * @crtc_state: CRTC atomic state
1706  * @clk: parent clock for display controller
1707  * @pclk: pixel clock
1708  * @div: shift clock divider
1709  *
1710  * Returns:
1711  * 0 on success or a negative error-code on failure.
1712  */
1713 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1714                                struct drm_crtc_state *crtc_state,
1715                                struct clk *clk, unsigned long pclk,
1716                                unsigned int div)
1717 {
1718         struct tegra_dc_state *state = to_dc_state(crtc_state);
1719
1720         if (!clk_has_parent(dc->clk, clk))
1721                 return -EINVAL;
1722
1723         state->clk = clk;
1724         state->pclk = pclk;
1725         state->div = div;
1726
1727         return 0;
1728 }
1729
1730 static void tegra_dc_commit_state(struct tegra_dc *dc,
1731                                   struct tegra_dc_state *state)
1732 {
1733         u32 value;
1734         int err;
1735
1736         err = clk_set_parent(dc->clk, state->clk);
1737         if (err < 0)
1738                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1739
1740         /*
1741          * Outputs may not want to change the parent clock rate. This is only
1742          * relevant to Tegra20 where only a single display PLL is available.
1743          * Since that PLL would typically be used for HDMI, an internal LVDS
1744          * panel would need to be driven by some other clock such as PLL_P
1745          * which is shared with other peripherals. Changing the clock rate
1746          * should therefore be avoided.
1747          */
1748         if (state->pclk > 0) {
1749                 err = clk_set_rate(state->clk, state->pclk);
1750                 if (err < 0)
1751                         dev_err(dc->dev,
1752                                 "failed to set clock rate to %lu Hz\n",
1753                                 state->pclk);
1754
1755                 err = clk_set_rate(dc->clk, state->pclk);
1756                 if (err < 0)
1757                         dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1758                                 dc->clk, state->pclk, err);
1759         }
1760
1761         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1762                       state->div);
1763         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1764
1765         if (!dc->soc->has_nvdisplay) {
1766                 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1767                 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1768         }
1769 }
1770
1771 static void tegra_dc_stop(struct tegra_dc *dc)
1772 {
1773         u32 value;
1774
1775         /* stop the display controller */
1776         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1777         value &= ~DISP_CTRL_MODE_MASK;
1778         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1779
1780         tegra_dc_commit(dc);
1781 }
1782
1783 static bool tegra_dc_idle(struct tegra_dc *dc)
1784 {
1785         u32 value;
1786
1787         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1788
1789         return (value & DISP_CTRL_MODE_MASK) == 0;
1790 }
1791
1792 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1793 {
1794         timeout = jiffies + msecs_to_jiffies(timeout);
1795
1796         while (time_before(jiffies, timeout)) {
1797                 if (tegra_dc_idle(dc))
1798                         return 0;
1799
1800                 usleep_range(1000, 2000);
1801         }
1802
1803         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1804         return -ETIMEDOUT;
1805 }
1806
1807 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1808                                       struct drm_atomic_state *state)
1809 {
1810         struct tegra_dc *dc = to_tegra_dc(crtc);
1811         u32 value;
1812         int err;
1813
1814         if (!tegra_dc_idle(dc)) {
1815                 tegra_dc_stop(dc);
1816
1817                 /*
1818                  * Ignore the return value, there isn't anything useful to do
1819                  * in case this fails.
1820                  */
1821                 tegra_dc_wait_idle(dc, 100);
1822         }
1823
1824         /*
1825          * This should really be part of the RGB encoder driver, but clearing
1826          * these bits has the side-effect of stopping the display controller.
1827          * When that happens no VBLANK interrupts will be raised. At the same
1828          * time the encoder is disabled before the display controller, so the
1829          * above code is always going to timeout waiting for the controller
1830          * to go idle.
1831          *
1832          * Given the close coupling between the RGB encoder and the display
1833          * controller doing it here is still kind of okay. None of the other
1834          * encoder drivers require these bits to be cleared.
1835          *
1836          * XXX: Perhaps given that the display controller is switched off at
1837          * this point anyway maybe clearing these bits isn't even useful for
1838          * the RGB encoder?
1839          */
1840         if (dc->rgb) {
1841                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1842                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1843                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1844                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1845         }
1846
1847         tegra_dc_stats_reset(&dc->stats);
1848         drm_crtc_vblank_off(crtc);
1849
1850         spin_lock_irq(&crtc->dev->event_lock);
1851
1852         if (crtc->state->event) {
1853                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1854                 crtc->state->event = NULL;
1855         }
1856
1857         spin_unlock_irq(&crtc->dev->event_lock);
1858
1859         err = host1x_client_suspend(&dc->client);
1860         if (err < 0)
1861                 dev_err(dc->dev, "failed to suspend: %d\n", err);
1862 }
1863
1864 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1865                                      struct drm_atomic_state *state)
1866 {
1867         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1868         struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
1869         struct tegra_dc *dc = to_tegra_dc(crtc);
1870         u32 value;
1871         int err;
1872
1873         err = host1x_client_resume(&dc->client);
1874         if (err < 0) {
1875                 dev_err(dc->dev, "failed to resume: %d\n", err);
1876                 return;
1877         }
1878
1879         /* initialize display controller */
1880         if (dc->syncpt) {
1881                 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1882
1883                 if (dc->soc->has_nvdisplay)
1884                         enable = 1 << 31;
1885                 else
1886                         enable = 1 << 8;
1887
1888                 value = SYNCPT_CNTRL_NO_STALL;
1889                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1890
1891                 value = enable | syncpt;
1892                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1893         }
1894
1895         if (dc->soc->has_nvdisplay) {
1896                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1897                         DSC_OBUF_UF_INT;
1898                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1899
1900                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1901                         DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1902                         HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1903                         REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1904                         VBLANK_INT | FRAME_END_INT;
1905                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1906
1907                 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1908                         FRAME_END_INT;
1909                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1910
1911                 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1912                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1913
1914                 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1915         } else {
1916                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1917                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1918                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1919
1920                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1921                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1922                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1923
1924                 /* initialize timer */
1925                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1926                         WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1927                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1928
1929                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1930                         WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1931                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1932
1933                 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1934                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1935                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1936
1937                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1938                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1939                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1940         }
1941
1942         if (dc->soc->supports_background_color)
1943                 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1944         else
1945                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1946
1947         /* apply PLL and pixel clock changes */
1948         tegra_dc_commit_state(dc, crtc_state);
1949
1950         /* program display mode */
1951         tegra_dc_set_timings(dc, mode);
1952
1953         /* interlacing isn't supported yet, so disable it */
1954         if (dc->soc->supports_interlacing) {
1955                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1956                 value &= ~INTERLACE_ENABLE;
1957                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1958         }
1959
1960         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1961         value &= ~DISP_CTRL_MODE_MASK;
1962         value |= DISP_CTRL_MODE_C_DISPLAY;
1963         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1964
1965         if (!dc->soc->has_nvdisplay) {
1966                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1967                 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1968                          PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1969                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1970         }
1971
1972         /* enable underflow reporting and display red for missing pixels */
1973         if (dc->soc->has_nvdisplay) {
1974                 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1975                 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1976         }
1977
1978         tegra_dc_commit(dc);
1979
1980         drm_crtc_vblank_on(crtc);
1981 }
1982
1983 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1984                                     struct drm_atomic_state *state)
1985 {
1986         unsigned long flags;
1987
1988         if (crtc->state->event) {
1989                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1990
1991                 if (drm_crtc_vblank_get(crtc) != 0)
1992                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
1993                 else
1994                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1995
1996                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1997
1998                 crtc->state->event = NULL;
1999         }
2000 }
2001
2002 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2003                                     struct drm_atomic_state *state)
2004 {
2005         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2006                                                                           crtc);
2007         struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2008         struct tegra_dc *dc = to_tegra_dc(crtc);
2009         u32 value;
2010
2011         value = dc_state->planes << 8 | GENERAL_UPDATE;
2012         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2013         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2014
2015         value = dc_state->planes | GENERAL_ACT_REQ;
2016         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2017         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2018 }
2019
2020 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2021         .atomic_begin = tegra_crtc_atomic_begin,
2022         .atomic_flush = tegra_crtc_atomic_flush,
2023         .atomic_enable = tegra_crtc_atomic_enable,
2024         .atomic_disable = tegra_crtc_atomic_disable,
2025 };
2026
2027 static irqreturn_t tegra_dc_irq(int irq, void *data)
2028 {
2029         struct tegra_dc *dc = data;
2030         unsigned long status;
2031
2032         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2033         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2034
2035         if (status & FRAME_END_INT) {
2036                 /*
2037                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2038                 */
2039                 dc->stats.frames++;
2040         }
2041
2042         if (status & VBLANK_INT) {
2043                 /*
2044                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2045                 */
2046                 drm_crtc_handle_vblank(&dc->base);
2047                 dc->stats.vblank++;
2048         }
2049
2050         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2051                 /*
2052                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2053                 */
2054                 dc->stats.underflow++;
2055         }
2056
2057         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2058                 /*
2059                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2060                 */
2061                 dc->stats.overflow++;
2062         }
2063
2064         if (status & HEAD_UF_INT) {
2065                 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2066                 dc->stats.underflow++;
2067         }
2068
2069         return IRQ_HANDLED;
2070 }
2071
2072 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2073 {
2074         unsigned int i;
2075
2076         if (!dc->soc->wgrps)
2077                 return true;
2078
2079         for (i = 0; i < dc->soc->num_wgrps; i++) {
2080                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2081
2082                 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2083                         return true;
2084         }
2085
2086         return false;
2087 }
2088
2089 static int tegra_dc_early_init(struct host1x_client *client)
2090 {
2091         struct drm_device *drm = dev_get_drvdata(client->host);
2092         struct tegra_drm *tegra = drm->dev_private;
2093
2094         tegra->num_crtcs++;
2095
2096         return 0;
2097 }
2098
2099 static int tegra_dc_init(struct host1x_client *client)
2100 {
2101         struct drm_device *drm = dev_get_drvdata(client->host);
2102         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2103         struct tegra_dc *dc = host1x_client_to_dc(client);
2104         struct tegra_drm *tegra = drm->dev_private;
2105         struct drm_plane *primary = NULL;
2106         struct drm_plane *cursor = NULL;
2107         int err;
2108
2109         /*
2110          * DC has been reset by now, so VBLANK syncpoint can be released
2111          * for general use.
2112          */
2113         host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2114
2115         /*
2116          * XXX do not register DCs with no window groups because we cannot
2117          * assign a primary plane to them, which in turn will cause KMS to
2118          * crash.
2119          */
2120         if (!tegra_dc_has_window_groups(dc))
2121                 return 0;
2122
2123         /*
2124          * Set the display hub as the host1x client parent for the display
2125          * controller. This is needed for the runtime reference counting that
2126          * ensures the display hub is always powered when any of the display
2127          * controllers are.
2128          */
2129         if (dc->soc->has_nvdisplay)
2130                 client->parent = &tegra->hub->client;
2131
2132         dc->syncpt = host1x_syncpt_request(client, flags);
2133         if (!dc->syncpt)
2134                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2135
2136         err = host1x_client_iommu_attach(client);
2137         if (err < 0 && err != -ENODEV) {
2138                 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2139                 return err;
2140         }
2141
2142         if (dc->soc->wgrps)
2143                 primary = tegra_dc_add_shared_planes(drm, dc);
2144         else
2145                 primary = tegra_dc_add_planes(drm, dc);
2146
2147         if (IS_ERR(primary)) {
2148                 err = PTR_ERR(primary);
2149                 goto cleanup;
2150         }
2151
2152         if (dc->soc->supports_cursor) {
2153                 cursor = tegra_dc_cursor_plane_create(drm, dc);
2154                 if (IS_ERR(cursor)) {
2155                         err = PTR_ERR(cursor);
2156                         goto cleanup;
2157                 }
2158         } else {
2159                 /* dedicate one overlay to mouse cursor */
2160                 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2161                 if (IS_ERR(cursor)) {
2162                         err = PTR_ERR(cursor);
2163                         goto cleanup;
2164                 }
2165         }
2166
2167         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2168                                         &tegra_crtc_funcs, NULL);
2169         if (err < 0)
2170                 goto cleanup;
2171
2172         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2173
2174         /*
2175          * Keep track of the minimum pitch alignment across all display
2176          * controllers.
2177          */
2178         if (dc->soc->pitch_align > tegra->pitch_align)
2179                 tegra->pitch_align = dc->soc->pitch_align;
2180
2181         /* track maximum resolution */
2182         if (dc->soc->has_nvdisplay)
2183                 drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2184         else
2185                 drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2186
2187         err = tegra_dc_rgb_init(drm, dc);
2188         if (err < 0 && err != -ENODEV) {
2189                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2190                 goto cleanup;
2191         }
2192
2193         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2194                                dev_name(dc->dev), dc);
2195         if (err < 0) {
2196                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2197                         err);
2198                 goto cleanup;
2199         }
2200
2201         /*
2202          * Inherit the DMA parameters (such as maximum segment size) from the
2203          * parent host1x device.
2204          */
2205         client->dev->dma_parms = client->host->dma_parms;
2206
2207         return 0;
2208
2209 cleanup:
2210         if (!IS_ERR_OR_NULL(cursor))
2211                 drm_plane_cleanup(cursor);
2212
2213         if (!IS_ERR(primary))
2214                 drm_plane_cleanup(primary);
2215
2216         host1x_client_iommu_detach(client);
2217         host1x_syncpt_put(dc->syncpt);
2218
2219         return err;
2220 }
2221
2222 static int tegra_dc_exit(struct host1x_client *client)
2223 {
2224         struct tegra_dc *dc = host1x_client_to_dc(client);
2225         int err;
2226
2227         if (!tegra_dc_has_window_groups(dc))
2228                 return 0;
2229
2230         /* avoid a dangling pointer just in case this disappears */
2231         client->dev->dma_parms = NULL;
2232
2233         devm_free_irq(dc->dev, dc->irq, dc);
2234
2235         err = tegra_dc_rgb_exit(dc);
2236         if (err) {
2237                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2238                 return err;
2239         }
2240
2241         host1x_client_iommu_detach(client);
2242         host1x_syncpt_put(dc->syncpt);
2243
2244         return 0;
2245 }
2246
2247 static int tegra_dc_late_exit(struct host1x_client *client)
2248 {
2249         struct drm_device *drm = dev_get_drvdata(client->host);
2250         struct tegra_drm *tegra = drm->dev_private;
2251
2252         tegra->num_crtcs--;
2253
2254         return 0;
2255 }
2256
2257 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2258 {
2259         struct tegra_dc *dc = host1x_client_to_dc(client);
2260         struct device *dev = client->dev;
2261         int err;
2262
2263         err = reset_control_assert(dc->rst);
2264         if (err < 0) {
2265                 dev_err(dev, "failed to assert reset: %d\n", err);
2266                 return err;
2267         }
2268
2269         if (dc->soc->has_powergate)
2270                 tegra_powergate_power_off(dc->powergate);
2271
2272         clk_disable_unprepare(dc->clk);
2273         pm_runtime_put_sync(dev);
2274
2275         return 0;
2276 }
2277
2278 static int tegra_dc_runtime_resume(struct host1x_client *client)
2279 {
2280         struct tegra_dc *dc = host1x_client_to_dc(client);
2281         struct device *dev = client->dev;
2282         int err;
2283
2284         err = pm_runtime_resume_and_get(dev);
2285         if (err < 0) {
2286                 dev_err(dev, "failed to get runtime PM: %d\n", err);
2287                 return err;
2288         }
2289
2290         if (dc->soc->has_powergate) {
2291                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2292                                                         dc->rst);
2293                 if (err < 0) {
2294                         dev_err(dev, "failed to power partition: %d\n", err);
2295                         goto put_rpm;
2296                 }
2297         } else {
2298                 err = clk_prepare_enable(dc->clk);
2299                 if (err < 0) {
2300                         dev_err(dev, "failed to enable clock: %d\n", err);
2301                         goto put_rpm;
2302                 }
2303
2304                 err = reset_control_deassert(dc->rst);
2305                 if (err < 0) {
2306                         dev_err(dev, "failed to deassert reset: %d\n", err);
2307                         goto disable_clk;
2308                 }
2309         }
2310
2311         return 0;
2312
2313 disable_clk:
2314         clk_disable_unprepare(dc->clk);
2315 put_rpm:
2316         pm_runtime_put_sync(dev);
2317         return err;
2318 }
2319
2320 static const struct host1x_client_ops dc_client_ops = {
2321         .early_init = tegra_dc_early_init,
2322         .init = tegra_dc_init,
2323         .exit = tegra_dc_exit,
2324         .late_exit = tegra_dc_late_exit,
2325         .suspend = tegra_dc_runtime_suspend,
2326         .resume = tegra_dc_runtime_resume,
2327 };
2328
2329 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2330         .supports_background_color = false,
2331         .supports_interlacing = false,
2332         .supports_cursor = false,
2333         .supports_block_linear = false,
2334         .supports_sector_layout = false,
2335         .has_legacy_blending = true,
2336         .pitch_align = 8,
2337         .has_powergate = false,
2338         .coupled_pm = true,
2339         .has_nvdisplay = false,
2340         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2341         .primary_formats = tegra20_primary_formats,
2342         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2343         .overlay_formats = tegra20_overlay_formats,
2344         .modifiers = tegra20_modifiers,
2345         .has_win_a_without_filters = true,
2346         .has_win_c_without_vert_filter = true,
2347 };
2348
2349 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2350         .supports_background_color = false,
2351         .supports_interlacing = false,
2352         .supports_cursor = false,
2353         .supports_block_linear = false,
2354         .supports_sector_layout = false,
2355         .has_legacy_blending = true,
2356         .pitch_align = 8,
2357         .has_powergate = false,
2358         .coupled_pm = false,
2359         .has_nvdisplay = false,
2360         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2361         .primary_formats = tegra20_primary_formats,
2362         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2363         .overlay_formats = tegra20_overlay_formats,
2364         .modifiers = tegra20_modifiers,
2365         .has_win_a_without_filters = false,
2366         .has_win_c_without_vert_filter = false,
2367 };
2368
2369 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2370         .supports_background_color = false,
2371         .supports_interlacing = false,
2372         .supports_cursor = false,
2373         .supports_block_linear = false,
2374         .supports_sector_layout = false,
2375         .has_legacy_blending = true,
2376         .pitch_align = 64,
2377         .has_powergate = true,
2378         .coupled_pm = false,
2379         .has_nvdisplay = false,
2380         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2381         .primary_formats = tegra114_primary_formats,
2382         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2383         .overlay_formats = tegra114_overlay_formats,
2384         .modifiers = tegra20_modifiers,
2385         .has_win_a_without_filters = false,
2386         .has_win_c_without_vert_filter = false,
2387 };
2388
2389 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2390         .supports_background_color = true,
2391         .supports_interlacing = true,
2392         .supports_cursor = true,
2393         .supports_block_linear = true,
2394         .supports_sector_layout = false,
2395         .has_legacy_blending = false,
2396         .pitch_align = 64,
2397         .has_powergate = true,
2398         .coupled_pm = false,
2399         .has_nvdisplay = false,
2400         .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2401         .primary_formats = tegra124_primary_formats,
2402         .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2403         .overlay_formats = tegra124_overlay_formats,
2404         .modifiers = tegra124_modifiers,
2405         .has_win_a_without_filters = false,
2406         .has_win_c_without_vert_filter = false,
2407 };
2408
2409 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2410         .supports_background_color = true,
2411         .supports_interlacing = true,
2412         .supports_cursor = true,
2413         .supports_block_linear = true,
2414         .supports_sector_layout = false,
2415         .has_legacy_blending = false,
2416         .pitch_align = 64,
2417         .has_powergate = true,
2418         .coupled_pm = false,
2419         .has_nvdisplay = false,
2420         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2421         .primary_formats = tegra114_primary_formats,
2422         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2423         .overlay_formats = tegra114_overlay_formats,
2424         .modifiers = tegra124_modifiers,
2425         .has_win_a_without_filters = false,
2426         .has_win_c_without_vert_filter = false,
2427 };
2428
2429 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2430         {
2431                 .index = 0,
2432                 .dc = 0,
2433                 .windows = (const unsigned int[]) { 0 },
2434                 .num_windows = 1,
2435         }, {
2436                 .index = 1,
2437                 .dc = 1,
2438                 .windows = (const unsigned int[]) { 1 },
2439                 .num_windows = 1,
2440         }, {
2441                 .index = 2,
2442                 .dc = 1,
2443                 .windows = (const unsigned int[]) { 2 },
2444                 .num_windows = 1,
2445         }, {
2446                 .index = 3,
2447                 .dc = 2,
2448                 .windows = (const unsigned int[]) { 3 },
2449                 .num_windows = 1,
2450         }, {
2451                 .index = 4,
2452                 .dc = 2,
2453                 .windows = (const unsigned int[]) { 4 },
2454                 .num_windows = 1,
2455         }, {
2456                 .index = 5,
2457                 .dc = 2,
2458                 .windows = (const unsigned int[]) { 5 },
2459                 .num_windows = 1,
2460         },
2461 };
2462
2463 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2464         .supports_background_color = true,
2465         .supports_interlacing = true,
2466         .supports_cursor = true,
2467         .supports_block_linear = true,
2468         .supports_sector_layout = false,
2469         .has_legacy_blending = false,
2470         .pitch_align = 64,
2471         .has_powergate = false,
2472         .coupled_pm = false,
2473         .has_nvdisplay = true,
2474         .wgrps = tegra186_dc_wgrps,
2475         .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2476 };
2477
2478 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2479         {
2480                 .index = 0,
2481                 .dc = 0,
2482                 .windows = (const unsigned int[]) { 0 },
2483                 .num_windows = 1,
2484         }, {
2485                 .index = 1,
2486                 .dc = 1,
2487                 .windows = (const unsigned int[]) { 1 },
2488                 .num_windows = 1,
2489         }, {
2490                 .index = 2,
2491                 .dc = 1,
2492                 .windows = (const unsigned int[]) { 2 },
2493                 .num_windows = 1,
2494         }, {
2495                 .index = 3,
2496                 .dc = 2,
2497                 .windows = (const unsigned int[]) { 3 },
2498                 .num_windows = 1,
2499         }, {
2500                 .index = 4,
2501                 .dc = 2,
2502                 .windows = (const unsigned int[]) { 4 },
2503                 .num_windows = 1,
2504         }, {
2505                 .index = 5,
2506                 .dc = 2,
2507                 .windows = (const unsigned int[]) { 5 },
2508                 .num_windows = 1,
2509         },
2510 };
2511
2512 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2513         .supports_background_color = true,
2514         .supports_interlacing = true,
2515         .supports_cursor = true,
2516         .supports_block_linear = true,
2517         .supports_sector_layout = true,
2518         .has_legacy_blending = false,
2519         .pitch_align = 64,
2520         .has_powergate = false,
2521         .coupled_pm = false,
2522         .has_nvdisplay = true,
2523         .wgrps = tegra194_dc_wgrps,
2524         .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2525 };
2526
2527 static const struct of_device_id tegra_dc_of_match[] = {
2528         {
2529                 .compatible = "nvidia,tegra194-dc",
2530                 .data = &tegra194_dc_soc_info,
2531         }, {
2532                 .compatible = "nvidia,tegra186-dc",
2533                 .data = &tegra186_dc_soc_info,
2534         }, {
2535                 .compatible = "nvidia,tegra210-dc",
2536                 .data = &tegra210_dc_soc_info,
2537         }, {
2538                 .compatible = "nvidia,tegra124-dc",
2539                 .data = &tegra124_dc_soc_info,
2540         }, {
2541                 .compatible = "nvidia,tegra114-dc",
2542                 .data = &tegra114_dc_soc_info,
2543         }, {
2544                 .compatible = "nvidia,tegra30-dc",
2545                 .data = &tegra30_dc_soc_info,
2546         }, {
2547                 .compatible = "nvidia,tegra20-dc",
2548                 .data = &tegra20_dc_soc_info,
2549         }, {
2550                 /* sentinel */
2551         }
2552 };
2553 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2554
2555 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2556 {
2557         struct device_node *np;
2558         u32 value = 0;
2559         int err;
2560
2561         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2562         if (err < 0) {
2563                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2564
2565                 /*
2566                  * If the nvidia,head property isn't present, try to find the
2567                  * correct head number by looking up the position of this
2568                  * display controller's node within the device tree. Assuming
2569                  * that the nodes are ordered properly in the DTS file and
2570                  * that the translation into a flattened device tree blob
2571                  * preserves that ordering this will actually yield the right
2572                  * head number.
2573                  *
2574                  * If those assumptions don't hold, this will still work for
2575                  * cases where only a single display controller is used.
2576                  */
2577                 for_each_matching_node(np, tegra_dc_of_match) {
2578                         if (np == dc->dev->of_node) {
2579                                 of_node_put(np);
2580                                 break;
2581                         }
2582
2583                         value++;
2584                 }
2585         }
2586
2587         dc->pipe = value;
2588
2589         return 0;
2590 }
2591
2592 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2593 {
2594         struct tegra_dc *dc = dev_get_drvdata(dev);
2595         unsigned int pipe = (unsigned long)(void *)data;
2596
2597         return dc->pipe == pipe;
2598 }
2599
2600 static int tegra_dc_couple(struct tegra_dc *dc)
2601 {
2602         /*
2603          * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2604          * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2605          * POWER_CONTROL registers during CRTC enabling.
2606          */
2607         if (dc->soc->coupled_pm && dc->pipe == 1) {
2608                 struct device *companion;
2609                 struct tegra_dc *parent;
2610
2611                 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
2612                                                tegra_dc_match_by_pipe);
2613                 if (!companion)
2614                         return -EPROBE_DEFER;
2615
2616                 parent = dev_get_drvdata(companion);
2617                 dc->client.parent = &parent->client;
2618
2619                 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
2620         }
2621
2622         return 0;
2623 }
2624
2625 static int tegra_dc_probe(struct platform_device *pdev)
2626 {
2627         u64 dma_mask = dma_get_mask(pdev->dev.parent);
2628         struct tegra_dc *dc;
2629         int err;
2630
2631         err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
2632         if (err < 0) {
2633                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
2634                 return err;
2635         }
2636
2637         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2638         if (!dc)
2639                 return -ENOMEM;
2640
2641         dc->soc = of_device_get_match_data(&pdev->dev);
2642
2643         INIT_LIST_HEAD(&dc->list);
2644         dc->dev = &pdev->dev;
2645
2646         err = tegra_dc_parse_dt(dc);
2647         if (err < 0)
2648                 return err;
2649
2650         err = tegra_dc_couple(dc);
2651         if (err < 0)
2652                 return err;
2653
2654         dc->clk = devm_clk_get(&pdev->dev, NULL);
2655         if (IS_ERR(dc->clk)) {
2656                 dev_err(&pdev->dev, "failed to get clock\n");
2657                 return PTR_ERR(dc->clk);
2658         }
2659
2660         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2661         if (IS_ERR(dc->rst)) {
2662                 dev_err(&pdev->dev, "failed to get reset\n");
2663                 return PTR_ERR(dc->rst);
2664         }
2665
2666         /* assert reset and disable clock */
2667         err = clk_prepare_enable(dc->clk);
2668         if (err < 0)
2669                 return err;
2670
2671         usleep_range(2000, 4000);
2672
2673         err = reset_control_assert(dc->rst);
2674         if (err < 0)
2675                 return err;
2676
2677         usleep_range(2000, 4000);
2678
2679         clk_disable_unprepare(dc->clk);
2680
2681         if (dc->soc->has_powergate) {
2682                 if (dc->pipe == 0)
2683                         dc->powergate = TEGRA_POWERGATE_DIS;
2684                 else
2685                         dc->powergate = TEGRA_POWERGATE_DISB;
2686
2687                 tegra_powergate_power_off(dc->powergate);
2688         }
2689
2690         dc->regs = devm_platform_ioremap_resource(pdev, 0);
2691         if (IS_ERR(dc->regs))
2692                 return PTR_ERR(dc->regs);
2693
2694         dc->irq = platform_get_irq(pdev, 0);
2695         if (dc->irq < 0)
2696                 return -ENXIO;
2697
2698         err = tegra_dc_rgb_probe(dc);
2699         if (err < 0 && err != -ENODEV) {
2700                 const char *level = KERN_ERR;
2701
2702                 if (err == -EPROBE_DEFER)
2703                         level = KERN_DEBUG;
2704
2705                 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
2706                            err);
2707                 return err;
2708         }
2709
2710         platform_set_drvdata(pdev, dc);
2711         pm_runtime_enable(&pdev->dev);
2712
2713         INIT_LIST_HEAD(&dc->client.list);
2714         dc->client.ops = &dc_client_ops;
2715         dc->client.dev = &pdev->dev;
2716
2717         err = host1x_client_register(&dc->client);
2718         if (err < 0) {
2719                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2720                         err);
2721                 goto disable_pm;
2722         }
2723
2724         return 0;
2725
2726 disable_pm:
2727         pm_runtime_disable(&pdev->dev);
2728         tegra_dc_rgb_remove(dc);
2729
2730         return err;
2731 }
2732
2733 static int tegra_dc_remove(struct platform_device *pdev)
2734 {
2735         struct tegra_dc *dc = platform_get_drvdata(pdev);
2736         int err;
2737
2738         err = host1x_client_unregister(&dc->client);
2739         if (err < 0) {
2740                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2741                         err);
2742                 return err;
2743         }
2744
2745         err = tegra_dc_rgb_remove(dc);
2746         if (err < 0) {
2747                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2748                 return err;
2749         }
2750
2751         pm_runtime_disable(&pdev->dev);
2752
2753         return 0;
2754 }
2755
2756 struct platform_driver tegra_dc_driver = {
2757         .driver = {
2758                 .name = "tegra-dc",
2759                 .of_match_table = tegra_dc_of_match,
2760         },
2761         .probe = tegra_dc_probe,
2762         .remove = tegra_dc_remove,
2763 };