drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:Mark Yao <mark.yao@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/overflow.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/reset.h>
  19
  20 #include <drm/drm.h>
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_uapi.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_flip_work.h>
  25 #include <drm/drm_fourcc.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27 #include <drm/drm_plane_helper.h>
  28 #include <drm/drm_probe_helper.h>
  29 #include <drm/drm_self_refresh_helper.h>
  30 #include <drm/drm_vblank.h>
  31
  32 #ifdef CONFIG_DRM_ANALOGIX_DP
  33 #include <drm/bridge/analogix_dp.h>
  34 #endif
  35
  36 #include "rockchip_drm_drv.h"
  37 #include "rockchip_drm_gem.h"
  38 #include "rockchip_drm_fb.h"
  39 #include "rockchip_drm_vop.h"
  40 #include "rockchip_rgb.h"
  41
  42 #define VOP_WIN_SET(vop, win, name, v) \
  43                 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
  44 #define VOP_SCL_SET(vop, win, name, v) \
  45                 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
  46 #define VOP_SCL_SET_EXT(vop, win, name, v) \
  47                 vop_reg_set(vop, &win->phy->scl->ext->name, \
  48                             win->base, ~0, v, #name)
  49
  50 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
  51         do { \
  52                 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
  53                         vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
  54         } while (0)
  55
  56 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
  57         do { \
  58                 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
  59                         vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
  60         } while (0)
  61
  62 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  63                 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
  64
  65 #define VOP_REG_SET(vop, group, name, v) \
  66                     vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
  67
  68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  69         do { \
  70                 int i, reg = 0, mask = 0; \
  71                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  72                         if (vop->data->intr->intrs[i] & type) { \
  73                                 reg |= (v) << i; \
  74                                 mask |= 1 << i; \
  75                         } \
  76                 } \
  77                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
  78         } while (0)
  79 #define VOP_INTR_GET_TYPE(vop, name, type) \
  80                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  81
  82 #define VOP_WIN_GET(vop, win, name) \
  83                 vop_read_reg(vop, win->base, &win->phy->name)
  84
  85 #define VOP_WIN_HAS_REG(win, name) \
  86         (!!(win->phy->name.mask))
  87
  88 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  89                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  90
  91 #define VOP_WIN_TO_INDEX(vop_win) \
  92         ((vop_win) - (vop_win)->vop->win)
  93
  94 #define to_vop(x) container_of(x, struct vop, crtc)
  95 #define to_vop_win(x) container_of(x, struct vop_win, base)
  96
  97 /*
  98  * The coefficients of the following matrix are all fixed points.
  99  * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
 100  * They are all represented in two's complement.
 101  */
 102 static const uint32_t bt601_yuv2rgb[] = {
 103         0x4A8, 0x0,    0x662,
 104         0x4A8, 0x1E6F, 0x1CBF,
 105         0x4A8, 0x812,  0x0,
 106         0x321168, 0x0877CF, 0x2EB127
 107 };
 108
 109 enum vop_pending {
 110         VOP_PENDING_FB_UNREF,
 111 };
 112
 113 struct vop_win {
 114         struct drm_plane base;
 115         const struct vop_win_data *data;
 116         const struct vop_win_yuv2yuv_data *yuv2yuv_data;
 117         struct vop *vop;
 118 };
 119
 120 struct rockchip_rgb;
 121 struct vop {
 122         struct drm_crtc crtc;
 123         struct device *dev;
 124         struct drm_device *drm_dev;
 125         bool is_enabled;
 126
 127         struct completion dsp_hold_completion;
 128         unsigned int win_enabled;
 129
 130         /* protected by dev->event_lock */
 131         struct drm_pending_vblank_event *event;
 132
 133         struct drm_flip_work fb_unref_work;
 134         unsigned long pending;
 135
 136         struct completion line_flag_completion;
 137
 138         const struct vop_data *data;
 139
 140         uint32_t *regsbak;
 141         void __iomem *regs;
 142
 143         /* physical map length of vop register */
 144         uint32_t len;
 145
 146         /* one time only one process allowed to config the register */
 147         spinlock_t reg_lock;
 148         /* lock vop irq reg */
 149         spinlock_t irq_lock;
 150         /* protects crtc enable/disable */
 151         struct mutex vop_lock;
 152
 153         unsigned int irq;
 154
 155         /* vop AHP clk */
 156         struct clk *hclk;
 157         /* vop dclk */
 158         struct clk *dclk;
 159         /* vop share memory frequency */
 160         struct clk *aclk;
 161
 162         /* vop dclk reset */
 163         struct reset_control *dclk_rst;
 164
 165         /* optional internal rgb encoder */
 166         struct rockchip_rgb *rgb;
 167
 168         struct vop_win win[];
 169 };
 170
 171 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 172 {
 173         writel(v, vop->regs + offset);
 174         vop->regsbak[offset >> 2] = v;
 175 }
 176
 177 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 178 {
 179         return readl(vop->regs + offset);
 180 }
 181
 182 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 183                                     const struct vop_reg *reg)
 184 {
 185         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 186 }
 187
 188 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
 189                         uint32_t _offset, uint32_t _mask, uint32_t v,
 190                         const char *reg_name)
 191 {
 192         int offset, mask, shift;
 193
 194         if (!reg || !reg->mask) {
 195                 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
 196                 return;
 197         }
 198
 199         offset = reg->offset + _offset;
 200         mask = reg->mask & _mask;
 201         shift = reg->shift;
 202
 203         if (reg->write_mask) {
 204                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 205         } else {
 206                 uint32_t cached_val = vop->regsbak[offset >> 2];
 207
 208                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 209                 vop->regsbak[offset >> 2] = v;
 210         }
 211
 212         if (reg->relaxed)
 213                 writel_relaxed(v, vop->regs + offset);
 214         else
 215                 writel(v, vop->regs + offset);
 216 }
 217
 218 static inline uint32_t vop_get_intr_type(struct vop *vop,
 219                                          const struct vop_reg *reg, int type)
 220 {
 221         uint32_t i, ret = 0;
 222         uint32_t regs = vop_read_reg(vop, 0, reg);
 223
 224         for (i = 0; i < vop->data->intr->nintrs; i++) {
 225                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 226                         ret |= vop->data->intr->intrs[i];
 227         }
 228
 229         return ret;
 230 }
 231
 232 static inline void vop_cfg_done(struct vop *vop)
 233 {
 234         VOP_REG_SET(vop, common, cfg_done, 1);
 235 }
 236
 237 static bool has_rb_swapped(uint32_t format)
 238 {
 239         switch (format) {
 240         case DRM_FORMAT_XBGR8888:
 241         case DRM_FORMAT_ABGR8888:
 242         case DRM_FORMAT_BGR888:
 243         case DRM_FORMAT_BGR565:
 244                 return true;
 245         default:
 246                 return false;
 247         }
 248 }
 249
 250 static enum vop_data_format vop_convert_format(uint32_t format)
 251 {
 252         switch (format) {
 253         case DRM_FORMAT_XRGB8888:
 254         case DRM_FORMAT_ARGB8888:
 255         case DRM_FORMAT_XBGR8888:
 256         case DRM_FORMAT_ABGR8888:
 257                 return VOP_FMT_ARGB8888;
 258         case DRM_FORMAT_RGB888:
 259         case DRM_FORMAT_BGR888:
 260                 return VOP_FMT_RGB888;
 261         case DRM_FORMAT_RGB565:
 262         case DRM_FORMAT_BGR565:
 263                 return VOP_FMT_RGB565;
 264         case DRM_FORMAT_NV12:
 265                 return VOP_FMT_YUV420SP;
 266         case DRM_FORMAT_NV16:
 267                 return VOP_FMT_YUV422SP;
 268         case DRM_FORMAT_NV24:
 269                 return VOP_FMT_YUV444SP;
 270         default:
 271                 DRM_ERROR("unsupported format[%08x]\n", format);
 272                 return -EINVAL;
 273         }
 274 }
 275
 276 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 277                                   uint32_t dst, bool is_horizontal,
 278                                   int vsu_mode, int *vskiplines)
 279 {
 280         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 281
 282         if (vskiplines)
 283                 *vskiplines = 0;
 284
 285         if (is_horizontal) {
 286                 if (mode == SCALE_UP)
 287                         val = GET_SCL_FT_BIC(src, dst);
 288                 else if (mode == SCALE_DOWN)
 289                         val = GET_SCL_FT_BILI_DN(src, dst);
 290         } else {
 291                 if (mode == SCALE_UP) {
 292                         if (vsu_mode == SCALE_UP_BIL)
 293                                 val = GET_SCL_FT_BILI_UP(src, dst);
 294                         else
 295                                 val = GET_SCL_FT_BIC(src, dst);
 296                 } else if (mode == SCALE_DOWN) {
 297                         if (vskiplines) {
 298                                 *vskiplines = scl_get_vskiplines(src, dst);
 299                                 val = scl_get_bili_dn_vskip(src, dst,
 300                                                             *vskiplines);
 301                         } else {
 302                                 val = GET_SCL_FT_BILI_DN(src, dst);
 303                         }
 304                 }
 305         }
 306
 307         return val;
 308 }
 309
 310 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 311                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 312                              uint32_t dst_h, const struct drm_format_info *info)
 313 {
 314         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 315         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 316         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 317         bool is_yuv = false;
 318         uint16_t cbcr_src_w = src_w / info->hsub;
 319         uint16_t cbcr_src_h = src_h / info->vsub;
 320         uint16_t vsu_mode;
 321         uint16_t lb_mode;
 322         uint32_t val;
 323         int vskiplines;
 324
 325         if (info->is_yuv)
 326                 is_yuv = true;
 327
 328         if (dst_w > 3840) {
 329                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 330                 return;
 331         }
 332
 333         if (!win->phy->scl->ext) {
 334                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 335                             scl_cal_scale2(src_w, dst_w));
 336                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 337                             scl_cal_scale2(src_h, dst_h));
 338                 if (is_yuv) {
 339                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 340                                     scl_cal_scale2(cbcr_src_w, dst_w));
 341                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 342                                     scl_cal_scale2(cbcr_src_h, dst_h));
 343                 }
 344                 return;
 345         }
 346
 347         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 348         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 349
 350         if (is_yuv) {
 351                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 352                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 353                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 354                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 355                 else
 356                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 357         } else {
 358                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 359                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 360                 else
 361                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 362         }
 363
 364         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 365         if (lb_mode == LB_RGB_3840X2) {
 366                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 367                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 368                         return;
 369                 }
 370                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 371                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 372                         return;
 373                 }
 374                 vsu_mode = SCALE_UP_BIL;
 375         } else if (lb_mode == LB_RGB_2560X4) {
 376                 vsu_mode = SCALE_UP_BIL;
 377         } else {
 378                 vsu_mode = SCALE_UP_BIC;
 379         }
 380
 381         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 382                                 true, 0, NULL);
 383         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 384         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 385                                 false, vsu_mode, &vskiplines);
 386         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 387
 388         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 389         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 390
 391         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 392         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 393         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 394         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 395         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 396         if (is_yuv) {
 397                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 398                                         dst_w, true, 0, NULL);
 399                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 400                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 401                                         dst_h, false, vsu_mode, &vskiplines);
 402                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 403
 404                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 405                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 406                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 407                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 408                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 409                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 410                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 411         }
 412 }
 413
 414 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 415 {
 416         unsigned long flags;
 417
 418         if (WARN_ON(!vop->is_enabled))
 419                 return;
 420
 421         spin_lock_irqsave(&vop->irq_lock, flags);
 422
 423         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 424         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 425
 426         spin_unlock_irqrestore(&vop->irq_lock, flags);
 427 }
 428
 429 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 430 {
 431         unsigned long flags;
 432
 433         if (WARN_ON(!vop->is_enabled))
 434                 return;
 435
 436         spin_lock_irqsave(&vop->irq_lock, flags);
 437
 438         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 439
 440         spin_unlock_irqrestore(&vop->irq_lock, flags);
 441 }
 442
 443 /*
 444  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 445  *     the "FRAME_SYNC" interrupt.
 446  * (2) the active data region of each frame ends at dsp_vact_end
 447  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 448  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 449  *
 450  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 451  * Interrupts
 452  * LINE_FLAG -------------------------------+
 453  * FRAME_SYNC ----+                         |
 454  *                |                         |
 455  *                v                         v
 456  *                | Vsync | Vbp |  Vactive  | Vfp |
 457  *                        ^     ^           ^     ^
 458  *                        |     |           |     |
 459  *                        |     |           |     |
 460  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 461  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 462  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 463  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 464  */
 465 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 466 {
 467         uint32_t line_flag_irq;
 468         unsigned long flags;
 469
 470         spin_lock_irqsave(&vop->irq_lock, flags);
 471
 472         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 473
 474         spin_unlock_irqrestore(&vop->irq_lock, flags);
 475
 476         return !!line_flag_irq;
 477 }
 478
 479 static void vop_line_flag_irq_enable(struct vop *vop)
 480 {
 481         unsigned long flags;
 482
 483         if (WARN_ON(!vop->is_enabled))
 484                 return;
 485
 486         spin_lock_irqsave(&vop->irq_lock, flags);
 487
 488         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 489         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 490
 491         spin_unlock_irqrestore(&vop->irq_lock, flags);
 492 }
 493
 494 static void vop_line_flag_irq_disable(struct vop *vop)
 495 {
 496         unsigned long flags;
 497
 498         if (WARN_ON(!vop->is_enabled))
 499                 return;
 500
 501         spin_lock_irqsave(&vop->irq_lock, flags);
 502
 503         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 504
 505         spin_unlock_irqrestore(&vop->irq_lock, flags);
 506 }
 507
 508 static int vop_core_clks_enable(struct vop *vop)
 509 {
 510         int ret;
 511
 512         ret = clk_enable(vop->hclk);
 513         if (ret < 0)
 514                 return ret;
 515
 516         ret = clk_enable(vop->aclk);
 517         if (ret < 0)
 518                 goto err_disable_hclk;
 519
 520         return 0;
 521
 522 err_disable_hclk:
 523         clk_disable(vop->hclk);
 524         return ret;
 525 }
 526
 527 static void vop_core_clks_disable(struct vop *vop)
 528 {
 529         clk_disable(vop->aclk);
 530         clk_disable(vop->hclk);
 531 }
 532
 533 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
 534 {
 535         const struct vop_win_data *win = vop_win->data;
 536
 537         if (win->phy->scl && win->phy->scl->ext) {
 538                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 539                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 540                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 541                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 542         }
 543
 544         VOP_WIN_SET(vop, win, enable, 0);
 545         vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
 546 }
 547
 548 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
 549 {
 550         struct vop *vop = to_vop(crtc);
 551         int ret, i;
 552
 553         ret = pm_runtime_get_sync(vop->dev);
 554         if (ret < 0) {
 555                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
 556                 return ret;
 557         }
 558
 559         ret = vop_core_clks_enable(vop);
 560         if (WARN_ON(ret < 0))
 561                 goto err_put_pm_runtime;
 562
 563         ret = clk_enable(vop->dclk);
 564         if (WARN_ON(ret < 0))
 565                 goto err_disable_core;
 566
 567         /*
 568          * Slave iommu shares power, irq and clock with vop.  It was associated
 569          * automatically with this master device via common driver code.
 570          * Now that we have enabled the clock we attach it to the shared drm
 571          * mapping.
 572          */
 573         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 574         if (ret) {
 575                 DRM_DEV_ERROR(vop->dev,
 576                               "failed to attach dma mapping, %d\n", ret);
 577                 goto err_disable_dclk;
 578         }
 579
 580         spin_lock(&vop->reg_lock);
 581         for (i = 0; i < vop->len; i += 4)
 582                 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
 583
 584         /*
 585          * We need to make sure that all windows are disabled before we
 586          * enable the crtc. Otherwise we might try to scan from a destroyed
 587          * buffer later.
 588          *
 589          * In the case of enable-after-PSR, we don't need to worry about this
 590          * case since the buffer is guaranteed to be valid and disabling the
 591          * window will result in screen glitches on PSR exit.
 592          */
 593         if (!old_state || !old_state->self_refresh_active) {
 594                 for (i = 0; i < vop->data->win_size; i++) {
 595                         struct vop_win *vop_win = &vop->win[i];
 596
 597                         vop_win_disable(vop, vop_win);
 598                 }
 599         }
 600         spin_unlock(&vop->reg_lock);
 601
 602         vop_cfg_done(vop);
 603
 604         /*
 605          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 606          */
 607         vop->is_enabled = true;
 608
 609         spin_lock(&vop->reg_lock);
 610
 611         VOP_REG_SET(vop, common, standby, 1);
 612
 613         spin_unlock(&vop->reg_lock);
 614
 615         drm_crtc_vblank_on(crtc);
 616
 617         return 0;
 618
 619 err_disable_dclk:
 620         clk_disable(vop->dclk);
 621 err_disable_core:
 622         vop_core_clks_disable(vop);
 623 err_put_pm_runtime:
 624         pm_runtime_put_sync(vop->dev);
 625         return ret;
 626 }
 627
 628 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
 629 {
 630         struct vop *vop = to_vop(crtc);
 631         int i;
 632
 633         spin_lock(&vop->reg_lock);
 634
 635         for (i = 0; i < vop->data->win_size; i++) {
 636                 struct vop_win *vop_win = &vop->win[i];
 637                 const struct vop_win_data *win = vop_win->data;
 638
 639                 VOP_WIN_SET(vop, win, enable,
 640                             enabled && (vop->win_enabled & BIT(i)));
 641         }
 642         vop_cfg_done(vop);
 643
 644         spin_unlock(&vop->reg_lock);
 645 }
 646
 647 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
 648                                     struct drm_crtc_state *old_state)
 649 {
 650         struct vop *vop = to_vop(crtc);
 651
 652         WARN_ON(vop->event);
 653
 654         if (crtc->state->self_refresh_active)
 655                 rockchip_drm_set_win_enabled(crtc, false);
 656
 657         mutex_lock(&vop->vop_lock);
 658
 659         drm_crtc_vblank_off(crtc);
 660
 661         if (crtc->state->self_refresh_active)
 662                 goto out;
 663
 664         /*
 665          * Vop standby will take effect at end of current frame,
 666          * if dsp hold valid irq happen, it means standby complete.
 667          *
 668          * we must wait standby complete when we want to disable aclk,
 669          * if not, memory bus maybe dead.
 670          */
 671         reinit_completion(&vop->dsp_hold_completion);
 672         vop_dsp_hold_valid_irq_enable(vop);
 673
 674         spin_lock(&vop->reg_lock);
 675
 676         VOP_REG_SET(vop, common, standby, 1);
 677
 678         spin_unlock(&vop->reg_lock);
 679
 680         wait_for_completion(&vop->dsp_hold_completion);
 681
 682         vop_dsp_hold_valid_irq_disable(vop);
 683
 684         vop->is_enabled = false;
 685
 686         /*
 687          * vop standby complete, so iommu detach is safe.
 688          */
 689         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 690
 691         clk_disable(vop->dclk);
 692         vop_core_clks_disable(vop);
 693         pm_runtime_put(vop->dev);
 694
 695 out:
 696         mutex_unlock(&vop->vop_lock);
 697
 698         if (crtc->state->event && !crtc->state->active) {
 699                 spin_lock_irq(&crtc->dev->event_lock);
 700                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 701                 spin_unlock_irq(&crtc->dev->event_lock);
 702
 703                 crtc->state->event = NULL;
 704         }
 705 }
 706
 707 static void vop_plane_destroy(struct drm_plane *plane)
 708 {
 709         drm_plane_cleanup(plane);
 710 }
 711
 712 static int vop_plane_atomic_check(struct drm_plane *plane,
 713                            struct drm_plane_state *state)
 714 {
 715         struct drm_crtc *crtc = state->crtc;
 716         struct drm_crtc_state *crtc_state;
 717         struct drm_framebuffer *fb = state->fb;
 718         struct vop_win *vop_win = to_vop_win(plane);
 719         const struct vop_win_data *win = vop_win->data;
 720         int ret;
 721         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 722                                         DRM_PLANE_HELPER_NO_SCALING;
 723         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 724                                         DRM_PLANE_HELPER_NO_SCALING;
 725
 726         if (!crtc || !fb)
 727                 return 0;
 728
 729         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 730         if (WARN_ON(!crtc_state))
 731                 return -EINVAL;
 732
 733         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 734                                                   min_scale, max_scale,
 735                                                   true, true);
 736         if (ret)
 737                 return ret;
 738
 739         if (!state->visible)
 740                 return 0;
 741
 742         ret = vop_convert_format(fb->format->format);
 743         if (ret < 0)
 744                 return ret;
 745
 746         /*
 747          * Src.x1 can be odd when do clip, but yuv plane start point
 748          * need align with 2 pixel.
 749          */
 750         if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
 751                 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
 752                 return -EINVAL;
 753         }
 754
 755         if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
 756                 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
 757                 return -EINVAL;
 758         }
 759
 760         return 0;
 761 }
 762
 763 static void vop_plane_atomic_disable(struct drm_plane *plane,
 764                                      struct drm_plane_state *old_state)
 765 {
 766         struct vop_win *vop_win = to_vop_win(plane);
 767         struct vop *vop = to_vop(old_state->crtc);
 768
 769         if (!old_state->crtc)
 770                 return;
 771
 772         spin_lock(&vop->reg_lock);
 773
 774         vop_win_disable(vop, vop_win);
 775
 776         spin_unlock(&vop->reg_lock);
 777 }
 778
 779 static void vop_plane_atomic_update(struct drm_plane *plane,
 780                 struct drm_plane_state *old_state)
 781 {
 782         struct drm_plane_state *state = plane->state;
 783         struct drm_crtc *crtc = state->crtc;
 784         struct vop_win *vop_win = to_vop_win(plane);
 785         const struct vop_win_data *win = vop_win->data;
 786         const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
 787         struct vop *vop = to_vop(state->crtc);
 788         struct drm_framebuffer *fb = state->fb;
 789         unsigned int actual_w, actual_h;
 790         unsigned int dsp_stx, dsp_sty;
 791         uint32_t act_info, dsp_info, dsp_st;
 792         struct drm_rect *src = &state->src;
 793         struct drm_rect *dest = &state->dst;
 794         struct drm_gem_object *obj, *uv_obj;
 795         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 796         unsigned long offset;
 797         dma_addr_t dma_addr;
 798         uint32_t val;
 799         bool rb_swap;
 800         int win_index = VOP_WIN_TO_INDEX(vop_win);
 801         int format;
 802         int is_yuv = fb->format->is_yuv;
 803         int i;
 804
 805         /*
 806          * can't update plane when vop is disabled.
 807          */
 808         if (WARN_ON(!crtc))
 809                 return;
 810
 811         if (WARN_ON(!vop->is_enabled))
 812                 return;
 813
 814         if (!state->visible) {
 815                 vop_plane_atomic_disable(plane, old_state);
 816                 return;
 817         }
 818
 819         obj = fb->obj[0];
 820         rk_obj = to_rockchip_obj(obj);
 821
 822         actual_w = drm_rect_width(src) >> 16;
 823         actual_h = drm_rect_height(src) >> 16;
 824         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 825
 826         dsp_info = (drm_rect_height(dest) - 1) << 16;
 827         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 828
 829         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 830         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 831         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 832
 833         offset = (src->x1 >> 16) * fb->format->cpp[0];
 834         offset += (src->y1 >> 16) * fb->pitches[0];
 835         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 836
 837         /*
 838          * For y-mirroring we need to move address
 839          * to the beginning of the last line.
 840          */
 841         if (state->rotation & DRM_MODE_REFLECT_Y)
 842                 dma_addr += (actual_h - 1) * fb->pitches[0];
 843
 844         format = vop_convert_format(fb->format->format);
 845
 846         spin_lock(&vop->reg_lock);
 847
 848         VOP_WIN_SET(vop, win, format, format);
 849         VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
 850         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 851         VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
 852         VOP_WIN_SET(vop, win, y_mir_en,
 853                     (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
 854         VOP_WIN_SET(vop, win, x_mir_en,
 855                     (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 856
 857         if (is_yuv) {
 858                 int hsub = fb->format->hsub;
 859                 int vsub = fb->format->vsub;
 860                 int bpp = fb->format->cpp[1];
 861
 862                 uv_obj = fb->obj[1];
 863                 rk_uv_obj = to_rockchip_obj(uv_obj);
 864
 865                 offset = (src->x1 >> 16) * bpp / hsub;
 866                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 867
 868                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 869                 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 870                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 871
 872                 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
 873                         VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
 874                                                         win_yuv2yuv,
 875                                                         y2r_coefficients[i],
 876                                                         bt601_yuv2rgb[i]);
 877                 }
 878         }
 879
 880         if (win->phy->scl)
 881                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 882                                     drm_rect_width(dest), drm_rect_height(dest),
 883                                     fb->format);
 884
 885         VOP_WIN_SET(vop, win, act_info, act_info);
 886         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 887         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 888
 889         rb_swap = has_rb_swapped(fb->format->format);
 890         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 891
 892         /*
 893          * Blending win0 with the background color doesn't seem to work
 894          * correctly. We only get the background color, no matter the contents
 895          * of the win0 framebuffer.  However, blending pre-multiplied color
 896          * with the default opaque black default background color is a no-op,
 897          * so we can just disable blending to get the correct result.
 898          */
 899         if (fb->format->has_alpha && win_index > 0) {
 900                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 901                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 902                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 903                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 904                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 905                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 906                         SRC_FACTOR_M0(ALPHA_ONE);
 907                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 908         } else {
 909                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 910         }
 911
 912         VOP_WIN_SET(vop, win, enable, 1);
 913         vop->win_enabled |= BIT(win_index);
 914         spin_unlock(&vop->reg_lock);
 915 }
 916
 917 static int vop_plane_atomic_async_check(struct drm_plane *plane,
 918                                         struct drm_plane_state *state)
 919 {
 920         struct vop_win *vop_win = to_vop_win(plane);
 921         const struct vop_win_data *win = vop_win->data;
 922         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 923                                         DRM_PLANE_HELPER_NO_SCALING;
 924         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 925                                         DRM_PLANE_HELPER_NO_SCALING;
 926         struct drm_crtc_state *crtc_state;
 927
 928         if (plane != state->crtc->cursor)
 929                 return -EINVAL;
 930
 931         if (!plane->state)
 932                 return -EINVAL;
 933
 934         if (!plane->state->fb)
 935                 return -EINVAL;
 936
 937         if (state->state)
 938                 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 939                                                                 state->crtc);
 940         else /* Special case for asynchronous cursor updates. */
 941                 crtc_state = plane->crtc->state;
 942
 943         return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
 944                                                    min_scale, max_scale,
 945                                                    true, true);
 946 }
 947
 948 static void vop_plane_atomic_async_update(struct drm_plane *plane,
 949                                           struct drm_plane_state *new_state)
 950 {
 951         struct vop *vop = to_vop(plane->state->crtc);
 952         struct drm_framebuffer *old_fb = plane->state->fb;
 953
 954         plane->state->crtc_x = new_state->crtc_x;
 955         plane->state->crtc_y = new_state->crtc_y;
 956         plane->state->crtc_h = new_state->crtc_h;
 957         plane->state->crtc_w = new_state->crtc_w;
 958         plane->state->src_x = new_state->src_x;
 959         plane->state->src_y = new_state->src_y;
 960         plane->state->src_h = new_state->src_h;
 961         plane->state->src_w = new_state->src_w;
 962         swap(plane->state->fb, new_state->fb);
 963
 964         if (vop->is_enabled) {
 965                 vop_plane_atomic_update(plane, plane->state);
 966                 spin_lock(&vop->reg_lock);
 967                 vop_cfg_done(vop);
 968                 spin_unlock(&vop->reg_lock);
 969
 970                 /*
 971                  * A scanout can still be occurring, so we can't drop the
 972                  * reference to the old framebuffer. To solve this we get a
 973                  * reference to old_fb and set a worker to release it later.
 974                  * FIXME: if we perform 500 async_update calls before the
 975                  * vblank, then we can have 500 different framebuffers waiting
 976                  * to be released.
 977                  */
 978                 if (old_fb && plane->state->fb != old_fb) {
 979                         drm_framebuffer_get(old_fb);
 980                         WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
 981                         drm_flip_work_queue(&vop->fb_unref_work, old_fb);
 982                         set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
 983                 }
 984         }
 985 }
 986
 987 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 988         .atomic_check = vop_plane_atomic_check,
 989         .atomic_update = vop_plane_atomic_update,
 990         .atomic_disable = vop_plane_atomic_disable,
 991         .atomic_async_check = vop_plane_atomic_async_check,
 992         .atomic_async_update = vop_plane_atomic_async_update,
 993         .prepare_fb = drm_gem_fb_prepare_fb,
 994 };
 995
 996 static const struct drm_plane_funcs vop_plane_funcs = {
 997         .update_plane   = drm_atomic_helper_update_plane,
 998         .disable_plane  = drm_atomic_helper_disable_plane,
 999         .destroy = vop_plane_destroy,
1000         .reset = drm_atomic_helper_plane_reset,
1001         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1002         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1003 };
1004
1005 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1006 {
1007         struct vop *vop = to_vop(crtc);
1008         unsigned long flags;
1009
1010         if (WARN_ON(!vop->is_enabled))
1011                 return -EPERM;
1012
1013         spin_lock_irqsave(&vop->irq_lock, flags);
1014
1015         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1016         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1017
1018         spin_unlock_irqrestore(&vop->irq_lock, flags);
1019
1020         return 0;
1021 }
1022
1023 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1024 {
1025         struct vop *vop = to_vop(crtc);
1026         unsigned long flags;
1027
1028         if (WARN_ON(!vop->is_enabled))
1029                 return;
1030
1031         spin_lock_irqsave(&vop->irq_lock, flags);
1032
1033         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1034
1035         spin_unlock_irqrestore(&vop->irq_lock, flags);
1036 }
1037
1038 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1039                                 const struct drm_display_mode *mode,
1040                                 struct drm_display_mode *adjusted_mode)
1041 {
1042         struct vop *vop = to_vop(crtc);
1043
1044         adjusted_mode->clock =
1045                 DIV_ROUND_UP(clk_round_rate(vop->dclk,
1046                                             adjusted_mode->clock * 1000), 1000);
1047
1048         return true;
1049 }
1050
1051 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1052                                    struct drm_crtc_state *old_state)
1053 {
1054         struct vop *vop = to_vop(crtc);
1055         const struct vop_data *vop_data = vop->data;
1056         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1057         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1058         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1059         u16 hdisplay = adjusted_mode->hdisplay;
1060         u16 htotal = adjusted_mode->htotal;
1061         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1062         u16 hact_end = hact_st + hdisplay;
1063         u16 vdisplay = adjusted_mode->vdisplay;
1064         u16 vtotal = adjusted_mode->vtotal;
1065         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1066         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1067         u16 vact_end = vact_st + vdisplay;
1068         uint32_t pin_pol, val;
1069         int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1070         int ret;
1071
1072         if (old_state && old_state->self_refresh_active) {
1073                 drm_crtc_vblank_on(crtc);
1074                 rockchip_drm_set_win_enabled(crtc, true);
1075                 return;
1076         }
1077
1078         mutex_lock(&vop->vop_lock);
1079
1080         WARN_ON(vop->event);
1081
1082         ret = vop_enable(crtc, old_state);
1083         if (ret) {
1084                 mutex_unlock(&vop->vop_lock);
1085                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1086                 return;
1087         }
1088
1089         pin_pol = BIT(DCLK_INVERT);
1090         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1091                    BIT(HSYNC_POSITIVE) : 0;
1092         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1093                    BIT(VSYNC_POSITIVE) : 0;
1094         VOP_REG_SET(vop, output, pin_pol, pin_pol);
1095         VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1096
1097         switch (s->output_type) {
1098         case DRM_MODE_CONNECTOR_LVDS:
1099                 VOP_REG_SET(vop, output, rgb_en, 1);
1100                 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1101                 break;
1102         case DRM_MODE_CONNECTOR_eDP:
1103                 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1104                 VOP_REG_SET(vop, output, edp_en, 1);
1105                 break;
1106         case DRM_MODE_CONNECTOR_HDMIA:
1107                 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1108                 VOP_REG_SET(vop, output, hdmi_en, 1);
1109                 break;
1110         case DRM_MODE_CONNECTOR_DSI:
1111                 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1112                 VOP_REG_SET(vop, output, mipi_en, 1);
1113                 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1114                             !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1115                 break;
1116         case DRM_MODE_CONNECTOR_DisplayPort:
1117                 pin_pol &= ~BIT(DCLK_INVERT);
1118                 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1119                 VOP_REG_SET(vop, output, dp_en, 1);
1120                 break;
1121         default:
1122                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1123                               s->output_type);
1124         }
1125
1126         /*
1127          * if vop is not support RGB10 output, need force RGB10 to RGB888.
1128          */
1129         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1130             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1131                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1132
1133         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1134                 VOP_REG_SET(vop, common, pre_dither_down, 1);
1135         else
1136                 VOP_REG_SET(vop, common, pre_dither_down, 0);
1137
1138         if (dither_bpc == 6) {
1139                 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1140                 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1141                 VOP_REG_SET(vop, common, dither_down_en, 1);
1142         } else {
1143                 VOP_REG_SET(vop, common, dither_down_en, 0);
1144         }
1145
1146         VOP_REG_SET(vop, common, out_mode, s->output_mode);
1147
1148         VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1149         val = hact_st << 16;
1150         val |= hact_end;
1151         VOP_REG_SET(vop, modeset, hact_st_end, val);
1152         VOP_REG_SET(vop, modeset, hpost_st_end, val);
1153
1154         VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1155         val = vact_st << 16;
1156         val |= vact_end;
1157         VOP_REG_SET(vop, modeset, vact_st_end, val);
1158         VOP_REG_SET(vop, modeset, vpost_st_end, val);
1159
1160         VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1161
1162         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1163
1164         VOP_REG_SET(vop, common, standby, 0);
1165         mutex_unlock(&vop->vop_lock);
1166 }
1167
1168 static bool vop_fs_irq_is_pending(struct vop *vop)
1169 {
1170         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1171 }
1172
1173 static void vop_wait_for_irq_handler(struct vop *vop)
1174 {
1175         bool pending;
1176         int ret;
1177
1178         /*
1179          * Spin until frame start interrupt status bit goes low, which means
1180          * that interrupt handler was invoked and cleared it. The timeout of
1181          * 10 msecs is really too long, but it is just a safety measure if
1182          * something goes really wrong. The wait will only happen in the very
1183          * unlikely case of a vblank happening exactly at the same time and
1184          * shouldn't exceed microseconds range.
1185          */
1186         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1187                                         !pending, 0, 10 * 1000);
1188         if (ret)
1189                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1190
1191         synchronize_irq(vop->irq);
1192 }
1193
1194 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1195                                   struct drm_crtc_state *old_crtc_state)
1196 {
1197         struct drm_atomic_state *old_state = old_crtc_state->state;
1198         struct drm_plane_state *old_plane_state, *new_plane_state;
1199         struct vop *vop = to_vop(crtc);
1200         struct drm_plane *plane;
1201         int i;
1202
1203         if (WARN_ON(!vop->is_enabled))
1204                 return;
1205
1206         spin_lock(&vop->reg_lock);
1207
1208         vop_cfg_done(vop);
1209
1210         spin_unlock(&vop->reg_lock);
1211
1212         /*
1213          * There is a (rather unlikely) possiblity that a vblank interrupt
1214          * fired before we set the cfg_done bit. To avoid spuriously
1215          * signalling flip completion we need to wait for it to finish.
1216          */
1217         vop_wait_for_irq_handler(vop);
1218
1219         spin_lock_irq(&crtc->dev->event_lock);
1220         if (crtc->state->event) {
1221                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1222                 WARN_ON(vop->event);
1223
1224                 vop->event = crtc->state->event;
1225                 crtc->state->event = NULL;
1226         }
1227         spin_unlock_irq(&crtc->dev->event_lock);
1228
1229         for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1230                                        new_plane_state, i) {
1231                 if (!old_plane_state->fb)
1232                         continue;
1233
1234                 if (old_plane_state->fb == new_plane_state->fb)
1235                         continue;
1236
1237                 drm_framebuffer_get(old_plane_state->fb);
1238                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1239                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1240                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1241         }
1242 }
1243
1244 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1245         .mode_fixup = vop_crtc_mode_fixup,
1246         .atomic_flush = vop_crtc_atomic_flush,
1247         .atomic_enable = vop_crtc_atomic_enable,
1248         .atomic_disable = vop_crtc_atomic_disable,
1249 };
1250
1251 static void vop_crtc_destroy(struct drm_crtc *crtc)
1252 {
1253         drm_crtc_cleanup(crtc);
1254 }
1255
1256 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1257 {
1258         struct rockchip_crtc_state *rockchip_state;
1259
1260         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1261         if (!rockchip_state)
1262                 return NULL;
1263
1264         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1265         return &rockchip_state->base;
1266 }
1267
1268 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1269                                    struct drm_crtc_state *state)
1270 {
1271         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1272
1273         __drm_atomic_helper_crtc_destroy_state(&s->base);
1274         kfree(s);
1275 }
1276
1277 static void vop_crtc_reset(struct drm_crtc *crtc)
1278 {
1279         struct rockchip_crtc_state *crtc_state =
1280                 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1281
1282         if (crtc->state)
1283                 vop_crtc_destroy_state(crtc, crtc->state);
1284
1285         __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1286 }
1287
1288 #ifdef CONFIG_DRM_ANALOGIX_DP
1289 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1290 {
1291         struct drm_connector *connector;
1292         struct drm_connector_list_iter conn_iter;
1293
1294         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1295         drm_for_each_connector_iter(connector, &conn_iter) {
1296                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1297                         drm_connector_list_iter_end(&conn_iter);
1298                         return connector;
1299                 }
1300         }
1301         drm_connector_list_iter_end(&conn_iter);
1302
1303         return NULL;
1304 }
1305
1306 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1307                                    const char *source_name)
1308 {
1309         struct vop *vop = to_vop(crtc);
1310         struct drm_connector *connector;
1311         int ret;
1312
1313         connector = vop_get_edp_connector(vop);
1314         if (!connector)
1315                 return -EINVAL;
1316
1317         if (source_name && strcmp(source_name, "auto") == 0)
1318                 ret = analogix_dp_start_crc(connector);
1319         else if (!source_name)
1320                 ret = analogix_dp_stop_crc(connector);
1321         else
1322                 ret = -EINVAL;
1323
1324         return ret;
1325 }
1326
1327 static int
1328 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1329                            size_t *values_cnt)
1330 {
1331         if (source_name && strcmp(source_name, "auto") != 0)
1332                 return -EINVAL;
1333
1334         *values_cnt = 3;
1335         return 0;
1336 }
1337
1338 #else
1339 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1340                                    const char *source_name)
1341 {
1342         return -ENODEV;
1343 }
1344
1345 static int
1346 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1347                            size_t *values_cnt)
1348 {
1349         return -ENODEV;
1350 }
1351 #endif
1352
1353 static const struct drm_crtc_funcs vop_crtc_funcs = {
1354         .set_config = drm_atomic_helper_set_config,
1355         .page_flip = drm_atomic_helper_page_flip,
1356         .destroy = vop_crtc_destroy,
1357         .reset = vop_crtc_reset,
1358         .atomic_duplicate_state = vop_crtc_duplicate_state,
1359         .atomic_destroy_state = vop_crtc_destroy_state,
1360         .enable_vblank = vop_crtc_enable_vblank,
1361         .disable_vblank = vop_crtc_disable_vblank,
1362         .set_crc_source = vop_crtc_set_crc_source,
1363         .verify_crc_source = vop_crtc_verify_crc_source,
1364 };
1365
1366 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1367 {
1368         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1369         struct drm_framebuffer *fb = val;
1370
1371         drm_crtc_vblank_put(&vop->crtc);
1372         drm_framebuffer_put(fb);
1373 }
1374
1375 static void vop_handle_vblank(struct vop *vop)
1376 {
1377         struct drm_device *drm = vop->drm_dev;
1378         struct drm_crtc *crtc = &vop->crtc;
1379
1380         spin_lock(&drm->event_lock);
1381         if (vop->event) {
1382                 drm_crtc_send_vblank_event(crtc, vop->event);
1383                 drm_crtc_vblank_put(crtc);
1384                 vop->event = NULL;
1385         }
1386         spin_unlock(&drm->event_lock);
1387
1388         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1389                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1390 }
1391
1392 static irqreturn_t vop_isr(int irq, void *data)
1393 {
1394         struct vop *vop = data;
1395         struct drm_crtc *crtc = &vop->crtc;
1396         uint32_t active_irqs;
1397         int ret = IRQ_NONE;
1398
1399         /*
1400          * The irq is shared with the iommu. If the runtime-pm state of the
1401          * vop-device is disabled the irq has to be targeted at the iommu.
1402          */
1403         if (!pm_runtime_get_if_in_use(vop->dev))
1404                 return IRQ_NONE;
1405
1406         if (vop_core_clks_enable(vop)) {
1407                 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1408                 goto out;
1409         }
1410
1411         /*
1412          * interrupt register has interrupt status, enable and clear bits, we
1413          * must hold irq_lock to avoid a race with enable/disable_vblank().
1414         */
1415         spin_lock(&vop->irq_lock);
1416
1417         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1418         /* Clear all active interrupt sources */
1419         if (active_irqs)
1420                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1421
1422         spin_unlock(&vop->irq_lock);
1423
1424         /* This is expected for vop iommu irqs, since the irq is shared */
1425         if (!active_irqs)
1426                 goto out_disable;
1427
1428         if (active_irqs & DSP_HOLD_VALID_INTR) {
1429                 complete(&vop->dsp_hold_completion);
1430                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1431                 ret = IRQ_HANDLED;
1432         }
1433
1434         if (active_irqs & LINE_FLAG_INTR) {
1435                 complete(&vop->line_flag_completion);
1436                 active_irqs &= ~LINE_FLAG_INTR;
1437                 ret = IRQ_HANDLED;
1438         }
1439
1440         if (active_irqs & FS_INTR) {
1441                 drm_crtc_handle_vblank(crtc);
1442                 vop_handle_vblank(vop);
1443                 active_irqs &= ~FS_INTR;
1444                 ret = IRQ_HANDLED;
1445         }
1446
1447         /* Unhandled irqs are spurious. */
1448         if (active_irqs)
1449                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1450                               active_irqs);
1451
1452 out_disable:
1453         vop_core_clks_disable(vop);
1454 out:
1455         pm_runtime_put(vop->dev);
1456         return ret;
1457 }
1458
1459 static void vop_plane_add_properties(struct drm_plane *plane,
1460                                      const struct vop_win_data *win_data)
1461 {
1462         unsigned int flags = 0;
1463
1464         flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1465         flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1466         if (flags)
1467                 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1468                                                    DRM_MODE_ROTATE_0 | flags);
1469 }
1470
1471 static int vop_create_crtc(struct vop *vop)
1472 {
1473         const struct vop_data *vop_data = vop->data;
1474         struct device *dev = vop->dev;
1475         struct drm_device *drm_dev = vop->drm_dev;
1476         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1477         struct drm_crtc *crtc = &vop->crtc;
1478         struct device_node *port;
1479         int ret;
1480         int i;
1481
1482         /*
1483          * Create drm_plane for primary and cursor planes first, since we need
1484          * to pass them to drm_crtc_init_with_planes, which sets the
1485          * "possible_crtcs" to the newly initialized crtc.
1486          */
1487         for (i = 0; i < vop_data->win_size; i++) {
1488                 struct vop_win *vop_win = &vop->win[i];
1489                 const struct vop_win_data *win_data = vop_win->data;
1490
1491                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1492                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1493                         continue;
1494
1495                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1496                                                0, &vop_plane_funcs,
1497                                                win_data->phy->data_formats,
1498                                                win_data->phy->nformats,
1499                                                NULL, win_data->type, NULL);
1500                 if (ret) {
1501                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1502                                       ret);
1503                         goto err_cleanup_planes;
1504                 }
1505
1506                 plane = &vop_win->base;
1507                 drm_plane_helper_add(plane, &plane_helper_funcs);
1508                 vop_plane_add_properties(plane, win_data);
1509                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1510                         primary = plane;
1511                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1512                         cursor = plane;
1513         }
1514
1515         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1516                                         &vop_crtc_funcs, NULL);
1517         if (ret)
1518                 goto err_cleanup_planes;
1519
1520         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1521
1522         /*
1523          * Create drm_planes for overlay windows with possible_crtcs restricted
1524          * to the newly created crtc.
1525          */
1526         for (i = 0; i < vop_data->win_size; i++) {
1527                 struct vop_win *vop_win = &vop->win[i];
1528                 const struct vop_win_data *win_data = vop_win->data;
1529                 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1530
1531                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1532                         continue;
1533
1534                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1535                                                possible_crtcs,
1536                                                &vop_plane_funcs,
1537                                                win_data->phy->data_formats,
1538                                                win_data->phy->nformats,
1539                                                NULL, win_data->type, NULL);
1540                 if (ret) {
1541                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1542                                       ret);
1543                         goto err_cleanup_crtc;
1544                 }
1545                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1546                 vop_plane_add_properties(&vop_win->base, win_data);
1547         }
1548
1549         port = of_get_child_by_name(dev->of_node, "port");
1550         if (!port) {
1551                 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1552                               dev->of_node);
1553                 ret = -ENOENT;
1554                 goto err_cleanup_crtc;
1555         }
1556
1557         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1558                            vop_fb_unref_worker);
1559
1560         init_completion(&vop->dsp_hold_completion);
1561         init_completion(&vop->line_flag_completion);
1562         crtc->port = port;
1563
1564         ret = drm_self_refresh_helper_init(crtc);
1565         if (ret)
1566                 DRM_DEV_DEBUG_KMS(vop->dev,
1567                         "Failed to init %s with SR helpers %d, ignoring\n",
1568                         crtc->name, ret);
1569
1570         return 0;
1571
1572 err_cleanup_crtc:
1573         drm_crtc_cleanup(crtc);
1574 err_cleanup_planes:
1575         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1576                                  head)
1577                 drm_plane_cleanup(plane);
1578         return ret;
1579 }
1580
1581 static void vop_destroy_crtc(struct vop *vop)
1582 {
1583         struct drm_crtc *crtc = &vop->crtc;
1584         struct drm_device *drm_dev = vop->drm_dev;
1585         struct drm_plane *plane, *tmp;
1586
1587         drm_self_refresh_helper_cleanup(crtc);
1588
1589         of_node_put(crtc->port);
1590
1591         /*
1592          * We need to cleanup the planes now.  Why?
1593          *
1594          * The planes are "&vop->win[i].base".  That means the memory is
1595          * all part of the big "struct vop" chunk of memory.  That memory
1596          * was devm allocated and associated with this component.  We need to
1597          * free it ourselves before vop_unbind() finishes.
1598          */
1599         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1600                                  head)
1601                 vop_plane_destroy(plane);
1602
1603         /*
1604          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1605          * references the CRTC.
1606          */
1607         drm_crtc_cleanup(crtc);
1608         drm_flip_work_cleanup(&vop->fb_unref_work);
1609 }
1610
1611 static int vop_initial(struct vop *vop)
1612 {
1613         struct reset_control *ahb_rst;
1614         int i, ret;
1615
1616         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1617         if (IS_ERR(vop->hclk)) {
1618                 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1619                 return PTR_ERR(vop->hclk);
1620         }
1621         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1622         if (IS_ERR(vop->aclk)) {
1623                 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1624                 return PTR_ERR(vop->aclk);
1625         }
1626         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1627         if (IS_ERR(vop->dclk)) {
1628                 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1629                 return PTR_ERR(vop->dclk);
1630         }
1631
1632         ret = pm_runtime_get_sync(vop->dev);
1633         if (ret < 0) {
1634                 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1635                 return ret;
1636         }
1637
1638         ret = clk_prepare(vop->dclk);
1639         if (ret < 0) {
1640                 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1641                 goto err_put_pm_runtime;
1642         }
1643
1644         /* Enable both the hclk and aclk to setup the vop */
1645         ret = clk_prepare_enable(vop->hclk);
1646         if (ret < 0) {
1647                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1648                 goto err_unprepare_dclk;
1649         }
1650
1651         ret = clk_prepare_enable(vop->aclk);
1652         if (ret < 0) {
1653                 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1654                 goto err_disable_hclk;
1655         }
1656
1657         /*
1658          * do hclk_reset, reset all vop registers.
1659          */
1660         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1661         if (IS_ERR(ahb_rst)) {
1662                 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1663                 ret = PTR_ERR(ahb_rst);
1664                 goto err_disable_aclk;
1665         }
1666         reset_control_assert(ahb_rst);
1667         usleep_range(10, 20);
1668         reset_control_deassert(ahb_rst);
1669
1670         VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1671         VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1672
1673         for (i = 0; i < vop->len; i += sizeof(u32))
1674                 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1675
1676         VOP_REG_SET(vop, misc, global_regdone_en, 1);
1677         VOP_REG_SET(vop, common, dsp_blank, 0);
1678
1679         for (i = 0; i < vop->data->win_size; i++) {
1680                 struct vop_win *vop_win = &vop->win[i];
1681                 const struct vop_win_data *win = vop_win->data;
1682                 int channel = i * 2 + 1;
1683
1684                 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1685                 vop_win_disable(vop, vop_win);
1686                 VOP_WIN_SET(vop, win, gate, 1);
1687         }
1688
1689         vop_cfg_done(vop);
1690
1691         /*
1692          * do dclk_reset, let all config take affect.
1693          */
1694         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1695         if (IS_ERR(vop->dclk_rst)) {
1696                 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1697                 ret = PTR_ERR(vop->dclk_rst);
1698                 goto err_disable_aclk;
1699         }
1700         reset_control_assert(vop->dclk_rst);
1701         usleep_range(10, 20);
1702         reset_control_deassert(vop->dclk_rst);
1703
1704         clk_disable(vop->hclk);
1705         clk_disable(vop->aclk);
1706
1707         vop->is_enabled = false;
1708
1709         pm_runtime_put_sync(vop->dev);
1710
1711         return 0;
1712
1713 err_disable_aclk:
1714         clk_disable_unprepare(vop->aclk);
1715 err_disable_hclk:
1716         clk_disable_unprepare(vop->hclk);
1717 err_unprepare_dclk:
1718         clk_unprepare(vop->dclk);
1719 err_put_pm_runtime:
1720         pm_runtime_put_sync(vop->dev);
1721         return ret;
1722 }
1723
1724 /*
1725  * Initialize the vop->win array elements.
1726  */
1727 static void vop_win_init(struct vop *vop)
1728 {
1729         const struct vop_data *vop_data = vop->data;
1730         unsigned int i;
1731
1732         for (i = 0; i < vop_data->win_size; i++) {
1733                 struct vop_win *vop_win = &vop->win[i];
1734                 const struct vop_win_data *win_data = &vop_data->win[i];
1735
1736                 vop_win->data = win_data;
1737                 vop_win->vop = vop;
1738
1739                 if (vop_data->win_yuv2yuv)
1740                         vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
1741         }
1742 }
1743
1744 /**
1745  * rockchip_drm_wait_vact_end
1746  * @crtc: CRTC to enable line flag
1747  * @mstimeout: millisecond for timeout
1748  *
1749  * Wait for vact_end line flag irq or timeout.
1750  *
1751  * Returns:
1752  * Zero on success, negative errno on failure.
1753  */
1754 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1755 {
1756         struct vop *vop = to_vop(crtc);
1757         unsigned long jiffies_left;
1758         int ret = 0;
1759
1760         if (!crtc || !vop->is_enabled)
1761                 return -ENODEV;
1762
1763         mutex_lock(&vop->vop_lock);
1764         if (mstimeout <= 0) {
1765                 ret = -EINVAL;
1766                 goto out;
1767         }
1768
1769         if (vop_line_flag_irq_is_enabled(vop)) {
1770                 ret = -EBUSY;
1771                 goto out;
1772         }
1773
1774         reinit_completion(&vop->line_flag_completion);
1775         vop_line_flag_irq_enable(vop);
1776
1777         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1778                                                    msecs_to_jiffies(mstimeout));
1779         vop_line_flag_irq_disable(vop);
1780
1781         if (jiffies_left == 0) {
1782                 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1783                 ret = -ETIMEDOUT;
1784                 goto out;
1785         }
1786
1787 out:
1788         mutex_unlock(&vop->vop_lock);
1789         return ret;
1790 }
1791 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1792
1793 static int vop_bind(struct device *dev, struct device *master, void *data)
1794 {
1795         struct platform_device *pdev = to_platform_device(dev);
1796         const struct vop_data *vop_data;
1797         struct drm_device *drm_dev = data;
1798         struct vop *vop;
1799         struct resource *res;
1800         int ret, irq;
1801
1802         vop_data = of_device_get_match_data(dev);
1803         if (!vop_data)
1804                 return -ENODEV;
1805
1806         /* Allocate vop struct and its vop_win array */
1807         vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1808                            GFP_KERNEL);
1809         if (!vop)
1810                 return -ENOMEM;
1811
1812         vop->dev = dev;
1813         vop->data = vop_data;
1814         vop->drm_dev = drm_dev;
1815         dev_set_drvdata(dev, vop);
1816
1817         vop_win_init(vop);
1818
1819         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820         vop->len = resource_size(res);
1821         vop->regs = devm_ioremap_resource(dev, res);
1822         if (IS_ERR(vop->regs))
1823                 return PTR_ERR(vop->regs);
1824
1825         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1826         if (!vop->regsbak)
1827                 return -ENOMEM;
1828
1829         irq = platform_get_irq(pdev, 0);
1830         if (irq < 0) {
1831                 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1832                 return irq;
1833         }
1834         vop->irq = (unsigned int)irq;
1835
1836         spin_lock_init(&vop->reg_lock);
1837         spin_lock_init(&vop->irq_lock);
1838         mutex_init(&vop->vop_lock);
1839
1840         ret = vop_create_crtc(vop);
1841         if (ret)
1842                 return ret;
1843
1844         pm_runtime_enable(&pdev->dev);
1845
1846         ret = vop_initial(vop);
1847         if (ret < 0) {
1848                 DRM_DEV_ERROR(&pdev->dev,
1849                               "cannot initial vop dev - err %d\n", ret);
1850                 goto err_disable_pm_runtime;
1851         }
1852
1853         ret = devm_request_irq(dev, vop->irq, vop_isr,
1854                                IRQF_SHARED, dev_name(dev), vop);
1855         if (ret)
1856                 goto err_disable_pm_runtime;
1857
1858         if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1859                 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1860                 if (IS_ERR(vop->rgb)) {
1861                         ret = PTR_ERR(vop->rgb);
1862                         goto err_disable_pm_runtime;
1863                 }
1864         }
1865
1866         return 0;
1867
1868 err_disable_pm_runtime:
1869         pm_runtime_disable(&pdev->dev);
1870         vop_destroy_crtc(vop);
1871         return ret;
1872 }
1873
1874 static void vop_unbind(struct device *dev, struct device *master, void *data)
1875 {
1876         struct vop *vop = dev_get_drvdata(dev);
1877
1878         if (vop->rgb)
1879                 rockchip_rgb_fini(vop->rgb);
1880
1881         pm_runtime_disable(dev);
1882         vop_destroy_crtc(vop);
1883
1884         clk_unprepare(vop->aclk);
1885         clk_unprepare(vop->hclk);
1886         clk_unprepare(vop->dclk);
1887 }
1888
1889 const struct component_ops vop_component_ops = {
1890         .bind = vop_bind,
1891         .unbind = vop_unbind,
1892 };
1893 EXPORT_SYMBOL_GPL(vop_component_ops);