5 * \author Gareth Hughes <gareth@valinux.com>
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
33 #include <linux/compat.h>
34 #include <linux/console.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/pci.h>
41 #include <drm/drm_aperture.h>
42 #include <drm/drm_agpsupport.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_drv.h>
45 #include <drm/drm_fb_helper.h>
46 #include <drm/drm_file.h>
47 #include <drm/drm_gem.h>
48 #include <drm/drm_ioctl.h>
49 #include <drm/drm_pciids.h>
50 #include <drm/drm_probe_helper.h>
51 #include <drm/drm_vblank.h>
52 #include <drm/radeon_drm.h>
54 #include "radeon_drv.h"
56 #include "radeon_kms.h"
57 #include "radeon_ttm.h"
58 #include "radeon_device.h"
59 #include "radeon_prime.h"
63 * - 2.0.0 - initial interface
64 * - 2.1.0 - add square tiling interface
65 * - 2.2.0 - add r6xx/r7xx const buffer support
66 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
67 * - 2.4.0 - add crtc id query
68 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
69 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
70 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
71 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
72 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
73 * 2.10.0 - fusion 2D tiling
74 * 2.11.0 - backend map, initial compute support for the CS checker
75 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
76 * 2.13.0 - virtual memory support, streamout
77 * 2.14.0 - add evergreen tiling informations
78 * 2.15.0 - add max_pipes query
79 * 2.16.0 - fix evergreen 2D tiled surface calculation
80 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
81 * 2.18.0 - r600-eg: allow "invalid" DB formats
82 * 2.19.0 - r600-eg: MSAA textures
83 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
84 * 2.21.0 - r600-r700: FMASK and CMASK
85 * 2.22.0 - r600 only: RESOLVE_BOX allowed
86 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
87 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
88 * 2.25.0 - eg+: new info request for num SE and num SH
89 * 2.26.0 - r600-eg: fix htile size computation
90 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
91 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
92 * 2.29.0 - R500 FP16 color clear registers
93 * 2.30.0 - fix for FMASK texturing
94 * 2.31.0 - Add fastfb support for rs690
95 * 2.32.0 - new info request for rings working
96 * 2.33.0 - Add SI tiling mode array query
97 * 2.34.0 - Add CIK tiling mode array query
98 * 2.35.0 - Add CIK macrotile mode array query
99 * 2.36.0 - Fix CIK DCE tiling setup
100 * 2.37.0 - allow GS ring setup on r6xx/r7xx
101 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
102 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
103 * 2.39.0 - Add INFO query for number of active CUs
104 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
105 * CS to GPU on >= r600
106 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
107 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
108 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
109 * 2.44.0 - SET_APPEND_CNT packet3 support
110 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
111 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
112 * 2.47.0 - Add UVD_NO_OP register support
113 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
114 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
115 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
117 #define KMS_DRIVER_MAJOR 2
118 #define KMS_DRIVER_MINOR 50
119 #define KMS_DRIVER_PATCHLEVEL 0
120 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
121 bool fbcon, bool freeze);
122 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
123 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
124 unsigned int flags, int *vpos, int *hpos,
125 ktime_t *stime, ktime_t *etime,
126 const struct drm_display_mode *mode);
127 extern bool radeon_is_px(struct drm_device *dev);
128 int radeon_mode_dumb_mmap(struct drm_file *filp,
129 struct drm_device *dev,
130 uint32_t handle, uint64_t *offset_p);
131 int radeon_mode_dumb_create(struct drm_file *file_priv,
132 struct drm_device *dev,
133 struct drm_mode_create_dumb *args);
136 #if defined(CONFIG_VGA_SWITCHEROO)
137 void radeon_register_atpx_handler(void);
138 void radeon_unregister_atpx_handler(void);
139 bool radeon_has_atpx_dgpu_power_cntl(void);
140 bool radeon_is_atpx_hybrid(void);
142 static inline void radeon_register_atpx_handler(void) {}
143 static inline void radeon_unregister_atpx_handler(void) {}
144 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
145 static inline bool radeon_is_atpx_hybrid(void) { return false; }
149 int radeon_modeset = -1;
150 int radeon_dynclks = -1;
151 int radeon_r4xx_atom = 0;
152 int radeon_agpmode = -1;
153 int radeon_vram_limit = 0;
154 int radeon_gart_size = -1; /* auto */
155 int radeon_benchmarking = 0;
156 int radeon_testing = 0;
157 int radeon_connector_table = 0;
159 int radeon_audio = -1;
160 int radeon_disp_priority = 0;
161 int radeon_hw_i2c = 0;
162 int radeon_pcie_gen2 = -1;
164 int radeon_lockup_timeout = 10000;
165 int radeon_fastfb = 0;
167 int radeon_aspm = -1;
168 int radeon_runtime_pm = -1;
169 int radeon_hard_reset = 0;
170 int radeon_vm_size = 8;
171 int radeon_vm_block_size = -1;
172 int radeon_deep_color = 0;
173 int radeon_use_pflipirq = 2;
174 int radeon_bapm = -1;
175 int radeon_backlight = -1;
176 int radeon_auxch = -1;
181 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
182 module_param_named(no_wb, radeon_no_wb, int, 0444);
184 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
185 module_param_named(modeset, radeon_modeset, int, 0400);
187 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
188 module_param_named(dynclks, radeon_dynclks, int, 0444);
190 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
191 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
193 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
194 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
196 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
197 module_param_named(agpmode, radeon_agpmode, int, 0444);
199 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
200 module_param_named(gartsize, radeon_gart_size, int, 0600);
202 MODULE_PARM_DESC(benchmark, "Run benchmark");
203 module_param_named(benchmark, radeon_benchmarking, int, 0444);
205 MODULE_PARM_DESC(test, "Run tests");
206 module_param_named(test, radeon_testing, int, 0444);
208 MODULE_PARM_DESC(connector_table, "Force connector table");
209 module_param_named(connector_table, radeon_connector_table, int, 0444);
211 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
212 module_param_named(tv, radeon_tv, int, 0444);
214 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
215 module_param_named(audio, radeon_audio, int, 0444);
217 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
218 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
220 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
221 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
223 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
224 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
226 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
227 module_param_named(msi, radeon_msi, int, 0444);
229 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
230 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
232 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
233 module_param_named(fastfb, radeon_fastfb, int, 0444);
235 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
236 module_param_named(dpm, radeon_dpm, int, 0444);
238 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
239 module_param_named(aspm, radeon_aspm, int, 0444);
241 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
242 module_param_named(runpm, radeon_runtime_pm, int, 0444);
244 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
245 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
247 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
248 module_param_named(vm_size, radeon_vm_size, int, 0444);
250 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
251 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
253 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
254 module_param_named(deep_color, radeon_deep_color, int, 0444);
256 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
257 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
259 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
260 module_param_named(bapm, radeon_bapm, int, 0444);
262 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
263 module_param_named(backlight, radeon_backlight, int, 0444);
265 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
266 module_param_named(auxch, radeon_auxch, int, 0444);
268 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
269 module_param_named(mst, radeon_mst, int, 0444);
271 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
272 module_param_named(uvd, radeon_uvd, int, 0444);
274 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
275 module_param_named(vce, radeon_vce, int, 0444);
277 int radeon_si_support = 1;
278 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
279 module_param_named(si_support, radeon_si_support, int, 0444);
281 int radeon_cik_support = 1;
282 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
283 module_param_named(cik_support, radeon_cik_support, int, 0444);
285 static struct pci_device_id pciidlist[] = {
289 MODULE_DEVICE_TABLE(pci, pciidlist);
291 static const struct drm_driver kms_driver;
293 static int radeon_pci_probe(struct pci_dev *pdev,
294 const struct pci_device_id *ent)
296 unsigned long flags = 0;
297 struct drm_device *dev;
301 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
303 flags = ent->driver_data;
305 if (!radeon_si_support) {
306 switch (flags & RADEON_FAMILY_MASK) {
313 "SI support disabled by module param\n");
317 if (!radeon_cik_support) {
318 switch (flags & RADEON_FAMILY_MASK) {
325 "CIK support disabled by module param\n");
330 if (vga_switcheroo_client_probe_defer(pdev))
331 return -EPROBE_DEFER;
333 /* Get rid of things like offb */
334 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb");
338 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
342 ret = pci_enable_device(pdev);
346 pci_set_drvdata(pdev, dev);
348 if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
349 dev->agp = radeon_agp_head_init(dev);
351 dev->agp->agp_mtrr = arch_phys_wc_add(
352 dev->agp->agp_info.aper_base,
353 dev->agp->agp_info.aper_size *
357 ret = drm_dev_register(dev, ent->driver_data);
365 arch_phys_wc_del(dev->agp->agp_mtrr);
367 pci_disable_device(pdev);
374 radeon_pci_remove(struct pci_dev *pdev)
376 struct drm_device *dev = pci_get_drvdata(pdev);
382 radeon_pci_shutdown(struct pci_dev *pdev)
384 /* if we are running in a VM, make sure the device
385 * torn down properly on reboot/shutdown
387 if (radeon_device_is_virtual())
388 radeon_pci_remove(pdev);
392 * Some adapters need to be suspended before a
393 * shutdown occurs in order to prevent an error
395 * Make this power specific becauase it breaks
396 * some non-power boards.
398 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
402 static int radeon_pmops_suspend(struct device *dev)
404 struct drm_device *drm_dev = dev_get_drvdata(dev);
405 return radeon_suspend_kms(drm_dev, true, true, false);
408 static int radeon_pmops_resume(struct device *dev)
410 struct drm_device *drm_dev = dev_get_drvdata(dev);
412 /* GPU comes up enabled by the bios on resume */
413 if (radeon_is_px(drm_dev)) {
414 pm_runtime_disable(dev);
415 pm_runtime_set_active(dev);
416 pm_runtime_enable(dev);
419 return radeon_resume_kms(drm_dev, true, true);
422 static int radeon_pmops_freeze(struct device *dev)
424 struct drm_device *drm_dev = dev_get_drvdata(dev);
425 return radeon_suspend_kms(drm_dev, false, true, true);
428 static int radeon_pmops_thaw(struct device *dev)
430 struct drm_device *drm_dev = dev_get_drvdata(dev);
431 return radeon_resume_kms(drm_dev, false, true);
434 static int radeon_pmops_runtime_suspend(struct device *dev)
436 struct pci_dev *pdev = to_pci_dev(dev);
437 struct drm_device *drm_dev = pci_get_drvdata(pdev);
439 if (!radeon_is_px(drm_dev)) {
440 pm_runtime_forbid(dev);
444 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
445 drm_kms_helper_poll_disable(drm_dev);
447 radeon_suspend_kms(drm_dev, false, false, false);
448 pci_save_state(pdev);
449 pci_disable_device(pdev);
450 pci_ignore_hotplug(pdev);
451 if (radeon_is_atpx_hybrid())
452 pci_set_power_state(pdev, PCI_D3cold);
453 else if (!radeon_has_atpx_dgpu_power_cntl())
454 pci_set_power_state(pdev, PCI_D3hot);
455 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
460 static int radeon_pmops_runtime_resume(struct device *dev)
462 struct pci_dev *pdev = to_pci_dev(dev);
463 struct drm_device *drm_dev = pci_get_drvdata(pdev);
466 if (!radeon_is_px(drm_dev))
469 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
471 if (radeon_is_atpx_hybrid() ||
472 !radeon_has_atpx_dgpu_power_cntl())
473 pci_set_power_state(pdev, PCI_D0);
474 pci_restore_state(pdev);
475 ret = pci_enable_device(pdev);
478 pci_set_master(pdev);
480 ret = radeon_resume_kms(drm_dev, false, false);
481 drm_kms_helper_poll_enable(drm_dev);
482 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
486 static int radeon_pmops_runtime_idle(struct device *dev)
488 struct drm_device *drm_dev = dev_get_drvdata(dev);
489 struct drm_crtc *crtc;
491 if (!radeon_is_px(drm_dev)) {
492 pm_runtime_forbid(dev);
496 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
498 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
503 pm_runtime_mark_last_busy(dev);
504 pm_runtime_autosuspend(dev);
505 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
509 long radeon_drm_ioctl(struct file *filp,
510 unsigned int cmd, unsigned long arg)
512 struct drm_file *file_priv = filp->private_data;
513 struct drm_device *dev;
515 dev = file_priv->minor->dev;
516 ret = pm_runtime_get_sync(dev->dev);
518 pm_runtime_put_autosuspend(dev->dev);
522 ret = drm_ioctl(filp, cmd, arg);
524 pm_runtime_mark_last_busy(dev->dev);
525 pm_runtime_put_autosuspend(dev->dev);
530 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
532 unsigned int nr = DRM_IOCTL_NR(cmd);
535 if (nr < DRM_COMMAND_BASE)
536 return drm_compat_ioctl(filp, cmd, arg);
538 ret = radeon_drm_ioctl(filp, cmd, arg);
544 static const struct dev_pm_ops radeon_pm_ops = {
545 .suspend = radeon_pmops_suspend,
546 .resume = radeon_pmops_resume,
547 .freeze = radeon_pmops_freeze,
548 .thaw = radeon_pmops_thaw,
549 .poweroff = radeon_pmops_freeze,
550 .restore = radeon_pmops_resume,
551 .runtime_suspend = radeon_pmops_runtime_suspend,
552 .runtime_resume = radeon_pmops_runtime_resume,
553 .runtime_idle = radeon_pmops_runtime_idle,
556 static const struct file_operations radeon_driver_kms_fops = {
557 .owner = THIS_MODULE,
559 .release = drm_release,
560 .unlocked_ioctl = radeon_drm_ioctl,
565 .compat_ioctl = radeon_kms_compat_ioctl,
569 static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
570 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
571 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
572 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
573 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
574 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
575 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
576 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
577 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
578 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
579 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
580 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
581 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
582 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
583 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
584 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
585 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
586 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
587 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
588 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
589 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
590 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
591 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
592 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
593 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
594 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
595 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
596 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
598 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
599 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
600 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
601 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
602 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
603 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
604 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
605 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
606 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
607 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
608 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
609 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
610 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
611 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
612 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
615 static const struct drm_driver kms_driver = {
617 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
618 .load = radeon_driver_load_kms,
619 .open = radeon_driver_open_kms,
620 .postclose = radeon_driver_postclose_kms,
621 .lastclose = radeon_driver_lastclose_kms,
622 .unload = radeon_driver_unload_kms,
623 .irq_preinstall = radeon_driver_irq_preinstall_kms,
624 .irq_postinstall = radeon_driver_irq_postinstall_kms,
625 .irq_uninstall = radeon_driver_irq_uninstall_kms,
626 .irq_handler = radeon_driver_irq_handler_kms,
627 .ioctls = radeon_ioctls_kms,
628 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
629 .dumb_create = radeon_mode_dumb_create,
630 .dumb_map_offset = radeon_mode_dumb_mmap,
631 .fops = &radeon_driver_kms_fops,
633 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
634 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
635 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
640 .major = KMS_DRIVER_MAJOR,
641 .minor = KMS_DRIVER_MINOR,
642 .patchlevel = KMS_DRIVER_PATCHLEVEL,
645 static struct pci_driver radeon_kms_pci_driver = {
647 .id_table = pciidlist,
648 .probe = radeon_pci_probe,
649 .remove = radeon_pci_remove,
650 .shutdown = radeon_pci_shutdown,
651 .driver.pm = &radeon_pm_ops,
654 static int __init radeon_module_init(void)
656 if (vgacon_text_force() && radeon_modeset == -1) {
657 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
661 if (radeon_modeset == 0) {
662 DRM_ERROR("No UMS support in radeon module!\n");
666 DRM_INFO("radeon kernel modesetting enabled.\n");
667 radeon_register_atpx_handler();
669 return pci_register_driver(&radeon_kms_pci_driver);
672 static void __exit radeon_module_exit(void)
674 pci_unregister_driver(&radeon_kms_pci_driver);
675 radeon_unregister_atpx_handler();
676 mmu_notifier_synchronize();
679 module_init(radeon_module_init);
680 module_exit(radeon_module_exit);
682 MODULE_AUTHOR(DRIVER_AUTHOR);
683 MODULE_DESCRIPTION(DRIVER_DESC);
684 MODULE_LICENSE("GPL and additional rights");