drivers/gpu/drm/omapdrm/omap_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Rob Clark <rob@ti.com>
   5  */
   6
   7 #include <linux/math64.h>
   8
   9 #include <drm/drm_atomic.h>
  10 #include <drm/drm_atomic_helper.h>
  11 #include <drm/drm_crtc.h>
  12 #include <drm/drm_mode.h>
  13 #include <drm/drm_plane_helper.h>
  14 #include <drm/drm_vblank.h>
  15
  16 #include "omap_drv.h"
  17
  18 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  19
  20 struct omap_crtc_state {
  21         /* Must be first. */
  22         struct drm_crtc_state base;
  23         /* Shadow values for legacy userspace support. */
  24         unsigned int rotation;
  25         unsigned int zpos;
  26         bool manually_updated;
  27 };
  28
  29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  30
  31 struct omap_crtc {
  32         struct drm_crtc base;
  33
  34         const char *name;
  35         struct omap_drm_pipeline *pipe;
  36         enum omap_channel channel;
  37
  38         struct videomode vm;
  39
  40         bool ignore_digit_sync_lost;
  41
  42         bool enabled;
  43         bool pending;
  44         wait_queue_head_t pending_wait;
  45         struct drm_pending_vblank_event *event;
  46         struct delayed_work update_work;
  47
  48         void (*framedone_handler)(void *);
  49         void *framedone_handler_data;
  50 };
  51
  52 /* -----------------------------------------------------------------------------
  53  * Helper Functions
  54  */
  55
  56 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  57 {
  58         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  59         return &omap_crtc->vm;
  60 }
  61
  62 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  63 {
  64         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  65         return omap_crtc->channel;
  66 }
  67
  68 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  69 {
  70         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  71         unsigned long flags;
  72         bool pending;
  73
  74         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  75         pending = omap_crtc->pending;
  76         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  77
  78         return pending;
  79 }
  80
  81 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  82 {
  83         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  84
  85         /*
  86          * Timeout is set to a "sufficiently" high value, which should cover
  87          * a single frame refresh even on slower displays.
  88          */
  89         return wait_event_timeout(omap_crtc->pending_wait,
  90                                   !omap_crtc_is_pending(crtc),
  91                                   msecs_to_jiffies(250));
  92 }
  93
  94 /* -----------------------------------------------------------------------------
  95  * DSS Manager Functions
  96  */
  97
  98 /*
  99  * Manager-ops, callbacks from output when they need to configure
 100  * the upstream part of the video pipe.
 101  */
 102
 103 static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
 104                                        enum omap_channel channel)
 105 {
 106         priv->dispc_ops->mgr_enable(priv->dispc, channel, true);
 107 }
 108
 109 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 110 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 111 {
 112         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 113         struct drm_device *dev = crtc->dev;
 114         struct omap_drm_private *priv = dev->dev_private;
 115         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 116         enum omap_channel channel = omap_crtc->channel;
 117         struct omap_irq_wait *wait;
 118         u32 framedone_irq, vsync_irq;
 119         int ret;
 120
 121         if (WARN_ON(omap_crtc->enabled == enable))
 122                 return;
 123
 124         if (omap_state->manually_updated) {
 125                 omap_irq_enable_framedone(crtc, enable);
 126                 omap_crtc->enabled = enable;
 127                 return;
 128         }
 129
 130         if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
 131                 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 132                 omap_crtc->enabled = enable;
 133                 return;
 134         }
 135
 136         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 137                 /*
 138                  * Digit output produces some sync lost interrupts during the
 139                  * first frame when enabling, so we need to ignore those.
 140                  */
 141                 omap_crtc->ignore_digit_sync_lost = true;
 142         }
 143
 144         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
 145                                                                channel);
 146         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
 147
 148         if (enable) {
 149                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 150         } else {
 151                 /*
 152                  * When we disable the digit output, we need to wait for
 153                  * FRAMEDONE to know that DISPC has finished with the output.
 154                  *
 155                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 156                  * that case we need to use vsync interrupt, and wait for both
 157                  * even and odd frames.
 158                  */
 159
 160                 if (framedone_irq)
 161                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 162                 else
 163                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 164         }
 165
 166         priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
 167         omap_crtc->enabled = enable;
 168
 169         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 170         if (ret) {
 171                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 172                                 omap_crtc->name, enable ? "enable" : "disable");
 173         }
 174
 175         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 176                 omap_crtc->ignore_digit_sync_lost = false;
 177                 /* make sure the irq handler sees the value above */
 178                 mb();
 179         }
 180 }
 181
 182
 183 static int omap_crtc_dss_enable(struct omap_drm_private *priv,
 184                                 enum omap_channel channel)
 185 {
 186         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 187         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 188
 189         priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
 190                                          &omap_crtc->vm);
 191         omap_crtc_set_enabled(&omap_crtc->base, true);
 192
 193         return 0;
 194 }
 195
 196 static void omap_crtc_dss_disable(struct omap_drm_private *priv,
 197                                   enum omap_channel channel)
 198 {
 199         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 200         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 201
 202         omap_crtc_set_enabled(&omap_crtc->base, false);
 203 }
 204
 205 static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
 206                 enum omap_channel channel,
 207                 const struct videomode *vm)
 208 {
 209         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 210         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 211
 212         DBG("%s", omap_crtc->name);
 213         omap_crtc->vm = *vm;
 214 }
 215
 216 static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
 217                 enum omap_channel channel,
 218                 const struct dss_lcd_mgr_config *config)
 219 {
 220         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 221         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 222
 223         DBG("%s", omap_crtc->name);
 224         priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
 225                                             config);
 226 }
 227
 228 static int omap_crtc_dss_register_framedone(
 229                 struct omap_drm_private *priv, enum omap_channel channel,
 230                 void (*handler)(void *), void *data)
 231 {
 232         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 233         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 234         struct drm_device *dev = omap_crtc->base.dev;
 235
 236         if (omap_crtc->framedone_handler)
 237                 return -EBUSY;
 238
 239         dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
 240
 241         omap_crtc->framedone_handler = handler;
 242         omap_crtc->framedone_handler_data = data;
 243
 244         return 0;
 245 }
 246
 247 static void omap_crtc_dss_unregister_framedone(
 248                 struct omap_drm_private *priv, enum omap_channel channel,
 249                 void (*handler)(void *), void *data)
 250 {
 251         struct drm_crtc *crtc = priv->channels[channel]->crtc;
 252         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 253         struct drm_device *dev = omap_crtc->base.dev;
 254
 255         dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
 256
 257         WARN_ON(omap_crtc->framedone_handler != handler);
 258         WARN_ON(omap_crtc->framedone_handler_data != data);
 259
 260         omap_crtc->framedone_handler = NULL;
 261         omap_crtc->framedone_handler_data = NULL;
 262 }
 263
 264 static const struct dss_mgr_ops mgr_ops = {
 265         .start_update = omap_crtc_dss_start_update,
 266         .enable = omap_crtc_dss_enable,
 267         .disable = omap_crtc_dss_disable,
 268         .set_timings = omap_crtc_dss_set_timings,
 269         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 270         .register_framedone_handler = omap_crtc_dss_register_framedone,
 271         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 272 };
 273
 274 /* -----------------------------------------------------------------------------
 275  * Setup, Flush and Page Flip
 276  */
 277
 278 void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
 279 {
 280         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 281
 282         if (omap_crtc->ignore_digit_sync_lost) {
 283                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 284                 if (!irqstatus)
 285                         return;
 286         }
 287
 288         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 289 }
 290
 291 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 292 {
 293         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 294         struct drm_device *dev = omap_crtc->base.dev;
 295         struct omap_drm_private *priv = dev->dev_private;
 296         bool pending;
 297
 298         spin_lock(&crtc->dev->event_lock);
 299         /*
 300          * If the dispc is busy we're racing the flush operation. Try again on
 301          * the next vblank interrupt.
 302          */
 303         if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
 304                 spin_unlock(&crtc->dev->event_lock);
 305                 return;
 306         }
 307
 308         /* Send the vblank event if one has been requested. */
 309         if (omap_crtc->event) {
 310                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 311                 omap_crtc->event = NULL;
 312         }
 313
 314         pending = omap_crtc->pending;
 315         omap_crtc->pending = false;
 316         spin_unlock(&crtc->dev->event_lock);
 317
 318         if (pending)
 319                 drm_crtc_vblank_put(crtc);
 320
 321         /* Wake up omap_atomic_complete. */
 322         wake_up(&omap_crtc->pending_wait);
 323
 324         DBG("%s: apply done", omap_crtc->name);
 325 }
 326
 327 void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
 328 {
 329         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 330
 331         if (!omap_crtc->framedone_handler)
 332                 return;
 333
 334         omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
 335
 336         spin_lock(&crtc->dev->event_lock);
 337         /* Send the vblank event if one has been requested. */
 338         if (omap_crtc->event) {
 339                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 340                 omap_crtc->event = NULL;
 341         }
 342         omap_crtc->pending = false;
 343         spin_unlock(&crtc->dev->event_lock);
 344
 345         /* Wake up omap_atomic_complete. */
 346         wake_up(&omap_crtc->pending_wait);
 347 }
 348
 349 void omap_crtc_flush(struct drm_crtc *crtc)
 350 {
 351         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 352         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 353
 354         if (!omap_state->manually_updated)
 355                 return;
 356
 357         if (!delayed_work_pending(&omap_crtc->update_work))
 358                 schedule_delayed_work(&omap_crtc->update_work, 0);
 359 }
 360
 361 static void omap_crtc_manual_display_update(struct work_struct *data)
 362 {
 363         struct omap_crtc *omap_crtc =
 364                         container_of(data, struct omap_crtc, update_work.work);
 365         struct omap_dss_device *dssdev = omap_crtc->pipe->output;
 366         struct drm_device *dev = omap_crtc->base.dev;
 367         int ret;
 368
 369         if (!dssdev) {
 370                 dev_err_once(dev->dev, "missing display dssdev!");
 371                 return;
 372         }
 373
 374         if (dssdev->type != OMAP_DISPLAY_TYPE_DSI || !dssdev->ops->dsi.update) {
 375                 dev_err_once(dev->dev, "no DSI update callback found!");
 376                 return;
 377         }
 378
 379         ret = dssdev->ops->dsi.update(dssdev);
 380         if (ret < 0) {
 381                 spin_lock_irq(&dev->event_lock);
 382                 omap_crtc->pending = false;
 383                 spin_unlock_irq(&dev->event_lock);
 384                 wake_up(&omap_crtc->pending_wait);
 385         }
 386 }
 387
 388 static s16 omap_crtc_s31_32_to_s2_8(s64 coef)
 389 {
 390         u64 sign_bit = 1ULL << 63;
 391         u64 cbits = (u64)coef;
 392
 393         s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1ff);
 394
 395         if (cbits & sign_bit)
 396                 ret = -ret;
 397
 398         return ret;
 399 }
 400
 401 static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm,
 402                                          struct omap_dss_cpr_coefs *cpr)
 403 {
 404         cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]);
 405         cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]);
 406         cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]);
 407         cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]);
 408         cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]);
 409         cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]);
 410         cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]);
 411         cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]);
 412         cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]);
 413 }
 414
 415 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 416 {
 417         struct omap_drm_private *priv = crtc->dev->dev_private;
 418         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 419         struct omap_overlay_manager_info info;
 420
 421         memset(&info, 0, sizeof(info));
 422
 423         info.default_color = 0x000000;
 424         info.trans_enabled = false;
 425         info.partial_alpha_enabled = false;
 426
 427         if (crtc->state->ctm) {
 428                 struct drm_color_ctm *ctm = crtc->state->ctm->data;
 429
 430                 info.cpr_enable = true;
 431                 omap_crtc_cpr_coefs_from_ctm(ctm, &info.cpr_coefs);
 432         } else {
 433                 info.cpr_enable = false;
 434         }
 435
 436         priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
 437 }
 438
 439 /* -----------------------------------------------------------------------------
 440  * CRTC Functions
 441  */
 442
 443 static void omap_crtc_destroy(struct drm_crtc *crtc)
 444 {
 445         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 446
 447         DBG("%s", omap_crtc->name);
 448
 449         drm_crtc_cleanup(crtc);
 450
 451         kfree(omap_crtc);
 452 }
 453
 454 static void omap_crtc_arm_event(struct drm_crtc *crtc)
 455 {
 456         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 457
 458         WARN_ON(omap_crtc->pending);
 459         omap_crtc->pending = true;
 460
 461         if (crtc->state->event) {
 462                 omap_crtc->event = crtc->state->event;
 463                 crtc->state->event = NULL;
 464         }
 465 }
 466
 467 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
 468                                     struct drm_atomic_state *state)
 469 {
 470         struct omap_drm_private *priv = crtc->dev->dev_private;
 471         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 472         struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
 473         int ret;
 474
 475         DBG("%s", omap_crtc->name);
 476
 477         priv->dispc_ops->runtime_get(priv->dispc);
 478
 479         /* manual updated display will not trigger vsync irq */
 480         if (omap_state->manually_updated)
 481                 return;
 482
 483         drm_crtc_vblank_on(crtc);
 484
 485         ret = drm_crtc_vblank_get(crtc);
 486         WARN_ON(ret != 0);
 487
 488         spin_lock_irq(&crtc->dev->event_lock);
 489         omap_crtc_arm_event(crtc);
 490         spin_unlock_irq(&crtc->dev->event_lock);
 491 }
 492
 493 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
 494                                      struct drm_atomic_state *state)
 495 {
 496         struct omap_drm_private *priv = crtc->dev->dev_private;
 497         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 498         struct drm_device *dev = crtc->dev;
 499
 500         DBG("%s", omap_crtc->name);
 501
 502         spin_lock_irq(&crtc->dev->event_lock);
 503         if (crtc->state->event) {
 504                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 505                 crtc->state->event = NULL;
 506         }
 507         spin_unlock_irq(&crtc->dev->event_lock);
 508
 509         cancel_delayed_work(&omap_crtc->update_work);
 510
 511         if (!omap_crtc_wait_pending(crtc))
 512                 dev_warn(dev->dev, "manual display update did not finish!");
 513
 514         drm_crtc_vblank_off(crtc);
 515
 516         priv->dispc_ops->runtime_put(priv->dispc);
 517 }
 518
 519 static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
 520                                         const struct drm_display_mode *mode)
 521 {
 522         struct omap_drm_private *priv = crtc->dev->dev_private;
 523         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 524         struct videomode vm = {0};
 525         int r;
 526
 527         drm_display_mode_to_videomode(mode, &vm);
 528
 529         /*
 530          * DSI might not call this, since the supplied mode is not a
 531          * valid DISPC mode. DSI will calculate and configure the
 532          * proper DISPC mode later.
 533          */
 534         if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) {
 535                 r = priv->dispc_ops->mgr_check_timings(priv->dispc,
 536                                                        omap_crtc->channel,
 537                                                        &vm);
 538                 if (r)
 539                         return r;
 540         }
 541
 542         /* Check for bandwidth limit */
 543         if (priv->max_bandwidth) {
 544                 /*
 545                  * Estimation for the bandwidth need of a given mode with one
 546                  * full screen plane:
 547                  * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
 548                  *                                      ^^ Refresh rate ^^
 549                  *
 550                  * The interlaced mode is taken into account by using the
 551                  * pixelclock in the calculation.
 552                  *
 553                  * The equation is rearranged for 64bit arithmetic.
 554                  */
 555                 uint64_t bandwidth = mode->clock * 1000;
 556                 unsigned int bpp = 4;
 557
 558                 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
 559                 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
 560
 561                 /*
 562                  * Reject modes which would need more bandwidth if used with one
 563                  * full resolution plane (most common use case).
 564                  */
 565                 if (priv->max_bandwidth < bandwidth)
 566                         return MODE_BAD;
 567         }
 568
 569         return MODE_OK;
 570 }
 571
 572 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 573 {
 574         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 575         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 576
 577         DBG("%s: set mode: " DRM_MODE_FMT,
 578             omap_crtc->name, DRM_MODE_ARG(mode));
 579
 580         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 581 }
 582
 583 static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
 584 {
 585         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 586         struct omap_dss_device *dssdev = omap_crtc->pipe->output;
 587
 588         if (dssdev->type != OMAP_DISPLAY_TYPE_DSI ||
 589             !dssdev->ops->dsi.is_video_mode)
 590                 return false;
 591
 592         if (dssdev->ops->dsi.is_video_mode(dssdev))
 593                 return false;
 594
 595         DBG("detected manually updated display!");
 596         return true;
 597 }
 598
 599 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 600                                 struct drm_atomic_state *state)
 601 {
 602         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 603                                                                           crtc);
 604         struct drm_plane_state *pri_state;
 605
 606         if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) {
 607                 unsigned int length = crtc_state->degamma_lut->length /
 608                         sizeof(struct drm_color_lut);
 609
 610                 if (length < 2)
 611                         return -EINVAL;
 612         }
 613
 614         pri_state = drm_atomic_get_new_plane_state(state,
 615                                                    crtc->primary);
 616         if (pri_state) {
 617                 struct omap_crtc_state *omap_crtc_state =
 618                         to_omap_crtc_state(crtc_state);
 619
 620                 /* Mirror new values for zpos and rotation in omap_crtc_state */
 621                 omap_crtc_state->zpos = pri_state->zpos;
 622                 omap_crtc_state->rotation = pri_state->rotation;
 623
 624                 /* Check if this CRTC is for a manually updated display */
 625                 omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
 626         }
 627
 628         return 0;
 629 }
 630
 631 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 632                                    struct drm_atomic_state *state)
 633 {
 634 }
 635
 636 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 637                                    struct drm_atomic_state *state)
 638 {
 639         struct omap_drm_private *priv = crtc->dev->dev_private;
 640         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 641         struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
 642         int ret;
 643
 644         if (crtc->state->color_mgmt_changed) {
 645                 struct drm_color_lut *lut = NULL;
 646                 unsigned int length = 0;
 647
 648                 if (crtc->state->degamma_lut) {
 649                         lut = (struct drm_color_lut *)
 650                                 crtc->state->degamma_lut->data;
 651                         length = crtc->state->degamma_lut->length /
 652                                 sizeof(*lut);
 653                 }
 654                 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
 655                                                lut, length);
 656         }
 657
 658         omap_crtc_write_crtc_properties(crtc);
 659
 660         /* Only flush the CRTC if it is currently enabled. */
 661         if (!omap_crtc->enabled)
 662                 return;
 663
 664         DBG("%s: GO", omap_crtc->name);
 665
 666         if (omap_crtc_state->manually_updated) {
 667                 /* send new image for page flips and modeset changes */
 668                 spin_lock_irq(&crtc->dev->event_lock);
 669                 omap_crtc_flush(crtc);
 670                 omap_crtc_arm_event(crtc);
 671                 spin_unlock_irq(&crtc->dev->event_lock);
 672                 return;
 673         }
 674
 675         ret = drm_crtc_vblank_get(crtc);
 676         WARN_ON(ret != 0);
 677
 678         spin_lock_irq(&crtc->dev->event_lock);
 679         priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
 680         omap_crtc_arm_event(crtc);
 681         spin_unlock_irq(&crtc->dev->event_lock);
 682 }
 683
 684 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 685                                          struct drm_crtc_state *state,
 686                                          struct drm_property *property,
 687                                          u64 val)
 688 {
 689         struct omap_drm_private *priv = crtc->dev->dev_private;
 690         struct drm_plane_state *plane_state;
 691
 692         /*
 693          * Delegate property set to the primary plane. Get the plane state and
 694          * set the property directly, the shadow copy will be assigned in the
 695          * omap_crtc_atomic_check callback. This way updates to plane state will
 696          * always be mirrored in the crtc state correctly.
 697          */
 698         plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
 699         if (IS_ERR(plane_state))
 700                 return PTR_ERR(plane_state);
 701
 702         if (property == crtc->primary->rotation_property)
 703                 plane_state->rotation = val;
 704         else if (property == priv->zorder_prop)
 705                 plane_state->zpos = val;
 706         else
 707                 return -EINVAL;
 708
 709         return 0;
 710 }
 711
 712 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 713                                          const struct drm_crtc_state *state,
 714                                          struct drm_property *property,
 715                                          u64 *val)
 716 {
 717         struct omap_drm_private *priv = crtc->dev->dev_private;
 718         struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
 719
 720         if (property == crtc->primary->rotation_property)
 721                 *val = omap_state->rotation;
 722         else if (property == priv->zorder_prop)
 723                 *val = omap_state->zpos;
 724         else
 725                 return -EINVAL;
 726
 727         return 0;
 728 }
 729
 730 static void omap_crtc_reset(struct drm_crtc *crtc)
 731 {
 732         struct omap_crtc_state *state;
 733
 734         if (crtc->state)
 735                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 736
 737         kfree(crtc->state);
 738
 739         state = kzalloc(sizeof(*state), GFP_KERNEL);
 740         if (state)
 741                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 742 }
 743
 744 static struct drm_crtc_state *
 745 omap_crtc_duplicate_state(struct drm_crtc *crtc)
 746 {
 747         struct omap_crtc_state *state, *current_state;
 748
 749         if (WARN_ON(!crtc->state))
 750                 return NULL;
 751
 752         current_state = to_omap_crtc_state(crtc->state);
 753
 754         state = kmalloc(sizeof(*state), GFP_KERNEL);
 755         if (!state)
 756                 return NULL;
 757
 758         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 759
 760         state->zpos = current_state->zpos;
 761         state->rotation = current_state->rotation;
 762         state->manually_updated = current_state->manually_updated;
 763
 764         return &state->base;
 765 }
 766
 767 static const struct drm_crtc_funcs omap_crtc_funcs = {
 768         .reset = omap_crtc_reset,
 769         .set_config = drm_atomic_helper_set_config,
 770         .destroy = omap_crtc_destroy,
 771         .page_flip = drm_atomic_helper_page_flip,
 772         .atomic_duplicate_state = omap_crtc_duplicate_state,
 773         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 774         .atomic_set_property = omap_crtc_atomic_set_property,
 775         .atomic_get_property = omap_crtc_atomic_get_property,
 776         .enable_vblank = omap_irq_enable_vblank,
 777         .disable_vblank = omap_irq_disable_vblank,
 778 };
 779
 780 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 781         .mode_set_nofb = omap_crtc_mode_set_nofb,
 782         .atomic_check = omap_crtc_atomic_check,
 783         .atomic_begin = omap_crtc_atomic_begin,
 784         .atomic_flush = omap_crtc_atomic_flush,
 785         .atomic_enable = omap_crtc_atomic_enable,
 786         .atomic_disable = omap_crtc_atomic_disable,
 787         .mode_valid = omap_crtc_mode_valid,
 788 };
 789
 790 /* -----------------------------------------------------------------------------
 791  * Init and Cleanup
 792  */
 793
 794 static const char *channel_names[] = {
 795         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 796         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 797         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 798         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 799 };
 800
 801 void omap_crtc_pre_init(struct omap_drm_private *priv)
 802 {
 803         dss_install_mgr_ops(priv->dss, &mgr_ops, priv);
 804 }
 805
 806 void omap_crtc_pre_uninit(struct omap_drm_private *priv)
 807 {
 808         dss_uninstall_mgr_ops(priv->dss);
 809 }
 810
 811 /* initialize crtc */
 812 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 813                                 struct omap_drm_pipeline *pipe,
 814                                 struct drm_plane *plane)
 815 {
 816         struct omap_drm_private *priv = dev->dev_private;
 817         struct drm_crtc *crtc = NULL;
 818         struct omap_crtc *omap_crtc;
 819         enum omap_channel channel;
 820         int ret;
 821
 822         channel = pipe->output->dispc_channel;
 823
 824         DBG("%s", channel_names[channel]);
 825
 826         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 827         if (!omap_crtc)
 828                 return ERR_PTR(-ENOMEM);
 829
 830         crtc = &omap_crtc->base;
 831
 832         init_waitqueue_head(&omap_crtc->pending_wait);
 833
 834         omap_crtc->pipe = pipe;
 835         omap_crtc->channel = channel;
 836         omap_crtc->name = channel_names[channel];
 837
 838         /*
 839          * We want to refresh manually updated displays from dirty callback,
 840          * which is called quite often (e.g. for each drawn line). This will
 841          * be used to do the display update asynchronously to avoid blocking
 842          * the rendering process and merges multiple dirty calls into one
 843          * update if they arrive very fast. We also call this function for
 844          * atomic display updates (e.g. for page flips), which means we do
 845          * not need extra locking. Atomic updates should be synchronous, but
 846          * need to wait for the framedone interrupt anyways.
 847          */
 848         INIT_DELAYED_WORK(&omap_crtc->update_work,
 849                           omap_crtc_manual_display_update);
 850
 851         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 852                                         &omap_crtc_funcs, NULL);
 853         if (ret < 0) {
 854                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 855                         __func__, pipe->output->name);
 856                 kfree(omap_crtc);
 857                 return ERR_PTR(ret);
 858         }
 859
 860         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 861
 862         /* The dispc API adapts to what ever size, but the HW supports
 863          * 256 element gamma table for LCDs and 1024 element table for
 864          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 865          * tables so lets use that. Size of HW gamma table can be
 866          * extracted with dispc_mgr_gamma_size(). If it returns 0
 867          * gamma table is not supported.
 868          */
 869         if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
 870                 unsigned int gamma_lut_size = 256;
 871
 872                 drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0);
 873                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 874         }
 875
 876         omap_plane_install_properties(crtc->primary, &crtc->base);
 877
 878         return crtc;
 879 }