2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/vga_switcheroo.h>
31 #include <linux/mmu_notifier.h>
33 #include <drm/drm_aperture.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_gem_ttm_helper.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_vblank.h>
39 #include <core/gpuobj.h>
40 #include <core/option.h>
42 #include <core/tegra.h>
44 #include <nvif/driver.h>
45 #include <nvif/fifo.h>
46 #include <nvif/push006c.h>
47 #include <nvif/user.h>
49 #include <nvif/class.h>
50 #include <nvif/cl0002.h>
51 #include <nvif/cla06f.h>
53 #include "nouveau_drv.h"
54 #include "nouveau_dma.h"
55 #include "nouveau_ttm.h"
56 #include "nouveau_gem.h"
57 #include "nouveau_vga.h"
58 #include "nouveau_led.h"
59 #include "nouveau_hwmon.h"
60 #include "nouveau_acpi.h"
61 #include "nouveau_bios.h"
62 #include "nouveau_ioctl.h"
63 #include "nouveau_abi16.h"
64 #include "nouveau_fbcon.h"
65 #include "nouveau_fence.h"
66 #include "nouveau_debugfs.h"
67 #include "nouveau_usif.h"
68 #include "nouveau_connector.h"
69 #include "nouveau_platform.h"
70 #include "nouveau_svm.h"
71 #include "nouveau_dmem.h"
73 MODULE_PARM_DESC(config, "option string to pass to driver core");
74 static char *nouveau_config;
75 module_param_named(config, nouveau_config, charp, 0400);
77 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
78 static char *nouveau_debug;
79 module_param_named(debug, nouveau_debug, charp, 0400);
81 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
82 static int nouveau_noaccel = 0;
83 module_param_named(noaccel, nouveau_noaccel, int, 0400);
85 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
86 "0 = disabled, 1 = enabled, 2 = headless)");
87 int nouveau_modeset = -1;
88 module_param_named(modeset, nouveau_modeset, int, 0400);
90 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
91 static int nouveau_atomic = 0;
92 module_param_named(atomic, nouveau_atomic, int, 0400);
94 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
95 static int nouveau_runtime_pm = -1;
96 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
98 static struct drm_driver driver_stub;
99 static struct drm_driver driver_pci;
100 static struct drm_driver driver_platform;
103 nouveau_pci_name(struct pci_dev *pdev)
105 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
106 name |= pdev->bus->number << 16;
107 name |= PCI_SLOT(pdev->devfn) << 8;
108 return name | PCI_FUNC(pdev->devfn);
112 nouveau_platform_name(struct platform_device *platformdev)
114 return platformdev->id;
118 nouveau_name(struct drm_device *dev)
120 if (dev_is_pci(dev->dev))
121 return nouveau_pci_name(to_pci_dev(dev->dev));
123 return nouveau_platform_name(to_platform_device(dev->dev));
127 nouveau_cli_work_ready(struct dma_fence *fence)
129 if (!dma_fence_is_signaled(fence))
131 dma_fence_put(fence);
136 nouveau_cli_work(struct work_struct *w)
138 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
139 struct nouveau_cli_work *work, *wtmp;
140 mutex_lock(&cli->lock);
141 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
142 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
143 list_del(&work->head);
147 mutex_unlock(&cli->lock);
151 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
153 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
154 schedule_work(&work->cli->work);
158 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
159 struct nouveau_cli_work *work)
161 work->fence = dma_fence_get(fence);
163 mutex_lock(&cli->lock);
164 list_add_tail(&work->head, &cli->worker);
165 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
166 nouveau_cli_work_fence(fence, &work->cb);
167 mutex_unlock(&cli->lock);
171 nouveau_cli_fini(struct nouveau_cli *cli)
173 /* All our channels are dead now, which means all the fences they
174 * own are signalled, and all callback functions have been called.
176 * So, after flushing the workqueue, there should be nothing left.
178 flush_work(&cli->work);
179 WARN_ON(!list_empty(&cli->worker));
181 usif_client_fini(cli);
182 nouveau_vmm_fini(&cli->svm);
183 nouveau_vmm_fini(&cli->vmm);
184 nvif_mmu_dtor(&cli->mmu);
185 nvif_device_dtor(&cli->device);
186 mutex_lock(&cli->drm->master.lock);
187 nvif_client_dtor(&cli->base);
188 mutex_unlock(&cli->drm->master.lock);
192 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
193 struct nouveau_cli *cli)
195 static const struct nvif_mclass
197 { NVIF_CLASS_MEM_GF100, -1 },
198 { NVIF_CLASS_MEM_NV50 , -1 },
199 { NVIF_CLASS_MEM_NV04 , -1 },
202 static const struct nvif_mclass
204 { NVIF_CLASS_MMU_GF100, -1 },
205 { NVIF_CLASS_MMU_NV50 , -1 },
206 { NVIF_CLASS_MMU_NV04 , -1 },
209 static const struct nvif_mclass
211 { NVIF_CLASS_VMM_GP100, -1 },
212 { NVIF_CLASS_VMM_GM200, -1 },
213 { NVIF_CLASS_VMM_GF100, -1 },
214 { NVIF_CLASS_VMM_NV50 , -1 },
215 { NVIF_CLASS_VMM_NV04 , -1 },
218 u64 device = nouveau_name(drm->dev);
221 snprintf(cli->name, sizeof(cli->name), "%s", sname);
223 mutex_init(&cli->mutex);
224 usif_client_init(cli);
226 INIT_WORK(&cli->work, nouveau_cli_work);
227 INIT_LIST_HEAD(&cli->worker);
228 mutex_init(&cli->lock);
230 if (cli == &drm->master) {
231 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
232 cli->name, device, &cli->base);
234 mutex_lock(&drm->master.lock);
235 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
237 mutex_unlock(&drm->master.lock);
240 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
244 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
245 &(struct nv_device_v0) {
248 }, sizeof(struct nv_device_v0),
251 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
255 ret = nvif_mclass(&cli->device.object, mmus);
257 NV_PRINTK(err, cli, "No supported MMU class\n");
261 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
264 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
268 ret = nvif_mclass(&cli->mmu.object, vmms);
270 NV_PRINTK(err, cli, "No supported VMM class\n");
274 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
276 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
280 ret = nvif_mclass(&cli->mmu.object, mems);
282 NV_PRINTK(err, cli, "No supported MEM class\n");
286 cli->mem = &mems[ret];
290 nouveau_cli_fini(cli);
295 nouveau_accel_ce_fini(struct nouveau_drm *drm)
297 nouveau_channel_idle(drm->cechan);
298 nvif_object_dtor(&drm->ttm.copy);
299 nouveau_channel_del(&drm->cechan);
303 nouveau_accel_ce_init(struct nouveau_drm *drm)
305 struct nvif_device *device = &drm->client.device;
308 /* Allocate channel that has access to a (preferably async) copy
309 * engine, to use for TTM buffer moves.
311 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
312 ret = nouveau_channel_new(drm, device,
313 nvif_fifo_runlist_ce(device), 0,
316 if (device->info.chipset >= 0xa3 &&
317 device->info.chipset != 0xaa &&
318 device->info.chipset != 0xac) {
319 /* Prior to Kepler, there's only a single runlist, so all
320 * engines can be accessed from any channel.
322 * We still want to use a separate channel though.
324 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
329 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
333 nouveau_accel_gr_fini(struct nouveau_drm *drm)
335 nouveau_channel_idle(drm->channel);
336 nvif_object_dtor(&drm->ntfy);
337 nvkm_gpuobj_del(&drm->notify);
338 nouveau_channel_del(&drm->channel);
342 nouveau_accel_gr_init(struct nouveau_drm *drm)
344 struct nvif_device *device = &drm->client.device;
348 /* Allocate channel that has access to the graphics engine. */
349 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
350 arg0 = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
357 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
360 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
361 nouveau_accel_gr_fini(drm);
365 /* A SW class is used on pre-NV50 HW to assist with handling the
366 * synchronisation of page flips, as well as to implement fences
367 * on TNT/TNT2 HW that lacks any kind of support in host.
369 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
370 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
371 NVDRM_NVSW, nouveau_abi16_swclass(drm),
372 NULL, 0, &drm->channel->nvsw);
374 struct nvif_push *push = drm->channel->chan.push;
375 ret = PUSH_WAIT(push, 2);
377 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
381 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
382 nouveau_accel_gr_fini(drm);
387 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
388 * even if notification is never requested, so, allocate a ctxdma on
389 * any GPU where it's possible we'll end up using M2MF for BO moves.
391 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
392 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
395 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
396 nouveau_accel_gr_fini(drm);
400 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
401 NvNotify0, NV_DMA_IN_MEMORY,
402 &(struct nv_dma_v0) {
403 .target = NV_DMA_V0_TARGET_VRAM,
404 .access = NV_DMA_V0_ACCESS_RDWR,
405 .start = drm->notify->addr,
406 .limit = drm->notify->addr + 31
407 }, sizeof(struct nv_dma_v0),
410 nouveau_accel_gr_fini(drm);
417 nouveau_accel_fini(struct nouveau_drm *drm)
419 nouveau_accel_ce_fini(drm);
420 nouveau_accel_gr_fini(drm);
422 nouveau_fence(drm)->dtor(drm);
426 nouveau_accel_init(struct nouveau_drm *drm)
428 struct nvif_device *device = &drm->client.device;
429 struct nvif_sclass *sclass;
435 /* Initialise global support for channels, and synchronisation. */
436 ret = nouveau_channels_init(drm);
440 /*XXX: this is crap, but the fence/channel stuff is a little
441 * backwards in some places. this will be fixed.
443 ret = n = nvif_object_sclass_get(&device->object, &sclass);
447 for (ret = -ENOSYS, i = 0; i < n; i++) {
448 switch (sclass[i].oclass) {
449 case NV03_CHANNEL_DMA:
450 ret = nv04_fence_create(drm);
452 case NV10_CHANNEL_DMA:
453 ret = nv10_fence_create(drm);
455 case NV17_CHANNEL_DMA:
456 case NV40_CHANNEL_DMA:
457 ret = nv17_fence_create(drm);
459 case NV50_CHANNEL_GPFIFO:
460 ret = nv50_fence_create(drm);
462 case G82_CHANNEL_GPFIFO:
463 ret = nv84_fence_create(drm);
465 case FERMI_CHANNEL_GPFIFO:
466 case KEPLER_CHANNEL_GPFIFO_A:
467 case KEPLER_CHANNEL_GPFIFO_B:
468 case MAXWELL_CHANNEL_GPFIFO_A:
469 case PASCAL_CHANNEL_GPFIFO_A:
470 case VOLTA_CHANNEL_GPFIFO_A:
471 case TURING_CHANNEL_GPFIFO_A:
472 ret = nvc0_fence_create(drm);
479 nvif_object_sclass_put(&sclass);
481 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
482 nouveau_accel_fini(drm);
486 /* Volta requires access to a doorbell register for kickoff. */
487 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
488 ret = nvif_user_ctor(device, "drmUsermode");
493 /* Allocate channels we need to support various functions. */
494 nouveau_accel_gr_init(drm);
495 nouveau_accel_ce_init(drm);
497 /* Initialise accelerated TTM buffer moves. */
498 nouveau_bo_move_init(drm);
501 static void __printf(2, 3)
502 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
504 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
505 struct va_format vaf;
511 NV_ERROR(drm, "%pV", &vaf);
515 static void __printf(2, 3)
516 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
518 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
519 struct va_format vaf;
525 NV_DEBUG(drm, "%pV", &vaf);
529 static const struct nvif_parent_func
531 .debugf = nouveau_drm_debugf,
532 .errorf = nouveau_drm_errorf,
536 nouveau_drm_device_init(struct drm_device *dev)
538 struct nouveau_drm *drm;
541 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
543 dev->dev_private = drm;
546 nvif_parent_ctor(&nouveau_parent, &drm->parent);
547 drm->master.base.object.parent = &drm->parent;
549 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
553 ret = nouveau_cli_init(drm, "DRM", &drm->client);
557 nvxx_client(&drm->client.base)->debug =
558 nvkm_dbgopt(nouveau_debug, "DRM");
560 INIT_LIST_HEAD(&drm->clients);
561 spin_lock_init(&drm->tile.lock);
563 /* workaround an odd issue on nvc1 by disabling the device's
564 * nosnoop capability. hopefully won't cause issues until a
565 * better fix is found - assuming there is one...
567 if (drm->client.device.info.chipset == 0xc1)
568 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
570 nouveau_vga_init(drm);
572 ret = nouveau_ttm_init(drm);
576 ret = nouveau_bios_init(dev);
580 nouveau_accel_init(drm);
582 ret = nouveau_display_create(dev);
586 if (dev->mode_config.num_crtc) {
587 ret = nouveau_display_init(dev, false, false);
592 nouveau_debugfs_init(drm);
593 nouveau_hwmon_init(dev);
594 nouveau_svm_init(drm);
595 nouveau_dmem_init(drm);
596 nouveau_fbcon_init(dev);
597 nouveau_led_init(dev);
599 if (nouveau_pmops_runtime()) {
600 pm_runtime_use_autosuspend(dev->dev);
601 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
602 pm_runtime_set_active(dev->dev);
603 pm_runtime_allow(dev->dev);
604 pm_runtime_mark_last_busy(dev->dev);
605 pm_runtime_put(dev->dev);
611 nouveau_display_destroy(dev);
613 nouveau_accel_fini(drm);
614 nouveau_bios_takedown(dev);
616 nouveau_ttm_fini(drm);
618 nouveau_vga_fini(drm);
619 nouveau_cli_fini(&drm->client);
621 nouveau_cli_fini(&drm->master);
623 nvif_parent_dtor(&drm->parent);
629 nouveau_drm_device_fini(struct drm_device *dev)
631 struct nouveau_drm *drm = nouveau_drm(dev);
633 if (nouveau_pmops_runtime()) {
634 pm_runtime_get_sync(dev->dev);
635 pm_runtime_forbid(dev->dev);
638 nouveau_led_fini(dev);
639 nouveau_fbcon_fini(dev);
640 nouveau_dmem_fini(drm);
641 nouveau_svm_fini(drm);
642 nouveau_hwmon_fini(dev);
643 nouveau_debugfs_fini(drm);
645 if (dev->mode_config.num_crtc)
646 nouveau_display_fini(dev, false, false);
647 nouveau_display_destroy(dev);
649 nouveau_accel_fini(drm);
650 nouveau_bios_takedown(dev);
652 nouveau_ttm_fini(drm);
653 nouveau_vga_fini(drm);
655 nouveau_cli_fini(&drm->client);
656 nouveau_cli_fini(&drm->master);
657 nvif_parent_dtor(&drm->parent);
662 * On some Intel PCIe bridge controllers doing a
663 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
664 * Skipping the intermediate D3hot step seems to make it work again. This is
665 * probably caused by not meeting the expectation the involved AML code has
666 * when the GPU is put into D3hot state before invoking it.
668 * This leads to various manifestations of this issue:
669 * - AML code execution to power on the GPU hits an infinite loop (as the
670 * code waits on device memory to change).
671 * - kernel crashes, as all PCI reads return -1, which most code isn't able
672 * to handle well enough.
674 * In all cases dmesg will contain at least one line like this:
675 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
676 * followed by a lot of nouveau timeouts.
678 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
679 * documented PCI config space register 0x248 of the Intel PCIe bridge
680 * controller (0x1901) in order to change the state of the PCIe link between
681 * the PCIe port and the GPU. There are alternative code paths using other
682 * registers, which seem to work fine (executed pre Windows 8):
683 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
684 * - 0xb0 bit 0x10 (link disable)
685 * Changing the conditions inside the firmware by poking into the relevant
686 * addresses does resolve the issue, but it seemed to be ACPI private memory
687 * and not any device accessible memory at all, so there is no portable way of
688 * changing the conditions.
689 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
691 * The only systems where this behavior can be seen are hybrid graphics laptops
692 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
693 * this issue only occurs in combination with listed Intel PCIe bridge
694 * controllers and the mentioned GPUs or other devices as well.
696 * documentation on the PCIe bridge controller can be found in the
697 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
698 * Section "12 PCI Express* Controller (x16) Registers"
701 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
703 struct drm_device *dev = pci_get_drvdata(pdev);
704 struct nouveau_drm *drm = nouveau_drm(dev);
705 struct pci_dev *bridge = pci_upstream_bridge(pdev);
707 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
710 switch (bridge->device) {
712 drm->old_pm_cap = pdev->pm_cap;
714 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
719 static int nouveau_drm_probe(struct pci_dev *pdev,
720 const struct pci_device_id *pent)
722 struct nvkm_device *device;
723 struct drm_device *drm_dev;
726 if (vga_switcheroo_client_probe_defer(pdev))
727 return -EPROBE_DEFER;
729 /* We need to check that the chipset is supported before booting
730 * fbdev off the hardware, as there's no way to put it back.
732 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
733 true, false, 0, &device);
737 nvkm_device_del(&device);
739 /* Remove conflicting drivers (vesafb, efifb etc). */
740 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci);
744 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
745 true, true, ~0ULL, &device);
749 pci_set_master(pdev);
752 driver_pci.driver_features |= DRIVER_ATOMIC;
754 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
755 if (IS_ERR(drm_dev)) {
756 ret = PTR_ERR(drm_dev);
760 ret = pci_enable_device(pdev);
764 pci_set_drvdata(pdev, drm_dev);
766 ret = nouveau_drm_device_init(drm_dev);
770 ret = drm_dev_register(drm_dev, pent->driver_data);
772 goto fail_drm_dev_init;
774 quirk_broken_nv_runpm(pdev);
778 nouveau_drm_device_fini(drm_dev);
780 pci_disable_device(pdev);
782 drm_dev_put(drm_dev);
784 nvkm_device_del(&device);
789 nouveau_drm_device_remove(struct drm_device *dev)
791 struct nouveau_drm *drm = nouveau_drm(dev);
792 struct nvkm_client *client;
793 struct nvkm_device *device;
795 drm_dev_unregister(dev);
797 client = nvxx_client(&drm->client.base);
798 device = nvkm_device_find(client->device);
800 nouveau_drm_device_fini(dev);
802 nvkm_device_del(&device);
806 nouveau_drm_remove(struct pci_dev *pdev)
808 struct drm_device *dev = pci_get_drvdata(pdev);
809 struct nouveau_drm *drm = nouveau_drm(dev);
811 /* revert our workaround */
813 pdev->pm_cap = drm->old_pm_cap;
814 nouveau_drm_device_remove(dev);
815 pci_disable_device(pdev);
819 nouveau_do_suspend(struct drm_device *dev, bool runtime)
821 struct nouveau_drm *drm = nouveau_drm(dev);
822 struct ttm_resource_manager *man;
825 nouveau_svm_suspend(drm);
826 nouveau_dmem_suspend(drm);
827 nouveau_led_suspend(dev);
829 if (dev->mode_config.num_crtc) {
830 NV_DEBUG(drm, "suspending console...\n");
831 nouveau_fbcon_set_suspend(dev, 1);
832 NV_DEBUG(drm, "suspending display...\n");
833 ret = nouveau_display_suspend(dev, runtime);
838 NV_DEBUG(drm, "evicting buffers...\n");
840 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
841 ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
843 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
845 ret = nouveau_channel_idle(drm->cechan);
851 ret = nouveau_channel_idle(drm->channel);
856 NV_DEBUG(drm, "suspending fence...\n");
857 if (drm->fence && nouveau_fence(drm)->suspend) {
858 if (!nouveau_fence(drm)->suspend(drm)) {
864 NV_DEBUG(drm, "suspending object tree...\n");
865 ret = nvif_client_suspend(&drm->master.base);
872 if (drm->fence && nouveau_fence(drm)->resume)
873 nouveau_fence(drm)->resume(drm);
876 if (dev->mode_config.num_crtc) {
877 NV_DEBUG(drm, "resuming display...\n");
878 nouveau_display_resume(dev, runtime);
884 nouveau_do_resume(struct drm_device *dev, bool runtime)
887 struct nouveau_drm *drm = nouveau_drm(dev);
889 NV_DEBUG(drm, "resuming object tree...\n");
890 ret = nvif_client_resume(&drm->master.base);
892 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
896 NV_DEBUG(drm, "resuming fence...\n");
897 if (drm->fence && nouveau_fence(drm)->resume)
898 nouveau_fence(drm)->resume(drm);
900 nouveau_run_vbios_init(dev);
902 if (dev->mode_config.num_crtc) {
903 NV_DEBUG(drm, "resuming display...\n");
904 nouveau_display_resume(dev, runtime);
905 NV_DEBUG(drm, "resuming console...\n");
906 nouveau_fbcon_set_suspend(dev, 0);
909 nouveau_led_resume(dev);
910 nouveau_dmem_resume(drm);
911 nouveau_svm_resume(drm);
916 nouveau_pmops_suspend(struct device *dev)
918 struct pci_dev *pdev = to_pci_dev(dev);
919 struct drm_device *drm_dev = pci_get_drvdata(pdev);
922 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
923 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
926 ret = nouveau_do_suspend(drm_dev, false);
930 pci_save_state(pdev);
931 pci_disable_device(pdev);
932 pci_set_power_state(pdev, PCI_D3hot);
938 nouveau_pmops_resume(struct device *dev)
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct drm_device *drm_dev = pci_get_drvdata(pdev);
944 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
945 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
948 pci_set_power_state(pdev, PCI_D0);
949 pci_restore_state(pdev);
950 ret = pci_enable_device(pdev);
953 pci_set_master(pdev);
955 ret = nouveau_do_resume(drm_dev, false);
957 /* Monitors may have been connected / disconnected during suspend */
958 nouveau_display_hpd_resume(drm_dev);
964 nouveau_pmops_freeze(struct device *dev)
966 struct pci_dev *pdev = to_pci_dev(dev);
967 struct drm_device *drm_dev = pci_get_drvdata(pdev);
968 return nouveau_do_suspend(drm_dev, false);
972 nouveau_pmops_thaw(struct device *dev)
974 struct pci_dev *pdev = to_pci_dev(dev);
975 struct drm_device *drm_dev = pci_get_drvdata(pdev);
976 return nouveau_do_resume(drm_dev, false);
980 nouveau_pmops_runtime(void)
982 if (nouveau_runtime_pm == -1)
983 return nouveau_is_optimus() || nouveau_is_v1_dsm();
984 return nouveau_runtime_pm == 1;
988 nouveau_pmops_runtime_suspend(struct device *dev)
990 struct pci_dev *pdev = to_pci_dev(dev);
991 struct drm_device *drm_dev = pci_get_drvdata(pdev);
994 if (!nouveau_pmops_runtime()) {
995 pm_runtime_forbid(dev);
999 nouveau_switcheroo_optimus_dsm();
1000 ret = nouveau_do_suspend(drm_dev, true);
1001 pci_save_state(pdev);
1002 pci_disable_device(pdev);
1003 pci_ignore_hotplug(pdev);
1004 pci_set_power_state(pdev, PCI_D3cold);
1005 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1010 nouveau_pmops_runtime_resume(struct device *dev)
1012 struct pci_dev *pdev = to_pci_dev(dev);
1013 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1014 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1015 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1018 if (!nouveau_pmops_runtime()) {
1019 pm_runtime_forbid(dev);
1023 pci_set_power_state(pdev, PCI_D0);
1024 pci_restore_state(pdev);
1025 ret = pci_enable_device(pdev);
1028 pci_set_master(pdev);
1030 ret = nouveau_do_resume(drm_dev, true);
1032 NV_ERROR(drm, "resume failed with: %d\n", ret);
1037 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1038 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1040 /* Monitors may have been connected / disconnected during suspend */
1041 nouveau_display_hpd_resume(drm_dev);
1047 nouveau_pmops_runtime_idle(struct device *dev)
1049 if (!nouveau_pmops_runtime()) {
1050 pm_runtime_forbid(dev);
1054 pm_runtime_mark_last_busy(dev);
1055 pm_runtime_autosuspend(dev);
1056 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1061 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1063 struct nouveau_drm *drm = nouveau_drm(dev);
1064 struct nouveau_cli *cli;
1065 char name[32], tmpname[TASK_COMM_LEN];
1068 /* need to bring up power immediately if opening device */
1069 ret = pm_runtime_get_sync(dev->dev);
1070 if (ret < 0 && ret != -EACCES) {
1071 pm_runtime_put_autosuspend(dev->dev);
1075 get_task_comm(tmpname, current);
1076 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1078 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1083 ret = nouveau_cli_init(drm, name, cli);
1087 fpriv->driver_priv = cli;
1089 mutex_lock(&drm->client.mutex);
1090 list_add(&cli->head, &drm->clients);
1091 mutex_unlock(&drm->client.mutex);
1095 nouveau_cli_fini(cli);
1099 pm_runtime_mark_last_busy(dev->dev);
1100 pm_runtime_put_autosuspend(dev->dev);
1105 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1107 struct nouveau_cli *cli = nouveau_cli(fpriv);
1108 struct nouveau_drm *drm = nouveau_drm(dev);
1110 pm_runtime_get_sync(dev->dev);
1112 mutex_lock(&cli->mutex);
1114 nouveau_abi16_fini(cli->abi16);
1115 mutex_unlock(&cli->mutex);
1117 mutex_lock(&drm->client.mutex);
1118 list_del(&cli->head);
1119 mutex_unlock(&drm->client.mutex);
1121 nouveau_cli_fini(cli);
1123 pm_runtime_mark_last_busy(dev->dev);
1124 pm_runtime_put_autosuspend(dev->dev);
1127 static const struct drm_ioctl_desc
1128 nouveau_ioctls[] = {
1129 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1130 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1131 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1132 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1133 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1134 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1135 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1136 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1137 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1138 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1139 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1140 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1141 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1142 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1146 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1148 struct drm_file *filp = file->private_data;
1149 struct drm_device *dev = filp->minor->dev;
1152 ret = pm_runtime_get_sync(dev->dev);
1153 if (ret < 0 && ret != -EACCES) {
1154 pm_runtime_put_autosuspend(dev->dev);
1158 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1159 case DRM_NOUVEAU_NVIF:
1160 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1163 ret = drm_ioctl(file, cmd, arg);
1167 pm_runtime_mark_last_busy(dev->dev);
1168 pm_runtime_put_autosuspend(dev->dev);
1172 static const struct file_operations
1173 nouveau_driver_fops = {
1174 .owner = THIS_MODULE,
1176 .release = drm_release,
1177 .unlocked_ioctl = nouveau_drm_ioctl,
1178 .mmap = drm_gem_mmap,
1181 #if defined(CONFIG_COMPAT)
1182 .compat_ioctl = nouveau_compat_ioctl,
1184 .llseek = noop_llseek,
1187 static struct drm_driver
1190 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
1191 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1192 | DRIVER_KMS_LEGACY_CONTEXT
1196 .open = nouveau_drm_open,
1197 .postclose = nouveau_drm_postclose,
1198 .lastclose = nouveau_vga_lastclose,
1200 #if defined(CONFIG_DEBUG_FS)
1201 .debugfs_init = nouveau_drm_debugfs_init,
1204 .ioctls = nouveau_ioctls,
1205 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1206 .fops = &nouveau_driver_fops,
1208 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1209 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1210 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1211 .gem_prime_mmap = drm_gem_prime_mmap,
1213 .dumb_create = nouveau_display_dumb_create,
1214 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1216 .name = DRIVER_NAME,
1217 .desc = DRIVER_DESC,
1219 .date = GIT_REVISION,
1221 .date = DRIVER_DATE,
1223 .major = DRIVER_MAJOR,
1224 .minor = DRIVER_MINOR,
1225 .patchlevel = DRIVER_PATCHLEVEL,
1228 static struct pci_device_id
1229 nouveau_drm_pci_table[] = {
1231 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1232 .class = PCI_BASE_CLASS_DISPLAY << 16,
1233 .class_mask = 0xff << 16,
1236 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1237 .class = PCI_BASE_CLASS_DISPLAY << 16,
1238 .class_mask = 0xff << 16,
1243 static void nouveau_display_options(void)
1245 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1247 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1248 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1249 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1250 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1251 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1252 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1253 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1254 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1255 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1256 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1257 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1260 static const struct dev_pm_ops nouveau_pm_ops = {
1261 .suspend = nouveau_pmops_suspend,
1262 .resume = nouveau_pmops_resume,
1263 .freeze = nouveau_pmops_freeze,
1264 .thaw = nouveau_pmops_thaw,
1265 .poweroff = nouveau_pmops_freeze,
1266 .restore = nouveau_pmops_resume,
1267 .runtime_suspend = nouveau_pmops_runtime_suspend,
1268 .runtime_resume = nouveau_pmops_runtime_resume,
1269 .runtime_idle = nouveau_pmops_runtime_idle,
1272 static struct pci_driver
1273 nouveau_drm_pci_driver = {
1275 .id_table = nouveau_drm_pci_table,
1276 .probe = nouveau_drm_probe,
1277 .remove = nouveau_drm_remove,
1278 .driver.pm = &nouveau_pm_ops,
1282 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1283 struct platform_device *pdev,
1284 struct nvkm_device **pdevice)
1286 struct drm_device *drm;
1289 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1290 true, true, ~0ULL, pdevice);
1294 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1300 err = nouveau_drm_device_init(drm);
1304 platform_set_drvdata(pdev, drm);
1311 nvkm_device_del(pdevice);
1313 return ERR_PTR(err);
1317 nouveau_drm_init(void)
1319 driver_pci = driver_stub;
1320 driver_platform = driver_stub;
1322 nouveau_display_options();
1324 if (nouveau_modeset == -1) {
1325 if (vgacon_text_force())
1326 nouveau_modeset = 0;
1329 if (!nouveau_modeset)
1332 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1333 platform_driver_register(&nouveau_platform_driver);
1336 nouveau_register_dsm_handler();
1337 nouveau_backlight_ctor();
1340 return pci_register_driver(&nouveau_drm_pci_driver);
1347 nouveau_drm_exit(void)
1349 if (!nouveau_modeset)
1353 pci_unregister_driver(&nouveau_drm_pci_driver);
1355 nouveau_backlight_dtor();
1356 nouveau_unregister_dsm_handler();
1358 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1359 platform_driver_unregister(&nouveau_platform_driver);
1361 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1362 mmu_notifier_synchronize();
1365 module_init(nouveau_drm_init);
1366 module_exit(nouveau_drm_exit);
1368 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1369 MODULE_AUTHOR(DRIVER_AUTHOR);
1370 MODULE_DESCRIPTION(DRIVER_DESC);
1371 MODULE_LICENSE("GPL and additional rights");