drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_chan.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40 #include "nouveau_mem.h"
  41 #include "nouveau_vmm.h"
  42
  43 #include <nvif/class.h>
  44 #include <nvif/if500b.h>
  45 #include <nvif/if900b.h>
  46
  47 static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
  48                                struct ttm_resource *reg);
  49
  50 /*
  51  * NV10-NV40 tiling helpers
  52  */
  53
  54 static void
  55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  56                            u32 addr, u32 size, u32 pitch, u32 flags)
  57 {
  58         struct nouveau_drm *drm = nouveau_drm(dev);
  59         int i = reg - drm->tile.reg;
  60         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
  61         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  62
  63         nouveau_fence_unref(&reg->fence);
  64
  65         if (tile->pitch)
  66                 nvkm_fb_tile_fini(fb, i, tile);
  67
  68         if (pitch)
  69                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  70
  71         nvkm_fb_tile_prog(fb, i, tile);
  72 }
  73
  74 static struct nouveau_drm_tile *
  75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  76 {
  77         struct nouveau_drm *drm = nouveau_drm(dev);
  78         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  79
  80         spin_lock(&drm->tile.lock);
  81
  82         if (!tile->used &&
  83             (!tile->fence || nouveau_fence_done(tile->fence)))
  84                 tile->used = true;
  85         else
  86                 tile = NULL;
  87
  88         spin_unlock(&drm->tile.lock);
  89         return tile;
  90 }
  91
  92 static void
  93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  94                         struct dma_fence *fence)
  95 {
  96         struct nouveau_drm *drm = nouveau_drm(dev);
  97
  98         if (tile) {
  99                 spin_lock(&drm->tile.lock);
 100                 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
 101                 tile->used = false;
 102                 spin_unlock(&drm->tile.lock);
 103         }
 104 }
 105
 106 static struct nouveau_drm_tile *
 107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 108                    u32 size, u32 pitch, u32 zeta)
 109 {
 110         struct nouveau_drm *drm = nouveau_drm(dev);
 111         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
 112         struct nouveau_drm_tile *tile, *found = NULL;
 113         int i;
 114
 115         for (i = 0; i < fb->tile.regions; i++) {
 116                 tile = nv10_bo_get_tile_region(dev, i);
 117
 118                 if (pitch && !found) {
 119                         found = tile;
 120                         continue;
 121
 122                 } else if (tile && fb->tile.region[i].pitch) {
 123                         /* Kill an unused tile region. */
 124                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 125                 }
 126
 127                 nv10_bo_put_tile_region(dev, tile, NULL);
 128         }
 129
 130         if (found)
 131                 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
 132         return found;
 133 }
 134
 135 static void
 136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 137 {
 138         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 139         struct drm_device *dev = drm->dev;
 140         struct nouveau_bo *nvbo = nouveau_bo(bo);
 141
 142         WARN_ON(nvbo->pin_refcnt > 0);
 143         nouveau_bo_del_io_reserve_lru(bo);
 144         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 145
 146         /*
 147          * If nouveau_bo_new() allocated this buffer, the GEM object was never
 148          * initialized, so don't attempt to release it.
 149          */
 150         if (bo->base.dev)
 151                 drm_gem_object_release(&bo->base);
 152
 153         kfree(nvbo);
 154 }
 155
 156 static inline u64
 157 roundup_64(u64 x, u32 y)
 158 {
 159         x += y - 1;
 160         do_div(x, y);
 161         return x * y;
 162 }
 163
 164 static void
 165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
 166 {
 167         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 168         struct nvif_device *device = &drm->client.device;
 169
 170         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 171                 if (nvbo->mode) {
 172                         if (device->info.chipset >= 0x40) {
 173                                 *align = 65536;
 174                                 *size = roundup_64(*size, 64 * nvbo->mode);
 175
 176                         } else if (device->info.chipset >= 0x30) {
 177                                 *align = 32768;
 178                                 *size = roundup_64(*size, 64 * nvbo->mode);
 179
 180                         } else if (device->info.chipset >= 0x20) {
 181                                 *align = 16384;
 182                                 *size = roundup_64(*size, 64 * nvbo->mode);
 183
 184                         } else if (device->info.chipset >= 0x10) {
 185                                 *align = 16384;
 186                                 *size = roundup_64(*size, 32 * nvbo->mode);
 187                         }
 188                 }
 189         } else {
 190                 *size = roundup_64(*size, (1 << nvbo->page));
 191                 *align = max((1 <<  nvbo->page), *align);
 192         }
 193
 194         *size = roundup_64(*size, PAGE_SIZE);
 195 }
 196
 197 struct nouveau_bo *
 198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
 199                  u32 tile_mode, u32 tile_flags)
 200 {
 201         struct nouveau_drm *drm = cli->drm;
 202         struct nouveau_bo *nvbo;
 203         struct nvif_mmu *mmu = &cli->mmu;
 204         struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
 205         int i, pi = -1;
 206
 207         if (!*size) {
 208                 NV_WARN(drm, "skipped size %016llx\n", *size);
 209                 return ERR_PTR(-EINVAL);
 210         }
 211
 212         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 213         if (!nvbo)
 214                 return ERR_PTR(-ENOMEM);
 215         INIT_LIST_HEAD(&nvbo->head);
 216         INIT_LIST_HEAD(&nvbo->entry);
 217         INIT_LIST_HEAD(&nvbo->vma_list);
 218         nvbo->bo.bdev = &drm->ttm.bdev;
 219
 220         /* This is confusing, and doesn't actually mean we want an uncached
 221          * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
 222          * into in nouveau_gem_new().
 223          */
 224         if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
 225                 /* Determine if we can get a cache-coherent map, forcing
 226                  * uncached mapping if we can't.
 227                  */
 228                 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
 229                         nvbo->force_coherent = true;
 230         }
 231
 232         if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
 233                 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
 234                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 235                         kfree(nvbo);
 236                         return ERR_PTR(-EINVAL);
 237                 }
 238
 239                 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
 240         } else
 241         if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 242                 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
 243                 nvbo->comp = (tile_flags & 0x00030000) >> 16;
 244                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 245                         kfree(nvbo);
 246                         return ERR_PTR(-EINVAL);
 247                 }
 248         } else {
 249                 nvbo->zeta = (tile_flags & 0x00000007);
 250         }
 251         nvbo->mode = tile_mode;
 252         nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
 253
 254         /* Determine the desirable target GPU page size for the buffer. */
 255         for (i = 0; i < vmm->page_nr; i++) {
 256                 /* Because we cannot currently allow VMM maps to fail
 257                  * during buffer migration, we need to determine page
 258                  * size for the buffer up-front, and pre-allocate its
 259                  * page tables.
 260                  *
 261                  * Skip page sizes that can't support needed domains.
 262                  */
 263                 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
 264                     (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
 265                         continue;
 266                 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
 267                     (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
 268                         continue;
 269
 270                 /* Select this page size if it's the first that supports
 271                  * the potential memory domains, or when it's compatible
 272                  * with the requested compression settings.
 273                  */
 274                 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
 275                         pi = i;
 276
 277                 /* Stop once the buffer is larger than the current page size. */
 278                 if (*size >= 1ULL << vmm->page[i].shift)
 279                         break;
 280         }
 281
 282         if (WARN_ON(pi < 0))
 283                 return ERR_PTR(-EINVAL);
 284
 285         /* Disable compression if suitable settings couldn't be found. */
 286         if (nvbo->comp && !vmm->page[pi].comp) {
 287                 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
 288                         nvbo->kind = mmu->kind[nvbo->kind];
 289                 nvbo->comp = 0;
 290         }
 291         nvbo->page = vmm->page[pi].shift;
 292
 293         nouveau_bo_fixup_align(nvbo, align, size);
 294
 295         return nvbo;
 296 }
 297
 298 int
 299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
 300                 struct sg_table *sg, struct dma_resv *robj)
 301 {
 302         int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
 303         size_t acc_size;
 304         int ret;
 305
 306         acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
 307
 308         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 309         nouveau_bo_placement_set(nvbo, domain, 0);
 310         INIT_LIST_HEAD(&nvbo->io_reserve_lru);
 311
 312         ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
 313                           &nvbo->placement, align >> PAGE_SHIFT, false,
 314                           acc_size, sg, robj, nouveau_bo_del_ttm);
 315         if (ret) {
 316                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 317                 return ret;
 318         }
 319
 320         return 0;
 321 }
 322
 323 int
 324 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
 325                uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
 326                struct sg_table *sg, struct dma_resv *robj,
 327                struct nouveau_bo **pnvbo)
 328 {
 329         struct nouveau_bo *nvbo;
 330         int ret;
 331
 332         nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
 333                                 tile_flags);
 334         if (IS_ERR(nvbo))
 335                 return PTR_ERR(nvbo);
 336
 337         ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
 338         if (ret)
 339                 return ret;
 340
 341         *pnvbo = nvbo;
 342         return 0;
 343 }
 344
 345 static void
 346 set_placement_list(struct nouveau_drm *drm, struct ttm_place *pl, unsigned *n,
 347                    uint32_t domain, uint32_t flags)
 348 {
 349         *n = 0;
 350
 351         if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
 352                 struct nvif_mmu *mmu = &drm->client.mmu;
 353
 354                 pl[*n].mem_type = TTM_PL_VRAM;
 355                 pl[*n].flags = flags & ~TTM_PL_FLAG_CACHED;
 356
 357                 /* Some BARs do not support being ioremapped WC */
 358                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 359                     mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
 360                         pl[*n].flags &= ~TTM_PL_FLAG_WC;
 361
 362                 (*n)++;
 363         }
 364         if (domain & NOUVEAU_GEM_DOMAIN_GART) {
 365                 pl[*n].mem_type = TTM_PL_TT;
 366                 pl[*n].flags = flags;
 367
 368                 if (drm->agp.bridge)
 369                         pl[*n].flags &= ~TTM_PL_FLAG_CACHED;
 370
 371                 (*n)++;
 372         }
 373         if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
 374                 pl[*n].mem_type = TTM_PL_SYSTEM;
 375                 pl[(*n)++].flags = flags;
 376         }
 377 }
 378
 379 static void
 380 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
 381 {
 382         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 383         u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
 384         unsigned i, fpfn, lpfn;
 385
 386         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 387             nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
 388             nvbo->bo.mem.num_pages < vram_pages / 4) {
 389                 /*
 390                  * Make sure that the color and depth buffers are handled
 391                  * by independent memory controller units. Up to a 9x
 392                  * speed up when alpha-blending and depth-test are enabled
 393                  * at the same time.
 394                  */
 395                 if (nvbo->zeta) {
 396                         fpfn = vram_pages / 2;
 397                         lpfn = ~0;
 398                 } else {
 399                         fpfn = 0;
 400                         lpfn = vram_pages / 2;
 401                 }
 402                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 403                         nvbo->placements[i].fpfn = fpfn;
 404                         nvbo->placements[i].lpfn = lpfn;
 405                 }
 406                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 407                         nvbo->busy_placements[i].fpfn = fpfn;
 408                         nvbo->busy_placements[i].lpfn = lpfn;
 409                 }
 410         }
 411 }
 412
 413 void
 414 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
 415                          uint32_t busy)
 416 {
 417         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 418         struct ttm_placement *pl = &nvbo->placement;
 419         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 420                                                  TTM_PL_MASK_CACHING) |
 421                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 422
 423         pl->placement = nvbo->placements;
 424         set_placement_list(drm, nvbo->placements, &pl->num_placement,
 425                            domain, flags);
 426
 427         pl->busy_placement = nvbo->busy_placements;
 428         set_placement_list(drm, nvbo->busy_placements, &pl->num_busy_placement,
 429                            domain | busy, flags);
 430
 431         set_placement_range(nvbo, domain);
 432 }
 433
 434 int
 435 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
 436 {
 437         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 438         struct ttm_buffer_object *bo = &nvbo->bo;
 439         bool force = false, evict = false;
 440         int ret;
 441
 442         ret = ttm_bo_reserve(bo, false, false, NULL);
 443         if (ret)
 444                 return ret;
 445
 446         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 447             domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
 448                 if (!nvbo->contig) {
 449                         nvbo->contig = true;
 450                         force = true;
 451                         evict = true;
 452                 }
 453         }
 454
 455         if (nvbo->pin_refcnt) {
 456                 bool error = evict;
 457
 458                 switch (bo->mem.mem_type) {
 459                 case TTM_PL_VRAM:
 460                         error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
 461                         break;
 462                 case TTM_PL_TT:
 463                         error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
 464                 default:
 465                         break;
 466                 }
 467
 468                 if (error) {
 469                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 470                                       "0x%08x vs 0x%08x\n", bo,
 471                                  bo->mem.mem_type, domain);
 472                         ret = -EBUSY;
 473                 }
 474                 nvbo->pin_refcnt++;
 475                 goto out;
 476         }
 477
 478         if (evict) {
 479                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
 480                 ret = nouveau_bo_validate(nvbo, false, false);
 481                 if (ret)
 482                         goto out;
 483         }
 484
 485         nvbo->pin_refcnt++;
 486         nouveau_bo_placement_set(nvbo, domain, 0);
 487
 488         /* drop pin_refcnt temporarily, so we don't trip the assertion
 489          * in nouveau_bo_move() that makes sure we're not trying to
 490          * move a pinned buffer
 491          */
 492         nvbo->pin_refcnt--;
 493         ret = nouveau_bo_validate(nvbo, false, false);
 494         if (ret)
 495                 goto out;
 496         nvbo->pin_refcnt++;
 497
 498         switch (bo->mem.mem_type) {
 499         case TTM_PL_VRAM:
 500                 drm->gem.vram_available -= bo->mem.size;
 501                 break;
 502         case TTM_PL_TT:
 503                 drm->gem.gart_available -= bo->mem.size;
 504                 break;
 505         default:
 506                 break;
 507         }
 508
 509 out:
 510         if (force && ret)
 511                 nvbo->contig = false;
 512         ttm_bo_unreserve(bo);
 513         return ret;
 514 }
 515
 516 int
 517 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 518 {
 519         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 520         struct ttm_buffer_object *bo = &nvbo->bo;
 521         int ret, ref;
 522
 523         ret = ttm_bo_reserve(bo, false, false, NULL);
 524         if (ret)
 525                 return ret;
 526
 527         ref = --nvbo->pin_refcnt;
 528         WARN_ON_ONCE(ref < 0);
 529         if (ref)
 530                 goto out;
 531
 532         switch (bo->mem.mem_type) {
 533         case TTM_PL_VRAM:
 534                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
 535                 break;
 536         case TTM_PL_TT:
 537                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
 538                 break;
 539         default:
 540                 break;
 541         }
 542
 543         ret = nouveau_bo_validate(nvbo, false, false);
 544         if (ret == 0) {
 545                 switch (bo->mem.mem_type) {
 546                 case TTM_PL_VRAM:
 547                         drm->gem.vram_available += bo->mem.size;
 548                         break;
 549                 case TTM_PL_TT:
 550                         drm->gem.gart_available += bo->mem.size;
 551                         break;
 552                 default:
 553                         break;
 554                 }
 555         }
 556
 557 out:
 558         ttm_bo_unreserve(bo);
 559         return ret;
 560 }
 561
 562 int
 563 nouveau_bo_map(struct nouveau_bo *nvbo)
 564 {
 565         int ret;
 566
 567         ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
 568         if (ret)
 569                 return ret;
 570
 571         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 572
 573         ttm_bo_unreserve(&nvbo->bo);
 574         return ret;
 575 }
 576
 577 void
 578 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 579 {
 580         if (!nvbo)
 581                 return;
 582
 583         ttm_bo_kunmap(&nvbo->kmap);
 584 }
 585
 586 void
 587 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 588 {
 589         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 590         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 591         int i;
 592
 593         if (!ttm_dma)
 594                 return;
 595
 596         /* Don't waste time looping if the object is coherent */
 597         if (nvbo->force_coherent)
 598                 return;
 599
 600         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 601                 dma_sync_single_for_device(drm->dev->dev,
 602                                            ttm_dma->dma_address[i],
 603                                            PAGE_SIZE, DMA_TO_DEVICE);
 604 }
 605
 606 void
 607 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 608 {
 609         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 610         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 611         int i;
 612
 613         if (!ttm_dma)
 614                 return;
 615
 616         /* Don't waste time looping if the object is coherent */
 617         if (nvbo->force_coherent)
 618                 return;
 619
 620         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 621                 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
 622                                         PAGE_SIZE, DMA_FROM_DEVICE);
 623 }
 624
 625 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
 626 {
 627         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 628         struct nouveau_bo *nvbo = nouveau_bo(bo);
 629
 630         mutex_lock(&drm->ttm.io_reserve_mutex);
 631         list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
 632         mutex_unlock(&drm->ttm.io_reserve_mutex);
 633 }
 634
 635 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
 636 {
 637         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 638         struct nouveau_bo *nvbo = nouveau_bo(bo);
 639
 640         mutex_lock(&drm->ttm.io_reserve_mutex);
 641         list_del_init(&nvbo->io_reserve_lru);
 642         mutex_unlock(&drm->ttm.io_reserve_mutex);
 643 }
 644
 645 int
 646 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 647                     bool no_wait_gpu)
 648 {
 649         struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 650         int ret;
 651
 652         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
 653         if (ret)
 654                 return ret;
 655
 656         nouveau_bo_sync_for_device(nvbo);
 657
 658         return 0;
 659 }
 660
 661 void
 662 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 663 {
 664         bool is_iomem;
 665         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 666
 667         mem += index;
 668
 669         if (is_iomem)
 670                 iowrite16_native(val, (void __force __iomem *)mem);
 671         else
 672                 *mem = val;
 673 }
 674
 675 u32
 676 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 677 {
 678         bool is_iomem;
 679         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 680
 681         mem += index;
 682
 683         if (is_iomem)
 684                 return ioread32_native((void __force __iomem *)mem);
 685         else
 686                 return *mem;
 687 }
 688
 689 void
 690 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 691 {
 692         bool is_iomem;
 693         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 694
 695         mem += index;
 696
 697         if (is_iomem)
 698                 iowrite32_native(val, (void __force __iomem *)mem);
 699         else
 700                 *mem = val;
 701 }
 702
 703 static struct ttm_tt *
 704 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
 705 {
 706 #if IS_ENABLED(CONFIG_AGP)
 707         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 708
 709         if (drm->agp.bridge) {
 710                 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
 711         }
 712 #endif
 713
 714         return nouveau_sgdma_create_ttm(bo, page_flags);
 715 }
 716
 717 static int
 718 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
 719                     struct ttm_resource *reg)
 720 {
 721 #if IS_ENABLED(CONFIG_AGP)
 722         struct nouveau_drm *drm = nouveau_bdev(bdev);
 723 #endif
 724         if (!reg)
 725                 return -EINVAL;
 726 #if IS_ENABLED(CONFIG_AGP)
 727         if (drm->agp.bridge)
 728                 return ttm_agp_bind(ttm, reg);
 729 #endif
 730         return nouveau_sgdma_bind(bdev, ttm, reg);
 731 }
 732
 733 static void
 734 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
 735 {
 736 #if IS_ENABLED(CONFIG_AGP)
 737         struct nouveau_drm *drm = nouveau_bdev(bdev);
 738
 739         if (drm->agp.bridge) {
 740                 ttm_agp_unbind(ttm);
 741                 return;
 742         }
 743 #endif
 744         nouveau_sgdma_unbind(bdev, ttm);
 745 }
 746
 747 static void
 748 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 749 {
 750         struct nouveau_bo *nvbo = nouveau_bo(bo);
 751
 752         switch (bo->mem.mem_type) {
 753         case TTM_PL_VRAM:
 754                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
 755                                          NOUVEAU_GEM_DOMAIN_CPU);
 756                 break;
 757         default:
 758                 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
 759                 break;
 760         }
 761
 762         *pl = nvbo->placement;
 763 }
 764
 765 static int
 766 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
 767                      struct ttm_resource *reg)
 768 {
 769         struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
 770         struct nouveau_mem *new_mem = nouveau_mem(reg);
 771         struct nvif_vmm *vmm = &drm->client.vmm.vmm;
 772         int ret;
 773
 774         ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
 775                            old_mem->mem.size, &old_mem->vma[0]);
 776         if (ret)
 777                 return ret;
 778
 779         ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
 780                            new_mem->mem.size, &old_mem->vma[1]);
 781         if (ret)
 782                 goto done;
 783
 784         ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
 785         if (ret)
 786                 goto done;
 787
 788         ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
 789 done:
 790         if (ret) {
 791                 nvif_vmm_put(vmm, &old_mem->vma[1]);
 792                 nvif_vmm_put(vmm, &old_mem->vma[0]);
 793         }
 794         return 0;
 795 }
 796
 797 static int
 798 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 799                      bool no_wait_gpu, struct ttm_resource *new_reg)
 800 {
 801         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 802         struct nouveau_channel *chan = drm->ttm.chan;
 803         struct nouveau_cli *cli = (void *)chan->user.client;
 804         struct nouveau_fence *fence;
 805         int ret;
 806
 807         /* create temporary vmas for the transfer and attach them to the
 808          * old nvkm_mem node, these will get cleaned up after ttm has
 809          * destroyed the ttm_resource
 810          */
 811         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 812                 ret = nouveau_bo_move_prep(drm, bo, new_reg);
 813                 if (ret)
 814                         return ret;
 815         }
 816
 817         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
 818         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
 819         if (ret == 0) {
 820                 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
 821                 if (ret == 0) {
 822                         ret = nouveau_fence_new(chan, false, &fence);
 823                         if (ret == 0) {
 824                                 ret = ttm_bo_move_accel_cleanup(bo,
 825                                                                 &fence->base,
 826                                                                 evict, false,
 827                                                                 new_reg);
 828                                 nouveau_fence_unref(&fence);
 829                         }
 830                 }
 831         }
 832         mutex_unlock(&cli->mutex);
 833         return ret;
 834 }
 835
 836 void
 837 nouveau_bo_move_init(struct nouveau_drm *drm)
 838 {
 839         static const struct _method_table {
 840                 const char *name;
 841                 int engine;
 842                 s32 oclass;
 843                 int (*exec)(struct nouveau_channel *,
 844                             struct ttm_buffer_object *,
 845                             struct ttm_resource *, struct ttm_resource *);
 846                 int (*init)(struct nouveau_channel *, u32 handle);
 847         } _methods[] = {
 848                 {  "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
 849                 {  "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
 850                 {  "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
 851                 {  "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
 852                 {  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
 853                 {  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
 854                 {  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
 855                 {  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 856                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
 857                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 858                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
 859                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 860                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
 861                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
 862                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
 863                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
 864                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
 865                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
 866                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
 867                 {},
 868         };
 869         const struct _method_table *mthd = _methods;
 870         const char *name = "CPU";
 871         int ret;
 872
 873         do {
 874                 struct nouveau_channel *chan;
 875
 876                 if (mthd->engine)
 877                         chan = drm->cechan;
 878                 else
 879                         chan = drm->channel;
 880                 if (chan == NULL)
 881                         continue;
 882
 883                 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
 884                                        mthd->oclass | (mthd->engine << 16),
 885                                        mthd->oclass, NULL, 0,
 886                                        &drm->ttm.copy);
 887                 if (ret == 0) {
 888                         ret = mthd->init(chan, drm->ttm.copy.handle);
 889                         if (ret) {
 890                                 nvif_object_dtor(&drm->ttm.copy);
 891                                 continue;
 892                         }
 893
 894                         drm->ttm.move = mthd->exec;
 895                         drm->ttm.chan = chan;
 896                         name = mthd->name;
 897                         break;
 898                 }
 899         } while ((++mthd)->exec);
 900
 901         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
 902 }
 903
 904 static int
 905 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 906                       bool no_wait_gpu, struct ttm_resource *new_reg)
 907 {
 908         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 909         struct ttm_place placement_memtype = {
 910                 .fpfn = 0,
 911                 .lpfn = 0,
 912                 .mem_type = TTM_PL_TT,
 913                 .flags = TTM_PL_MASK_CACHING
 914         };
 915         struct ttm_placement placement;
 916         struct ttm_resource tmp_reg;
 917         int ret;
 918
 919         placement.num_placement = placement.num_busy_placement = 1;
 920         placement.placement = placement.busy_placement = &placement_memtype;
 921
 922         tmp_reg = *new_reg;
 923         tmp_reg.mm_node = NULL;
 924         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 925         if (ret)
 926                 return ret;
 927
 928         ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
 929         if (ret)
 930                 goto out;
 931
 932         ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_reg);
 933         if (ret)
 934                 goto out;
 935
 936         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
 937         if (ret)
 938                 goto out;
 939
 940         ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
 941 out:
 942         ttm_resource_free(bo, &tmp_reg);
 943         return ret;
 944 }
 945
 946 static int
 947 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 948                       bool no_wait_gpu, struct ttm_resource *new_reg)
 949 {
 950         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 951         struct ttm_place placement_memtype = {
 952                 .fpfn = 0,
 953                 .lpfn = 0,
 954                 .mem_type = TTM_PL_TT,
 955                 .flags = TTM_PL_MASK_CACHING
 956         };
 957         struct ttm_placement placement;
 958         struct ttm_resource tmp_reg;
 959         int ret;
 960
 961         placement.num_placement = placement.num_busy_placement = 1;
 962         placement.placement = placement.busy_placement = &placement_memtype;
 963
 964         tmp_reg = *new_reg;
 965         tmp_reg.mm_node = NULL;
 966         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 967         if (ret)
 968                 return ret;
 969
 970         ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
 971         if (ret)
 972                 goto out;
 973
 974         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
 975         if (ret)
 976                 goto out;
 977
 978 out:
 979         ttm_resource_free(bo, &tmp_reg);
 980         return ret;
 981 }
 982
 983 static void
 984 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
 985                      struct ttm_resource *new_reg)
 986 {
 987         struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
 988         struct nouveau_bo *nvbo = nouveau_bo(bo);
 989         struct nouveau_vma *vma;
 990
 991         /* ttm can now (stupidly) pass the driver bos it didn't create... */
 992         if (bo->destroy != nouveau_bo_del_ttm)
 993                 return;
 994
 995         nouveau_bo_del_io_reserve_lru(bo);
 996
 997         if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
 998             mem->mem.page == nvbo->page) {
 999                 list_for_each_entry(vma, &nvbo->vma_list, head) {
1000                         nouveau_vma_map(vma, mem);
1001                 }
1002         } else {
1003                 list_for_each_entry(vma, &nvbo->vma_list, head) {
1004                         WARN_ON(ttm_bo_wait(bo, false, false));
1005                         nouveau_vma_unmap(vma);
1006                 }
1007         }
1008
1009         if (new_reg) {
1010                 if (new_reg->mm_node)
1011                         nvbo->offset = (new_reg->start << PAGE_SHIFT);
1012                 else
1013                         nvbo->offset = 0;
1014         }
1015
1016 }
1017
1018 static int
1019 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1020                    struct nouveau_drm_tile **new_tile)
1021 {
1022         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1023         struct drm_device *dev = drm->dev;
1024         struct nouveau_bo *nvbo = nouveau_bo(bo);
1025         u64 offset = new_reg->start << PAGE_SHIFT;
1026
1027         *new_tile = NULL;
1028         if (new_reg->mem_type != TTM_PL_VRAM)
1029                 return 0;
1030
1031         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1032                 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1033                                                nvbo->mode, nvbo->zeta);
1034         }
1035
1036         return 0;
1037 }
1038
1039 static void
1040 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1041                       struct nouveau_drm_tile *new_tile,
1042                       struct nouveau_drm_tile **old_tile)
1043 {
1044         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1045         struct drm_device *dev = drm->dev;
1046         struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1047
1048         nv10_bo_put_tile_region(dev, *old_tile, fence);
1049         *old_tile = new_tile;
1050 }
1051
1052 static int
1053 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1054                 struct ttm_operation_ctx *ctx,
1055                 struct ttm_resource *new_reg)
1056 {
1057         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1058         struct nouveau_bo *nvbo = nouveau_bo(bo);
1059         struct ttm_resource *old_reg = &bo->mem;
1060         struct nouveau_drm_tile *new_tile = NULL;
1061         int ret = 0;
1062
1063         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1064         if (ret)
1065                 return ret;
1066
1067         if (nvbo->pin_refcnt)
1068                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1069
1070         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1071                 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1072                 if (ret)
1073                         return ret;
1074         }
1075
1076         /* Fake bo copy. */
1077         if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1078                 ttm_bo_move_null(bo, new_reg);
1079                 goto out;
1080         }
1081
1082         /* Hardware assisted copy. */
1083         if (drm->ttm.move) {
1084                 if (new_reg->mem_type == TTM_PL_SYSTEM)
1085                         ret = nouveau_bo_move_flipd(bo, evict,
1086                                                     ctx->interruptible,
1087                                                     ctx->no_wait_gpu, new_reg);
1088                 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1089                         ret = nouveau_bo_move_flips(bo, evict,
1090                                                     ctx->interruptible,
1091                                                     ctx->no_wait_gpu, new_reg);
1092                 else
1093                         ret = nouveau_bo_move_m2mf(bo, evict,
1094                                                    ctx->interruptible,
1095                                                    ctx->no_wait_gpu, new_reg);
1096                 if (!ret)
1097                         goto out;
1098         }
1099
1100         /* Fallback to software copy. */
1101         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1102         if (ret == 0)
1103                 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1104
1105 out:
1106         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1107                 if (ret)
1108                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1109                 else
1110                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1111         }
1112
1113         return ret;
1114 }
1115
1116 static int
1117 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1118 {
1119         struct nouveau_bo *nvbo = nouveau_bo(bo);
1120
1121         return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1122                                           filp->private_data);
1123 }
1124
1125 static void
1126 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1127                                struct ttm_resource *reg)
1128 {
1129         struct nouveau_mem *mem = nouveau_mem(reg);
1130
1131         if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1132                 switch (reg->mem_type) {
1133                 case TTM_PL_TT:
1134                         if (mem->kind)
1135                                 nvif_object_unmap_handle(&mem->mem.object);
1136                         break;
1137                 case TTM_PL_VRAM:
1138                         nvif_object_unmap_handle(&mem->mem.object);
1139                         break;
1140                 default:
1141                         break;
1142                 }
1143         }
1144 }
1145
1146 static int
1147 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1148 {
1149         struct nouveau_drm *drm = nouveau_bdev(bdev);
1150         struct nvkm_device *device = nvxx_device(&drm->client.device);
1151         struct nouveau_mem *mem = nouveau_mem(reg);
1152         int ret;
1153
1154         mutex_lock(&drm->ttm.io_reserve_mutex);
1155 retry:
1156         switch (reg->mem_type) {
1157         case TTM_PL_SYSTEM:
1158                 /* System memory */
1159                 ret = 0;
1160                 goto out;
1161         case TTM_PL_TT:
1162 #if IS_ENABLED(CONFIG_AGP)
1163                 if (drm->agp.bridge) {
1164                         reg->bus.offset = (reg->start << PAGE_SHIFT) +
1165                                 drm->agp.base;
1166                         reg->bus.is_iomem = !drm->agp.cma;
1167                 }
1168 #endif
1169                 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1170                     !mem->kind) {
1171                         /* untiled */
1172                         ret = 0;
1173                         break;
1174                 }
1175                 fallthrough;    /* tiled memory */
1176         case TTM_PL_VRAM:
1177                 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1178                         device->func->resource_addr(device, 1);
1179                 reg->bus.is_iomem = true;
1180                 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1181                         union {
1182                                 struct nv50_mem_map_v0 nv50;
1183                                 struct gf100_mem_map_v0 gf100;
1184                         } args;
1185                         u64 handle, length;
1186                         u32 argc = 0;
1187
1188                         switch (mem->mem.object.oclass) {
1189                         case NVIF_CLASS_MEM_NV50:
1190                                 args.nv50.version = 0;
1191                                 args.nv50.ro = 0;
1192                                 args.nv50.kind = mem->kind;
1193                                 args.nv50.comp = mem->comp;
1194                                 argc = sizeof(args.nv50);
1195                                 break;
1196                         case NVIF_CLASS_MEM_GF100:
1197                                 args.gf100.version = 0;
1198                                 args.gf100.ro = 0;
1199                                 args.gf100.kind = mem->kind;
1200                                 argc = sizeof(args.gf100);
1201                                 break;
1202                         default:
1203                                 WARN_ON(1);
1204                                 break;
1205                         }
1206
1207                         ret = nvif_object_map_handle(&mem->mem.object,
1208                                                      &args, argc,
1209                                                      &handle, &length);
1210                         if (ret != 1) {
1211                                 if (WARN_ON(ret == 0))
1212                                         ret = -EINVAL;
1213                                 goto out;
1214                         }
1215
1216                         reg->bus.offset = handle;
1217                         ret = 0;
1218                 }
1219                 break;
1220         default:
1221                 ret = -EINVAL;
1222         }
1223
1224 out:
1225         if (ret == -ENOSPC) {
1226                 struct nouveau_bo *nvbo;
1227
1228                 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1229                                                 typeof(*nvbo),
1230                                                 io_reserve_lru);
1231                 if (nvbo) {
1232                         list_del_init(&nvbo->io_reserve_lru);
1233                         drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1234                                            bdev->dev_mapping);
1235                         nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1236                         goto retry;
1237                 }
1238
1239         }
1240         mutex_unlock(&drm->ttm.io_reserve_mutex);
1241         return ret;
1242 }
1243
1244 static void
1245 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1246 {
1247         struct nouveau_drm *drm = nouveau_bdev(bdev);
1248
1249         mutex_lock(&drm->ttm.io_reserve_mutex);
1250         nouveau_ttm_io_mem_free_locked(drm, reg);
1251         mutex_unlock(&drm->ttm.io_reserve_mutex);
1252 }
1253
1254 static int
1255 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1256 {
1257         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1258         struct nouveau_bo *nvbo = nouveau_bo(bo);
1259         struct nvkm_device *device = nvxx_device(&drm->client.device);
1260         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1261         int i, ret;
1262
1263         /* as long as the bo isn't in vram, and isn't tiled, we've got
1264          * nothing to do here.
1265          */
1266         if (bo->mem.mem_type != TTM_PL_VRAM) {
1267                 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1268                     !nvbo->kind)
1269                         return 0;
1270
1271                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1272                         nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
1273                                                  0);
1274
1275                         ret = nouveau_bo_validate(nvbo, false, false);
1276                         if (ret)
1277                                 return ret;
1278                 }
1279                 return 0;
1280         }
1281
1282         /* make sure bo is in mappable vram */
1283         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1284             bo->mem.start + bo->mem.num_pages < mappable)
1285                 return 0;
1286
1287         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1288                 nvbo->placements[i].fpfn = 0;
1289                 nvbo->placements[i].lpfn = mappable;
1290         }
1291
1292         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1293                 nvbo->busy_placements[i].fpfn = 0;
1294                 nvbo->busy_placements[i].lpfn = mappable;
1295         }
1296
1297         nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1298         return nouveau_bo_validate(nvbo, false, false);
1299 }
1300
1301 static int
1302 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
1303                         struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1304 {
1305         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1306         struct nouveau_drm *drm;
1307         struct device *dev;
1308         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1309
1310         if (ttm_tt_is_populated(ttm))
1311                 return 0;
1312
1313         if (slave && ttm->sg) {
1314                 /* make userspace faulting work */
1315                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1316                                                  ttm_dma->dma_address, ttm->num_pages);
1317                 ttm_tt_set_populated(ttm);
1318                 return 0;
1319         }
1320
1321         drm = nouveau_bdev(bdev);
1322         dev = drm->dev->dev;
1323
1324 #if IS_ENABLED(CONFIG_AGP)
1325         if (drm->agp.bridge) {
1326                 return ttm_pool_populate(ttm, ctx);
1327         }
1328 #endif
1329
1330 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1331         if (swiotlb_nr_tbl()) {
1332                 return ttm_dma_populate((void *)ttm, dev, ctx);
1333         }
1334 #endif
1335         return ttm_populate_and_map_pages(dev, ttm_dma, ctx);
1336 }
1337
1338 static void
1339 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1340                           struct ttm_tt *ttm)
1341 {
1342         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1343         struct nouveau_drm *drm;
1344         struct device *dev;
1345         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1346
1347         if (slave)
1348                 return;
1349
1350         drm = nouveau_bdev(bdev);
1351         dev = drm->dev->dev;
1352
1353 #if IS_ENABLED(CONFIG_AGP)
1354         if (drm->agp.bridge) {
1355                 ttm_pool_unpopulate(ttm);
1356                 return;
1357         }
1358 #endif
1359
1360 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1361         if (swiotlb_nr_tbl()) {
1362                 ttm_dma_unpopulate((void *)ttm, dev);
1363                 return;
1364         }
1365 #endif
1366
1367         ttm_unmap_and_unpopulate_pages(dev, ttm_dma);
1368 }
1369
1370 static void
1371 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
1372                        struct ttm_tt *ttm)
1373 {
1374 #if IS_ENABLED(CONFIG_AGP)
1375         struct nouveau_drm *drm = nouveau_bdev(bdev);
1376         if (drm->agp.bridge) {
1377                 ttm_agp_unbind(ttm);
1378                 ttm_tt_destroy_common(bdev, ttm);
1379                 ttm_agp_destroy(ttm);
1380                 return;
1381         }
1382 #endif
1383         nouveau_sgdma_destroy(bdev, ttm);
1384 }
1385
1386 void
1387 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1388 {
1389         struct dma_resv *resv = nvbo->bo.base.resv;
1390
1391         if (exclusive)
1392                 dma_resv_add_excl_fence(resv, &fence->base);
1393         else if (fence)
1394                 dma_resv_add_shared_fence(resv, &fence->base);
1395 }
1396
1397 struct ttm_bo_driver nouveau_bo_driver = {
1398         .ttm_tt_create = &nouveau_ttm_tt_create,
1399         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1400         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1401         .ttm_tt_bind = &nouveau_ttm_tt_bind,
1402         .ttm_tt_unbind = &nouveau_ttm_tt_unbind,
1403         .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1404         .eviction_valuable = ttm_bo_eviction_valuable,
1405         .evict_flags = nouveau_bo_evict_flags,
1406         .move_notify = nouveau_bo_move_ntfy,
1407         .move = nouveau_bo_move,
1408         .verify_access = nouveau_bo_verify_access,
1409         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1410         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1411         .io_mem_free = &nouveau_ttm_io_mem_free,
1412 };